xref: /llvm-project/llvm/test/CodeGen/AVR/llrint.ll (revision 0408b131eb66ef842e7d57c1a0410a2a14f891ac)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s
3
4define i64 @testmsxs_builtin(float %x) {
5; CHECK-LABEL: testmsxs_builtin:
6; CHECK:       ; %bb.0: ; %entry
7; CHECK-NEXT:    call llrintf
8; CHECK-NEXT:    ret
9entry:
10  %0 = tail call i64 @llvm.llrint.f32(float %x)
11  ret i64 %0
12}
13
14define i64 @testmsxd_builtin(double %x) {
15; CHECK-LABEL: testmsxd_builtin:
16; CHECK:       ; %bb.0: ; %entry
17; CHECK-NEXT:    call llrint
18; CHECK-NEXT:    ret
19entry:
20  %0 = tail call i64 @llvm.llrint.f64(double %x)
21  ret i64 %0
22}
23
24declare i64 @llvm.llrint.f32(float) nounwind readnone
25declare i64 @llvm.llrint.f64(double) nounwind readnone
26