1; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s 3 4; CHECK-LABEL: {{^}}test1: 5; CHECK-NOT: s_waitcnt 6; CHECK: image_store 7; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}} 8; CHECK-NEXT: image_store 9; CHECK-NEXT: s_endpgm 10define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <4 x float> %d0, <4 x float> %d1, i32 %c0, i32 %c1) { 11 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %d0, i32 15, i32 %c0, <8 x i32> %rsrc, i32 0, i32 0) 12 call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00 13 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %d1, i32 15, i32 %c1, <8 x i32> %rsrc, i32 0, i32 0) 14 ret void 15} 16 17; Test that the intrinsic is merged with automatically generated waits and 18; emitted as late as possible. 19; 20; CHECK-LABEL: {{^}}test2: 21; CHECK-NOT: s_waitcnt 22; CHECK: image_load 23; CHECK-NEXT: v_lshlrev_b32 24; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}} 25; CHECK-NEXT: image_store 26define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) { 27 %t = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0) 28 call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00 29 %c.1 = mul i32 %c, 2 30 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %t, i32 15, i32 %c.1, <8 x i32> %rsrc, i32 0, i32 0) 31 ret void 32} 33 34; CHECK-LABEL: {{^}}test3: 35; CHECK: image_load 36; CHECK: s_waitcnt vmcnt(0) lgkmcnt(0) 37; CHECK: image_store 38define amdgpu_ps void @test3(<8 x i32> inreg %rsrc, i32 %c) { 39 %t = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %c, <8 x i32> %rsrc, i32 0, i32 0) 40 call void @llvm.amdgcn.s.waitcnt(i32 49279) ; not isInt<16>, but isUInt<16> 41 %c.1 = mul i32 %c, 2 42 call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %t, i32 15, i32 %c.1, <8 x i32> %rsrc, i32 0, i32 0) 43 ret void 44} 45 46declare void @llvm.amdgcn.s.waitcnt(i32) #0 47 48declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #1 49declare void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float>, i32, i32, <8 x i32>, i32, i32) #0 50 51attributes #0 = { nounwind } 52attributes #1 = { nounwind readonly } 53