xref: /llvm-project/llvm/test/CodeGen/AArch64/reduce-or.ll (revision 1dd0d3cf40f21b842dbee107b3d203db9fbaa4ae) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
3; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=1 | FileCheck %s --check-prefix=GISEL
4
5
6define i1 @test_redor_v1i1(<1 x i1> %a) {
7; CHECK-LABEL: test_redor_v1i1:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    and w0, w0, #0x1
10; CHECK-NEXT:    ret
11;
12; GISEL-LABEL: test_redor_v1i1:
13; GISEL:       // %bb.0:
14; GISEL-NEXT:    and w0, w0, #0x1
15; GISEL-NEXT:    ret
16  %or_result = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)
17  ret i1 %or_result
18}
19
20define i1 @test_redor_v2i1(<2 x i1> %a) {
21; CHECK-LABEL: test_redor_v2i1:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    shl v0.2s, v0.2s, #31
24; CHECK-NEXT:    cmlt v0.2s, v0.2s, #0
25; CHECK-NEXT:    umaxp v0.2s, v0.2s, v0.2s
26; CHECK-NEXT:    fmov w8, s0
27; CHECK-NEXT:    and w0, w8, #0x1
28; CHECK-NEXT:    ret
29;
30; GISEL-LABEL: test_redor_v2i1:
31; GISEL:       // %bb.0:
32; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
33; GISEL-NEXT:    mov w8, v0.s[1]
34; GISEL-NEXT:    fmov w9, s0
35; GISEL-NEXT:    orr w8, w9, w8
36; GISEL-NEXT:    and w0, w8, #0x1
37; GISEL-NEXT:    ret
38  %or_result = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %a)
39  ret i1 %or_result
40}
41
42define i1 @test_redor_v4i1(<4 x i1> %a) {
43; CHECK-LABEL: test_redor_v4i1:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    shl v0.4h, v0.4h, #15
46; CHECK-NEXT:    cmlt v0.4h, v0.4h, #0
47; CHECK-NEXT:    umaxv h0, v0.4h
48; CHECK-NEXT:    fmov w8, s0
49; CHECK-NEXT:    and w0, w8, #0x1
50; CHECK-NEXT:    ret
51;
52; GISEL-LABEL: test_redor_v4i1:
53; GISEL:       // %bb.0:
54; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
55; GISEL-NEXT:    umov w8, v0.h[0]
56; GISEL-NEXT:    umov w9, v0.h[1]
57; GISEL-NEXT:    umov w10, v0.h[2]
58; GISEL-NEXT:    umov w11, v0.h[3]
59; GISEL-NEXT:    orr w8, w8, w9
60; GISEL-NEXT:    orr w9, w10, w11
61; GISEL-NEXT:    orr w8, w8, w9
62; GISEL-NEXT:    and w0, w8, #0x1
63; GISEL-NEXT:    ret
64  %or_result = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> %a)
65  ret i1 %or_result
66}
67
68define i1 @test_redor_v8i1(<8 x i1> %a) {
69; CHECK-LABEL: test_redor_v8i1:
70; CHECK:       // %bb.0:
71; CHECK-NEXT:    shl v0.8b, v0.8b, #7
72; CHECK-NEXT:    cmlt v0.8b, v0.8b, #0
73; CHECK-NEXT:    umaxv b0, v0.8b
74; CHECK-NEXT:    fmov w8, s0
75; CHECK-NEXT:    and w0, w8, #0x1
76; CHECK-NEXT:    ret
77;
78; GISEL-LABEL: test_redor_v8i1:
79; GISEL:       // %bb.0:
80; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
81; GISEL-NEXT:    umov w8, v0.b[0]
82; GISEL-NEXT:    umov w9, v0.b[1]
83; GISEL-NEXT:    umov w10, v0.b[2]
84; GISEL-NEXT:    umov w11, v0.b[3]
85; GISEL-NEXT:    umov w12, v0.b[4]
86; GISEL-NEXT:    umov w13, v0.b[5]
87; GISEL-NEXT:    umov w14, v0.b[6]
88; GISEL-NEXT:    umov w15, v0.b[7]
89; GISEL-NEXT:    orr w8, w8, w9
90; GISEL-NEXT:    orr w9, w10, w11
91; GISEL-NEXT:    orr w10, w12, w13
92; GISEL-NEXT:    orr w11, w14, w15
93; GISEL-NEXT:    orr w8, w8, w9
94; GISEL-NEXT:    orr w9, w10, w11
95; GISEL-NEXT:    orr w8, w8, w9
96; GISEL-NEXT:    and w0, w8, #0x1
97; GISEL-NEXT:    ret
98  %or_result = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> %a)
99  ret i1 %or_result
100}
101
102define i1 @test_redor_v16i1(<16 x i1> %a) {
103; CHECK-LABEL: test_redor_v16i1:
104; CHECK:       // %bb.0:
105; CHECK-NEXT:    shl v0.16b, v0.16b, #7
106; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
107; CHECK-NEXT:    umaxv b0, v0.16b
108; CHECK-NEXT:    fmov w8, s0
109; CHECK-NEXT:    and w0, w8, #0x1
110; CHECK-NEXT:    ret
111;
112; GISEL-LABEL: test_redor_v16i1:
113; GISEL:       // %bb.0:
114; GISEL-NEXT:    umov w8, v0.b[0]
115; GISEL-NEXT:    umov w9, v0.b[1]
116; GISEL-NEXT:    umov w10, v0.b[2]
117; GISEL-NEXT:    umov w11, v0.b[3]
118; GISEL-NEXT:    umov w12, v0.b[4]
119; GISEL-NEXT:    umov w13, v0.b[5]
120; GISEL-NEXT:    umov w14, v0.b[6]
121; GISEL-NEXT:    umov w15, v0.b[7]
122; GISEL-NEXT:    umov w16, v0.b[8]
123; GISEL-NEXT:    umov w17, v0.b[9]
124; GISEL-NEXT:    umov w18, v0.b[10]
125; GISEL-NEXT:    umov w0, v0.b[11]
126; GISEL-NEXT:    orr w8, w8, w9
127; GISEL-NEXT:    umov w1, v0.b[12]
128; GISEL-NEXT:    umov w2, v0.b[13]
129; GISEL-NEXT:    orr w9, w10, w11
130; GISEL-NEXT:    orr w10, w12, w13
131; GISEL-NEXT:    umov w3, v0.b[14]
132; GISEL-NEXT:    orr w11, w14, w15
133; GISEL-NEXT:    orr w8, w8, w9
134; GISEL-NEXT:    umov w4, v0.b[15]
135; GISEL-NEXT:    orr w12, w16, w17
136; GISEL-NEXT:    orr w13, w18, w0
137; GISEL-NEXT:    orr w9, w10, w11
138; GISEL-NEXT:    orr w14, w1, w2
139; GISEL-NEXT:    orr w10, w12, w13
140; GISEL-NEXT:    orr w8, w8, w9
141; GISEL-NEXT:    orr w15, w3, w4
142; GISEL-NEXT:    orr w11, w14, w15
143; GISEL-NEXT:    orr w9, w10, w11
144; GISEL-NEXT:    orr w8, w8, w9
145; GISEL-NEXT:    and w0, w8, #0x1
146; GISEL-NEXT:    ret
147  %or_result = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)
148  ret i1 %or_result
149}
150
151define <16 x i1> @test_redor_ins_v16i1(<16 x i1> %a) {
152; CHECK-LABEL: test_redor_ins_v16i1:
153; CHECK:       // %bb.0:
154; CHECK-NEXT:    shl v0.16b, v0.16b, #7
155; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
156; CHECK-NEXT:    umaxv b0, v0.16b
157; CHECK-NEXT:    ret
158;
159; GISEL-LABEL: test_redor_ins_v16i1:
160; GISEL:       // %bb.0:
161; GISEL-NEXT:    umov w8, v0.b[0]
162; GISEL-NEXT:    umov w9, v0.b[1]
163; GISEL-NEXT:    umov w10, v0.b[2]
164; GISEL-NEXT:    umov w11, v0.b[3]
165; GISEL-NEXT:    umov w12, v0.b[4]
166; GISEL-NEXT:    umov w13, v0.b[5]
167; GISEL-NEXT:    umov w14, v0.b[6]
168; GISEL-NEXT:    umov w15, v0.b[7]
169; GISEL-NEXT:    umov w16, v0.b[8]
170; GISEL-NEXT:    umov w17, v0.b[9]
171; GISEL-NEXT:    umov w18, v0.b[10]
172; GISEL-NEXT:    umov w0, v0.b[11]
173; GISEL-NEXT:    orr w8, w8, w9
174; GISEL-NEXT:    umov w1, v0.b[12]
175; GISEL-NEXT:    umov w2, v0.b[13]
176; GISEL-NEXT:    orr w9, w10, w11
177; GISEL-NEXT:    orr w10, w12, w13
178; GISEL-NEXT:    umov w3, v0.b[14]
179; GISEL-NEXT:    orr w11, w14, w15
180; GISEL-NEXT:    orr w8, w8, w9
181; GISEL-NEXT:    umov w4, v0.b[15]
182; GISEL-NEXT:    orr w12, w16, w17
183; GISEL-NEXT:    orr w13, w18, w0
184; GISEL-NEXT:    orr w9, w10, w11
185; GISEL-NEXT:    orr w14, w1, w2
186; GISEL-NEXT:    orr w10, w12, w13
187; GISEL-NEXT:    orr w8, w8, w9
188; GISEL-NEXT:    orr w15, w3, w4
189; GISEL-NEXT:    orr w11, w14, w15
190; GISEL-NEXT:    orr w9, w10, w11
191; GISEL-NEXT:    orr w8, w8, w9
192; GISEL-NEXT:    fmov s0, w8
193; GISEL-NEXT:    ret
194  %or_result = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %a)
195  %ins = insertelement <16 x i1> poison, i1 %or_result, i64 0
196  ret <16 x i1> %ins
197}
198
199define i8 @test_redor_v1i8(<1 x i8> %a) {
200; CHECK-LABEL: test_redor_v1i8:
201; CHECK:       // %bb.0:
202; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
203; CHECK-NEXT:    umov w0, v0.b[0]
204; CHECK-NEXT:    ret
205;
206; GISEL-LABEL: test_redor_v1i8:
207; GISEL:       // %bb.0:
208; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
209; GISEL-NEXT:    umov w0, v0.b[0]
210; GISEL-NEXT:    ret
211  %or_result = call i8 @llvm.vector.reduce.or.v1i8(<1 x i8> %a)
212  ret i8 %or_result
213}
214
215define i8 @test_redor_v3i8(<3 x i8> %a) {
216; CHECK-LABEL: test_redor_v3i8:
217; CHECK:       // %bb.0:
218; CHECK-NEXT:    movi v0.2d, #0000000000000000
219; CHECK-NEXT:    mov v0.h[0], w0
220; CHECK-NEXT:    mov v0.h[1], w1
221; CHECK-NEXT:    fmov x8, d0
222; CHECK-NEXT:    mov v0.h[2], w2
223; CHECK-NEXT:    fmov x9, d0
224; CHECK-NEXT:    lsr x10, x9, #32
225; CHECK-NEXT:    lsr x9, x9, #16
226; CHECK-NEXT:    orr w8, w8, w10
227; CHECK-NEXT:    orr w0, w8, w9
228; CHECK-NEXT:    ret
229;
230; GISEL-LABEL: test_redor_v3i8:
231; GISEL:       // %bb.0:
232; GISEL-NEXT:    orr w8, w0, w1
233; GISEL-NEXT:    orr w0, w8, w2
234; GISEL-NEXT:    ret
235  %or_result = call i8 @llvm.vector.reduce.or.v3i8(<3 x i8> %a)
236  ret i8 %or_result
237}
238
239define i8 @test_redor_v4i8(<4 x i8> %a) {
240; CHECK-LABEL: test_redor_v4i8:
241; CHECK:       // %bb.0:
242; CHECK-NEXT:    fmov x8, d0
243; CHECK-NEXT:    orr x8, x8, x8, lsr #32
244; CHECK-NEXT:    lsr x9, x8, #16
245; CHECK-NEXT:    orr w0, w8, w9
246; CHECK-NEXT:    ret
247;
248; GISEL-LABEL: test_redor_v4i8:
249; GISEL:       // %bb.0:
250; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
251; GISEL-NEXT:    umov w8, v0.h[0]
252; GISEL-NEXT:    umov w9, v0.h[1]
253; GISEL-NEXT:    umov w10, v0.h[2]
254; GISEL-NEXT:    umov w11, v0.h[3]
255; GISEL-NEXT:    orr w8, w8, w9
256; GISEL-NEXT:    orr w9, w10, w11
257; GISEL-NEXT:    orr w0, w8, w9
258; GISEL-NEXT:    ret
259  %or_result = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a)
260  ret i8 %or_result
261}
262
263define i8 @test_redor_v8i8(<8 x i8> %a) {
264; CHECK-LABEL: test_redor_v8i8:
265; CHECK:       // %bb.0:
266; CHECK-NEXT:    fmov x8, d0
267; CHECK-NEXT:    orr x8, x8, x8, lsr #32
268; CHECK-NEXT:    orr x8, x8, x8, lsr #16
269; CHECK-NEXT:    lsr x9, x8, #8
270; CHECK-NEXT:    orr w0, w8, w9
271; CHECK-NEXT:    ret
272;
273; GISEL-LABEL: test_redor_v8i8:
274; GISEL:       // %bb.0:
275; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
276; GISEL-NEXT:    umov w8, v0.b[0]
277; GISEL-NEXT:    umov w9, v0.b[1]
278; GISEL-NEXT:    umov w10, v0.b[2]
279; GISEL-NEXT:    umov w11, v0.b[3]
280; GISEL-NEXT:    umov w12, v0.b[4]
281; GISEL-NEXT:    umov w13, v0.b[5]
282; GISEL-NEXT:    umov w14, v0.b[6]
283; GISEL-NEXT:    umov w15, v0.b[7]
284; GISEL-NEXT:    orr w8, w8, w9
285; GISEL-NEXT:    orr w9, w10, w11
286; GISEL-NEXT:    orr w10, w12, w13
287; GISEL-NEXT:    orr w11, w14, w15
288; GISEL-NEXT:    orr w8, w8, w9
289; GISEL-NEXT:    orr w9, w10, w11
290; GISEL-NEXT:    orr w0, w8, w9
291; GISEL-NEXT:    ret
292  %or_result = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)
293  ret i8 %or_result
294}
295
296define i8 @test_redor_v16i8(<16 x i8> %a) {
297; CHECK-LABEL: test_redor_v16i8:
298; CHECK:       // %bb.0:
299; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
300; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
301; CHECK-NEXT:    fmov x8, d0
302; CHECK-NEXT:    orr x8, x8, x8, lsr #32
303; CHECK-NEXT:    orr x8, x8, x8, lsr #16
304; CHECK-NEXT:    lsr x9, x8, #8
305; CHECK-NEXT:    orr w0, w8, w9
306; CHECK-NEXT:    ret
307;
308; GISEL-LABEL: test_redor_v16i8:
309; GISEL:       // %bb.0:
310; GISEL-NEXT:    mov d1, v0.d[1]
311; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
312; GISEL-NEXT:    umov w8, v0.b[0]
313; GISEL-NEXT:    umov w9, v0.b[1]
314; GISEL-NEXT:    umov w10, v0.b[2]
315; GISEL-NEXT:    umov w11, v0.b[3]
316; GISEL-NEXT:    umov w12, v0.b[4]
317; GISEL-NEXT:    umov w13, v0.b[5]
318; GISEL-NEXT:    umov w14, v0.b[6]
319; GISEL-NEXT:    umov w15, v0.b[7]
320; GISEL-NEXT:    orr w8, w8, w9
321; GISEL-NEXT:    orr w9, w10, w11
322; GISEL-NEXT:    orr w10, w12, w13
323; GISEL-NEXT:    orr w11, w14, w15
324; GISEL-NEXT:    orr w8, w8, w9
325; GISEL-NEXT:    orr w9, w10, w11
326; GISEL-NEXT:    orr w0, w8, w9
327; GISEL-NEXT:    ret
328  %or_result = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)
329  ret i8 %or_result
330}
331
332define i8 @test_redor_v32i8(<32 x i8> %a) {
333; CHECK-LABEL: test_redor_v32i8:
334; CHECK:       // %bb.0:
335; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
336; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
337; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
338; CHECK-NEXT:    fmov x8, d0
339; CHECK-NEXT:    orr x8, x8, x8, lsr #32
340; CHECK-NEXT:    orr x8, x8, x8, lsr #16
341; CHECK-NEXT:    lsr x9, x8, #8
342; CHECK-NEXT:    orr w0, w8, w9
343; CHECK-NEXT:    ret
344;
345; GISEL-LABEL: test_redor_v32i8:
346; GISEL:       // %bb.0:
347; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
348; GISEL-NEXT:    mov d1, v0.d[1]
349; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
350; GISEL-NEXT:    umov w8, v0.b[0]
351; GISEL-NEXT:    umov w9, v0.b[1]
352; GISEL-NEXT:    umov w10, v0.b[2]
353; GISEL-NEXT:    umov w11, v0.b[3]
354; GISEL-NEXT:    umov w12, v0.b[4]
355; GISEL-NEXT:    umov w13, v0.b[5]
356; GISEL-NEXT:    umov w14, v0.b[6]
357; GISEL-NEXT:    umov w15, v0.b[7]
358; GISEL-NEXT:    orr w8, w8, w9
359; GISEL-NEXT:    orr w9, w10, w11
360; GISEL-NEXT:    orr w10, w12, w13
361; GISEL-NEXT:    orr w11, w14, w15
362; GISEL-NEXT:    orr w8, w8, w9
363; GISEL-NEXT:    orr w9, w10, w11
364; GISEL-NEXT:    orr w0, w8, w9
365; GISEL-NEXT:    ret
366  %or_result = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %a)
367  ret i8 %or_result
368}
369
370define i16 @test_redor_v4i16(<4 x i16> %a) {
371; CHECK-LABEL: test_redor_v4i16:
372; CHECK:       // %bb.0:
373; CHECK-NEXT:    fmov x8, d0
374; CHECK-NEXT:    orr x8, x8, x8, lsr #32
375; CHECK-NEXT:    lsr x9, x8, #16
376; CHECK-NEXT:    orr w0, w8, w9
377; CHECK-NEXT:    ret
378;
379; GISEL-LABEL: test_redor_v4i16:
380; GISEL:       // %bb.0:
381; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
382; GISEL-NEXT:    umov w8, v0.h[0]
383; GISEL-NEXT:    umov w9, v0.h[1]
384; GISEL-NEXT:    umov w10, v0.h[2]
385; GISEL-NEXT:    umov w11, v0.h[3]
386; GISEL-NEXT:    orr w8, w8, w9
387; GISEL-NEXT:    orr w9, w10, w11
388; GISEL-NEXT:    orr w0, w8, w9
389; GISEL-NEXT:    ret
390  %or_result = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)
391  ret i16 %or_result
392}
393
394define i16 @test_redor_v8i16(<8 x i16> %a) {
395; CHECK-LABEL: test_redor_v8i16:
396; CHECK:       // %bb.0:
397; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
398; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
399; CHECK-NEXT:    fmov x8, d0
400; CHECK-NEXT:    orr x8, x8, x8, lsr #32
401; CHECK-NEXT:    lsr x9, x8, #16
402; CHECK-NEXT:    orr w0, w8, w9
403; CHECK-NEXT:    ret
404;
405; GISEL-LABEL: test_redor_v8i16:
406; GISEL:       // %bb.0:
407; GISEL-NEXT:    mov d1, v0.d[1]
408; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
409; GISEL-NEXT:    umov w8, v0.h[0]
410; GISEL-NEXT:    umov w9, v0.h[1]
411; GISEL-NEXT:    umov w10, v0.h[2]
412; GISEL-NEXT:    umov w11, v0.h[3]
413; GISEL-NEXT:    orr w8, w8, w9
414; GISEL-NEXT:    orr w9, w10, w11
415; GISEL-NEXT:    orr w0, w8, w9
416; GISEL-NEXT:    ret
417  %or_result = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)
418  ret i16 %or_result
419}
420
421define i16 @test_redor_v16i16(<16 x i16> %a) {
422; CHECK-LABEL: test_redor_v16i16:
423; CHECK:       // %bb.0:
424; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
425; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
426; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
427; CHECK-NEXT:    fmov x8, d0
428; CHECK-NEXT:    orr x8, x8, x8, lsr #32
429; CHECK-NEXT:    lsr x9, x8, #16
430; CHECK-NEXT:    orr w0, w8, w9
431; CHECK-NEXT:    ret
432;
433; GISEL-LABEL: test_redor_v16i16:
434; GISEL:       // %bb.0:
435; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
436; GISEL-NEXT:    mov d1, v0.d[1]
437; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
438; GISEL-NEXT:    umov w8, v0.h[0]
439; GISEL-NEXT:    umov w9, v0.h[1]
440; GISEL-NEXT:    umov w10, v0.h[2]
441; GISEL-NEXT:    umov w11, v0.h[3]
442; GISEL-NEXT:    orr w8, w8, w9
443; GISEL-NEXT:    orr w9, w10, w11
444; GISEL-NEXT:    orr w0, w8, w9
445; GISEL-NEXT:    ret
446  %or_result = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %a)
447  ret i16 %or_result
448}
449
450define i32 @test_redor_v2i32(<2 x i32> %a) {
451; CHECK-LABEL: test_redor_v2i32:
452; CHECK:       // %bb.0:
453; CHECK-NEXT:    fmov x8, d0
454; CHECK-NEXT:    lsr x9, x8, #32
455; CHECK-NEXT:    orr w0, w8, w9
456; CHECK-NEXT:    ret
457;
458; GISEL-LABEL: test_redor_v2i32:
459; GISEL:       // %bb.0:
460; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
461; GISEL-NEXT:    mov w8, v0.s[1]
462; GISEL-NEXT:    fmov w9, s0
463; GISEL-NEXT:    orr w0, w9, w8
464; GISEL-NEXT:    ret
465  %or_result = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)
466  ret i32 %or_result
467}
468
469define i32 @test_redor_v4i32(<4 x i32> %a) {
470; CHECK-LABEL: test_redor_v4i32:
471; CHECK:       // %bb.0:
472; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
473; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
474; CHECK-NEXT:    fmov x8, d0
475; CHECK-NEXT:    lsr x9, x8, #32
476; CHECK-NEXT:    orr w0, w8, w9
477; CHECK-NEXT:    ret
478;
479; GISEL-LABEL: test_redor_v4i32:
480; GISEL:       // %bb.0:
481; GISEL-NEXT:    mov d1, v0.d[1]
482; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
483; GISEL-NEXT:    mov w8, v0.s[1]
484; GISEL-NEXT:    fmov w9, s0
485; GISEL-NEXT:    orr w0, w9, w8
486; GISEL-NEXT:    ret
487  %or_result = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
488  ret i32 %or_result
489}
490
491define i32 @test_redor_v8i32(<8 x i32> %a) {
492; CHECK-LABEL: test_redor_v8i32:
493; CHECK:       // %bb.0:
494; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
495; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
496; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
497; CHECK-NEXT:    fmov x8, d0
498; CHECK-NEXT:    lsr x9, x8, #32
499; CHECK-NEXT:    orr w0, w8, w9
500; CHECK-NEXT:    ret
501;
502; GISEL-LABEL: test_redor_v8i32:
503; GISEL:       // %bb.0:
504; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
505; GISEL-NEXT:    mov d1, v0.d[1]
506; GISEL-NEXT:    orr v0.8b, v0.8b, v1.8b
507; GISEL-NEXT:    mov w8, v0.s[1]
508; GISEL-NEXT:    fmov w9, s0
509; GISEL-NEXT:    orr w0, w9, w8
510; GISEL-NEXT:    ret
511  %or_result = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %a)
512  ret i32 %or_result
513}
514
515define i64 @test_redor_v2i64(<2 x i64> %a) {
516; CHECK-LABEL: test_redor_v2i64:
517; CHECK:       // %bb.0:
518; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
519; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
520; CHECK-NEXT:    fmov x0, d0
521; CHECK-NEXT:    ret
522;
523; GISEL-LABEL: test_redor_v2i64:
524; GISEL:       // %bb.0:
525; GISEL-NEXT:    mov x8, v0.d[1]
526; GISEL-NEXT:    fmov x9, d0
527; GISEL-NEXT:    orr x0, x9, x8
528; GISEL-NEXT:    ret
529  %or_result = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)
530  ret i64 %or_result
531}
532
533define i64 @test_redor_v4i64(<4 x i64> %a) {
534; CHECK-LABEL: test_redor_v4i64:
535; CHECK:       // %bb.0:
536; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
537; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
538; CHECK-NEXT:    orr v0.8b, v0.8b, v1.8b
539; CHECK-NEXT:    fmov x0, d0
540; CHECK-NEXT:    ret
541;
542; GISEL-LABEL: test_redor_v4i64:
543; GISEL:       // %bb.0:
544; GISEL-NEXT:    orr v0.16b, v0.16b, v1.16b
545; GISEL-NEXT:    mov x8, v0.d[1]
546; GISEL-NEXT:    fmov x9, d0
547; GISEL-NEXT:    orr x0, x9, x8
548; GISEL-NEXT:    ret
549  %or_result = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %a)
550  ret i64 %or_result
551}
552
553declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
554declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
555declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
556declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>)
557declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>)
558declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
559declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
560declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
561declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
562declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
563declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
564declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
565declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)
566declare i8 @llvm.vector.reduce.or.v1i8(<1 x i8>)
567declare i8 @llvm.vector.reduce.or.v3i8(<3 x i8>)
568declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
569declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
570declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
571declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
572