1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_PHI - remainder of a PHI, identifies a program point where values 89/// merge under control flow. 90HANDLE_TARGET_OPCODE(DBG_PHI) 91 92/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 93HANDLE_TARGET_OPCODE(DBG_LABEL) 94 95/// REG_SEQUENCE - This variadic instruction is used to form a register that 96/// represents a consecutive sequence of sub-registers. It's used as a 97/// register coalescing / allocation aid and must be eliminated before code 98/// emission. 99// In SDNode form, the first operand encodes the register class created by 100// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 101// pair. Once it has been lowered to a MachineInstr, the regclass operand 102// is no longer present. 103/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 104/// After register coalescing references of v1024 should be replace with 105/// v1027:3, v1025 with v1027:4, etc. 106 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 107 108/// COPY - Target-independent register copy. This instruction can also be 109/// used to copy between subregisters of virtual registers. 110 HANDLE_TARGET_OPCODE(COPY) 111 112/// BUNDLE - This instruction represents an instruction bundle. Instructions 113/// which immediately follow a BUNDLE instruction which are marked with 114/// 'InsideBundle' flag are inside the bundle. 115HANDLE_TARGET_OPCODE(BUNDLE) 116 117/// Lifetime markers. 118HANDLE_TARGET_OPCODE(LIFETIME_START) 119HANDLE_TARGET_OPCODE(LIFETIME_END) 120 121/// Pseudo probe 122HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 123 124/// Arithmetic fence. 125HANDLE_TARGET_OPCODE(ARITH_FENCE) 126 127/// A Stackmap instruction captures the location of live variables at its 128/// position in the instruction stream. It is followed by a shadow of bytes 129/// that must lie within the function and not contain another stackmap. 130HANDLE_TARGET_OPCODE(STACKMAP) 131 132/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 133HANDLE_TARGET_OPCODE(FENTRY_CALL) 134 135/// Patchable call instruction - this instruction represents a call to a 136/// constant address, followed by a series of NOPs. It is intended to 137/// support optimizations for dynamic languages (such as javascript) that 138/// rewrite calls to runtimes with more efficient code sequences. 139/// This also implies a stack map. 140HANDLE_TARGET_OPCODE(PATCHPOINT) 141 142/// This pseudo-instruction loads the stack guard value. Targets which need 143/// to prevent the stack guard value or address from being spilled to the 144/// stack should override TargetLowering::emitLoadStackGuardNode and 145/// additionally expand this pseudo after register allocation. 146HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 147 148/// These are used to support call sites that must have the stack adjusted 149/// before the call (e.g. to initialize an argument passed by value). 150/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 151HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 152HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 153 154/// Call instruction with associated vm state for deoptimization and list 155/// of live pointers for relocation by the garbage collector. It is 156/// intended to support garbage collection with fully precise relocating 157/// collectors and deoptimizations in either the callee or caller. 158HANDLE_TARGET_OPCODE(STATEPOINT) 159 160/// Instruction that records the offset of a local stack allocation passed to 161/// llvm.localescape. It has two arguments: the symbol for the label and the 162/// frame index of the local stack allocation. 163HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 164 165/// Wraps a machine instruction which can fault, bundled with associated 166/// information on how to handle such a fault. 167/// For example loading instruction that may page fault, bundled with associated 168/// information on how to handle such a page fault. It is intended to support 169/// "zero cost" null checks in managed languages by allowing LLVM to fold 170/// comparisons into existing memory operations. 171HANDLE_TARGET_OPCODE(FAULTING_OP) 172 173/// Wraps a machine instruction to add patchability constraints. An 174/// instruction wrapped in PATCHABLE_OP has to either have a minimum 175/// size or be preceded with a nop of that size. The first operand is 176/// an immediate denoting the minimum size of the instruction, the 177/// second operand is an immediate denoting the opcode of the original 178/// instruction. The rest of the operands are the operands of the 179/// original instruction. 180/// PATCHABLE_OP can be used as second operand to only insert a nop of 181/// required size. 182HANDLE_TARGET_OPCODE(PATCHABLE_OP) 183 184/// This is a marker instruction which gets translated into a nop sled, useful 185/// for inserting instrumentation instructions at runtime. 186HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 187 188/// Wraps a return instruction and its operands to enable adding nop sleds 189/// either before or after the return. The nop sleds are useful for inserting 190/// instrumentation instructions at runtime. 191/// The patch here replaces the return instruction. 192HANDLE_TARGET_OPCODE(PATCHABLE_RET) 193 194/// This is a marker instruction which gets translated into a nop sled, useful 195/// for inserting instrumentation instructions at runtime. 196/// The patch here prepends the return instruction. 197/// The same thing as in x86_64 is not possible for ARM because it has multiple 198/// return instructions. Furthermore, CPU allows parametrized and even 199/// conditional return instructions. In the current ARM implementation we are 200/// making use of the fact that currently LLVM doesn't seem to generate 201/// conditional return instructions. 202/// On ARM, the same instruction can be used for popping multiple registers 203/// from the stack and returning (it just pops pc register too), and LLVM 204/// generates it sometimes. So we can't insert the sled between this stack 205/// adjustment and the return without splitting the original instruction into 2 206/// instructions. So on ARM, rather than jumping into the exit trampoline, we 207/// call it, it does the tracing, preserves the stack and returns. 208HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 209 210/// Wraps a tail call instruction and its operands to enable adding nop sleds 211/// either before or after the tail exit. We use this as a disambiguation from 212/// PATCHABLE_RET which specifically only works for return instructions. 213HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 214 215/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 216/// be patched to insert instrumentation instructions. 217HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 218 219/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 220/// can be patched to insert instrumentation instructions. 221HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 222 223HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 224 225// This is a fence with the singlethread scope. It represents a compiler memory 226// barrier, but does not correspond to any generated instruction. 227HANDLE_TARGET_OPCODE(MEMBARRIER) 228 229/// The following generic opcodes are not supposed to appear after ISel. 230/// This is something we might want to relax, but for now, this is convenient 231/// to produce diagnostics. 232 233/// Instructions which should not exist past instruction selection, but do not 234/// generate code. These instructions only act as optimization hints. 235HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 236HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 237HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) 238HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 239 G_ASSERT_SEXT) 240HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 241 G_ASSERT_ALIGN) 242 243/// Generic ADD instruction. This is an integer add. 244HANDLE_TARGET_OPCODE(G_ADD) 245HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 246 247/// Generic SUB instruction. This is an integer sub. 248HANDLE_TARGET_OPCODE(G_SUB) 249 250// Generic multiply instruction. 251HANDLE_TARGET_OPCODE(G_MUL) 252 253// Generic signed division instruction. 254HANDLE_TARGET_OPCODE(G_SDIV) 255 256// Generic unsigned division instruction. 257HANDLE_TARGET_OPCODE(G_UDIV) 258 259// Generic signed remainder instruction. 260HANDLE_TARGET_OPCODE(G_SREM) 261 262// Generic unsigned remainder instruction. 263HANDLE_TARGET_OPCODE(G_UREM) 264 265// Generic signed divrem instruction. 266HANDLE_TARGET_OPCODE(G_SDIVREM) 267 268// Generic unsigned divrem instruction. 269HANDLE_TARGET_OPCODE(G_UDIVREM) 270 271/// Generic bitwise and instruction. 272HANDLE_TARGET_OPCODE(G_AND) 273 274/// Generic bitwise or instruction. 275HANDLE_TARGET_OPCODE(G_OR) 276 277/// Generic bitwise exclusive-or instruction. 278HANDLE_TARGET_OPCODE(G_XOR) 279 280 281HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 282 283/// Generic PHI instruction with types. 284HANDLE_TARGET_OPCODE(G_PHI) 285 286/// Generic instruction to materialize the address of an alloca or other 287/// stack-based object. 288HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 289 290/// Generic reference to global value. 291HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 292 293/// Generic instruction to extract blocks of bits from the register given 294/// (typically a sub-register COPY after instruction selection). 295HANDLE_TARGET_OPCODE(G_EXTRACT) 296 297HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 298 299/// Generic instruction to insert blocks of bits from the registers given into 300/// the source. 301HANDLE_TARGET_OPCODE(G_INSERT) 302 303/// Generic instruction to paste a variable number of components together into a 304/// larger register. 305HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 306 307/// Generic instruction to create a vector value from a number of scalar 308/// components. 309HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 310 311/// Generic instruction to create a vector value from a number of scalar 312/// components, which have types larger than the result vector elt type. 313HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 314 315/// Generic instruction to create a vector by concatenating multiple vectors. 316HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 317 318/// Generic pointer to int conversion. 319HANDLE_TARGET_OPCODE(G_PTRTOINT) 320 321/// Generic int to pointer conversion. 322HANDLE_TARGET_OPCODE(G_INTTOPTR) 323 324/// Generic bitcast. The source and destination types must be different, or a 325/// COPY is the relevant instruction. 326HANDLE_TARGET_OPCODE(G_BITCAST) 327 328/// Generic freeze. 329HANDLE_TARGET_OPCODE(G_FREEZE) 330 331// INTRINSIC fptrunc_round intrinsic. 332HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND) 333 334/// INTRINSIC trunc intrinsic. 335HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 336 337/// INTRINSIC round intrinsic. 338HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 339 340/// INTRINSIC round to integer intrinsic. 341HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 342 343/// INTRINSIC roundeven intrinsic. 344HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 345 346/// INTRINSIC readcyclecounter 347HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 348 349/// Generic load (including anyext load) 350HANDLE_TARGET_OPCODE(G_LOAD) 351 352/// Generic signext load 353HANDLE_TARGET_OPCODE(G_SEXTLOAD) 354 355/// Generic zeroext load 356HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 357 358/// Generic indexed load (including anyext load) 359HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 360 361/// Generic indexed signext load 362HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 363 364/// Generic indexed zeroext load 365HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 366 367/// Generic store. 368HANDLE_TARGET_OPCODE(G_STORE) 369 370/// Generic indexed store. 371HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 372 373/// Generic atomic cmpxchg with internal success check. 374HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 375 376/// Generic atomic cmpxchg. 377HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 378 379/// Generic atomicrmw. 380HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 381HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 382HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 383HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 384HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 385HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 386HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 387HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 388HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 389HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 390HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 391HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 392HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 393HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) 394HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) 395HANDLE_TARGET_OPCODE(G_ATOMICRMW_UINC_WRAP) 396HANDLE_TARGET_OPCODE(G_ATOMICRMW_UDEC_WRAP) 397 398// Marker for start of Generic AtomicRMW opcodes 399HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG) 400 401// Marker for end of Generic AtomicRMW opcodes 402HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_UDEC_WRAP) 403 404// Generic atomic fence 405HANDLE_TARGET_OPCODE(G_FENCE) 406 407/// Generic conditional branch instruction. 408HANDLE_TARGET_OPCODE(G_BRCOND) 409 410/// Generic indirect branch instruction. 411HANDLE_TARGET_OPCODE(G_BRINDIRECT) 412 413/// Begin an invoke region marker. 414HANDLE_TARGET_OPCODE(G_INVOKE_REGION_START) 415 416/// Generic intrinsic use (without side effects). 417HANDLE_TARGET_OPCODE(G_INTRINSIC) 418 419/// Generic intrinsic use (with side effects). 420HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 421 422/// Generic extension allowing rubbish in high bits. 423HANDLE_TARGET_OPCODE(G_ANYEXT) 424 425/// Generic instruction to discard the high bits of a register. This differs 426/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 427/// each element individually, G_EXTRACT will typically discard the high 428/// elements of the vector. 429HANDLE_TARGET_OPCODE(G_TRUNC) 430 431/// Generic integer constant. 432HANDLE_TARGET_OPCODE(G_CONSTANT) 433 434/// Generic floating constant. 435HANDLE_TARGET_OPCODE(G_FCONSTANT) 436 437/// Generic va_start instruction. Stores to its one pointer operand. 438HANDLE_TARGET_OPCODE(G_VASTART) 439 440/// Generic va_start instruction. Stores to its one pointer operand. 441HANDLE_TARGET_OPCODE(G_VAARG) 442 443// Generic sign extend 444HANDLE_TARGET_OPCODE(G_SEXT) 445HANDLE_TARGET_OPCODE(G_SEXT_INREG) 446 447// Generic zero extend 448HANDLE_TARGET_OPCODE(G_ZEXT) 449 450// Generic left-shift 451HANDLE_TARGET_OPCODE(G_SHL) 452 453// Generic logical right-shift 454HANDLE_TARGET_OPCODE(G_LSHR) 455 456// Generic arithmetic right-shift 457HANDLE_TARGET_OPCODE(G_ASHR) 458 459// Generic funnel left shift 460HANDLE_TARGET_OPCODE(G_FSHL) 461 462// Generic funnel right shift 463HANDLE_TARGET_OPCODE(G_FSHR) 464 465// Generic right rotate 466HANDLE_TARGET_OPCODE(G_ROTR) 467 468// Generic left rotate 469HANDLE_TARGET_OPCODE(G_ROTL) 470 471/// Generic integer-base comparison, also applicable to vectors of integers. 472HANDLE_TARGET_OPCODE(G_ICMP) 473 474/// Generic floating-point comparison, also applicable to vectors. 475HANDLE_TARGET_OPCODE(G_FCMP) 476 477/// Generic select. 478HANDLE_TARGET_OPCODE(G_SELECT) 479 480/// Generic unsigned add instruction, consuming the normal operands and 481/// producing the result and a carry flag. 482HANDLE_TARGET_OPCODE(G_UADDO) 483 484/// Generic unsigned add instruction, consuming the normal operands plus a carry 485/// flag, and similarly producing the result and a carry flag. 486HANDLE_TARGET_OPCODE(G_UADDE) 487 488/// Generic unsigned sub instruction, consuming the normal operands and 489/// producing the result and a carry flag. 490HANDLE_TARGET_OPCODE(G_USUBO) 491 492/// Generic unsigned subtract instruction, consuming the normal operands plus a 493/// carry flag, and similarly producing the result and a carry flag. 494HANDLE_TARGET_OPCODE(G_USUBE) 495 496/// Generic signed add instruction, producing the result and a signed overflow 497/// flag. 498HANDLE_TARGET_OPCODE(G_SADDO) 499 500/// Generic signed add instruction, consuming the normal operands plus a carry 501/// flag, and similarly producing the result and a carry flag. 502HANDLE_TARGET_OPCODE(G_SADDE) 503 504/// Generic signed subtract instruction, producing the result and a signed 505/// overflow flag. 506HANDLE_TARGET_OPCODE(G_SSUBO) 507 508/// Generic signed sub instruction, consuming the normal operands plus a carry 509/// flag, and similarly producing the result and a carry flag. 510HANDLE_TARGET_OPCODE(G_SSUBE) 511 512/// Generic unsigned multiply instruction, producing the result and a signed 513/// overflow flag. 514HANDLE_TARGET_OPCODE(G_UMULO) 515 516/// Generic signed multiply instruction, producing the result and a signed 517/// overflow flag. 518HANDLE_TARGET_OPCODE(G_SMULO) 519 520// Multiply two numbers at twice the incoming bit width (unsigned) and return 521// the high half of the result. 522HANDLE_TARGET_OPCODE(G_UMULH) 523 524// Multiply two numbers at twice the incoming bit width (signed) and return 525// the high half of the result. 526HANDLE_TARGET_OPCODE(G_SMULH) 527 528/// Generic saturating unsigned addition. 529HANDLE_TARGET_OPCODE(G_UADDSAT) 530 531/// Generic saturating signed addition. 532HANDLE_TARGET_OPCODE(G_SADDSAT) 533 534/// Generic saturating unsigned subtraction. 535HANDLE_TARGET_OPCODE(G_USUBSAT) 536 537/// Generic saturating signed subtraction. 538HANDLE_TARGET_OPCODE(G_SSUBSAT) 539 540/// Generic saturating unsigned left shift. 541HANDLE_TARGET_OPCODE(G_USHLSAT) 542 543/// Generic saturating signed left shift. 544HANDLE_TARGET_OPCODE(G_SSHLSAT) 545 546// Perform signed fixed point multiplication 547HANDLE_TARGET_OPCODE(G_SMULFIX) 548 549// Perform unsigned fixed point multiplication 550HANDLE_TARGET_OPCODE(G_UMULFIX) 551 552// Perform signed, saturating fixed point multiplication 553HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 554 555// Perform unsigned, saturating fixed point multiplication 556HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 557 558// Perform signed fixed point division 559HANDLE_TARGET_OPCODE(G_SDIVFIX) 560 561// Perform unsigned fixed point division 562HANDLE_TARGET_OPCODE(G_UDIVFIX) 563 564// Perform signed, saturating fixed point division 565HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 566 567// Perform unsigned, saturating fixed point division 568HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 569 570/// Generic FP addition. 571HANDLE_TARGET_OPCODE(G_FADD) 572 573/// Generic FP subtraction. 574HANDLE_TARGET_OPCODE(G_FSUB) 575 576/// Generic FP multiplication. 577HANDLE_TARGET_OPCODE(G_FMUL) 578 579/// Generic FMA multiplication. Behaves like llvm fma intrinsic 580HANDLE_TARGET_OPCODE(G_FMA) 581 582/// Generic FP multiply and add. Behaves as separate fmul and fadd. 583HANDLE_TARGET_OPCODE(G_FMAD) 584 585/// Generic FP division. 586HANDLE_TARGET_OPCODE(G_FDIV) 587 588/// Generic FP remainder. 589HANDLE_TARGET_OPCODE(G_FREM) 590 591/// Generic FP exponentiation. 592HANDLE_TARGET_OPCODE(G_FPOW) 593 594/// Generic FP exponentiation, with an integer exponent. 595HANDLE_TARGET_OPCODE(G_FPOWI) 596 597/// Generic base-e exponential of a value. 598HANDLE_TARGET_OPCODE(G_FEXP) 599 600/// Generic base-2 exponential of a value. 601HANDLE_TARGET_OPCODE(G_FEXP2) 602 603/// Floating point base-e logarithm of a value. 604HANDLE_TARGET_OPCODE(G_FLOG) 605 606/// Floating point base-2 logarithm of a value. 607HANDLE_TARGET_OPCODE(G_FLOG2) 608 609/// Floating point base-10 logarithm of a value. 610HANDLE_TARGET_OPCODE(G_FLOG10) 611 612/// Generic FP negation. 613HANDLE_TARGET_OPCODE(G_FNEG) 614 615/// Generic FP extension. 616HANDLE_TARGET_OPCODE(G_FPEXT) 617 618/// Generic float to signed-int conversion 619HANDLE_TARGET_OPCODE(G_FPTRUNC) 620 621/// Generic float to signed-int conversion 622HANDLE_TARGET_OPCODE(G_FPTOSI) 623 624/// Generic float to unsigned-int conversion 625HANDLE_TARGET_OPCODE(G_FPTOUI) 626 627/// Generic signed-int to float conversion 628HANDLE_TARGET_OPCODE(G_SITOFP) 629 630/// Generic unsigned-int to float conversion 631HANDLE_TARGET_OPCODE(G_UITOFP) 632 633/// Generic FP absolute value. 634HANDLE_TARGET_OPCODE(G_FABS) 635 636/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 637/// not require that X and Y have the same type, just that they are both 638/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 639/// f64) is allowed. 640HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 641 642/// Generic test for floating-point class. 643HANDLE_TARGET_OPCODE(G_IS_FPCLASS) 644 645/// Generic FP canonicalize value. 646HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 647 648/// FP min/max matching libm's fmin/fmax 649HANDLE_TARGET_OPCODE(G_FMINNUM) 650HANDLE_TARGET_OPCODE(G_FMAXNUM) 651 652/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 653HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 654HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 655 656/// FP min/max matching IEEE-754 2018 draft semantics. 657HANDLE_TARGET_OPCODE(G_FMINIMUM) 658HANDLE_TARGET_OPCODE(G_FMAXIMUM) 659 660/// Generic pointer offset 661HANDLE_TARGET_OPCODE(G_PTR_ADD) 662 663/// Clear the specified bits in a pointer. 664HANDLE_TARGET_OPCODE(G_PTRMASK) 665 666/// Generic signed integer minimum. 667HANDLE_TARGET_OPCODE(G_SMIN) 668 669/// Generic signed integer maximum. 670HANDLE_TARGET_OPCODE(G_SMAX) 671 672/// Generic unsigned integer maximum. 673HANDLE_TARGET_OPCODE(G_UMIN) 674 675/// Generic unsigned integer maximum. 676HANDLE_TARGET_OPCODE(G_UMAX) 677 678/// Generic integer absolute value. 679HANDLE_TARGET_OPCODE(G_ABS) 680 681HANDLE_TARGET_OPCODE(G_LROUND) 682HANDLE_TARGET_OPCODE(G_LLROUND) 683 684/// Generic BRANCH instruction. This is an unconditional branch. 685HANDLE_TARGET_OPCODE(G_BR) 686 687/// Generic branch to jump table entry. 688HANDLE_TARGET_OPCODE(G_BRJT) 689 690/// Generic insertelement. 691HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 692 693/// Generic extractelement. 694HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 695 696/// Generic shufflevector. 697HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 698 699/// Generic count trailing zeroes. 700HANDLE_TARGET_OPCODE(G_CTTZ) 701 702/// Same as above, undefined for zero inputs. 703HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 704 705/// Generic count leading zeroes. 706HANDLE_TARGET_OPCODE(G_CTLZ) 707 708/// Same as above, undefined for zero inputs. 709HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 710 711/// Generic count bits. 712HANDLE_TARGET_OPCODE(G_CTPOP) 713 714/// Generic byte swap. 715HANDLE_TARGET_OPCODE(G_BSWAP) 716 717/// Generic bit reverse. 718HANDLE_TARGET_OPCODE(G_BITREVERSE) 719 720/// Floating point ceil. 721HANDLE_TARGET_OPCODE(G_FCEIL) 722 723/// Floating point cosine. 724HANDLE_TARGET_OPCODE(G_FCOS) 725 726/// Floating point sine. 727HANDLE_TARGET_OPCODE(G_FSIN) 728 729/// Floating point square root. 730HANDLE_TARGET_OPCODE(G_FSQRT) 731 732/// Floating point floor. 733HANDLE_TARGET_OPCODE(G_FFLOOR) 734 735/// Floating point round to next integer. 736HANDLE_TARGET_OPCODE(G_FRINT) 737 738/// Floating point round to nearest integer. 739HANDLE_TARGET_OPCODE(G_FNEARBYINT) 740 741/// Generic AddressSpaceCast. 742HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 743 744/// Generic block address 745HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 746 747/// Generic jump table address 748HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 749 750/// Generic dynamic stack allocation. 751HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 752 753/// Strict floating point instructions. 754HANDLE_TARGET_OPCODE(G_STRICT_FADD) 755HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 756HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 757HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 758HANDLE_TARGET_OPCODE(G_STRICT_FREM) 759HANDLE_TARGET_OPCODE(G_STRICT_FMA) 760HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 761 762/// read_register intrinsic 763HANDLE_TARGET_OPCODE(G_READ_REGISTER) 764 765/// write_register intrinsic 766HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 767 768/// llvm.memcpy intrinsic 769HANDLE_TARGET_OPCODE(G_MEMCPY) 770 771/// llvm.memcpy.inline intrinsic 772HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 773 774/// llvm.memmove intrinsic 775HANDLE_TARGET_OPCODE(G_MEMMOVE) 776 777/// llvm.memset intrinsic 778HANDLE_TARGET_OPCODE(G_MEMSET) 779HANDLE_TARGET_OPCODE(G_BZERO) 780 781/// Vector reductions 782HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 783HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 784HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 785HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 786HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 787HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 788HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 789HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 790HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 791HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 792HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 793HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 794HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 795HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 796HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 797 798HANDLE_TARGET_OPCODE(G_SBFX) 799HANDLE_TARGET_OPCODE(G_UBFX) 800 801/// Marker for the end of the generic opcode. 802/// This is used to check if an opcode is in the range of the 803/// generic opcodes. 804HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 805 806/// BUILTIN_OP_END - This must be the last enum value in this list. 807/// The target-specific post-isel opcode values start here. 808HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 809