1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// SUBREG_TO_REG - Assert the value of bits in a super register. 60/// The result of this instruction is the value of the second operand inserted 61/// into the subregister specified by the third operand. All other bits are 62/// assumed to be equal to the bits in the immediate integer constant in the 63/// first operand. This instruction just communicates information; No code 64/// should be generated. 65/// This is typically used after an instruction where the write to a subregister 66/// implicitly cleared the bits in the super registers. 67HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 68 69/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 70/// register-to-register copy into a specific register class. This is only 71/// used between instruction selection and MachineInstr creation, before 72/// virtual registers have been created for all the instructions, and it's 73/// only needed in cases where the register classes implied by the 74/// instructions are insufficient. It is emitted as a COPY MachineInstr. 75 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 76 77/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 78HANDLE_TARGET_OPCODE(DBG_VALUE) 79 80/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 81/// list of locations 82HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 83 84/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 85/// that defines the value, rather than a virtual register. 86HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 87 88/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 89HANDLE_TARGET_OPCODE(DBG_LABEL) 90 91/// REG_SEQUENCE - This variadic instruction is used to form a register that 92/// represents a consecutive sequence of sub-registers. It's used as a 93/// register coalescing / allocation aid and must be eliminated before code 94/// emission. 95// In SDNode form, the first operand encodes the register class created by 96// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 97// pair. Once it has been lowered to a MachineInstr, the regclass operand 98// is no longer present. 99/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 100/// After register coalescing references of v1024 should be replace with 101/// v1027:3, v1025 with v1027:4, etc. 102 HANDLE_TARGET_OPCODE(REG_SEQUENCE) 103 104/// COPY - Target-independent register copy. This instruction can also be 105/// used to copy between subregisters of virtual registers. 106 HANDLE_TARGET_OPCODE(COPY) 107 108/// BUNDLE - This instruction represents an instruction bundle. Instructions 109/// which immediately follow a BUNDLE instruction which are marked with 110/// 'InsideBundle' flag are inside the bundle. 111HANDLE_TARGET_OPCODE(BUNDLE) 112 113/// Lifetime markers. 114HANDLE_TARGET_OPCODE(LIFETIME_START) 115HANDLE_TARGET_OPCODE(LIFETIME_END) 116 117/// Pseudo probe 118HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 119 120/// A Stackmap instruction captures the location of live variables at its 121/// position in the instruction stream. It is followed by a shadow of bytes 122/// that must lie within the function and not contain another stackmap. 123HANDLE_TARGET_OPCODE(STACKMAP) 124 125/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 126HANDLE_TARGET_OPCODE(FENTRY_CALL) 127 128/// Patchable call instruction - this instruction represents a call to a 129/// constant address, followed by a series of NOPs. It is intended to 130/// support optimizations for dynamic languages (such as javascript) that 131/// rewrite calls to runtimes with more efficient code sequences. 132/// This also implies a stack map. 133HANDLE_TARGET_OPCODE(PATCHPOINT) 134 135/// This pseudo-instruction loads the stack guard value. Targets which need 136/// to prevent the stack guard value or address from being spilled to the 137/// stack should override TargetLowering::emitLoadStackGuardNode and 138/// additionally expand this pseudo after register allocation. 139HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 140 141/// These are used to support call sites that must have the stack adjusted 142/// before the call (e.g. to initialize an argument passed by value). 143/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 144HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 145HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 146 147/// Call instruction with associated vm state for deoptimization and list 148/// of live pointers for relocation by the garbage collector. It is 149/// intended to support garbage collection with fully precise relocating 150/// collectors and deoptimizations in either the callee or caller. 151HANDLE_TARGET_OPCODE(STATEPOINT) 152 153/// Instruction that records the offset of a local stack allocation passed to 154/// llvm.localescape. It has two arguments: the symbol for the label and the 155/// frame index of the local stack allocation. 156HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 157 158/// Wraps a machine instruction which can fault, bundled with associated 159/// information on how to handle such a fault. 160/// For example loading instruction that may page fault, bundled with associated 161/// information on how to handle such a page fault. It is intended to support 162/// "zero cost" null checks in managed languages by allowing LLVM to fold 163/// comparisons into existing memory operations. 164HANDLE_TARGET_OPCODE(FAULTING_OP) 165 166/// Wraps a machine instruction to add patchability constraints. An 167/// instruction wrapped in PATCHABLE_OP has to either have a minimum 168/// size or be preceded with a nop of that size. The first operand is 169/// an immediate denoting the minimum size of the instruction, the 170/// second operand is an immediate denoting the opcode of the original 171/// instruction. The rest of the operands are the operands of the 172/// original instruction. 173HANDLE_TARGET_OPCODE(PATCHABLE_OP) 174 175/// This is a marker instruction which gets translated into a nop sled, useful 176/// for inserting instrumentation instructions at runtime. 177HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 178 179/// Wraps a return instruction and its operands to enable adding nop sleds 180/// either before or after the return. The nop sleds are useful for inserting 181/// instrumentation instructions at runtime. 182/// The patch here replaces the return instruction. 183HANDLE_TARGET_OPCODE(PATCHABLE_RET) 184 185/// This is a marker instruction which gets translated into a nop sled, useful 186/// for inserting instrumentation instructions at runtime. 187/// The patch here prepends the return instruction. 188/// The same thing as in x86_64 is not possible for ARM because it has multiple 189/// return instructions. Furthermore, CPU allows parametrized and even 190/// conditional return instructions. In the current ARM implementation we are 191/// making use of the fact that currently LLVM doesn't seem to generate 192/// conditional return instructions. 193/// On ARM, the same instruction can be used for popping multiple registers 194/// from the stack and returning (it just pops pc register too), and LLVM 195/// generates it sometimes. So we can't insert the sled between this stack 196/// adjustment and the return without splitting the original instruction into 2 197/// instructions. So on ARM, rather than jumping into the exit trampoline, we 198/// call it, it does the tracing, preserves the stack and returns. 199HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 200 201/// Wraps a tail call instruction and its operands to enable adding nop sleds 202/// either before or after the tail exit. We use this as a disambiguation from 203/// PATCHABLE_RET which specifically only works for return instructions. 204HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 205 206/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 207/// be patched to insert instrumentation instructions. 208HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 209 210/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 211/// can be patched to insert instrumentation instructions. 212HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 213 214HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 215 216/// The following generic opcodes are not supposed to appear after ISel. 217/// This is something we might want to relax, but for now, this is convenient 218/// to produce diagnostics. 219 220/// Instructions which should not exist past instruction selection, but do not 221/// generate code. These instructions only act as optimization hints. 222HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 223HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 224HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 225 G_ASSERT_SEXT) 226HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 227 G_ASSERT_ZEXT) 228 229/// Generic ADD instruction. This is an integer add. 230HANDLE_TARGET_OPCODE(G_ADD) 231HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 232 233/// Generic SUB instruction. This is an integer sub. 234HANDLE_TARGET_OPCODE(G_SUB) 235 236// Generic multiply instruction. 237HANDLE_TARGET_OPCODE(G_MUL) 238 239// Generic signed division instruction. 240HANDLE_TARGET_OPCODE(G_SDIV) 241 242// Generic unsigned division instruction. 243HANDLE_TARGET_OPCODE(G_UDIV) 244 245// Generic signed remainder instruction. 246HANDLE_TARGET_OPCODE(G_SREM) 247 248// Generic unsigned remainder instruction. 249HANDLE_TARGET_OPCODE(G_UREM) 250 251// Generic signed divrem instruction. 252HANDLE_TARGET_OPCODE(G_SDIVREM) 253 254// Generic unsigned divrem instruction. 255HANDLE_TARGET_OPCODE(G_UDIVREM) 256 257/// Generic bitwise and instruction. 258HANDLE_TARGET_OPCODE(G_AND) 259 260/// Generic bitwise or instruction. 261HANDLE_TARGET_OPCODE(G_OR) 262 263/// Generic bitwise exclusive-or instruction. 264HANDLE_TARGET_OPCODE(G_XOR) 265 266 267HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 268 269/// Generic PHI instruction with types. 270HANDLE_TARGET_OPCODE(G_PHI) 271 272/// Generic instruction to materialize the address of an alloca or other 273/// stack-based object. 274HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 275 276/// Generic reference to global value. 277HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 278 279/// Generic instruction to extract blocks of bits from the register given 280/// (typically a sub-register COPY after instruction selection). 281HANDLE_TARGET_OPCODE(G_EXTRACT) 282 283HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 284 285/// Generic instruction to insert blocks of bits from the registers given into 286/// the source. 287HANDLE_TARGET_OPCODE(G_INSERT) 288 289/// Generic instruction to paste a variable number of components together into a 290/// larger register. 291HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 292 293/// Generic instruction to create a vector value from a number of scalar 294/// components. 295HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 296 297/// Generic instruction to create a vector value from a number of scalar 298/// components, which have types larger than the result vector elt type. 299HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 300 301/// Generic instruction to create a vector by concatenating multiple vectors. 302HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 303 304/// Generic pointer to int conversion. 305HANDLE_TARGET_OPCODE(G_PTRTOINT) 306 307/// Generic int to pointer conversion. 308HANDLE_TARGET_OPCODE(G_INTTOPTR) 309 310/// Generic bitcast. The source and destination types must be different, or a 311/// COPY is the relevant instruction. 312HANDLE_TARGET_OPCODE(G_BITCAST) 313 314/// Generic freeze. 315HANDLE_TARGET_OPCODE(G_FREEZE) 316 317/// INTRINSIC trunc intrinsic. 318HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 319 320/// INTRINSIC round intrinsic. 321HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 322 323/// INTRINSIC round to integer intrinsic. 324HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 325 326/// INTRINSIC roundeven intrinsic. 327HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 328 329/// INTRINSIC readcyclecounter 330HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 331 332/// Generic load (including anyext load) 333HANDLE_TARGET_OPCODE(G_LOAD) 334 335/// Generic signext load 336HANDLE_TARGET_OPCODE(G_SEXTLOAD) 337 338/// Generic zeroext load 339HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 340 341/// Generic indexed load (including anyext load) 342HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 343 344/// Generic indexed signext load 345HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 346 347/// Generic indexed zeroext load 348HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 349 350/// Generic store. 351HANDLE_TARGET_OPCODE(G_STORE) 352 353/// Generic indexed store. 354HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 355 356/// Generic atomic cmpxchg with internal success check. 357HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 358 359/// Generic atomic cmpxchg. 360HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 361 362/// Generic atomicrmw. 363HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 364HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 365HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 366HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 367HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 368HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 369HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 370HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 371HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 372HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 373HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 374HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 375HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 376 377// Generic atomic fence 378HANDLE_TARGET_OPCODE(G_FENCE) 379 380/// Generic conditional branch instruction. 381HANDLE_TARGET_OPCODE(G_BRCOND) 382 383/// Generic indirect branch instruction. 384HANDLE_TARGET_OPCODE(G_BRINDIRECT) 385 386/// Generic intrinsic use (without side effects). 387HANDLE_TARGET_OPCODE(G_INTRINSIC) 388 389/// Generic intrinsic use (with side effects). 390HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 391 392/// Generic extension allowing rubbish in high bits. 393HANDLE_TARGET_OPCODE(G_ANYEXT) 394 395/// Generic instruction to discard the high bits of a register. This differs 396/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 397/// each element individually, G_EXTRACT will typically discard the high 398/// elements of the vector. 399HANDLE_TARGET_OPCODE(G_TRUNC) 400 401/// Generic integer constant. 402HANDLE_TARGET_OPCODE(G_CONSTANT) 403 404/// Generic floating constant. 405HANDLE_TARGET_OPCODE(G_FCONSTANT) 406 407/// Generic va_start instruction. Stores to its one pointer operand. 408HANDLE_TARGET_OPCODE(G_VASTART) 409 410/// Generic va_start instruction. Stores to its one pointer operand. 411HANDLE_TARGET_OPCODE(G_VAARG) 412 413// Generic sign extend 414HANDLE_TARGET_OPCODE(G_SEXT) 415HANDLE_TARGET_OPCODE(G_SEXT_INREG) 416 417// Generic zero extend 418HANDLE_TARGET_OPCODE(G_ZEXT) 419 420// Generic left-shift 421HANDLE_TARGET_OPCODE(G_SHL) 422 423// Generic logical right-shift 424HANDLE_TARGET_OPCODE(G_LSHR) 425 426// Generic arithmetic right-shift 427HANDLE_TARGET_OPCODE(G_ASHR) 428 429// Generic funnel left shift 430HANDLE_TARGET_OPCODE(G_FSHL) 431 432// Generic funnel right shift 433HANDLE_TARGET_OPCODE(G_FSHR) 434 435// Generic right rotate 436HANDLE_TARGET_OPCODE(G_ROTR) 437 438// Generic left rotate 439HANDLE_TARGET_OPCODE(G_ROTL) 440 441/// Generic integer-base comparison, also applicable to vectors of integers. 442HANDLE_TARGET_OPCODE(G_ICMP) 443 444/// Generic floating-point comparison, also applicable to vectors. 445HANDLE_TARGET_OPCODE(G_FCMP) 446 447/// Generic select. 448HANDLE_TARGET_OPCODE(G_SELECT) 449 450/// Generic unsigned add instruction, consuming the normal operands and 451/// producing the result and a carry flag. 452HANDLE_TARGET_OPCODE(G_UADDO) 453 454/// Generic unsigned add instruction, consuming the normal operands plus a carry 455/// flag, and similarly producing the result and a carry flag. 456HANDLE_TARGET_OPCODE(G_UADDE) 457 458/// Generic unsigned sub instruction, consuming the normal operands and 459/// producing the result and a carry flag. 460HANDLE_TARGET_OPCODE(G_USUBO) 461 462/// Generic unsigned subtract instruction, consuming the normal operands plus a 463/// carry flag, and similarly producing the result and a carry flag. 464HANDLE_TARGET_OPCODE(G_USUBE) 465 466/// Generic signed add instruction, producing the result and a signed overflow 467/// flag. 468HANDLE_TARGET_OPCODE(G_SADDO) 469 470/// Generic signed add instruction, consuming the normal operands plus a carry 471/// flag, and similarly producing the result and a carry flag. 472HANDLE_TARGET_OPCODE(G_SADDE) 473 474/// Generic signed subtract instruction, producing the result and a signed 475/// overflow flag. 476HANDLE_TARGET_OPCODE(G_SSUBO) 477 478/// Generic signed sub instruction, consuming the normal operands plus a carry 479/// flag, and similarly producing the result and a carry flag. 480HANDLE_TARGET_OPCODE(G_SSUBE) 481 482/// Generic unsigned multiply instruction, producing the result and a signed 483/// overflow flag. 484HANDLE_TARGET_OPCODE(G_UMULO) 485 486/// Generic signed multiply instruction, producing the result and a signed 487/// overflow flag. 488HANDLE_TARGET_OPCODE(G_SMULO) 489 490// Multiply two numbers at twice the incoming bit width (unsigned) and return 491// the high half of the result. 492HANDLE_TARGET_OPCODE(G_UMULH) 493 494// Multiply two numbers at twice the incoming bit width (signed) and return 495// the high half of the result. 496HANDLE_TARGET_OPCODE(G_SMULH) 497 498/// Generic saturating unsigned addition. 499HANDLE_TARGET_OPCODE(G_UADDSAT) 500 501/// Generic saturating signed addition. 502HANDLE_TARGET_OPCODE(G_SADDSAT) 503 504/// Generic saturating unsigned subtraction. 505HANDLE_TARGET_OPCODE(G_USUBSAT) 506 507/// Generic saturating signed subtraction. 508HANDLE_TARGET_OPCODE(G_SSUBSAT) 509 510/// Generic saturating unsigned left shift. 511HANDLE_TARGET_OPCODE(G_USHLSAT) 512 513/// Generic saturating signed left shift. 514HANDLE_TARGET_OPCODE(G_SSHLSAT) 515 516// Perform signed fixed point multiplication 517HANDLE_TARGET_OPCODE(G_SMULFIX) 518 519// Perform unsigned fixed point multiplication 520HANDLE_TARGET_OPCODE(G_UMULFIX) 521 522// Perform signed, saturating fixed point multiplication 523HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 524 525// Perform unsigned, saturating fixed point multiplication 526HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 527 528// Perform signed fixed point division 529HANDLE_TARGET_OPCODE(G_SDIVFIX) 530 531// Perform unsigned fixed point division 532HANDLE_TARGET_OPCODE(G_UDIVFIX) 533 534// Perform signed, saturating fixed point division 535HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 536 537// Perform unsigned, saturating fixed point division 538HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 539 540/// Generic FP addition. 541HANDLE_TARGET_OPCODE(G_FADD) 542 543/// Generic FP subtraction. 544HANDLE_TARGET_OPCODE(G_FSUB) 545 546/// Generic FP multiplication. 547HANDLE_TARGET_OPCODE(G_FMUL) 548 549/// Generic FMA multiplication. Behaves like llvm fma intrinsic 550HANDLE_TARGET_OPCODE(G_FMA) 551 552/// Generic FP multiply and add. Behaves as separate fmul and fadd. 553HANDLE_TARGET_OPCODE(G_FMAD) 554 555/// Generic FP division. 556HANDLE_TARGET_OPCODE(G_FDIV) 557 558/// Generic FP remainder. 559HANDLE_TARGET_OPCODE(G_FREM) 560 561/// Generic FP exponentiation. 562HANDLE_TARGET_OPCODE(G_FPOW) 563 564/// Generic FP exponentiation, with an integer exponent. 565HANDLE_TARGET_OPCODE(G_FPOWI) 566 567/// Generic base-e exponential of a value. 568HANDLE_TARGET_OPCODE(G_FEXP) 569 570/// Generic base-2 exponential of a value. 571HANDLE_TARGET_OPCODE(G_FEXP2) 572 573/// Floating point base-e logarithm of a value. 574HANDLE_TARGET_OPCODE(G_FLOG) 575 576/// Floating point base-2 logarithm of a value. 577HANDLE_TARGET_OPCODE(G_FLOG2) 578 579/// Floating point base-10 logarithm of a value. 580HANDLE_TARGET_OPCODE(G_FLOG10) 581 582/// Generic FP negation. 583HANDLE_TARGET_OPCODE(G_FNEG) 584 585/// Generic FP extension. 586HANDLE_TARGET_OPCODE(G_FPEXT) 587 588/// Generic float to signed-int conversion 589HANDLE_TARGET_OPCODE(G_FPTRUNC) 590 591/// Generic float to signed-int conversion 592HANDLE_TARGET_OPCODE(G_FPTOSI) 593 594/// Generic float to unsigned-int conversion 595HANDLE_TARGET_OPCODE(G_FPTOUI) 596 597/// Generic signed-int to float conversion 598HANDLE_TARGET_OPCODE(G_SITOFP) 599 600/// Generic unsigned-int to float conversion 601HANDLE_TARGET_OPCODE(G_UITOFP) 602 603/// Generic FP absolute value. 604HANDLE_TARGET_OPCODE(G_FABS) 605 606/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 607/// not require that X and Y have the same type, just that they are both 608/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 609/// f64) is allowed. 610HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 611 612/// Generic FP canonicalize value. 613HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 614 615/// FP min/max matching libm's fmin/fmax 616HANDLE_TARGET_OPCODE(G_FMINNUM) 617HANDLE_TARGET_OPCODE(G_FMAXNUM) 618 619/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 620HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 621HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 622 623/// FP min/max matching IEEE-754 2018 draft semantics. 624HANDLE_TARGET_OPCODE(G_FMINIMUM) 625HANDLE_TARGET_OPCODE(G_FMAXIMUM) 626 627/// Generic pointer offset 628HANDLE_TARGET_OPCODE(G_PTR_ADD) 629 630/// Clear the specified bits in a pointer. 631HANDLE_TARGET_OPCODE(G_PTRMASK) 632 633/// Generic signed integer minimum. 634HANDLE_TARGET_OPCODE(G_SMIN) 635 636/// Generic signed integer maximum. 637HANDLE_TARGET_OPCODE(G_SMAX) 638 639/// Generic unsigned integer maximum. 640HANDLE_TARGET_OPCODE(G_UMIN) 641 642/// Generic unsigned integer maximum. 643HANDLE_TARGET_OPCODE(G_UMAX) 644 645/// Generic integer absolute value. 646HANDLE_TARGET_OPCODE(G_ABS) 647 648/// Generic BRANCH instruction. This is an unconditional branch. 649HANDLE_TARGET_OPCODE(G_BR) 650 651/// Generic branch to jump table entry. 652HANDLE_TARGET_OPCODE(G_BRJT) 653 654/// Generic insertelement. 655HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 656 657/// Generic extractelement. 658HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 659 660/// Generic shufflevector. 661HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 662 663/// Generic count trailing zeroes. 664HANDLE_TARGET_OPCODE(G_CTTZ) 665 666/// Same as above, undefined for zero inputs. 667HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 668 669/// Generic count leading zeroes. 670HANDLE_TARGET_OPCODE(G_CTLZ) 671 672/// Same as above, undefined for zero inputs. 673HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 674 675/// Generic count bits. 676HANDLE_TARGET_OPCODE(G_CTPOP) 677 678/// Generic byte swap. 679HANDLE_TARGET_OPCODE(G_BSWAP) 680 681/// Generic bit reverse. 682HANDLE_TARGET_OPCODE(G_BITREVERSE) 683 684/// Floating point ceil. 685HANDLE_TARGET_OPCODE(G_FCEIL) 686 687/// Floating point cosine. 688HANDLE_TARGET_OPCODE(G_FCOS) 689 690/// Floating point sine. 691HANDLE_TARGET_OPCODE(G_FSIN) 692 693/// Floating point square root. 694HANDLE_TARGET_OPCODE(G_FSQRT) 695 696/// Floating point floor. 697HANDLE_TARGET_OPCODE(G_FFLOOR) 698 699/// Floating point round to next integer. 700HANDLE_TARGET_OPCODE(G_FRINT) 701 702/// Floating point round to nearest integer. 703HANDLE_TARGET_OPCODE(G_FNEARBYINT) 704 705/// Generic AddressSpaceCast. 706HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 707 708/// Generic block address 709HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 710 711/// Generic jump table address 712HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 713 714/// Generic dynamic stack allocation. 715HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 716 717/// Strict floating point instructions. 718HANDLE_TARGET_OPCODE(G_STRICT_FADD) 719HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 720HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 721HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 722HANDLE_TARGET_OPCODE(G_STRICT_FREM) 723HANDLE_TARGET_OPCODE(G_STRICT_FMA) 724HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 725 726/// read_register intrinsic 727HANDLE_TARGET_OPCODE(G_READ_REGISTER) 728 729/// write_register intrinsic 730HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 731 732/// llvm.memcpy intrinsic 733HANDLE_TARGET_OPCODE(G_MEMCPY) 734 735/// llvm.memmove intrinsic 736HANDLE_TARGET_OPCODE(G_MEMMOVE) 737 738/// llvm.memset intrinsic 739HANDLE_TARGET_OPCODE(G_MEMSET) 740HANDLE_TARGET_OPCODE(G_BZERO) 741 742/// Vector reductions 743HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 744HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 745HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 746HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 747HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 748HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 749HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 750HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 751HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 752HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 753HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 754HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 755HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 756HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 757HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 758 759HANDLE_TARGET_OPCODE(G_SBFX) 760HANDLE_TARGET_OPCODE(G_UBFX) 761 762/// Marker for the end of the generic opcode. 763/// This is used to check if an opcode is in the range of the 764/// generic opcodes. 765HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 766 767/// BUILTIN_OP_END - This must be the last enum value in this list. 768/// The target-specific post-isel opcode values start here. 769HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 770