1//===-- llvm/Support/TargetOpcodes.def - Target Indep Opcodes ---*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target independent instruction opcodes. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value. 16/// 17#ifndef HANDLE_TARGET_OPCODE 18#define HANDLE_TARGET_OPCODE(OPC, NUM) 19#endif 20 21/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode. 22/// 23#ifndef HANDLE_TARGET_OPCODE_MARKER 24#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) 25#endif 26 27/// Every instruction defined here must also appear in Target.td. 28/// 29HANDLE_TARGET_OPCODE(PHI) 30HANDLE_TARGET_OPCODE(INLINEASM) 31HANDLE_TARGET_OPCODE(INLINEASM_BR) 32HANDLE_TARGET_OPCODE(CFI_INSTRUCTION) 33HANDLE_TARGET_OPCODE(EH_LABEL) 34HANDLE_TARGET_OPCODE(GC_LABEL) 35HANDLE_TARGET_OPCODE(ANNOTATION_LABEL) 36 37/// KILL - This instruction is a noop that is used only to adjust the 38/// liveness of registers. This can be useful when dealing with 39/// sub-registers. 40HANDLE_TARGET_OPCODE(KILL) 41 42/// EXTRACT_SUBREG - This instruction takes two operands: a register 43/// that has subregisters, and a subregister index. It returns the 44/// extracted subregister value. This is commonly used to implement 45/// truncation operations on target architectures which support it. 46HANDLE_TARGET_OPCODE(EXTRACT_SUBREG) 47 48/// INSERT_SUBREG - This instruction takes three operands: a register that 49/// has subregisters, a register providing an insert value, and a 50/// subregister index. It returns the value of the first register with the 51/// value of the second register inserted. The first register is often 52/// defined by an IMPLICIT_DEF, because it is commonly used to implement 53/// anyext operations on target architectures which support it. 54HANDLE_TARGET_OPCODE(INSERT_SUBREG) 55 56/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef. 57HANDLE_TARGET_OPCODE(IMPLICIT_DEF) 58 59/// Explicit undef initialization used past IMPLICIT_DEF elimination in cases 60/// where an undef operand must be allocated to a different register than an 61/// early-clobber result operand. 62HANDLE_TARGET_OPCODE(INIT_UNDEF) 63 64/// SUBREG_TO_REG - Assert the value of bits in a super register. 65/// The result of this instruction is the value of the second operand inserted 66/// into the subregister specified by the third operand. All other bits are 67/// assumed to be equal to the bits in the immediate integer constant in the 68/// first operand. This instruction just communicates information; No code 69/// should be generated. 70/// This is typically used after an instruction where the write to a subregister 71/// implicitly cleared the bits in the super registers. 72HANDLE_TARGET_OPCODE(SUBREG_TO_REG) 73 74/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain 75/// register-to-register copy into a specific register class. This is only 76/// used between instruction selection and MachineInstr creation, before 77/// virtual registers have been created for all the instructions, and it's 78/// only needed in cases where the register classes implied by the 79/// instructions are insufficient. It is emitted as a COPY MachineInstr. 80HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS) 81 82/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic 83HANDLE_TARGET_OPCODE(DBG_VALUE) 84 85/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic with a variadic 86/// list of locations 87HANDLE_TARGET_OPCODE(DBG_VALUE_LIST) 88 89/// DBG_INSTR_REF - A mapping of llvm.dbg.value referring to the instruction 90/// that defines the value, rather than a virtual register. 91HANDLE_TARGET_OPCODE(DBG_INSTR_REF) 92 93/// DBG_PHI - remainder of a PHI, identifies a program point where values 94/// merge under control flow. 95HANDLE_TARGET_OPCODE(DBG_PHI) 96 97/// DBG_LABEL - a mapping of the llvm.dbg.label intrinsic 98HANDLE_TARGET_OPCODE(DBG_LABEL) 99 100/// REG_SEQUENCE - This variadic instruction is used to form a register that 101/// represents a consecutive sequence of sub-registers. It's used as a 102/// register coalescing / allocation aid and must be eliminated before code 103/// emission. 104// In SDNode form, the first operand encodes the register class created by 105// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index 106// pair. Once it has been lowered to a MachineInstr, the regclass operand 107// is no longer present. 108/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 109/// After register coalescing references of v1024 should be replace with 110/// v1027:3, v1025 with v1027:4, etc. 111HANDLE_TARGET_OPCODE(REG_SEQUENCE) 112 113/// COPY - Target-independent register copy. This instruction can also be 114/// used to copy between subregisters of virtual registers. 115HANDLE_TARGET_OPCODE(COPY) 116 117/// BUNDLE - This instruction represents an instruction bundle. Instructions 118/// which immediately follow a BUNDLE instruction which are marked with 119/// 'InsideBundle' flag are inside the bundle. 120HANDLE_TARGET_OPCODE(BUNDLE) 121 122/// Lifetime markers. 123HANDLE_TARGET_OPCODE(LIFETIME_START) 124HANDLE_TARGET_OPCODE(LIFETIME_END) 125 126/// Pseudo probe 127HANDLE_TARGET_OPCODE(PSEUDO_PROBE) 128 129/// Arithmetic fence. 130HANDLE_TARGET_OPCODE(ARITH_FENCE) 131 132/// A Stackmap instruction captures the location of live variables at its 133/// position in the instruction stream. It is followed by a shadow of bytes 134/// that must lie within the function and not contain another stackmap. 135HANDLE_TARGET_OPCODE(STACKMAP) 136 137/// FEntry all - This is a marker instruction which gets translated into a raw fentry call. 138HANDLE_TARGET_OPCODE(FENTRY_CALL) 139 140/// Patchable call instruction - this instruction represents a call to a 141/// constant address, followed by a series of NOPs. It is intended to 142/// support optimizations for dynamic languages (such as javascript) that 143/// rewrite calls to runtimes with more efficient code sequences. 144/// This also implies a stack map. 145HANDLE_TARGET_OPCODE(PATCHPOINT) 146 147/// This pseudo-instruction loads the stack guard value. Targets which need 148/// to prevent the stack guard value or address from being spilled to the 149/// stack should override TargetLowering::emitLoadStackGuardNode and 150/// additionally expand this pseudo after register allocation. 151HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD) 152 153/// These are used to support call sites that must have the stack adjusted 154/// before the call (e.g. to initialize an argument passed by value). 155/// See llvm.call.preallocated.{setup,arg} in the LangRef for more details. 156HANDLE_TARGET_OPCODE(PREALLOCATED_SETUP) 157HANDLE_TARGET_OPCODE(PREALLOCATED_ARG) 158 159/// Call instruction with associated vm state for deoptimization and list 160/// of live pointers for relocation by the garbage collector. It is 161/// intended to support garbage collection with fully precise relocating 162/// collectors and deoptimizations in either the callee or caller. 163HANDLE_TARGET_OPCODE(STATEPOINT) 164 165/// Instruction that records the offset of a local stack allocation passed to 166/// llvm.localescape. It has two arguments: the symbol for the label and the 167/// frame index of the local stack allocation. 168HANDLE_TARGET_OPCODE(LOCAL_ESCAPE) 169 170/// Wraps a machine instruction which can fault, bundled with associated 171/// information on how to handle such a fault. 172/// For example loading instruction that may page fault, bundled with associated 173/// information on how to handle such a page fault. It is intended to support 174/// "zero cost" null checks in managed languages by allowing LLVM to fold 175/// comparisons into existing memory operations. 176HANDLE_TARGET_OPCODE(FAULTING_OP) 177 178/// Precedes a machine instruction to add patchability constraints. An 179/// instruction after PATCHABLE_OP has to either have a minimum 180/// size or be preceded with a nop of that size. The first operand is 181/// an immediate denoting the minimum size of the following instruction. 182HANDLE_TARGET_OPCODE(PATCHABLE_OP) 183 184/// This is a marker instruction which gets translated into a nop sled, useful 185/// for inserting instrumentation instructions at runtime. 186HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_ENTER) 187 188/// Wraps a return instruction and its operands to enable adding nop sleds 189/// either before or after the return. The nop sleds are useful for inserting 190/// instrumentation instructions at runtime. 191/// The patch here replaces the return instruction. 192HANDLE_TARGET_OPCODE(PATCHABLE_RET) 193 194/// This is a marker instruction which gets translated into a nop sled, useful 195/// for inserting instrumentation instructions at runtime. 196/// The patch here prepends the return instruction. 197/// The same thing as in x86_64 is not possible for ARM because it has multiple 198/// return instructions. Furthermore, CPU allows parametrized and even 199/// conditional return instructions. In the current ARM implementation we are 200/// making use of the fact that currently LLVM doesn't seem to generate 201/// conditional return instructions. 202/// On ARM, the same instruction can be used for popping multiple registers 203/// from the stack and returning (it just pops pc register too), and LLVM 204/// generates it sometimes. So we can't insert the sled between this stack 205/// adjustment and the return without splitting the original instruction into 2 206/// instructions. So on ARM, rather than jumping into the exit trampoline, we 207/// call it, it does the tracing, preserves the stack and returns. 208HANDLE_TARGET_OPCODE(PATCHABLE_FUNCTION_EXIT) 209 210/// Wraps a tail call instruction and its operands to enable adding nop sleds 211/// either before or after the tail exit. We use this as a disambiguation from 212/// PATCHABLE_RET which specifically only works for return instructions. 213HANDLE_TARGET_OPCODE(PATCHABLE_TAIL_CALL) 214 215/// Wraps a logging call and its arguments with nop sleds. At runtime, this can 216/// be patched to insert instrumentation instructions. 217HANDLE_TARGET_OPCODE(PATCHABLE_EVENT_CALL) 218 219/// Wraps a typed logging call and its argument with nop sleds. At runtime, this 220/// can be patched to insert instrumentation instructions. 221HANDLE_TARGET_OPCODE(PATCHABLE_TYPED_EVENT_CALL) 222 223HANDLE_TARGET_OPCODE(ICALL_BRANCH_FUNNEL) 224 225/// Represents a use of the operand but generates no code. 226HANDLE_TARGET_OPCODE(FAKE_USE) 227 228// This is a fence with the singlethread scope. It represents a compiler memory 229// barrier, but does not correspond to any generated instruction. 230HANDLE_TARGET_OPCODE(MEMBARRIER) 231 232// Provides information about what jump table the following indirect branch is 233// using. 234HANDLE_TARGET_OPCODE(JUMP_TABLE_DEBUG_INFO) 235 236HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ENTRY) 237HANDLE_TARGET_OPCODE(CONVERGENCECTRL_ANCHOR) 238HANDLE_TARGET_OPCODE(CONVERGENCECTRL_LOOP) 239HANDLE_TARGET_OPCODE(CONVERGENCECTRL_GLUE) 240 241/// The following generic opcodes are not supposed to appear after ISel. 242/// This is something we might want to relax, but for now, this is convenient 243/// to produce diagnostics. 244 245/// Instructions which should not exist past instruction selection, but do not 246/// generate code. These instructions only act as optimization hints. 247HANDLE_TARGET_OPCODE(G_ASSERT_SEXT) 248HANDLE_TARGET_OPCODE(G_ASSERT_ZEXT) 249HANDLE_TARGET_OPCODE(G_ASSERT_ALIGN) 250HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START, 251 G_ASSERT_SEXT) 252HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END, 253 G_ASSERT_ALIGN) 254 255/// Generic ADD instruction. This is an integer add. 256HANDLE_TARGET_OPCODE(G_ADD) 257HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD) 258 259/// Generic SUB instruction. This is an integer sub. 260HANDLE_TARGET_OPCODE(G_SUB) 261 262// Generic multiply instruction. 263HANDLE_TARGET_OPCODE(G_MUL) 264 265// Generic signed division instruction. 266HANDLE_TARGET_OPCODE(G_SDIV) 267 268// Generic unsigned division instruction. 269HANDLE_TARGET_OPCODE(G_UDIV) 270 271// Generic signed remainder instruction. 272HANDLE_TARGET_OPCODE(G_SREM) 273 274// Generic unsigned remainder instruction. 275HANDLE_TARGET_OPCODE(G_UREM) 276 277// Generic signed divrem instruction. 278HANDLE_TARGET_OPCODE(G_SDIVREM) 279 280// Generic unsigned divrem instruction. 281HANDLE_TARGET_OPCODE(G_UDIVREM) 282 283/// Generic bitwise and instruction. 284HANDLE_TARGET_OPCODE(G_AND) 285 286/// Generic bitwise or instruction. 287HANDLE_TARGET_OPCODE(G_OR) 288 289/// Generic bitwise exclusive-or instruction. 290HANDLE_TARGET_OPCODE(G_XOR) 291 292/// Generic absolute difference signed instruction. 293HANDLE_TARGET_OPCODE(G_ABDS) 294 295/// Generic absolute difference unsigned instruction. 296HANDLE_TARGET_OPCODE(G_ABDU) 297 298 299HANDLE_TARGET_OPCODE(G_IMPLICIT_DEF) 300 301/// Generic PHI instruction with types. 302HANDLE_TARGET_OPCODE(G_PHI) 303 304/// Generic instruction to materialize the address of an alloca or other 305/// stack-based object. 306HANDLE_TARGET_OPCODE(G_FRAME_INDEX) 307 308/// Generic reference to global value. 309HANDLE_TARGET_OPCODE(G_GLOBAL_VALUE) 310 311/// Generic ptrauth-signed reference to global value. 312HANDLE_TARGET_OPCODE(G_PTRAUTH_GLOBAL_VALUE) 313 314/// Generic instruction to materialize the address of an object in the constant 315/// pool. 316HANDLE_TARGET_OPCODE(G_CONSTANT_POOL) 317 318/// Generic instruction to extract blocks of bits from the register given 319/// (typically a sub-register COPY after instruction selection). 320HANDLE_TARGET_OPCODE(G_EXTRACT) 321 322HANDLE_TARGET_OPCODE(G_UNMERGE_VALUES) 323 324/// Generic instruction to insert blocks of bits from the registers given into 325/// the source. 326HANDLE_TARGET_OPCODE(G_INSERT) 327 328/// Generic instruction to paste a variable number of components together into a 329/// larger register. 330HANDLE_TARGET_OPCODE(G_MERGE_VALUES) 331 332/// Generic instruction to create a vector value from a number of scalar 333/// components. 334HANDLE_TARGET_OPCODE(G_BUILD_VECTOR) 335 336/// Generic instruction to create a vector value from a number of scalar 337/// components, which have types larger than the result vector elt type. 338HANDLE_TARGET_OPCODE(G_BUILD_VECTOR_TRUNC) 339 340/// Generic instruction to create a vector by concatenating multiple vectors. 341HANDLE_TARGET_OPCODE(G_CONCAT_VECTORS) 342 343/// Generic pointer to int conversion. 344HANDLE_TARGET_OPCODE(G_PTRTOINT) 345 346/// Generic int to pointer conversion. 347HANDLE_TARGET_OPCODE(G_INTTOPTR) 348 349/// Generic bitcast. The source and destination types must be different, or a 350/// COPY is the relevant instruction. 351HANDLE_TARGET_OPCODE(G_BITCAST) 352 353/// Generic freeze. 354HANDLE_TARGET_OPCODE(G_FREEZE) 355 356/// Constant folding barrier. 357HANDLE_TARGET_OPCODE(G_CONSTANT_FOLD_BARRIER) 358 359// INTRINSIC fptrunc_round intrinsic. 360HANDLE_TARGET_OPCODE(G_INTRINSIC_FPTRUNC_ROUND) 361 362/// INTRINSIC trunc intrinsic. 363HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC) 364 365/// INTRINSIC round intrinsic. 366HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND) 367 368/// INTRINSIC round to integer intrinsic. 369HANDLE_TARGET_OPCODE(G_INTRINSIC_LRINT) 370 371/// INTRINSIC long round to integer intrinsic. 372HANDLE_TARGET_OPCODE(G_INTRINSIC_LLRINT) 373 374/// INTRINSIC roundeven intrinsic. 375HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUNDEVEN) 376 377/// INTRINSIC readcyclecounter 378HANDLE_TARGET_OPCODE(G_READCYCLECOUNTER) 379 380/// INTRINSIC readsteadycounter 381HANDLE_TARGET_OPCODE(G_READSTEADYCOUNTER) 382 383/// Generic load (including anyext load) 384HANDLE_TARGET_OPCODE(G_LOAD) 385 386/// Generic signext load 387HANDLE_TARGET_OPCODE(G_SEXTLOAD) 388 389/// Generic zeroext load 390HANDLE_TARGET_OPCODE(G_ZEXTLOAD) 391 392/// Generic indexed load (including anyext load) 393HANDLE_TARGET_OPCODE(G_INDEXED_LOAD) 394 395/// Generic indexed signext load 396HANDLE_TARGET_OPCODE(G_INDEXED_SEXTLOAD) 397 398/// Generic indexed zeroext load 399HANDLE_TARGET_OPCODE(G_INDEXED_ZEXTLOAD) 400 401/// Generic store. 402HANDLE_TARGET_OPCODE(G_STORE) 403 404/// Generic indexed store. 405HANDLE_TARGET_OPCODE(G_INDEXED_STORE) 406 407/// Generic atomic cmpxchg with internal success check. 408HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG_WITH_SUCCESS) 409 410/// Generic atomic cmpxchg. 411HANDLE_TARGET_OPCODE(G_ATOMIC_CMPXCHG) 412 413/// Generic atomicrmw. 414HANDLE_TARGET_OPCODE(G_ATOMICRMW_XCHG) 415HANDLE_TARGET_OPCODE(G_ATOMICRMW_ADD) 416HANDLE_TARGET_OPCODE(G_ATOMICRMW_SUB) 417HANDLE_TARGET_OPCODE(G_ATOMICRMW_AND) 418HANDLE_TARGET_OPCODE(G_ATOMICRMW_NAND) 419HANDLE_TARGET_OPCODE(G_ATOMICRMW_OR) 420HANDLE_TARGET_OPCODE(G_ATOMICRMW_XOR) 421HANDLE_TARGET_OPCODE(G_ATOMICRMW_MAX) 422HANDLE_TARGET_OPCODE(G_ATOMICRMW_MIN) 423HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMAX) 424HANDLE_TARGET_OPCODE(G_ATOMICRMW_UMIN) 425HANDLE_TARGET_OPCODE(G_ATOMICRMW_FADD) 426HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) 427HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) 428HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) 429HANDLE_TARGET_OPCODE(G_ATOMICRMW_UINC_WRAP) 430HANDLE_TARGET_OPCODE(G_ATOMICRMW_UDEC_WRAP) 431HANDLE_TARGET_OPCODE(G_ATOMICRMW_USUB_COND) 432HANDLE_TARGET_OPCODE(G_ATOMICRMW_USUB_SAT) 433 434// Marker for start of Generic AtomicRMW opcodes 435HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG) 436 437// Marker for end of Generic AtomicRMW opcodes 438HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_USUB_SAT) 439 440// Generic atomic fence 441HANDLE_TARGET_OPCODE(G_FENCE) 442 443/// Generic prefetch 444HANDLE_TARGET_OPCODE(G_PREFETCH) 445 446/// Generic conditional branch instruction. 447HANDLE_TARGET_OPCODE(G_BRCOND) 448 449/// Generic indirect branch instruction. 450HANDLE_TARGET_OPCODE(G_BRINDIRECT) 451 452/// Begin an invoke region marker. 453HANDLE_TARGET_OPCODE(G_INVOKE_REGION_START) 454 455/// Generic intrinsic use (without side effects). 456HANDLE_TARGET_OPCODE(G_INTRINSIC) 457 458/// Generic intrinsic use (with side effects). 459HANDLE_TARGET_OPCODE(G_INTRINSIC_W_SIDE_EFFECTS) 460 461/// Generic intrinsic use (without side effects). 462HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT) 463 464/// Generic intrinsic use (with side effects). 465HANDLE_TARGET_OPCODE(G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) 466 467/// Generic extension allowing rubbish in high bits. 468HANDLE_TARGET_OPCODE(G_ANYEXT) 469 470/// Generic instruction to discard the high bits of a register. This differs 471/// from (G_EXTRACT val, 0) on its action on vectors: G_TRUNC will truncate 472/// each element individually, G_EXTRACT will typically discard the high 473/// elements of the vector. 474HANDLE_TARGET_OPCODE(G_TRUNC) 475 476/// Generic integer constant. 477HANDLE_TARGET_OPCODE(G_CONSTANT) 478 479/// Generic floating constant. 480HANDLE_TARGET_OPCODE(G_FCONSTANT) 481 482/// Generic va_start instruction. Stores to its one pointer operand. 483HANDLE_TARGET_OPCODE(G_VASTART) 484 485/// Generic va_arg instruction. Stores to its one pointer operand. 486HANDLE_TARGET_OPCODE(G_VAARG) 487 488// Generic sign extend 489HANDLE_TARGET_OPCODE(G_SEXT) 490HANDLE_TARGET_OPCODE(G_SEXT_INREG) 491 492// Generic zero extend 493HANDLE_TARGET_OPCODE(G_ZEXT) 494 495// Generic left-shift 496HANDLE_TARGET_OPCODE(G_SHL) 497 498// Generic logical right-shift 499HANDLE_TARGET_OPCODE(G_LSHR) 500 501// Generic arithmetic right-shift 502HANDLE_TARGET_OPCODE(G_ASHR) 503 504// Generic funnel left shift 505HANDLE_TARGET_OPCODE(G_FSHL) 506 507// Generic funnel right shift 508HANDLE_TARGET_OPCODE(G_FSHR) 509 510// Generic right rotate 511HANDLE_TARGET_OPCODE(G_ROTR) 512 513// Generic left rotate 514HANDLE_TARGET_OPCODE(G_ROTL) 515 516/// Generic integer-base comparison, also applicable to vectors of integers. 517HANDLE_TARGET_OPCODE(G_ICMP) 518 519/// Generic floating-point comparison, also applicable to vectors. 520HANDLE_TARGET_OPCODE(G_FCMP) 521 522/// Generic signed 3-way comparison. 523HANDLE_TARGET_OPCODE(G_SCMP) 524 525/// Generic unsigned 3-way comparison. 526HANDLE_TARGET_OPCODE(G_UCMP) 527 528/// Generic select. 529HANDLE_TARGET_OPCODE(G_SELECT) 530 531/// Generic unsigned add instruction, consuming the normal operands and 532/// producing the result and a carry flag. 533HANDLE_TARGET_OPCODE(G_UADDO) 534 535/// Generic unsigned add instruction, consuming the normal operands plus a carry 536/// flag, and similarly producing the result and a carry flag. 537HANDLE_TARGET_OPCODE(G_UADDE) 538 539/// Generic unsigned sub instruction, consuming the normal operands and 540/// producing the result and a carry flag. 541HANDLE_TARGET_OPCODE(G_USUBO) 542 543/// Generic unsigned subtract instruction, consuming the normal operands plus a 544/// carry flag, and similarly producing the result and a carry flag. 545HANDLE_TARGET_OPCODE(G_USUBE) 546 547/// Generic signed add instruction, producing the result and a signed overflow 548/// flag. 549HANDLE_TARGET_OPCODE(G_SADDO) 550 551/// Generic signed add instruction, consuming the normal operands plus a carry 552/// flag, and similarly producing the result and a carry flag. 553HANDLE_TARGET_OPCODE(G_SADDE) 554 555/// Generic signed subtract instruction, producing the result and a signed 556/// overflow flag. 557HANDLE_TARGET_OPCODE(G_SSUBO) 558 559/// Generic signed sub instruction, consuming the normal operands plus a carry 560/// flag, and similarly producing the result and a carry flag. 561HANDLE_TARGET_OPCODE(G_SSUBE) 562 563/// Generic unsigned multiply instruction, producing the result and a signed 564/// overflow flag. 565HANDLE_TARGET_OPCODE(G_UMULO) 566 567/// Generic signed multiply instruction, producing the result and a signed 568/// overflow flag. 569HANDLE_TARGET_OPCODE(G_SMULO) 570 571// Multiply two numbers at twice the incoming bit width (unsigned) and return 572// the high half of the result. 573HANDLE_TARGET_OPCODE(G_UMULH) 574 575// Multiply two numbers at twice the incoming bit width (signed) and return 576// the high half of the result. 577HANDLE_TARGET_OPCODE(G_SMULH) 578 579/// Generic saturating unsigned addition. 580HANDLE_TARGET_OPCODE(G_UADDSAT) 581 582/// Generic saturating signed addition. 583HANDLE_TARGET_OPCODE(G_SADDSAT) 584 585/// Generic saturating unsigned subtraction. 586HANDLE_TARGET_OPCODE(G_USUBSAT) 587 588/// Generic saturating signed subtraction. 589HANDLE_TARGET_OPCODE(G_SSUBSAT) 590 591/// Generic saturating unsigned left shift. 592HANDLE_TARGET_OPCODE(G_USHLSAT) 593 594/// Generic saturating signed left shift. 595HANDLE_TARGET_OPCODE(G_SSHLSAT) 596 597// Perform signed fixed point multiplication 598HANDLE_TARGET_OPCODE(G_SMULFIX) 599 600// Perform unsigned fixed point multiplication 601HANDLE_TARGET_OPCODE(G_UMULFIX) 602 603// Perform signed, saturating fixed point multiplication 604HANDLE_TARGET_OPCODE(G_SMULFIXSAT) 605 606// Perform unsigned, saturating fixed point multiplication 607HANDLE_TARGET_OPCODE(G_UMULFIXSAT) 608 609// Perform signed fixed point division 610HANDLE_TARGET_OPCODE(G_SDIVFIX) 611 612// Perform unsigned fixed point division 613HANDLE_TARGET_OPCODE(G_UDIVFIX) 614 615// Perform signed, saturating fixed point division 616HANDLE_TARGET_OPCODE(G_SDIVFIXSAT) 617 618// Perform unsigned, saturating fixed point division 619HANDLE_TARGET_OPCODE(G_UDIVFIXSAT) 620 621/// Generic FP addition. 622HANDLE_TARGET_OPCODE(G_FADD) 623 624/// Generic FP subtraction. 625HANDLE_TARGET_OPCODE(G_FSUB) 626 627/// Generic FP multiplication. 628HANDLE_TARGET_OPCODE(G_FMUL) 629 630/// Generic FMA multiplication. Behaves like llvm fma intrinsic 631HANDLE_TARGET_OPCODE(G_FMA) 632 633/// Generic FP multiply and add. Behaves as separate fmul and fadd. 634HANDLE_TARGET_OPCODE(G_FMAD) 635 636/// Generic FP division. 637HANDLE_TARGET_OPCODE(G_FDIV) 638 639/// Generic FP remainder. 640HANDLE_TARGET_OPCODE(G_FREM) 641 642/// Generic FP exponentiation. 643HANDLE_TARGET_OPCODE(G_FPOW) 644 645/// Generic FP exponentiation, with an integer exponent. 646HANDLE_TARGET_OPCODE(G_FPOWI) 647 648/// Generic base-e exponential of a value. 649HANDLE_TARGET_OPCODE(G_FEXP) 650 651/// Generic base-2 exponential of a value. 652HANDLE_TARGET_OPCODE(G_FEXP2) 653 654/// Generic base-10 exponential of a value. 655HANDLE_TARGET_OPCODE(G_FEXP10) 656 657/// Floating point base-e logarithm of a value. 658HANDLE_TARGET_OPCODE(G_FLOG) 659 660/// Floating point base-2 logarithm of a value. 661HANDLE_TARGET_OPCODE(G_FLOG2) 662 663/// Floating point base-10 logarithm of a value. 664HANDLE_TARGET_OPCODE(G_FLOG10) 665 666/// Floating point x * 2^n 667HANDLE_TARGET_OPCODE(G_FLDEXP) 668 669/// Floating point extract fraction and exponent. 670HANDLE_TARGET_OPCODE(G_FFREXP) 671 672/// Generic FP negation. 673HANDLE_TARGET_OPCODE(G_FNEG) 674 675/// Generic FP extension. 676HANDLE_TARGET_OPCODE(G_FPEXT) 677 678/// Generic float to signed-int conversion 679HANDLE_TARGET_OPCODE(G_FPTRUNC) 680 681/// Generic float to signed-int conversion 682HANDLE_TARGET_OPCODE(G_FPTOSI) 683 684/// Generic float to unsigned-int conversion 685HANDLE_TARGET_OPCODE(G_FPTOUI) 686 687/// Generic signed-int to float conversion 688HANDLE_TARGET_OPCODE(G_SITOFP) 689 690/// Generic unsigned-int to float conversion 691HANDLE_TARGET_OPCODE(G_UITOFP) 692 693/// Generic saturating float to signed-int conversion 694HANDLE_TARGET_OPCODE(G_FPTOSI_SAT) 695 696/// Generic saturating float to unsigned-int conversion 697HANDLE_TARGET_OPCODE(G_FPTOUI_SAT) 698 699/// Generic FP absolute value. 700HANDLE_TARGET_OPCODE(G_FABS) 701 702/// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This does 703/// not require that X and Y have the same type, just that they are both 704/// floating point. X and the result must have the same type. FCOPYSIGN(f32, 705/// f64) is allowed. 706HANDLE_TARGET_OPCODE(G_FCOPYSIGN) 707 708/// Generic test for floating-point class. 709HANDLE_TARGET_OPCODE(G_IS_FPCLASS) 710 711/// Generic FP canonicalize value. 712HANDLE_TARGET_OPCODE(G_FCANONICALIZE) 713 714/// FP min/max matching libm's fmin/fmax 715HANDLE_TARGET_OPCODE(G_FMINNUM) 716HANDLE_TARGET_OPCODE(G_FMAXNUM) 717 718/// FP min/max matching IEEE-754 2008's minnum/maxnum semantics. 719HANDLE_TARGET_OPCODE(G_FMINNUM_IEEE) 720HANDLE_TARGET_OPCODE(G_FMAXNUM_IEEE) 721 722/// FP min/max matching IEEE-754 2018 draft semantics. 723HANDLE_TARGET_OPCODE(G_FMINIMUM) 724HANDLE_TARGET_OPCODE(G_FMAXIMUM) 725 726/// Access to FP environment. 727HANDLE_TARGET_OPCODE(G_GET_FPENV) 728HANDLE_TARGET_OPCODE(G_SET_FPENV) 729HANDLE_TARGET_OPCODE(G_RESET_FPENV) 730HANDLE_TARGET_OPCODE(G_GET_FPMODE) 731HANDLE_TARGET_OPCODE(G_SET_FPMODE) 732HANDLE_TARGET_OPCODE(G_RESET_FPMODE) 733 734/// Generic pointer offset 735HANDLE_TARGET_OPCODE(G_PTR_ADD) 736 737/// Clear the specified bits in a pointer. 738HANDLE_TARGET_OPCODE(G_PTRMASK) 739 740/// Generic signed integer minimum. 741HANDLE_TARGET_OPCODE(G_SMIN) 742 743/// Generic signed integer maximum. 744HANDLE_TARGET_OPCODE(G_SMAX) 745 746/// Generic unsigned integer maximum. 747HANDLE_TARGET_OPCODE(G_UMIN) 748 749/// Generic unsigned integer maximum. 750HANDLE_TARGET_OPCODE(G_UMAX) 751 752/// Generic integer absolute value. 753HANDLE_TARGET_OPCODE(G_ABS) 754 755HANDLE_TARGET_OPCODE(G_LROUND) 756HANDLE_TARGET_OPCODE(G_LLROUND) 757 758/// Generic BRANCH instruction. This is an unconditional branch. 759HANDLE_TARGET_OPCODE(G_BR) 760 761/// Generic branch to jump table entry. 762HANDLE_TARGET_OPCODE(G_BRJT) 763 764/// Generic vscale. 765HANDLE_TARGET_OPCODE(G_VSCALE) 766 767/// Generic insert subvector. 768HANDLE_TARGET_OPCODE(G_INSERT_SUBVECTOR) 769 770/// Generic extract subvector. 771HANDLE_TARGET_OPCODE(G_EXTRACT_SUBVECTOR) 772 773/// Generic insertelement. 774HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT) 775 776/// Generic extractelement. 777HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT) 778 779/// Generic shufflevector. 780HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR) 781 782/// Generic splatvector. 783HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR) 784 785/// Generic stepvector. 786HANDLE_TARGET_OPCODE(G_STEP_VECTOR) 787 788/// Generic masked compress. 789HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS) 790 791/// Generic count trailing zeroes. 792HANDLE_TARGET_OPCODE(G_CTTZ) 793 794/// Same as above, undefined for zero inputs. 795HANDLE_TARGET_OPCODE(G_CTTZ_ZERO_UNDEF) 796 797/// Generic count leading zeroes. 798HANDLE_TARGET_OPCODE(G_CTLZ) 799 800/// Same as above, undefined for zero inputs. 801HANDLE_TARGET_OPCODE(G_CTLZ_ZERO_UNDEF) 802 803/// Generic count bits. 804HANDLE_TARGET_OPCODE(G_CTPOP) 805 806/// Generic byte swap. 807HANDLE_TARGET_OPCODE(G_BSWAP) 808 809/// Generic bit reverse. 810HANDLE_TARGET_OPCODE(G_BITREVERSE) 811 812/// Floating point ceil. 813HANDLE_TARGET_OPCODE(G_FCEIL) 814 815/// Floating point cosine. 816HANDLE_TARGET_OPCODE(G_FCOS) 817 818/// Floating point sine. 819HANDLE_TARGET_OPCODE(G_FSIN) 820 821/// Floating point combined sine and cosine. 822HANDLE_TARGET_OPCODE(G_FSINCOS) 823 824/// Floating point tangent. 825HANDLE_TARGET_OPCODE(G_FTAN) 826 827/// Floating point arccosine. 828HANDLE_TARGET_OPCODE(G_FACOS) 829 830/// Floating point arcsine. 831HANDLE_TARGET_OPCODE(G_FASIN) 832 833/// Floating point arctangent. 834HANDLE_TARGET_OPCODE(G_FATAN) 835 836/// Floating point arctangent of y/x. 837HANDLE_TARGET_OPCODE(G_FATAN2) 838 839/// Floating point hyperbolic cosine. 840HANDLE_TARGET_OPCODE(G_FCOSH) 841 842/// Floating point hyperbolic sine. 843HANDLE_TARGET_OPCODE(G_FSINH) 844 845/// Floating point hyperbolic tangent. 846HANDLE_TARGET_OPCODE(G_FTANH) 847 848/// Floating point square root. 849HANDLE_TARGET_OPCODE(G_FSQRT) 850 851/// Floating point floor. 852HANDLE_TARGET_OPCODE(G_FFLOOR) 853 854/// Floating point round to next integer. 855HANDLE_TARGET_OPCODE(G_FRINT) 856 857/// Floating point round to nearest integer. 858HANDLE_TARGET_OPCODE(G_FNEARBYINT) 859 860/// Generic AddressSpaceCast. 861HANDLE_TARGET_OPCODE(G_ADDRSPACE_CAST) 862 863/// Generic block address 864HANDLE_TARGET_OPCODE(G_BLOCK_ADDR) 865 866/// Generic jump table address 867HANDLE_TARGET_OPCODE(G_JUMP_TABLE) 868 869/// Generic dynamic stack allocation. 870HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC) 871 872/// Generic stack pointer save. 873HANDLE_TARGET_OPCODE(G_STACKSAVE) 874 875/// Generic stack pointer restore. 876HANDLE_TARGET_OPCODE(G_STACKRESTORE) 877 878/// Strict floating point instructions. 879HANDLE_TARGET_OPCODE(G_STRICT_FADD) 880HANDLE_TARGET_OPCODE(G_STRICT_FSUB) 881HANDLE_TARGET_OPCODE(G_STRICT_FMUL) 882HANDLE_TARGET_OPCODE(G_STRICT_FDIV) 883HANDLE_TARGET_OPCODE(G_STRICT_FREM) 884HANDLE_TARGET_OPCODE(G_STRICT_FMA) 885HANDLE_TARGET_OPCODE(G_STRICT_FSQRT) 886HANDLE_TARGET_OPCODE(G_STRICT_FLDEXP) 887 888/// read_register intrinsic 889HANDLE_TARGET_OPCODE(G_READ_REGISTER) 890 891/// write_register intrinsic 892HANDLE_TARGET_OPCODE(G_WRITE_REGISTER) 893 894/// llvm.memcpy intrinsic 895HANDLE_TARGET_OPCODE(G_MEMCPY) 896 897/// llvm.memcpy.inline intrinsic 898HANDLE_TARGET_OPCODE(G_MEMCPY_INLINE) 899 900/// llvm.memmove intrinsic 901HANDLE_TARGET_OPCODE(G_MEMMOVE) 902 903/// llvm.memset intrinsic 904HANDLE_TARGET_OPCODE(G_MEMSET) 905HANDLE_TARGET_OPCODE(G_BZERO) 906 907/// llvm.trap, llvm.debugtrap and llvm.ubsantrap intrinsics 908HANDLE_TARGET_OPCODE(G_TRAP) 909HANDLE_TARGET_OPCODE(G_DEBUGTRAP) 910HANDLE_TARGET_OPCODE(G_UBSANTRAP) 911 912/// Vector reductions 913HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FADD) 914HANDLE_TARGET_OPCODE(G_VECREDUCE_SEQ_FMUL) 915HANDLE_TARGET_OPCODE(G_VECREDUCE_FADD) 916HANDLE_TARGET_OPCODE(G_VECREDUCE_FMUL) 917HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAX) 918HANDLE_TARGET_OPCODE(G_VECREDUCE_FMIN) 919HANDLE_TARGET_OPCODE(G_VECREDUCE_FMAXIMUM) 920HANDLE_TARGET_OPCODE(G_VECREDUCE_FMINIMUM) 921HANDLE_TARGET_OPCODE(G_VECREDUCE_ADD) 922HANDLE_TARGET_OPCODE(G_VECREDUCE_MUL) 923HANDLE_TARGET_OPCODE(G_VECREDUCE_AND) 924HANDLE_TARGET_OPCODE(G_VECREDUCE_OR) 925HANDLE_TARGET_OPCODE(G_VECREDUCE_XOR) 926HANDLE_TARGET_OPCODE(G_VECREDUCE_SMAX) 927HANDLE_TARGET_OPCODE(G_VECREDUCE_SMIN) 928HANDLE_TARGET_OPCODE(G_VECREDUCE_UMAX) 929HANDLE_TARGET_OPCODE(G_VECREDUCE_UMIN) 930 931HANDLE_TARGET_OPCODE(G_SBFX) 932HANDLE_TARGET_OPCODE(G_UBFX) 933 934/// Marker for the end of the generic opcode. 935/// This is used to check if an opcode is in the range of the 936/// generic opcodes. 937HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_UBFX) 938 939/// BUILTIN_OP_END - This must be the last enum value in this list. 940/// The target-specific post-isel opcode values start here. 941HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END) 942