1 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise AArch64 hardware features 10 // such as FPU/CPU/ARCH and extension names. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_SUPPORT_AARCH64TARGETPARSER_H 15 #define LLVM_SUPPORT_AARCH64TARGETPARSER_H 16 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/Support/ARMTargetParser.h" 20 #include <vector> 21 22 // FIXME:This should be made into class design,to avoid dupplication. 23 namespace llvm { 24 25 class Triple; 26 27 namespace AArch64 { 28 29 // Arch extension modifiers for CPUs. 30 enum ArchExtKind : uint64_t { 31 AEK_INVALID = 0, 32 AEK_NONE = 1, 33 AEK_CRC = 1 << 1, 34 AEK_CRYPTO = 1 << 2, 35 AEK_FP = 1 << 3, 36 AEK_SIMD = 1 << 4, 37 AEK_FP16 = 1 << 5, 38 AEK_PROFILE = 1 << 6, 39 AEK_RAS = 1 << 7, 40 AEK_LSE = 1 << 8, 41 AEK_SVE = 1 << 9, 42 AEK_DOTPROD = 1 << 10, 43 AEK_RCPC = 1 << 11, 44 AEK_RDM = 1 << 12, 45 AEK_SM4 = 1 << 13, 46 AEK_SHA3 = 1 << 14, 47 AEK_SHA2 = 1 << 15, 48 AEK_AES = 1 << 16, 49 AEK_FP16FML = 1 << 17, 50 AEK_RAND = 1 << 18, 51 AEK_MTE = 1 << 19, 52 AEK_SSBS = 1 << 20, 53 AEK_SB = 1 << 21, 54 AEK_PREDRES = 1 << 22, 55 AEK_SVE2 = 1 << 23, 56 AEK_SVE2AES = 1 << 24, 57 AEK_SVE2SM4 = 1 << 25, 58 AEK_SVE2SHA3 = 1 << 26, 59 AEK_SVE2BITPERM = 1 << 27, 60 AEK_TME = 1 << 28, 61 AEK_BF16 = 1 << 29, 62 AEK_I8MM = 1 << 30, 63 AEK_F32MM = 1ULL << 31, 64 AEK_F64MM = 1ULL << 32, 65 AEK_LS64 = 1ULL << 33, 66 AEK_BRBE = 1ULL << 34, 67 AEK_PAUTH = 1ULL << 35, 68 AEK_FLAGM = 1ULL << 36, 69 }; 70 71 enum class ArchKind { 72 #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID, 73 #include "AArch64TargetParser.def" 74 }; 75 76 const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = { 77 #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, \ 78 ARCH_BASE_EXT) \ 79 {NAME, \ 80 sizeof(NAME) - 1, \ 81 CPU_ATTR, \ 82 sizeof(CPU_ATTR) - 1, \ 83 SUB_ARCH, \ 84 sizeof(SUB_ARCH) - 1, \ 85 ARM::FPUKind::ARCH_FPU, \ 86 ARCH_BASE_EXT, \ 87 AArch64::ArchKind::ID, \ 88 ARCH_ATTR}, 89 #include "AArch64TargetParser.def" 90 }; 91 92 const ARM::ExtName AArch64ARCHExtNames[] = { 93 #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \ 94 {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE}, 95 #include "AArch64TargetParser.def" 96 }; 97 98 const ARM::CpuNames<ArchKind> AArch64CPUNames[] = { 99 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ 100 {NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT}, 101 #include "AArch64TargetParser.def" 102 }; 103 104 const ArchKind ArchKinds[] = { 105 #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \ 106 ArchKind::ID, 107 #include "AArch64TargetParser.def" 108 }; 109 110 // FIXME: These should be moved to TargetTuple once it exists 111 bool getExtensionFeatures(uint64_t Extensions, 112 std::vector<StringRef> &Features); 113 bool getArchFeatures(ArchKind AK, std::vector<StringRef> &Features); 114 115 StringRef getArchName(ArchKind AK); 116 unsigned getArchAttr(ArchKind AK); 117 StringRef getCPUAttr(ArchKind AK); 118 StringRef getSubArch(ArchKind AK); 119 StringRef getArchExtName(unsigned ArchExtKind); 120 StringRef getArchExtFeature(StringRef ArchExt); 121 122 // Information by Name 123 unsigned getDefaultFPU(StringRef CPU, ArchKind AK); 124 uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK); 125 StringRef getDefaultCPU(StringRef Arch); 126 ArchKind getCPUArchKind(StringRef CPU); 127 128 // Parser 129 ArchKind parseArch(StringRef Arch); 130 ArchExtKind parseArchExt(StringRef ArchExt); 131 ArchKind parseCPUArch(StringRef CPU); 132 // Used by target parser tests 133 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values); 134 135 bool isX18ReservedByDefault(const Triple &TT); 136 137 struct ParsedBranchProtection { 138 StringRef Scope; 139 StringRef Key; 140 bool BranchTargetEnforcement; 141 }; 142 143 bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, 144 StringRef &Err); 145 146 } // namespace AArch64 147 } // namespace llvm 148 149 #endif 150