xref: /llvm-project/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td (revision 00128a20eec27246719d73ba427bf821883b00b4) 
1//===- IntrinsicsRISCVXCV.td - CORE-V intrinsics -----------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines all of the CORE-V vendor intrinsics for RISC-V.
10//
11//===----------------------------------------------------------------------===//
12
13class ScalarCoreVBitManipGprGprIntrinsic
14    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
15                            [IntrNoMem, IntrSpeculatable]>;
16
17class ScalarCoreVBitManipGprIntrinsic
18    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
19                            [IntrNoMem, IntrSpeculatable]>;
20
21class ScalarCoreVAluGprIntrinsic
22  : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
23                          [IntrNoMem, IntrSpeculatable]>;
24
25class ScalarCoreVAluGprGprIntrinsic
26  : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
27                          [IntrNoMem, IntrSpeculatable]>;
28
29class ScalarCoreVAluGprGprGprIntrinsic
30  : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
31                          [IntrNoMem, IntrSpeculatable]>;
32
33class ScalarCoreVMacGprGprGprIntrinsic
34  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
35              [IntrNoMem, IntrWillReturn, IntrSpeculatable]>;
36
37class ScalarCoreVMacGprGPRImmIntrinsic
38    : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
39                [IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;
40
41class ScalarCoreVMacGprGprGprImmIntrinsic
42  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
43              [IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<3>>]>;
44
45let TargetPrefix = "riscv" in {
46  def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic;
47  def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic;
48  def int_riscv_cv_bitmanip_bclr : ScalarCoreVBitManipGprGprIntrinsic;
49  def int_riscv_cv_bitmanip_bset : ScalarCoreVBitManipGprGprIntrinsic;
50
51  def int_riscv_cv_bitmanip_insert
52    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
53                            [IntrNoMem, IntrSpeculatable]>;
54
55  def int_riscv_cv_bitmanip_clb : ScalarCoreVBitManipGprIntrinsic;
56
57  def int_riscv_cv_bitmanip_bitrev
58    : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
59                            [IntrNoMem, IntrWillReturn, IntrSpeculatable,
60                            ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
61
62  def int_riscv_cv_alu_clip   : ScalarCoreVAluGprGprIntrinsic;
63  def int_riscv_cv_alu_clipu  : ScalarCoreVAluGprGprIntrinsic;
64  def int_riscv_cv_alu_addN   : ScalarCoreVAluGprGprGprIntrinsic;
65  def int_riscv_cv_alu_adduN  : ScalarCoreVAluGprGprGprIntrinsic;
66  def int_riscv_cv_alu_addRN  : ScalarCoreVAluGprGprGprIntrinsic;
67  def int_riscv_cv_alu_adduRN : ScalarCoreVAluGprGprGprIntrinsic;
68  def int_riscv_cv_alu_subN   : ScalarCoreVAluGprGprGprIntrinsic;
69  def int_riscv_cv_alu_subuN  : ScalarCoreVAluGprGprGprIntrinsic;
70  def int_riscv_cv_alu_subRN  : ScalarCoreVAluGprGprGprIntrinsic;
71  def int_riscv_cv_alu_subuRN : ScalarCoreVAluGprGprGprIntrinsic;
72
73  def int_riscv_cv_mac_mac : ScalarCoreVMacGprGprGprIntrinsic;
74  def int_riscv_cv_mac_msu : ScalarCoreVMacGprGprGprIntrinsic;
75
76  def int_riscv_cv_mac_muluN    : ScalarCoreVMacGprGPRImmIntrinsic;
77  def int_riscv_cv_mac_mulhhuN  : ScalarCoreVMacGprGPRImmIntrinsic;
78  def int_riscv_cv_mac_mulsN    : ScalarCoreVMacGprGPRImmIntrinsic;
79  def int_riscv_cv_mac_mulhhsN  : ScalarCoreVMacGprGPRImmIntrinsic;
80  def int_riscv_cv_mac_muluRN   : ScalarCoreVMacGprGPRImmIntrinsic;
81  def int_riscv_cv_mac_mulhhuRN : ScalarCoreVMacGprGPRImmIntrinsic;
82  def int_riscv_cv_mac_mulsRN   : ScalarCoreVMacGprGPRImmIntrinsic;
83  def int_riscv_cv_mac_mulhhsRN : ScalarCoreVMacGprGPRImmIntrinsic;
84
85  def int_riscv_cv_mac_macuN    : ScalarCoreVMacGprGprGprImmIntrinsic;
86  def int_riscv_cv_mac_machhuN  : ScalarCoreVMacGprGprGprImmIntrinsic;
87  def int_riscv_cv_mac_macsN    : ScalarCoreVMacGprGprGprImmIntrinsic;
88  def int_riscv_cv_mac_machhsN  : ScalarCoreVMacGprGprGprImmIntrinsic;
89  def int_riscv_cv_mac_macuRN   : ScalarCoreVMacGprGprGprImmIntrinsic;
90  def int_riscv_cv_mac_machhuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
91  def int_riscv_cv_mac_macsRN   : ScalarCoreVMacGprGprGprImmIntrinsic;
92  def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
93} // TargetPrefix = "riscv"
94