1 /* $NetBSD: ixgbe_osdep.h,v 1.31 2021/12/24 05:02:11 msaitoh Exp $ */
2
3 /******************************************************************************
4 SPDX-License-Identifier: BSD-3-Clause
5
6 Copyright (c) 2001-2020, Intel Corporation
7 All rights reserved.
8
9 Redistribution and use in source and binary forms, with or without
10 modification, are permitted provided that the following conditions are met:
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12 1. Redistributions of source code must retain the above copyright notice,
13 this list of conditions and the following disclaimer.
14
15 2. Redistributions in binary form must reproduce the above copyright
16 notice, this list of conditions and the following disclaimer in the
17 documentation and/or other materials provided with the distribution.
18
19 3. Neither the name of the Intel Corporation nor the names of its
20 contributors may be used to endorse or promote products derived from
21 this software without specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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33 POSSIBILITY OF SUCH DAMAGE.
34
35 ******************************************************************************/
36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.h 327031 2017-12-20 18:15:06Z erj $*/
37
38 #ifndef _IXGBE_OSDEP_H_
39 #define _IXGBE_OSDEP_H_
40
41 #include <sys/types.h>
42 #include <sys/param.h>
43 #include <sys/endian.h>
44 #include <sys/systm.h>
45 #include <sys/mbuf.h>
46 #include <sys/protosw.h>
47 #include <sys/socket.h>
48 #include <sys/malloc.h>
49 #include <sys/kernel.h>
50 #include <sys/cprng.h>
51 #include <sys/bus.h>
52 #include <dev/pci/pcivar.h>
53 #include <dev/pci/pcireg.h>
54 #include <net/if.h>
55 #include <net/if_ether.h>
56
57 #define ASSERT(x) if (!(x)) panic("IXGBE: x")
58 #define EWARN(H, W) printf(W)
59
60 enum {
61 IXGBE_ERROR_SOFTWARE,
62 IXGBE_ERROR_POLLING,
63 IXGBE_ERROR_INVALID_STATE,
64 IXGBE_ERROR_UNSUPPORTED,
65 IXGBE_ERROR_ARGUMENT,
66 IXGBE_ERROR_CAUTION,
67 };
68
69 #define usec_delay(x) ixgbe_delay(x)
70 #define msec_delay(x) ixgbe_delay((x) * 1000)
71 void ixgbe_delay(unsigned int);
72
73 #define DBG 0
74 #define MSGOUT(S, A, B) printf(S "\n", A, B)
75 #define DEBUGFUNC(F) DEBUGOUT(F);
76 #if DBG
77 #define DEBUGOUT(S) printf(S "\n")
78 #define DEBUGOUT1(S,A) printf(S "\n",A)
79 #define DEBUGOUT2(S,A,B) printf(S "\n",A,B)
80 #define DEBUGOUT3(S,A,B,C) printf(S "\n",A,B,C)
81 #define DEBUGOUT4(S,A,B,C,D) printf(S "\n",A,B,C,D)
82 #define DEBUGOUT5(S,A,B,C,D,E) printf(S "\n",A,B,C,D,E)
83 #define DEBUGOUT6(S,A,B,C,D,E,F) printf(S "\n",A,B,C,D,E,F)
84 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S "\n",A,B,C,D,E,F,G)
85 #define ERROR_REPORT1 ERROR_REPORT
86 #define ERROR_REPORT2 ERROR_REPORT
87 #define ERROR_REPORT3 ERROR_REPORT
88 #define ERROR_REPORT(level, format, arg...) do { \
89 switch (level) { \
90 case IXGBE_ERROR_SOFTWARE: \
91 case IXGBE_ERROR_CAUTION: \
92 case IXGBE_ERROR_POLLING: \
93 case IXGBE_ERROR_INVALID_STATE: \
94 case IXGBE_ERROR_UNSUPPORTED: \
95 case IXGBE_ERROR_ARGUMENT: \
96 device_printf(ixgbe_dev_from_hw(hw), format, ## arg); \
97 break; \
98 default: \
99 break; \
100 } \
101 } while (0)
102 #else
103 #define DEBUGOUT(S) do { } while (/*CONSTCOND*/false)
104 #define DEBUGOUT1(S,A) do { } while (/*CONSTCOND*/false)
105 #define DEBUGOUT2(S,A,B) do { } while (/*CONSTCOND*/false)
106 #define DEBUGOUT3(S,A,B,C) do { } while (/*CONSTCOND*/false)
107 #define DEBUGOUT4(S,A,B,C,D) do { } while (/*CONSTCOND*/false)
108 #define DEBUGOUT5(S,A,B,C,D,E) do { } while (/*CONSTCOND*/false)
109 #define DEBUGOUT6(S,A,B,C,D,E,F) \
110 do { } while (/*CONSTCOND*/false)
111 #define DEBUGOUT7(S,A,B,C,D,E,F,G) \
112 do { } while (/*CONSTCOND*/false)
113 #define ERROR_REPORT1(S,A) do { } while (/*CONSTCOND*/false)
114 #define ERROR_REPORT2(S,A,B) do { } while (/*CONSTCOND*/false)
115 #define ERROR_REPORT3(S,A,B,C) do { } while (/*CONSTCOND*/false)
116 #endif
117
118 #define FALSE 0
119 #define false 0 /* shared code requires this */
120 #define TRUE 1
121 #define true 1
122 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
123 #define PCI_COMMAND_REGISTER PCIR_COMMAND
124
125 /* Shared code dropped this define.. */
126 #define IXGBE_INTEL_VENDOR_ID 0x8086
127
128 /* Bunch of defines for shared code bogosity */
129 #define UNREFERENCED_PARAMETER(_p)
130 #define UNREFERENCED_1PARAMETER(_p)
131 #define UNREFERENCED_2PARAMETER(_p, _q)
132 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
133 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
134
135 #define IXGBE_NTOHL(_i) ntohl(_i)
136 #define IXGBE_NTOHS(_i) ntohs(_i)
137
138 /* XXX these need to be revisited */
139 #define IXGBE_CPU_TO_LE16 htole16
140 #define IXGBE_CPU_TO_LE32 htole32
141 #define IXGBE_LE32_TO_CPU le32toh
142 #define IXGBE_LE32_TO_CPUS(x) (*(x) = le32toh(*(x)))
143 #define IXGBE_CPU_TO_BE16 htobe16
144 #define IXGBE_CPU_TO_BE32 htobe32
145 #define IXGBE_BE32_TO_CPU be32toh
146
147 typedef uint8_t u8;
148 typedef int8_t s8;
149 typedef uint16_t u16;
150 typedef int16_t s16;
151 typedef uint32_t u32;
152 typedef int32_t s32;
153 typedef uint64_t u64;
154
155 #define le16_to_cpu
156
157 /* This device driver's max interrupt numbers. */
158 #define IXG_MAX_NINTR 64
159
160 #if defined(__i386__) || defined(__amd64__)
161 static __inline
prefetch(void * x)162 void prefetch(void *x)
163 {
164 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
165 }
166 #else
167 #define prefetch(x)
168 #endif
169
170 struct ixgbe_osdep
171 {
172 struct ethercom ec;
173 pci_chipset_tag_t pc;
174 pcitag_t tag;
175 bus_space_tag_t mem_bus_space_tag;
176 bus_space_handle_t mem_bus_space_handle;
177 bus_size_t mem_size;
178 bus_dma_tag_t dmat;
179 pci_intr_handle_t *intrs;
180 int nintrs;
181 void *ihs[IXG_MAX_NINTR];
182 bool attached;
183 bool detaching;
184 };
185
186 /* These routines need struct ixgbe_hw declared */
187 struct ixgbe_hw;
188 device_t ixgbe_dev_from_hw(struct ixgbe_hw *hw);
189
190 /* These routines are needed by the shared code */
191 extern u16 ixgbe_read_pci_cfg(struct ixgbe_hw *, u32);
192 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
193
194 extern void ixgbe_write_pci_cfg(struct ixgbe_hw *, u32, u16);
195 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg
196
197 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
198
199 extern u32 ixgbe_read_reg(struct ixgbe_hw *, u32);
200 #define IXGBE_READ_REG(a, reg) ixgbe_read_reg(a, reg)
201
202 extern void ixgbe_write_reg(struct ixgbe_hw *, u32, u32);
203 #define IXGBE_WRITE_REG(a, reg, val) ixgbe_write_reg(a, reg, val)
204
205 extern u32 ixgbe_read_reg_array(struct ixgbe_hw *, u32, u32);
206 #define IXGBE_READ_REG_ARRAY(a, reg, offset) \
207 ixgbe_read_reg_array(a, reg, offset)
208
209 extern void ixgbe_write_reg_array(struct ixgbe_hw *, u32, u32, u32);
210 #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, val) \
211 ixgbe_write_reg_array(a, reg, offset, val)
212
213 extern void ixgbe_write_barrier(struct ixgbe_hw *);
214 #define IXGBE_WRITE_BARRIER(a) \
215 ixgbe_write_barrier(a)
216
217 #endif /* _IXGBE_OSDEP_H_ */
218