1# Intel(r) Wireless MMX(tm) technology testcase for WMUL 2# mach: xscale 3# as: -mcpu=xscale+iwmmxt 4 5 .include "testutils.inc" 6 7 start 8 9 .global wmul 10wmul: 11 # Enable access to CoProcessors 0 & 1 before 12 # we attempt these instructions. 13 14 mvi_h_gr r1, 3 15 mcr p15, 0, r1, cr15, cr1, 0 16 17 # Test Unsigned, Most Significant Multiply 18 19 mvi_h_gr r0, 0x12345678 20 mvi_h_gr r1, 0x9abcdef0 21 mvi_h_gr r2, 0x11111111 22 mvi_h_gr r3, 0x22222222 23 mvi_h_gr r4, 0 24 mvi_h_gr r5, 0 25 26 tmcrr wr0, r0, r1 27 tmcrr wr1, r2, r3 28 tmcrr wr2, r4, r5 29 30 wmulum wr2, wr0, wr1 31 32 tmrrc r0, r1, wr0 33 tmrrc r2, r3, wr1 34 tmrrc r4, r5, wr2 35 36 test_h_gr r0, 0x12345678 37 test_h_gr r1, 0x9abcdef0 38 test_h_gr r2, 0x11111111 39 test_h_gr r3, 0x22222222 40 test_h_gr r4, 0x013605c3 41 test_h_gr r5, 0x14a11db9 42 43 # Test Unsigned, Least Significant Multiply 44 45 mvi_h_gr r0, 0x12345678 46 mvi_h_gr r1, 0x9abcdef0 47 mvi_h_gr r2, 0x11111111 48 mvi_h_gr r3, 0x22222222 49 mvi_h_gr r4, 0 50 mvi_h_gr r5, 0 51 52 tmcrr wr0, r0, r1 53 tmcrr wr1, r2, r3 54 tmcrr wr2, r4, r5 55 56 wmulul wr2, wr0, wr1 57 58 tmrrc r0, r1, wr0 59 tmrrc r2, r3, wr1 60 tmrrc r4, r5, wr2 61 62 test_h_gr r0, 0x12345678 63 test_h_gr r1, 0x9abcdef0 64 test_h_gr r2, 0x11111111 65 test_h_gr r3, 0x22222222 66 test_h_gr r4, 0xa974b5f8 67 test_h_gr r5, 0x84f87be0 68 69 # Test Signed, Most Significant Multiply 70 71 mvi_h_gr r0, 0x12345678 72 mvi_h_gr r1, 0x9abcdef0 73 mvi_h_gr r2, 0x11111111 74 mvi_h_gr r3, 0x22222222 75 mvi_h_gr r4, 0 76 mvi_h_gr r5, 0 77 78 tmcrr wr0, r0, r1 79 tmcrr wr1, r2, r3 80 tmcrr wr2, r4, r5 81 82 wmulsm wr2, wr0, wr1 83 84 tmrrc r0, r1, wr0 85 tmrrc r2, r3, wr1 86 tmrrc r4, r5, wr2 87 88 test_h_gr r0, 0x12345678 89 test_h_gr r1, 0x9abcdef0 90 test_h_gr r2, 0x11111111 91 test_h_gr r3, 0x22222222 92 test_h_gr r4, 0x013605c3 93 test_h_gr r5, 0xf27ffb97 94 95 # Test Signed, Least Significant Multiply 96 97 mvi_h_gr r0, 0x12345678 98 mvi_h_gr r1, 0x9abcdef0 99 mvi_h_gr r2, 0x11111111 100 mvi_h_gr r3, 0x22222222 101 mvi_h_gr r4, 0 102 mvi_h_gr r5, 0 103 104 tmcrr wr0, r0, r1 105 tmcrr wr1, r2, r3 106 tmcrr wr2, r4, r5 107 108 wmulsl wr2, wr0, wr1 109 110 tmrrc r0, r1, wr0 111 tmrrc r2, r3, wr1 112 tmrrc r4, r5, wr2 113 114 test_h_gr r0, 0x12345678 115 test_h_gr r1, 0x9abcdef0 116 test_h_gr r2, 0x11111111 117 test_h_gr r3, 0x22222222 118 test_h_gr r4, 0xa974b5f8 119 test_h_gr r5, 0x84f87be0 120 121 pass 122