1 /* $NetBSD: irqsrcs_sdma1_5_0.h,v 1.2 2021/12/18 23:45:25 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #ifndef __IRQSRCS_SDMA1_5_0_H__ 25 #define __IRQSRCS_SDMA1_5_0_H__ 26 27 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete 28 #define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout 29 #define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt 30 #define SDMA1_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error 31 #define SDMA1_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3 32 #define SDMA1_5_0__SRCID__SDMA_PAGE_NULL 222 // 0xDE Page Null from UTCL2 when nack=2 33 #define SDMA1_5_0__SRCID__SDMA_XNACK 223 // 0xDF Page retry timeout after UTCL2 return nack=1 34 #define SDMA1_5_0__SRCID__SDMA_TRAP 224 // 0xE0 Trap 35 #define SDMA1_5_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 225 // 0xE1 0xDAGPF (Sem incomplete timeout) 36 #define SDMA1_5_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 226 // 0xE2 Semaphore wait fail timeout 37 #define SDMA1_5_0__SRCID__SDMA_SRAM_ECC 228 // 0xE4 SRAM ECC Error 38 #define SDMA1_5_0__SRCID__SDMA_PREEMPT 240 // 0xF0 SDMA New Run List 39 #define SDMA1_5_0__SRCID__SDMA_VM_HOLE 242 // 0xF2 MC or SEM address in VM hole 40 #define SDMA1_5_0__SRCID__SDMA_CTXEMPTY 243 // 0xF3 Context Empty 41 #define SDMA1_5_0__SRCID__SDMA_DOORBELL_INVALID 244 // 0xF4 Doorbell BE invalid 42 #define SDMA1_5_0__SRCID__SDMA_FROZEN 245 // 0xF5 SDMA Frozen 43 #define SDMA1_5_0__SRCID__SDMA_POLL_TIMEOUT 246 // 0xF6 SRBM read poll timeout 44 #define SDMA1_5_0__SRCID__SDMA_SRBMWRITE 247 // 0xF7 SRBM write Protection 45 46 #endif 47