1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2022 Advanced Micro Devices, Inc.
3 */
4
5 #ifndef _IONIC_DEV_H_
6 #define _IONIC_DEV_H_
7
8 #include <stdbool.h>
9
10 #include "ionic_common.h"
11 #include "ionic_if.h"
12 #include "ionic_regs.h"
13
14 #define VLAN_TAG_SIZE 4
15
16 #define IONIC_MIN_MTU RTE_ETHER_MIN_MTU
17 #define IONIC_MAX_MTU 9750
18 #define IONIC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE)
19
20 #define IONIC_MAX_RING_DESC 32768
21 #define IONIC_MIN_RING_DESC 16
22 #define IONIC_DEF_TXRX_DESC 4096
23 #define IONIC_DEF_TXRX_BURST 32
24
25 struct ionic_adapter;
26
ionic_struct_size_checks(void)27 static inline void ionic_struct_size_checks(void)
28 {
29 RTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8);
30 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr) != 32);
31 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr_status) != 8);
32
33 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_regs) != 4096);
34 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_info_regs) != 2048);
35 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_cmd_regs) != 2048);
36
37 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_stats) != 1024);
38
39 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_cmd) != 64);
40 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_comp) != 16);
41 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_cmd) != 64);
42 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_comp) != 16);
43
44 /* Device commands */
45 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_cmd) != 64);
46 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_comp) != 16);
47 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_cmd) != 64);
48 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_comp) != 16);
49 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_cmd) != 64);
50 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_comp) != 16);
51 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_cmd) != 64);
52 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_comp) != 16);
53 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_cmd) != 64);
54 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_comp) != 16);
55
56 /* Port commands */
57 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_cmd) != 64);
58 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_comp) != 16);
59 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_cmd) != 64);
60 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_comp) != 16);
61 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_cmd) != 64);
62 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_comp) != 16);
63 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_cmd) != 64);
64 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_comp) != 16);
65 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_cmd) != 64);
66 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_comp) != 16);
67
68 /* LIF commands */
69 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_cmd) != 64);
70 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_comp) != 16);
71 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_reset_cmd) != 64);
72 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_cmd) != 64);
73 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_comp) != 16);
74 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_cmd) != 64);
75 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_comp) != 16);
76
77 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_cmd) != 64);
78 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_comp) != 16);
79 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_control_cmd) != 64);
80
81 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_mode_set_cmd) != 64);
82 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_cmd) != 64);
83 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_comp) != 16);
84
85 /* RDMA commands */
86 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_reset_cmd) != 64);
87 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_queue_cmd) != 64);
88
89 /* Events */
90 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_cmd) != 4);
91 RTE_BUILD_BUG_ON(sizeof(union ionic_notifyq_comp) != 64);
92 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_event) != 64);
93 RTE_BUILD_BUG_ON(sizeof(struct ionic_link_change_event) != 64);
94 RTE_BUILD_BUG_ON(sizeof(struct ionic_reset_event) != 64);
95 RTE_BUILD_BUG_ON(sizeof(struct ionic_heartbeat_event) != 64);
96 RTE_BUILD_BUG_ON(sizeof(struct ionic_log_event) != 64);
97
98 /* I/O */
99 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_desc) != 16);
100 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc_v1) != 256);
101 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_comp) != 16);
102
103 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_desc) != 16);
104 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_sg_desc) != 128);
105 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_comp) != 16);
106 }
107
108 struct ionic_dev {
109 union ionic_dev_info_regs __iomem *dev_info;
110 union ionic_dev_cmd_regs __iomem *dev_cmd;
111
112 struct ionic_doorbell __iomem *db_pages;
113 struct ionic_intr __iomem *intr_ctrl;
114 struct ionic_intr_status __iomem *intr_status;
115
116 struct ionic_port_info *port_info;
117 const struct rte_memzone *port_info_z;
118 rte_iova_t port_info_pa;
119 uint32_t port_info_sz;
120 };
121
122 #define Q_NEXT_TO_POST(_q, _n) (((_q)->head_idx + (_n)) & ((_q)->size_mask))
123 #define Q_NEXT_TO_SRVC(_q, _n) (((_q)->tail_idx + (_n)) & ((_q)->size_mask))
124
125 #define IONIC_INFO_IDX(_q, _i) ((_i) * (_q)->num_segs)
126 #define IONIC_INFO_PTR(_q, _i) (&(_q)->info[IONIC_INFO_IDX((_q), _i)])
127
128 struct ionic_queue {
129 uint16_t num_descs;
130 uint16_t num_segs;
131 uint16_t head_idx;
132 uint16_t cmb_head_idx;
133 uint16_t tail_idx;
134 uint16_t size_mask;
135 uint8_t type;
136 uint8_t hw_type;
137 void *base;
138 void *cmb_base;
139 void *sg_base;
140 struct ionic_doorbell __iomem *db;
141 void **info;
142
143 uint32_t index;
144 uint32_t hw_index;
145 rte_iova_t base_pa;
146 rte_iova_t sg_base_pa;
147 rte_iova_t cmb_base_pa;
148 };
149
150 struct ionic_cq {
151 uint16_t tail_idx;
152 uint16_t num_descs;
153 uint16_t size_mask;
154 bool done_color;
155 void *base;
156 rte_iova_t base_pa;
157 };
158
159 struct ionic_lif;
160 struct ionic_adapter;
161 struct ionic_qcq;
162 struct rte_mempool;
163 struct rte_eth_dev;
164 struct rte_devargs;
165
166 struct ionic_dev_intf {
167 int (*setup)(struct ionic_adapter *adapter);
168 int (*devargs)(struct ionic_adapter *adapter,
169 struct rte_devargs *devargs);
170 void (*copy_bus_info)(struct ionic_adapter *adapter,
171 struct rte_eth_dev *eth_dev);
172 int (*configure_intr)(struct ionic_adapter *adapter);
173 void (*unconfigure_intr)(struct ionic_adapter *adapter);
174 void (*poll)(struct ionic_adapter *adapter);
175 void (*unmap_bars)(struct ionic_adapter *adapter);
176 };
177
178 void ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
179 unsigned long index);
180
181 const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode);
182
183 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
184 uint8_t ionic_dev_cmd_status(struct ionic_dev *idev);
185 bool ionic_dev_cmd_done(struct ionic_dev *idev);
186 void ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem);
187
188 void ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver);
189 void ionic_dev_cmd_init(struct ionic_dev *idev);
190 void ionic_dev_cmd_reset(struct ionic_dev *idev);
191
192 void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
193 void ionic_dev_cmd_port_init(struct ionic_dev *idev);
194 void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
195 void ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state);
196 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed);
197 void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu);
198 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable);
199 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type);
200 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type);
201 void ionic_dev_cmd_port_loopback(struct ionic_dev *idev,
202 uint8_t loopback_mode);
203
204 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
205 uint16_t lif_type, uint8_t qtype, uint8_t qver);
206
207 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type,
208 uint8_t ver);
209 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr);
210 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev);
211
212 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq);
213
214 struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif,
215 struct ionic_queue *q);
216
217 int ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs);
218 void ionic_cq_reset(struct ionic_cq *cq);
219 void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa);
220 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint16_t cq_desc_index,
221 void *cb_arg);
222 uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
223 ionic_cq_cb cb, void *cb_arg);
224
225 int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs);
226 void ionic_q_reset(struct ionic_queue *q);
227 void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa,
228 void *cmb_base, rte_iova_t cmb_base_pa);
229 void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa);
230
231 static inline uint16_t
ionic_q_space_avail(struct ionic_queue * q)232 ionic_q_space_avail(struct ionic_queue *q)
233 {
234 uint16_t avail = q->tail_idx;
235
236 if (q->head_idx >= avail)
237 avail += q->num_descs - q->head_idx - 1;
238 else
239 avail -= q->head_idx + 1;
240
241 return avail;
242 }
243
244 static inline void
ionic_q_flush(struct ionic_queue * q)245 ionic_q_flush(struct ionic_queue *q)
246 {
247 uint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx;
248
249 #if defined(RTE_LIBRTE_IONIC_PMD_BARRIER_ERRATA)
250 /* On some devices the standard 'dmb' barrier is insufficient */
251 asm volatile("dsb st" : : : "memory");
252 rte_write64_relaxed(rte_cpu_to_le_64(val), q->db);
253 #else
254 rte_write64(rte_cpu_to_le_64(val), q->db);
255 #endif
256 }
257
258 static inline bool
ionic_is_embedded(void)259 ionic_is_embedded(void)
260 {
261 #if defined(RTE_LIBRTE_IONIC_PMD_EMBEDDED)
262 return true;
263 #else
264 return false;
265 #endif
266 }
267
268 #endif /* _IONIC_DEV_H_ */
269