1//===- XeGPUAttrs.td - XeGPU dialect attributes definition --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#ifndef MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD 10#define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD 11 12include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td" 13include "mlir/IR/AttrTypeBase.td" 14include "mlir/IR/EnumAttr.td" 15 16class XeGPUAttr<string name, string attrMnemonic, list<Trait> traits = [], 17 string baseCppClass = "::mlir::Attribute"> 18 : AttrDef<XeGPU_Dialect, name, traits, baseCppClass> { 19 let mnemonic = attrMnemonic; 20} 21 22class XeGPU_TensorDescAttr<string name, string attrMnemonic, list<Trait> traits = [], 23 string baseCppClass = "::mlir::Attribute"> 24 : XeGPUAttr<name, attrMnemonic, traits, baseCppClass> { 25 let assemblyFormat = "`<` struct(params) `>`"; 26} 27 28def XeGPU_BlockTensorDescAttr: XeGPU_TensorDescAttr<"BlockTensorDesc", "block_tdesc_attr"> { 29 let summary = [{a composite attribute for `TensorDescType`}]; 30 let description = [{`BlockTensorDesc` (or `block_tdesc_attr`) is a composite 31 attribute defined for `TensorDescType` for describing following 32 properties of a `TensorDesc`. 33 1. `memory_space`: It describes where the data block described by the 34 TensorDesc is located, `Global` device memory or `Shared` local memory. 35 It is default to `Global`. 36 2. `array_length`: It describes how many horizontally consecutive blocks 37 will be loaded by a hardware load instruction. If the TensorDesc shape 38 is 8x16, with array_length = 2. The loaded block shape will be acctually 39 8x32. Its default value is 1. 40 3. `boundary_check`: It is used to indicates the hardware whether to do 41 out-of-boundary check. The default value is true. 42 }]; 43 44 let parameters = (ins 45 OptionalParameter<"MemorySpaceAttr">: $memory_space, 46 OptionalParameter<"IntegerAttr", "1">: $array_length, 47 OptionalParameter<"BoolAttr", "true">: $boundary_check 48 ); 49 50 let builders = [ 51 AttrBuilder<(ins 52 CArg<"xegpu::MemorySpace", "xegpu::MemorySpace::Global">:$memory_space, 53 CArg<"int", "1">:$array_length, 54 CArg<"bool", "true">: $boundary_check 55 )> 56 ]; 57 58} 59 60def XeGPU_ScatterTensorDescAttr: XeGPU_TensorDescAttr<"ScatterTensorDesc", "scatter_tdesc_attr"> { 61 let summary = [{a composite attribute for `TensorDescType`}]; 62 let description = [{`ScatterTensorDesc` (or `scatter_tdesc_attr`) is a composite 63 attribute defined for `TensorDescType` for describing following 64 properties of a `TensorDesc`. 65 1. `memory_space`: It describes where the data block described by the 66 TensorDesc is located, `Global` device memory or `Shared` local memory. 67 It is default to `Global`. 68 2. `chunk_size`: indicates number of continious elements accessed for each 69 offset, default is 1. It is used with `scattered` attr only. 70 }]; 71 72 let parameters = (ins 73 OptionalParameter<"MemorySpaceAttr">: $memory_space, 74 OptionalParameter<"IntegerAttr", "1">: $chunk_size 75 ); 76 77 let builders = [ 78 AttrBuilder<(ins 79 CArg<"xegpu::MemorySpace", "xegpu::MemorySpace::Global">:$memory_space, 80 CArg<"int", "1">: $chunk_size 81 )> 82 ]; 83 } 84 85//===----------------------------------------------------------------------===// 86// XeGPU Memory Scope Enums. 87//===----------------------------------------------------------------------===// 88def XeGPU_MemorySpaceGlobal: I32EnumAttrCase<"Global", 0, "global">; 89def XeGPU_MemorySpaceShared: I32EnumAttrCase<"SLM", 3, "slm">; 90def XeGPU_MemorySpace: I32EnumAttr<"MemorySpace", 91 "The address space of the memory the tensor descritor is created for", 92 [XeGPU_MemorySpaceGlobal, XeGPU_MemorySpaceShared]> { 93 let genSpecializedAttr = 0; 94 let cppNamespace = "::mlir::xegpu"; 95} 96 97def XeGPU_MemorySpaceAttr: 98 EnumAttr<XeGPU_Dialect, XeGPU_MemorySpace, "memory_space"> { 99 let summary = [{Describe the location of data described by a `TensorDesc`: 100 Global device memory (`Global`) or Shared local memory (`SLM`).}]; 101 let assemblyFormat = "$value"; 102} 103 104//===----------------------------------------------------------------------===// 105// XeGPU Cache Enums. 106//===----------------------------------------------------------------------===// 107def XeGPU_CachePolicyCached: I32EnumAttrCase<"CACHED", 0, "cached">; // valid for read and write 108def XeGPU_CachePolicyUncached: I32EnumAttrCase<"UNCACHED", 1, "uncached">; // valid for read and write 109def XeGPU_CachePolicyStreaming: I32EnumAttrCase<"STREAMING", 2, "streaming">; // valid for read only 110def XeGPU_CachePolicyInvalid: I32EnumAttrCase<"READ_INVALIDATE", 3, "read_invalidate">; // valid for read only 111def XeGPU_CachePolicyWriteBack: I32EnumAttrCase<"WRITE_BACK", 4, "write_back">; // valid for write only 112def XeGPU_CachePolicyWriteThrough: I32EnumAttrCase<"WRITE_THROUGH", 5, "write_through">; // valid for write only 113 114def XeGPU_CachePolicyEnums : I32EnumAttr<"CachePolicy", "Cache policy", 115 [XeGPU_CachePolicyCached, XeGPU_CachePolicyUncached, 116 XeGPU_CachePolicyStreaming, XeGPU_CachePolicyInvalid, 117 XeGPU_CachePolicyWriteBack, XeGPU_CachePolicyWriteThrough]> { 118 let genSpecializedAttr = 0; 119 let cppNamespace = "::mlir::xegpu"; 120} 121 122def XeGPU_CacheHintAttr 123 : EnumAttr<XeGPU_Dialect, XeGPU_CachePolicyEnums, "cache_hint"> { 124 let summary = [{Describe the cache settings for prefetch/load/store operators}]; 125 let assemblyFormat = "`<` $value `>`"; 126} 127 128def XeGPU_FenceScopeWorkgroup: I32EnumAttrCase<"Workgroup", 0, "workgroup">; 129def XeGPU_FenceScopeGPU: I32EnumAttrCase<"GPU", 1, "gpu">; 130def XeGPU_FenceScope: I32EnumAttr<"FenceScope", 131 "The enumeration for the scope of fence operation.", 132 [XeGPU_FenceScopeWorkgroup, XeGPU_FenceScopeGPU]> { 133 let genSpecializedAttr = 0; 134 let cppNamespace = "::mlir::xegpu"; 135} 136 137def XeGPU_FenceScopeAttr: 138 EnumAttr<XeGPU_Dialect, XeGPU_FenceScope, "fence_scope"> { 139 let summary = [{Describes the scope of fence. 140 "workgroup" means that the scope is within each work group. 141 "gpu" means the scope is across work groups within the gpu.}]; 142 let assemblyFormat = "$value"; 143} 144 145def XeGPU_SGMapAttr : XeGPUAttr<"SGMap", "sg_map"> { 146 let summary = [{ 147 Describes the mapping between work item (WI) and the 2D tensor specified by the tensor descriptor. 148 }]; 149 let description = [{ 150 To distribute the XeGPU operation to work items, the tensor_desc must be specified with the sg_map 151 attribute at the tensor description creation time. 152 Within the `sg_map`, `wi_layout` specifies the layout of work items, 153 describing the mapping of work items to the tensor. 154 wi_layout[0] x wi_layout[1] must be equal to the total number of work items within a subgroup. 155 `wi_data` specifies the minimum number of data elements assigned to each work item for a single distribution. 156 157 E.g., #xegpu.sg_map<wi_layout = [1, 16], wi_data = [1, 1]> 158 In this example, the subgroup has 16 work items in wi_layout=[1, 16], 159 each accessing 1 element as specified by wi_data=[1, 1]. 160 161 `wi_data[0] * wi_data[1]` can be greater than 1, meaning that each work item operates on multiple elements, 162 which is eventually lowered to "SIMT-flavor" vector, like SPIR-V vector or llvm vector, or packed to a storage data type. 163 The multiple elements indicated by `wi_data` can only be from one dimension and must be contiguous in the memory along either dimension. 164 }]; 165 let parameters = (ins 166 ArrayRefParameter<"uint32_t">:$wi_layout, 167 ArrayRefParameter<"uint32_t">:$wi_data 168 ); 169 170 171 let hasCustomAssemblyFormat = 1; 172 let genVerifyDecl = 1; 173} 174 175#endif // MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD 176