1 /* $NetBSD: imxcspireg.h,v 1.3 2023/08/01 21:26:27 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_IMX_IMXCSPIREG_H_ 30 #define _ARM_IMX_IMXCSPIREG_H_ 31 32 #define CSPI_RXDATA 0x00 33 #define CSPI_TXDATA 0x04 34 #define CSPI_CONREG 0x08 35 #define CSPI_IMX31_CON_CS __BITS(25, 24) 36 #define CSPI_IMX31_CON_DRCTL __BITS(21, 20) 37 #define CSPI_IMX31_CON_BITCOUNT __BITS(12, 8) 38 #define CSPI_IMX35_CON_CS __BITS(13, 12) 39 #define CSPI_IMX35_CON_DRCTL __BITS( 9, 8) 40 #define CSPI_IMX35_CON_BITCOUNT __BITS(31, 20) 41 #define CSPI_CON_DIV __BITS(18, 16) 42 #define CSPI_CON_SSPOL __BIT(7) /* SPI SS Polarity Select */ 43 #define CSPI_CON_SSCTL __BIT(6) /* In master mode, this bit 44 * selects the output wave form 45 * for the SS signal. 46 */ 47 #define CSPI_CON_PHA __BIT(5) /* PHA */ 48 #define CSPI_CON_POL __BIT(4) /* POL */ 49 #define CSPI_CON_SMC __BIT(3) /* SMC */ 50 #define CSPI_CON_XCH __BIT(2) /* XCH */ 51 #define CSPI_CON_MODE __BIT(1) /* MODE */ 52 #define CSPI_CON_ENABLE __BIT(0) /* EN */ 53 #define CSPI_INTREG 0x0c 54 #define CSPI_INTR_ALL_EN 0x000001ff /* All Interrupts Enabled */ 55 #define CSPI_IMX31_INTR_TC_EN __BIT(8) /* TX Complete */ 56 #define CSPI_IMX31_INTR_BO_EN __BIT(7) /* Bit Counter Overflow */ 57 #define CSPI_IMX35_INTR_TC_EN __BIT(7) /* TX Complete */ 58 #define CSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */ 59 #define CSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */ 60 #define CSPI_INTR_RH_EN __BIT(4) /* RXFIFO Half Full */ 61 #define CSPI_INTR_RR_EN __BIT(3) /* RXFIFO Ready */ 62 #define CSPI_INTR_TF_EN __BIT(2) /* TXFIFO Full */ 63 #define CSPI_INTR_TH_EN __BIT(1) /* TXFIFO Half Empty */ 64 #define CSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */ 65 #define CSPI_DMAREG 0x10 66 #define CSPI_STATREG 0x14 67 #define CSPI_IMX31_STAT_CLR_TC __BIT(8) /* Clear TC of status register */ 68 #define CSPI_IMX31_STAT_CLR_BO __BIT(7) /* Clear BO of status register */ 69 #define CSPI_IMX31_STAT_CLR (CSPI_IMX31_STAT_CLR_TC | CSPI_IMX31_STAT_CLR_BO) 70 #define CSPI_IMX35_STAT_CLR_TC __BIT(7) /* Clear TC of status register */ 71 #define CSPI_IMX35_STAT_CLR CSPI_IMX35_STAT_CLR_TC 72 #define CSPI_STAT_RO __BIT(6) /* RXFIFO Overflow */ 73 #define CSPI_STAT_RF __BIT(5) /* RXFIFO Full */ 74 #define CSPI_STAT_RH __BIT(4) /* RXFIFO Half Full */ 75 #define CSPI_STAT_RR __BIT(3) /* RXFIFO Ready */ 76 #define CSPI_STAT_TF __BIT(2) /* TXFIFO Full */ 77 #define CSPI_STAT_TH __BIT(1) /* TXFIFO Half Empty */ 78 #define CSPI_STAT_TE __BIT(0) /* TXFIFO Empty */ 79 #define CSPI_PERIODREG 0x18 80 #define CSPI_TESTREG 0x1c 81 82 #define SPI_SIZE 0x100 83 84 #endif /* _ARM_IMX_IMXCSPIREG_H_ */ 85