1 /* $Id: imx23_apbhdmareg.h,v 1.2 2013/03/03 10:33:56 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_APBHDMAREG_H_ 33 #define _ARM_IMX_IMX23_APBHDMAREG_H_ 34 35 #include <sys/cdefs.h> 36 37 #define HW_APBHDMA_BASE 0x80004000 38 #define HW_APBHDMA_SIZE 0x2000 /* 8 kB */ 39 40 /* 41 * AHB to APBH Bridge Control and Status Register 0. 42 */ 43 #define HW_APBH_CTRL0 0x000 44 #define HW_APBH_CTRL0_SET 0x004 45 #define HW_APBH_CTRL0_CLR 0x008 46 #define HW_APBH_CTRL0_TOG 0x00C 47 48 #define HW_APBH_CTRL0_SFTRST __BIT(31) 49 #define HW_APBH_CTRL0_CLKGATE __BIT(30) 50 #define HW_APBH_CTRL0_AHB_BURST8_EN __BIT(29) 51 #define HW_APBH_CTRL0_APB_BURST4_EN __BIT(28) 52 #define HW_APBH_CTRL0_RSVD0 __BITS(27, 24) 53 #define HW_APBH_CTRL0_RESET_CHANNEL __BITS(23, 16) 54 #define HW_APBH_CTRL0_CLKGATE_CHANNEL __BITS(15, 8) 55 #define HW_APBH_CTRL0_FREEZE_CHANNEL __BITS(7, 0) 56 57 /* 58 * AHB to APBH Bridge Control and Status Register 1. 59 */ 60 #define HW_APBH_CTRL1 0x010 61 #define HW_APBH_CTRL1_SET 0x014 62 #define HW_APBH_CTRL1_CLR 0x018 63 #define HW_APBH_CTRL1_TOG 0x01C 64 65 #define HW_APBH_CTRL1_RSVD1 __BITS(31, 24) 66 #define HW_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN __BIT(23) 67 #define HW_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN __BIT(22) 68 #define HW_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN __BIT(21) 69 #define HW_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN __BIT(20) 70 #define HW_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN __BIT(19) 71 #define HW_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN __BIT(18) 72 #define HW_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN __BIT(17) 73 #define HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN __BIT(16) 74 #define HW_APBH_CTRL1_RSVD0 __BITS(15, 8) 75 #define HW_APBH_CTRL1_CH7_CMDCMPLT_IRQ __BIT(7) 76 #define HW_APBH_CTRL1_CH6_CMDCMPLT_IRQ __BIT(6) 77 #define HW_APBH_CTRL1_CH5_CMDCMPLT_IRQ __BIT(5) 78 #define HW_APBH_CTRL1_CH4_CMDCMPLT_IRQ __BIT(4) 79 #define HW_APBH_CTRL1_CH3_CMDCMPLT_IRQ __BIT(3) 80 #define HW_APBH_CTRL1_CH2_CMDCMPLT_IRQ __BIT(2) 81 #define HW_APBH_CTRL1_CH1_CMDCMPLT_IRQ __BIT(1) 82 #define HW_APBH_CTRL1_CH0_CMDCMPLT_IRQ __BIT(0) 83 84 /* 85 * AHB to APBH Bridge Control and Status Register 2. 86 */ 87 #define HW_APBH_CTRL2 0x020 88 #define HW_APBH_CTRL2_SET 0x024 89 #define HW_APBH_CTRL2_CLR 0x028 90 #define HW_APBH_CTRL2_TOG 0x02C 91 92 #define HW_APBH_CTRL2_RSVD1 __BITS(31, 24) 93 #define HW_APBH_CTRL2_CH7_ERROR_STATUS __BIT(23) 94 #define HW_APBH_CTRL2_CH6_ERROR_STATUS __BIT(22) 95 #define HW_APBH_CTRL2_CH5_ERROR_STATUS __BIT(21) 96 #define HW_APBH_CTRL2_CH4_ERROR_STATUS __BIT(20) 97 #define HW_APBH_CTRL2_CH3_ERROR_STATUS __BIT(19) 98 #define HW_APBH_CTRL2_CH2_ERROR_STATUS __BIT(18) 99 #define HW_APBH_CTRL2_CH1_ERROR_STATUS __BIT(17) 100 #define HW_APBH_CTRL2_CH0_ERROR_STATUS __BIT(16) 101 #define HW_APBH_CTRL2_RSVD0 __BITS(15, 8) 102 #define HW_APBH_CTRL2_CH7_ERROR_IRQ __BIT(7) 103 #define HW_APBH_CTRL2_CH6_ERROR_IRQ __BIT(6) 104 #define HW_APBH_CTRL2_CH5_ERROR_IRQ __BIT(5) 105 #define HW_APBH_CTRL2_CH4_ERROR_IRQ __BIT(4) 106 #define HW_APBH_CTRL2_CH3_ERROR_IRQ __BIT(3) 107 #define HW_APBH_CTRL2_CH2_ERROR_IRQ __BIT(2) 108 #define HW_APBH_CTRL2_CH1_ERROR_IRQ __BIT(1) 109 #define HW_APBH_CTRL2_CH0_ERROR_IRQ __BIT(0) 110 111 /* 112 * AHB to APBH DMA Device Assignment Register. 113 */ 114 #define HW_APBH_DEVSEL 0x030 115 116 #define HW_APBH_DEVSEL_CH7 __BITS(31, 28) 117 #define HW_APBH_DEVSEL_CH6 __BITS(27, 24) 118 #define HW_APBH_DEVSEL_CH5 __BITS(23, 20) 119 #define HW_APBH_DEVSEL_CH4 __BITS(19, 16) 120 #define HW_APBH_DEVSEL_CH3 __BITS(15, 12) 121 #define HW_APBH_DEVSEL_CH2 __BITS(11, 8) 122 #define HW_APBH_DEVSEL_CH1 __BITS(7, 4) 123 #define HW_APBH_DEVSEL_CH0 __BITS(3, 0) 124 125 /* 126 * APBH DMA Channel 0 Current Command Address Register. 127 */ 128 #define HW_APBH_CH0_CURCMDAR 0x040 129 130 #define HW_APBH_CH0_CURCMDAR_CMD_ADDR __BITS(31, 0) 131 132 /* 133 * APBH DMA Channel 0 Next Command Address. 134 */ 135 #define HW_APBH_CH0_NXTCMDAR 0x050 136 137 #define HW_APBH_CH0_NXTCMDAR_CMD_ADDR __BITS(31, 0) 138 139 /* 140 * APBH DMA Channel 0 Semaphore Register. 141 */ 142 #define HW_APBH_CH0_SEMA 0x080 143 144 #define HW_APBH_CH0_SEMA_RSVD2 __BITS(31, 24) 145 #define HW_APBH_CH0_SEMA_PHORE __BITS(23, 16) 146 #define HW_APBH_CH0_SEMA_RSVD1 __BITS(15, 8) 147 #define HW_APBH_CH0_SEMA_INCREMENT_SEMA __BITS(7, 0) 148 149 /* 150 * APBH DMA Channel 1 Current Command Address Register. 151 */ 152 #define HW_APBH_CH1_CURCMDAR 0x0B0 153 154 #define HW_APBH_CH1_CURCMDAR_CMD_ADDR __BITS(31, 0) 155 156 /* 157 * APBH DMA Channel 1 Next Command Address Register. 158 */ 159 #define HW_APBH_CH1_NXTCMDAR 0x0C0 160 161 #define HW_APBH_CH1_NXTCMDAR_CMD_ADDR __BITS(31, 0) 162 163 /* 164 * APBH DMA Channel 1 Command Register. 165 */ 166 #define HW_APBH_CH1_CMD 0x0D0 167 168 #define HW_APBH_CH1_CMD_XFER_COUNT __BITS(31, 16) 169 #define HW_APBH_CH1_CMD_CMDWORDS __BITS(15, 12) 170 #define HW_APBH_CH1_CMD_RSVD1 __BITS(11, 9) 171 #define HW_APBH_CH1_CMD_HALTONTERMINATE __BIT(8) 172 #define HW_APBH_CH1_CMD_WAIT4ENDCMD __BIT(7) 173 #define HW_APBH_CH1_CMD_SEMAPHORE __BIT(6) 174 #define HW_APBH_CH1_CMD_NANDWAIT4READY __BIT(5) 175 #define HW_APBH_CH1_CMD_NANDLOCK __BIT(4) 176 #define HW_APBH_CH1_CMD_IRQONCMPLT __BIT(3) 177 #define HW_APBH_CH1_CMD_CHAIN __BIT(2) 178 #define HW_APBH_CH1_CMD_COMMAND __BITS(1, 0) 179 180 /* 181 * APBH DMA Channel 1 Buffer Address Register. 182 */ 183 #define HW_APBH_CH1_BAR 0x0E0 184 185 #define HW_APBH_CH1_BAR_ADDRESS __BITS(31, 0) 186 187 /* 188 * APBH DMA Channel 1 Semaphore Register. 189 */ 190 #define HW_APBH_CH1_SEMA 0x0F0 191 192 #define HW_APBH_CH1_SEMA_RSVD2 __BITS(31, 24) 193 #define HW_APBH_CH1_SEMA_PHORE __BITS(23, 16) 194 #define HW_APBH_CH1_SEMA_RSVD1 __BITS(15, 8) 195 #define HW_APBH_CH1_SEMA_INCREMENT_SEMA __BITS(7, 0) 196 197 /* 198 * AHB to APBH DMA Channel 1 Debug Information. 199 */ 200 #define HW_APBH_CH1_DEBUG1 0x100 201 202 #define HW_APBH_CH1_DEBUG1_REQ __BIT(31) 203 #define HW_APBH_CH1_DEBUG1_BURST __BIT(30) 204 #define HW_APBH_CH1_DEBUG1_KICK __BIT(29) 205 #define HW_APBH_CH1_DEBUG1_END __BIT(28) 206 #define HW_APBH_CH1_DEBUG1_SENSE __BIT(27) 207 #define HW_APBH_CH1_DEBUG1_READY __BIT(26) 208 #define HW_APBH_CH1_DEBUG1_LOCK __BIT(25) 209 #define HW_APBH_CH1_DEBUG1_NEXTCMDADDRVALID __BIT(24) 210 #define HW_APBH_CH1_DEBUG1_RD_FIFO_EMPTY __BIT(23) 211 #define HW_APBH_CH1_DEBUG1_RD_FIFO_FULL __BIT(22) 212 #define HW_APBH_CH1_DEBUG1_WR_FIFO_EMPTY __BIT(21) 213 #define HW_APBH_CH1_DEBUG1_WR_FIFO_FULL __BIT(20) 214 #define HW_APBH_CH1_DEBUG1_RSVD1 __BITS(19, 5) 215 #define HW_APBH_CH1_DEBUG1_STATEMACHINE __BITS(4, 0) 216 217 /* 218 * AHB to APBH DMA Channel 1 Debug Information. 219 */ 220 #define HW_APBH_CH1_DEBUG2 0x110 221 222 #define HW_APBH_CH1_DEBUG2_APB_BYTES __BITS(31, 16) 223 #define HW_APBH_CH1_DEBUG2_AHB_BYTES __BITS(15, 0) 224 225 #endif /* !_ARM_IMX_IMX23_APBHDMAREG_H_ */ 226