1 /* $Id: imx23_apbdmareg.h,v 1.3 2015/01/10 12:13:00 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_APBDMAREG_H_ 33 #define _ARM_IMX_IMX23_APBDMAREG_H_ 34 35 #include <sys/cdefs.h> 36 37 /* 38 * Common register definitions for both APBH and APBX. 39 */ 40 41 /* 42 * AHB to APB{H,X} Bridge Control and Status Register 0. 43 */ 44 #define HW_APB_CTRL0 0x000 45 #define HW_APB_CTRL0_SET 0x004 46 #define HW_APB_CTRL0_CLR 0x008 47 #define HW_APB_CTRL0_TOG 0x00C 48 49 #define HW_APB_CTRL0_SFTRST __BIT(31) 50 #define HW_APB_CTRL0_CLKGATE __BIT(30) 51 #define HW_APB_CTRL0_RSVD0 __BITS(29, 0) 52 53 /* 54 * AHB to APB{H,X} Bridge Control Register 1. 55 */ 56 #define HW_APB_CTRL1 0x010 57 #define HW_APB_CTRL1_SET 0x014 58 #define HW_APB_CTRL1_CLR 0x018 59 #define HW_APB_CTRL1_TOG 0x01C 60 61 /* 62 * AHB to APB{H,X} Bridge Control and Status Register 2. 63 */ 64 #define HW_APB_CTRL2 0x020 65 #define HW_APB_CTRL2_SET 0x024 66 #define HW_APB_CTRL2_CLR 0x028 67 #define HW_APB_CTRL2_TOG 0x02C 68 69 #define HW_APBX_CHANNEL_CTRL 0x30 70 #define HW_APBX_CHANNEL_CTRL_SET 0x34 71 #endif /* !_ARM_IMX_IMX23_APBDMAREG_H_ */ 72