1 enum{ 2 Nuart = 1, /* Number of SMC Uarts */ 3 }; 4 5 enum{ 6 /* Vectors */ 7 VecXXX0, 8 VecI2C, 9 VecSPI, 10 VecRisc, 11 VecSMC1, 12 VecSMC2, 13 VecIDMA1, 14 VecIDMA2, 15 VecIDMA3, 16 VecIDMA4, 17 VecSDMA, 18 VecXXX11, 19 VecTimer1, 20 VecTimer2, 21 VecTimer3, 22 VecTimer4, 23 VecTMCNT, 24 VecPIT, 25 VecXXX18, 26 VecIRQ1, 27 VecIRQ2, 28 VecIRQ3, 29 VecIRQ4, 30 VecIRQ5, 31 VecIRQ6, 32 VecIRQ7, 33 VecXXX26, 34 VecXXX27, 35 VecXXX28, 36 VecXXX29, 37 VecXXX30, 38 VecXXX31, 39 VecFCC1, 40 VecFCC2, 41 VecFCC3, 42 VecXXX35, 43 VecMCC1, 44 VecMCC2, 45 VecXXX38, 46 VecXXX39, 47 VecSCC1, 48 VecSCC2, 49 VecSCC3, 50 VecSCC4, 51 VecXXX44, 52 VecXXX45, 53 VecXXX46, 54 VecXXX47, 55 VecPC15, 56 VecPC14, 57 VecPC13, 58 VecPC12, 59 VecPC11, 60 VecPC10, 61 VecPC9, 62 VecPC8, 63 VecPC7, 64 VecPC6, 65 VecPC5, 66 VecPC4, 67 VecPC3, 68 VecPC2, 69 VecPC1, 70 VecPC0, 71 }; 72 73 typedef struct BD BD; 74 struct BD { 75 ushort status; 76 ushort length; 77 ulong addr; 78 }; 79 80 enum{ 81 BDEmpty= SBIT(0), 82 BDReady= SBIT(0), 83 BDWrap= SBIT(2), 84 BDInt= SBIT(3), 85 BDLast= SBIT(4), 86 BDFirst= SBIT(5), 87 }; 88 89 typedef struct Ring Ring; 90 91 struct Ring { 92 BD* rdr; /* receive descriptor ring */ 93 void* rrb; /* receive ring buffers */ 94 int rdrx; /* index into rdr */ 95 int nrdre; /* length of rdr */ 96 97 BD* tdr; /* transmit descriptor ring */ 98 void** txb; /* corresponding transmit ring buffers */ 99 int tdrh; /* host index into tdr */ 100 int tdri; /* interface index into tdr */ 101 int ntdre; /* length of tdr */ 102 int ntq; /* pending transmit requests */ 103 }; 104 105 int ioringinit(Ring*, int, int, int); 106 107 /* 108 * MCC parameters 109 */ 110 typedef struct MCCparam MCCparam; 111 struct MCCparam { 112 /*0x00*/ ulong mccbase; 113 /*0x04*/ ushort mccstate; 114 /*0x06*/ ushort mrblr; 115 /*0x08*/ ushort grfthr; 116 /*0x0a*/ ushort grfcnt; 117 /*0x0c*/ ulong rinttmp; 118 /*0x10*/ ulong data0; 119 /*0x14*/ ulong data1; 120 /*0x18*/ ulong tintbase; 121 /*0x1c*/ ulong tintptr; 122 /*0x20*/ ulong tinttmp; 123 /*0x24*/ ushort sctpbase; 124 /*0x26*/ ushort Rsvd26; 125 /*0x28*/ ulong cmask32; 126 /*0x2c*/ ushort xtrabase; 127 /*0x2e*/ ushort cmask16; 128 /*0x30*/ ulong rinttmp[4]; 129 /*0x40*/ struct { 130 ulong base; 131 ulong ptr; 132 } rint[4]; 133 /*0x60*/ ulong tstmp; 134 /*0x64*/ 135 }; 136 /* 137 * IO controller parameters 138 */ 139 typedef struct IOCparam IOCparam; 140 struct IOCparam { 141 /*0x00*/ ushort rbase; 142 /*0x02*/ ushort tbase; 143 /*0x04*/ uchar rfcr; 144 /*0x05*/ uchar tfcr; 145 /*0x06*/ ushort mrblr; 146 /*0x08*/ ulong rstate; 147 /*0x0c*/ ulong rxidp; 148 /*0x10*/ ushort rbptr; 149 /*0x12*/ ushort rxibc; 150 /*0x14*/ ulong rxtemp; 151 /*0x18*/ ulong tstate; 152 /*0x1c*/ ulong txidp; 153 /*0x20*/ ushort tbptr; 154 /*0x22*/ ushort txibc; 155 /*0x24*/ ulong txtemp; 156 /*0x28*/ 157 }; 158 159 typedef struct SCCparam SCCparam; 160 struct SCCparam { 161 IOCparam; 162 ulong rcrc; 163 ulong tcrc; 164 }; 165 166 typedef struct FCCparam FCCparam; 167 struct FCCparam { 168 /*0x00*/ ushort riptr; 169 /*0x02*/ ushort tiptr; 170 /*0x04*/ ushort Rsvd04; 171 /*0x06*/ ushort mrblr; 172 /*0x08*/ ulong rstate; 173 /*0x0c*/ ulong rbase; 174 /*0x10*/ ushort rbdstat; 175 /*0x12*/ ushort rbdlen; 176 /*0x14*/ char* rdptr; 177 /*0x18*/ ulong tstate; 178 /*0x1c*/ ulong tbase; 179 /*0x20*/ ushort tbdstat; 180 /*0x22*/ ushort tbdlen; 181 /*0x24*/ ulong tdptr; 182 /*0x28*/ ulong rbptr; 183 /*0x2c*/ ulong tbptr; 184 /*0x30*/ ulong rcrc; 185 /*0x34*/ ulong Rsvd34; 186 /*0x38*/ ulong tcrc; 187 /*0x3c*/ 188 }; 189 190 typedef struct SCC SCC; 191 struct SCC { 192 ulong gsmrl; 193 ulong gsmrh; 194 ushort psmr; 195 uchar rsvscc0[2]; 196 ushort todr; 197 ushort dsr; 198 ushort scce; 199 uchar rsvscc1[2]; 200 ushort sccm; 201 uchar rsvscc2; 202 uchar sccs; 203 ushort irmode; 204 ushort irsip; 205 uchar rsvscc3[4]; /* BUG */ 206 }; 207 208 typedef struct FCC FCC; 209 struct FCC { 210 /*0x00*/ ulong gfmr; /* general mode register 28.2/28-3 */ 211 /*0x04*/ ulong fpsmr; /* protocol-specific mode reg. 29.13.2(ATM) 30.18.1(Ether) */ 212 /*0x08*/ ushort ftodr; /* transmit on demand register 28.5/28-7 */ 213 /*0x0A*/ ushort Rsvd0A; 214 /*0x0C*/ ushort fdsr; /* data synchronization register 28.4/28-7 */ 215 /*0x0E*/ ushort Rsvd0E; 216 /*0x10*/ ushort fcce; /* event register 29.13.3 (ATM), 30.18.2 (Ethernet) */ 217 /*0x12*/ ushort Rsvd12; 218 /*0x14*/ ushort fccm; /* mask register */ 219 /*0x16*/ ushort Rsvd16; 220 /*0x18*/ uchar fccs; /* status register 8 bits 31.10 (HDLC) */ 221 /*0x19*/ uchar Rsvd19[3]; 222 /*0x1C*/ uchar ftirrphy[4]; /* transmit internal rate registers for PHY0DH3 29.13.4/29-88 (ATM) */ 223 /*0x20*/ 224 }; 225 226 typedef struct SMC SMC; 227 struct SMC { 228 /*0x0*/ ushort pad1; 229 /*0x2*/ ushort smcmr; 230 /*0x4*/ ushort pad2; 231 /*0x6*/ uchar smce; 232 /*0x7*/ uchar pad3[3]; 233 /*0xa*/ uchar smcm; 234 /*0xb*/ uchar pad4[5]; 235 /*0x10*/ 236 }; 237 238 typedef struct SPI SPI; 239 struct SPI { 240 ushort spmode; 241 uchar res1[4]; 242 uchar spie; 243 uchar res2[3]; 244 uchar spim; 245 uchar res3[2]; 246 uchar spcom; 247 uchar res4[2]; 248 }; 249 250 typedef struct Bankmap Bankmap; 251 struct Bankmap { 252 /*0*/ ulong br; /* Base register bank 32 bits 10.3.1/10-14 */ 253 /*4*/ ulong or; /* Option register bank 32 bits 10.3.2/10-16 */ 254 /*8*/ 255 }; 256 257 typedef struct Port Port; 258 struct Port { 259 /*0x00*/ ulong pdir; /* Port A data direction register 32 bits 35.2.3/35-3 */ 260 /*0x04*/ ulong ppar; /* Port Apin assignment register 32 bits 35.2.4/35-4 */ 261 /*0x08*/ ulong psor; /* Port A special options register 32 bits 35.2.5/35-4 */ 262 /*0x0C*/ ulong podr; /* Port Aopen drain register 32 bits 35.2.1/35-2 */ 263 /*0x10*/ ulong pdat; /* Port A data register 32 bits 35.2.2/35-2 */ 264 /*0x14*/ uchar Rsvd14[12]; 265 /*0x20*/ 266 }; 267 268 typedef struct IDMA IDMA; 269 struct IDMA { 270 /*0x0*/ uchar idsr; /* IDMA event register 8 bits 18.8.4/18-22 */ 271 /*0x1*/ uchar Rsvd1[3]; 272 /*0x4*/ uchar idmr; /* IDMA mask register 8 bits 18.8.4/18-22 */ 273 /*0x5*/ uchar Rsvd5[3]; 274 /*0x8*/ 275 }; 276 277 typedef struct PrmSCC PrmSCC; 278 struct PrmSCC { 279 uchar sccbytes[0x100]; 280 }; 281 282 typedef struct PrmFCC PrmFCC; 283 struct PrmFCC { 284 uchar fccbytes[0x100]; 285 }; 286 287 typedef struct Bases Bases; 288 struct Bases { 289 /*0x00*/ uchar mcc[0x80]; 290 /*0x80*/ uchar Rsvd80[0x60]; 291 /*0xe0*/ uchar risctimers[0x10]; 292 /*0xf0*/ ushort revnum; 293 /*0xf2*/ uchar Rsvdf2[6]; 294 /*0xf8*/ ulong rand; 295 /*0xfc*/ ushort smcbase; 296 #define i2cbase smcbase 297 /*0xfe*/ ushort idmabase; 298 /*0x100*/ 299 }; 300 301 typedef struct Uartsmc Uartsmc; 302 struct Uartsmc { 303 /*0x00*/ IOCparam; 304 /*0x28*/ ushort maxidl; 305 /*0x2a*/ ushort idlc; 306 /*0x2c*/ ushort brkln; 307 /*0x2e*/ ushort brkec; 308 /*0x30*/ ushort brkcr; 309 /*0x32*/ ushort r_mask; 310 /*0x34*/ ulong sdminternal; 311 /*0x38*/ uchar Rsvd38[8]; 312 /*0x40*/ 313 }; 314 315 typedef struct SI SI; 316 struct SI { 317 /*0x11B20*/ ushort siamr; /* SI TDMA1 mode register 16 bits 14.5.2/14-17 */ 318 /*0x11B22*/ ushort sibmr; /* SI TDMB1 mode register 16 bits */ 319 /*0x11B24*/ ushort sicmr; /* SI TDMC1 mode register 16 bits */ 320 /*0x11B26*/ ushort sidmr; /* SI TDMD1 mode register 16 bits */ 321 /*0x11B28*/ uchar sigmr; /* SI global mode register 8 bits 14.5.1/14-17 */ 322 /*0x11B29*/ uchar Rsvd11B29; 323 /*0x11B2A*/ ushort sicmdr; /* SI command register 8 bits 14.5.4/14-24 */ 324 /*0x11B2C*/ ushort sistr; /* SI status register 8 bits 14.5.5/14-25 */ 325 /*0x11B2E*/ ushort sirsr; /* SI RAM shadow address register 16 bits 14.5.3/14-23 */ 326 }; 327 328 typedef struct RegMap RegMap; 329 struct RegMap { 330 /* General SIU */ 331 /*0x10000*/ ulong siumcr; /* SIU module configuration register 32 bits 4.3.2.6/4-31 */ 332 /*0x10004*/ ulong sypcr; /* System protection control register 32 bits 4.3.2.8/4-35 */ 333 /*0x10008*/ uchar Rsvd10008[0xe-0x8]; 334 /*0x1000E*/ ushort swsr; /* Softwareservice register 16 bits 4.3.2.9/4-36 */ 335 /*0x10010*/ uchar Rsvd10010[0x14]; 336 /*0x10024*/ ulong bcr; /* Bus configuration register 32 bits 4.3.2.1/4-25 */ 337 /*0x10028*/ ulong PPC_ACR; /* 60x bus arbiter configuration register 8 bits 4.3.2.2/4-28 */ 338 /*0x1002C*/ ulong PPCALRH; /* 60x bus arbitration-level register high (first 8 clients) 32 bits 4.3.2.3/4-28 */ 339 /*0x10030*/ ulong PPC_ALRL; /* 60x bus arbitration-level register low (next 8 clients) 32 bits 4.3.2.3/4-28 */ 340 /*0x10034*/ ulong LCL_ACR; /* Local arbiter configuration register 8 bits 4.3.2.4/4-29 */ 341 /*0x10038*/ ulong LCL_ALRH; /* Local arbitration-level register (first 8 clients) 32 bits 4.3.2.5/4-30 */ 342 343 /*0x1003C*/ ulong LCL_ALRL; /* Local arbitration-level register (next 8 clients) 32 bits 4.3.2.3/4-28 */ 344 /*0x10040*/ ulong TESCR1; /* 60x bus transfer error status control register1 32 bits 4.3.2.10/4-36 */ 345 /*0x10044*/ ulong TESCR2; /* 60x bus transfer error status control register2 32 bits 4.3.2.11/4-37 */ 346 /*0x10048*/ ulong L_TESCR1; /* Local bus transfer error status control register1 32 bits 4.3.2.12/4-38 */ 347 /*0x1004C*/ ulong L_TESCR2; /* Local bus transfer error status control register2 32 bits 4.3.2.13/4-39 */ 348 /*0x10050*/ ulong pdtea; /* 60x bus DMAtransfer error address 32 bits 18.2.3/18-4 */ 349 /*0x10054*/ uchar pdtem; /* 60x bus DMAtransfer error MSNUM 8 bits 18.2.4/18-4 */ 350 /*0x10055*/ uchar Rsvd10055[3]; 351 /*0x10058*/ void* ldtea; /* Local bus DMA transfer error address 32 bits 18.2.3/18-4 */ 352 /*0x1005C*/ uchar ldtem; /* Local bus DMA transfer error MSNUM 8 bits 18.2.4/18-4 */ 353 /*0x1005D*/ uchar Rsvd1005D[163]; 354 355 /* Memory Controller */ 356 /*0x10100*/ Bankmap bank[12]; 357 358 /*0x10160*/ uchar Rsvd10160[8]; 359 /*0x10168*/ void* MAR; /* Memory address register 32 bits 10.3.7/10-29 */ 360 /*0x1016C*/ ulong Rsvd1016C; 361 /*0x10170*/ ulong MAMR; /* Machine A mode register 32 bits 10.3.5/10-26 */ 362 /*0x10174*/ ulong MBMR; /* Machine B mode register 32 bits */ 363 /*0x10178*/ ulong MCMR; /* Machine C mode register 32 bits */ 364 /*0x1017C*/ uchar Rsvd1017C[6]; 365 /*0x10184*/ ulong mptpr; /* Memory periodic timer prescaler 16 bits 10.3.12/10-32 */ 366 /*0x10188*/ ulong mdr; /* Memorydata register 32 bits 10.3.6/10-28 */ 367 /*0x1018C*/ ulong Rsvd1018C; 368 /*0x10190*/ ulong psdmr; /* 60x bus SDRAM mode register 32 bits 10.3.3/10-21 */ 369 /*0x10194*/ ulong lsdmr; /* Local bus SDRAM mode register 32 bits 10.3.4/10-24 */ 370 /*0x10198*/ ulong PURT; /* 60x bus-assigned UPM refresh timer 8 bits 10.3.8/10-30 */ 371 /*0x1019C*/ ulong PSRT; /* 60x bus-assigned SDRAM refresh timer 8 bits 10.3.10/10-31 */ 372 373 /*0x101A0*/ ulong LURT; /* Local bus-assigned UPM refresh timer8 bits 10.3.9/10-30 */ 374 /*0x101A4*/ ulong LSRT; /* Local bus-assigned SDRAM refresh timer 8 bits 10.3.11/10-32 */ 375 376 /*0x101A8*/ ulong immr; /* Internal memory map register 32 bits 4.3.2.7/4-34 */ 377 /*0x101AC*/ uchar Rsvd101AC[84]; 378 /* System Integration Timers */ 379 /*0x10200*/ uchar Rsvd10200[32]; 380 /*0x10220*/ ulong TMCNTSC; /* Time counter statusand control register 16 bits 4.3.2.14/4-40 */ 381 382 /*0x10224*/ ulong TMCNT; /* Time counter register 32 bits 4.3.2.15/4-41 */ 383 /*0x10228*/ ulong Rsvd10228; 384 /*0x1022C*/ ulong TMCNTAL; /* Time counter alarm register 32 bits 4.3.2.16/4-41 */ 385 /*0x10230*/ uchar Rsvd10230[0x10]; 386 /*0x10240*/ ulong PISCR; /* Periodic interrupt statusand control register 16 bits 4.3.3.1/4-42 */ 387 388 /*0x10244*/ ulong PITC; /* Periodic interrupt count register 32 bits 4.3.3.2/4-43 */ 389 /*0x10248*/ ulong PITR; /* Periodic interrupt timer register 32 bits 4.3.3.3/4-44 */ 390 /*0x1024C*/ uchar Rsvd1024C[94]; 391 /*0x102AA*/ uchar Rsvd102AA[2390]; 392 393 /* Interrupt Controller */ 394 /*0x10C00*/ ushort sicr; /* SIU interrupt configuration register 16 bits 4.3.1.1/4-17 */ 395 /*0x10C02*/ ushort Rsvd10C02; 396 /*0x10C04*/ ulong sivec; /* SIU interrupt vector register 32 bits 4.3.1.6/4-23 */ 397 /*0x10C08*/ ulong sipnr_h; /* SIU interrupt pending register(high) 32 bits 4.3.1.4/4-21 */ 398 /*0x10C0C*/ ulong sipnr_l; /* SIU interrupt pending register(low) 32 bits 4.3.1.4/4-21 */ 399 /*0x10C10*/ ulong siprr; /* SIU interrupt priority register 32 bits 4.3.1.2/4-18 */ 400 /*0x10C14*/ ulong scprr_h; /* CPM interrupt priority register(high) 32 bits 4.3.1.3/4-19 */ 401 /*0x10C18*/ ulong scprr_l; /* CPM interrupt priority register(low) 32 bits 4.3.1.3/4-19 */ 402 /*0x10C1C*/ ulong simr_h; /* SIU interrupt mask register(high) 32 bits 4.3.1.5/4-22 */ 403 /*0x10C20*/ ulong simr_l; /* SIU interrupt mask register(low) 32 bits 4.3.1.5/4-22 */ 404 /*0x10C24*/ ulong siexr; /* SIUexternal interrupt control register 32 bits 4.3.1.7/4-24 */ 405 /*0x10C28*/ uchar Rsvd10C28[88]; 406 407 /* Clocks and Reset */ 408 /*0x10C80*/ ulong sccr; /* System clock control register 32 bits 9.8/9-8 */ 409 /*0x10C84*/ uchar Rsvd10C84[4]; 410 /*0x10C88*/ ulong scmr; /* System clock mode register 32 bits 9.9/9-9 */ 411 /*0x10C8C*/ uchar Rsvd10C8C[4]; 412 /*0x10C90*/ ulong rsr; /* Reset status register 32 bits 5.2/5-4 */ 413 /*0x10C94*/ ulong rmr; /* Reset mode register 32 bits 5.3/5-5 */ 414 /*0x10C98*/ uchar Rsvd10C98[104]; 415 416 /* Part I.Overview Input/Output Port */ 417 /*0x10D00*/ Port port[4]; 418 419 /* CPMTimers */ 420 /*0x10D80*/ uchar tgcr1; /* Timer1 and timer2 global configuration register 8 bits 17.2.2/17-4 */ 421 422 /*0x10D81*/ uchar Rsvd10D81[3]; 423 /*0x10D84*/ uchar tgcr2; /* Timer3 and timer4 global configuration register 8 bits 17.2.2/17-4 */ 424 /*0x10D85*/ uchar Rsvd10D85[3]; 425 426 /*0x10D88*/ uchar Rsvd10D88[8]; 427 /*0x10D90*/ ushort tmr1; /* Timer1 mode register 16 bits 17.2.3/17-6 */ 428 /*0x10D92*/ ushort tmr2; /* Timer2 mode register 16 bits 17.2.3/17-6 */ 429 union{ 430 struct { 431 /*0x10D94*/ ushort trr1; /* Timer1 reference register 16 bits 17.2.4/17-7 */ 432 /*0x10D96*/ ushort trr2; /* Timer2 reference register 16 bits 17.2.4/17-7 */ 433 }; 434 /*0x10D94*/ ulong trrl1; /* Combined Timer 1/2 trr register */ 435 }; 436 union{ 437 struct { 438 /*0x10D98*/ ushort tcr1; /* Timer1 capture register 16 bits 17.2.5/17-8 */ 439 /*0x10D9A*/ ushort tcr2; /* Timer2 capture register 16 bits 17.2.5/17-8 */ 440 }; 441 /*0x10D98*/ ulong tcrl1; /* Combined timer1/2 capture register */ 442 }; 443 union{ 444 struct { 445 /*0x10D9C*/ ushort tcn1; /* Timer1 counter 16 bits 17.2.6/17-8 */ 446 /*0x10D9E*/ ushort tcn2; /* Timer2 counter 16 bits 17.2.6/17-8 */ 447 }; 448 /*0x10D9C*/ ulong tcnl1; /* Combined timer1/2 counter */ 449 }; 450 /*0x10DA0*/ ushort tmr3; /* Timer3 mode register 16 bits 17.2.3/17-6 */ 451 /*0x10DA2*/ ushort tmr4; /* Timer4 mode register 16 bits 17.2.3/17-6 */ 452 union{ 453 struct { 454 /*0x10DA4*/ ushort trr3; /* Timer3 reference register 16 bits 17.2.4/17-7 */ 455 /*0x10DA6*/ ushort trr4; /* Timer4 reference register 16 bits 17.2.4/17-7 */ 456 }; 457 /*0x10DA4*/ ulong trrl3; 458 }; 459 union{ 460 struct { 461 /*0x10DA8*/ ushort tcr3; /* Timer3 capture register 16 bits 17.2.5/17-8 */ 462 /*0x10DAA*/ ushort tcr4; /* Timer4 capture register 16 bits 17.2.5/17-8 */ 463 }; 464 /*0x10DA8*/ ulong tcrl3; 465 }; 466 union{ 467 struct { 468 /*0x10DAC*/ ushort tcn3; /* Timer3 counter 16 bits 17.2.6/17-8 */ 469 /*0x10DAE*/ ushort tcn4; /* Timer4 counter 16 bits 17.2.6/17-8 */ 470 }; 471 /*0x10DAC*/ ulong tcnl3; 472 }; 473 /*0x10DB0*/ ushort ter1; /* Timer1 event register 16 bits 17.2.7/17-8 */ 474 /*0x10DB2*/ ushort ter2; /* Timer2 event register 16 bits 17.2.7/17-8 */ 475 /*0x10DB4*/ ushort ter3; /* Timer3 event register 16 bits 17.2.7/17-8 */ 476 /*0x10DB6*/ ushort ter4; /* Timer4 event register 16 bits 17.2.7/17-8 */ 477 /*0x10DB8*/ uchar Rsvd10DB8[608]; 478 479 /* SDMADHGeneral */ 480 /*0x11018*/ uchar sdsr; /* SDMA status register 8 bits 18.2.1/18-3 */ 481 /*0x11019*/ uchar Rsvd11019[3]; 482 /*0x1101C*/ uchar sdmr; /* SDMA mask register 8 bits 18.2.2/18-4 */ 483 /*0x1101D*/ uchar Rsvd1101D[3]; 484 485 /* IDMA */ 486 /*0x11020*/ IDMA idma[4]; 487 488 /*0x11040*/ uchar Rsvd11040[704]; 489 490 /*0x11300*/ FCC fcc[3]; 491 492 /*0x11360*/ uchar Rsvd11360[0x290]; 493 494 /* BRGs5DH8 */ 495 /*0x115F0*/ ulong BRGC5; /* BRG5 configuration register 32 bits 16.1/16-2 */ 496 /*0x115F4*/ ulong BRGC6; /* BRG6configuration register 32 bits */ 497 /*0x115F8*/ ulong BRGC7; /* BRG7configuration register 32 bits */ 498 /*0x115FC*/ ulong BRGC8; /* BRG8configuration register 32 bits */ 499 /*0x11600*/ uchar Rsvd11600[0x260]; 500 /*0x11860*/ uchar I2MOD; /* I2C mode register 8 bits 34.4.1/34-6 */ 501 /*0x11861*/ uchar Rsvd11861[3]; 502 /*0x11864*/ uchar I2ADD; /* I2C address register 8 bits 34.4.2/34-7 */ 503 /*0x11865*/ uchar Rsvd11865[3]; 504 /*0x11868*/ uchar I2BRG; /* I2C BRG register 8 bits 34.4.3/34-7 */ 505 /*0x11869*/ uchar Rsvd11869[3]; 506 /*0x1186C*/ uchar I2COM; /* I2C command register 8 bits 34.4.5/34-8 */ 507 /*0x1186D*/ uchar Rsvd1186D[3]; 508 /*0x11870*/ uchar I2CER; /* I2C event register 8 bits 34.4.4/34-8 */ 509 /*0x11871*/ uchar Rsvd11871[3]; 510 /*0x11874*/ uchar I2CMR; /* I2C mask register 8 bits 34.4.4/34-8 */ 511 /*0x11875*/ uchar Rsvd11875[331]; 512 513 /* Communications Processor */ 514 /*0x119C0*/ ulong cpcr; /* Communications processor command register 32 bits 13.4.1/13-11 */ 515 516 /*0x119C4*/ ulong rccr; /* CP configuration register 32 bits 13.3.6/13-7 */ 517 /*0x119C8*/ uchar Rsvd119C8[14]; 518 /*0x119D6*/ ushort rter; /* CP timers event register 16 bits 13.6.4/13-21 */ 519 /*0x119D8*/ ushort Rsvd119D8; 520 /*0x119DA*/ ushort rtmr; /* CP timers mask register 16 bits */ 521 /*0x119DC*/ ushort rtscr; /* CPtime-stamp timer control register 16 bits 13.3.7/13-9 */ 522 /*0x119DE*/ ushort Rsvd119DE; 523 /*0x119E0*/ ulong rtsr; /* CPtime-stamp register 32 bits 13.3.8/13-10 */ 524 /*0x119E4*/ uchar Rsvd119E4[12]; 525 526 /*0x119F0*/ ulong brgc[4]; /* BRG configuration registers 32 bits 16.1/16-2 */ 527 528 /*0x11A00*/ SCC scc[4]; 529 530 /*0x11A80*/ SMC smc[2]; 531 532 SPI; 533 534 /*0x11AB0*/ uchar Rsvd11AB0[80]; 535 536 /* CPMMux */ 537 /*0x11B00*/ uchar cmxsi1cr; /* CPM mux SI1clock route register 8 bits 15.4.2/15-10 */ 538 /*0x11B01*/ uchar Rsvd11B01; 539 /*0x11B02*/ uchar cmxsi2cr; /* CPM mux SI2clock route register 8 bits 15.4.3/15-11 */ 540 /*0x11B03*/ uchar Rsvd11B03; 541 /*0x11B04*/ ulong cmxfcr; /* CPM mux FCC clock route register 32 bits 15.4.4/15-12 */ 542 /*0x11B08*/ ulong cmxscr; /* CPM mux SCC clock route register 32 bits 15.4.5/15-14 */ 543 /*0x11B0C*/ uchar cmxsmr; /* CPM mux SMC clock route register 8 bits 15.4.6/15-17 */ 544 /*0x11B0D*/ uchar Rsvd11B0D; 545 /*0x11B0E*/ ushort cmxuar; /* CPM mux UTOPIA address register 16 bits 15.4.1/15-7 */ 546 /*0x11B10*/ uchar Rsvd11B10[16]; 547 548 SI si1; /* SI 1 Registers */ 549 550 /* MCC1Registers */ 551 /*0x11B30*/ ushort MCCE1; /* MCC1 event register 16 bits 27.10.1/27-18 */ 552 /*0x11B32*/ ushort Rsvd11B32; 553 /*0x11B34*/ ushort MCCM1; /* MCC1 mask register 16 bits */ 554 /*0x11B36*/ ushort Rsvd11B36; 555 /*0x11B38*/ uchar MCCF1; /* MCC1 configuration register 8 bits 27.8/27-15 */ 556 /*0x11B39*/ uchar Rsvd11B39[7]; 557 558 SI si2; /* SI 2 Registers */ 559 560 /* MCC2Registers */ 561 /*0x11B50*/ ushort MCCE2; /* MCC2 event register 16 bits 27.10.1/27-18 */ 562 /*0x11B52*/ ushort Rsvd11B52; 563 /*0x11B54*/ ushort MCCM2; /* MCC2 mask register 16 bits */ 564 /*0x11B56*/ ushort Rsvd11B56; 565 /*0x11B58*/ uchar MCCF2; /* MCC2 configuration register 8 bits 27.8/27-15 */ 566 /*0x11B59*/ uchar Rsvd11B59[1191]; 567 568 /* SI1RAM */ 569 /*0x12000*/ uchar SI1TxRAM[0x200];/* SI1 transmit routing RAM 512 14.4.3/14-10 */ 570 /*0x12200*/ uchar Rsvd12200[0x200]; 571 /*0x12400*/ uchar SI1RxRAM[0x200];/* SI1 receive routing RAM 512 14.4.3/14-10 */ 572 /*0x12600*/ uchar Rsvd12600[0x200]; 573 574 /* SI2RAM */ 575 /*0x12800*/ uchar SI2TxRAM[0x200];/* SI2 transmit routing RAM 512 14.4.3/14-10 */ 576 /*0x12A00*/ uchar Rsvd12A00[0x200]; 577 /*0x12C00*/ uchar SI2RxRAM[0x200];/* SI2 receive routing RAM 512 14.4.3/14-10 */ 578 /*0x12E00*/ uchar Rsvd12E00[0x200]; 579 /*0x13000*/ uchar Rsvd13000[0x800]; 580 /*0x13800*/ uchar Rsvd13800[0x800]; 581 }; 582 583 typedef struct FCCextra FCCextra; 584 struct FCCextra { 585 /*0x00*/ uchar ri[0x20]; 586 /*0x20*/ uchar ti[0x20]; 587 /*0x40*/ uchar pad[0x20]; 588 }; 589 590 typedef struct IMM IMM; 591 struct IMM { 592 /* CPMDual-Port RAM */ 593 /*0x00000*/ uchar dpram1[0x3800]; /* Dual-port RAM 16Kbytes 13.5/13-15 */ 594 /*0x03800*/ FCCextra fccextra[4]; 595 /*0x03980*/ Uartsmc uartsmc[2]; 596 /*0x03a00*/ uchar dsp1p[0x40]; 597 /*0x03a40*/ uchar dsp2p[0x40]; 598 /*0x03a80*/ BD bd[(0x04000-0x03a80)/sizeof(BD)]; /* Buffer descriptors */ 599 /*0x04000*/ uchar Rsvd4000[0x04000]; 600 601 /* Dual port RAM bank 2 -- Parameter Ram, Section 13.5 */ 602 /*0x08000*/ PrmSCC prmscc[4]; 603 /*0x08400*/ PrmFCC prmfcc[3]; 604 /*0x08700*/ Bases param[4]; 605 /*0x08b00*/ uchar dpram2[0x500]; 606 607 /*0x09000*/ uchar Rsvd9000[0x2000]; 608 609 /* Dual port RAM bank 3 -- Section 13.5 */ 610 /*0x0B000*/ uchar dpram3[0x1000]; /* Dual-port RAM 4Kbytes 13.5/13-15 */ 611 /*0x0C000*/ uchar Rsvdc000[0x4000]; 612 613 /*0x10000*/ RegMap; 614 }; 615 616 enum { 617 /* CPM Command register. */ 618 cpm_rst = 0x80000000, 619 cpm_page = 0x7c000000, 620 cpm_sblock = 0x03e00000, 621 cpm_flg = 0x00010000, 622 cpm_mcn = 0x00003fc0, 623 cpm_opcode = 0x0000000f, 624 625 /* Device sub-block and page codes. */ 626 cpm_fcc1_sblock = 0x10, 627 cpm_fcc2_sblock = 0x11, 628 cpm_fcc3_sblock = 0x12, 629 cpm_scc1_sblock = 0x04, 630 cpm_scc2_sblock = 0x05, 631 cpm_scc3_sblock = 0x06, 632 cpm_scc4_sblock = 0x07, 633 cpm_smc1_sblock = 0x08, 634 cpm_smc2_sblock = 0x09, 635 cpm_rand_sblock = 0x0e, 636 cpm_spi_sblock = 0x0a, 637 cpm_i2c_sblock = 0x0b, 638 cpm_timer_sblock = 0x0f, 639 cpm_mcc1_sblock = 0x1c, 640 cpm_mcc2_sblock = 0x1d, 641 cpm_idma1_sblock = 0x14, 642 cpm_idma2_sblock = 0x15, 643 cpm_idma3_sblock = 0x16, 644 cpm_idma4_sblock = 0x17, 645 646 cpm_scc1_page = 0x00, 647 cpm_scc2_page = 0x01, 648 cpm_scc3_page = 0x02, 649 cpm_scc4_page = 0x03, 650 cpm_smc1_page = 0x07, 651 cpm_smc2_page = 0x08, 652 cpm_spi_page = 0x09, 653 cpm_i2c_page = 0x0a, 654 cpm_timer_page = 0x0a, 655 cpm_rand_page = 0x0a, 656 cpm_fcc1_page = 0x04, 657 cpm_fcc2_page = 0x05, 658 cpm_fcc3_page = 0x06, 659 cpm_idma1_page = 0x07, 660 cpm_idma2_page = 0x08, 661 cpm_idma3_page = 0x09, 662 cpm_idma4_page = 0x0a, 663 cpm_mcc1_page = 0x07, 664 cpm_mcc2_page = 0x08, 665 666 }; 667 668 /* 669 * CPM 670 */ 671 enum { 672 /* commands */ 673 InitRxTx = 0, 674 InitRx = 1, 675 InitTx = 2, 676 EnterHunt= 3, 677 StopTx= 4, 678 GracefulStopTx = 5, 679 InitIDMA = 5, 680 RestartTx = 6, 681 CloseRxBD = 7, 682 SetGroupAddr = 8, 683 SetTimer = 8, 684 GCITimeout = 9, 685 GCIAbort = 10, 686 StopIDMA = 11, 687 StartDSP = 12, 688 ArmIDMA = 13, 689 InitDSP = 13, 690 USBCmd = 15, 691 692 /* channel IDs */ 693 SCC1ID= cpm_scc1_page << 5 | cpm_scc1_sblock, 694 SCC2ID= cpm_scc2_page << 5 | cpm_scc2_sblock, 695 SCC3ID= cpm_scc3_page << 5 | cpm_scc3_sblock, 696 SMC1ID= cpm_smc1_page << 5 | cpm_smc1_sblock, 697 SMC2ID= cpm_smc2_page << 5 | cpm_smc2_sblock, 698 FCC1ID= cpm_fcc1_page << 5 | cpm_fcc1_sblock, 699 FCC2ID= cpm_fcc2_page << 5 | cpm_fcc2_sblock, 700 FCC3ID= cpm_fcc3_page << 5 | cpm_fcc3_sblock, 701 // USBID= 0, These are wrong 702 // I2CID= 1, 703 // IDMA1ID= 1, 704 // SPIID= 5, 705 // IDMA2ID= 5, 706 // TIMERID= 5, 707 // DSP1ID=9, 708 // SCC4ID= 10, 709 // DSP2ID= 13, 710 711 /* sicr */ 712 BRG1 = 0, 713 BRG2 = 1, 714 BRG3 = 2, 715 BRG4 = 4, 716 CLK1 = 4, 717 CLK2 = 5, 718 CLK3 = 6, 719 CLK4 = 7, 720 721 }; 722 723 extern IMM* imm; 724 extern int uartsmcoffset[]; 725 726 BD* bdalloc(int); 727 void cpmop(int, int, int); 728 void ioplock(void); 729 void iopunlock(void); 730 void kreboot(ulong); 731