1 /* $NetBSD: ifpga_io.c,v 1.15 2023/04/21 14:58:34 skrll Exp $ */
2
3 /*
4 * Copyright (c) 1997 Causality Limited
5 * Copyright (c) 1997 Mark Brinicombe.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Mark Brinicombe
19 * for the NetBSD Project.
20 * 4. The name of the company nor the name of the author may be used to
21 * endorse or promote products derived from this software without specific
22 * prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * From arm/footbridge/footbridge_io.c
37 */
38
39 /*
40 * bus_space I/O functions for IFPGA
41 */
42
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: ifpga_io.c,v 1.15 2023/04/21 14:58:34 skrll Exp $");
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/bus.h>
49 #include <uvm/uvm_extern.h>
50
51 #include <evbarm/ifpga/ifpgavar.h>
52 #include <evbarm/ifpga/ifpgamem.h>
53
54 /* Proto types for all the bus_space structure functions */
55
56 bs_protos(ifpga);
57 bs_protos(generic);
58 bs_protos(generic_armv4);
59 bs_protos(bs_notimpl);
60 bs_map_proto(ifpga_mem);
61 bs_unmap_proto(ifpga_mem);
62
63 /* Declare the ifpga bus space tag */
64
65 struct bus_space ifpga_bs_tag = {
66 /* cookie */
67 .bs_cookie = (void *) 0, /* Physical base address */
68
69 /* mapping/unmapping */
70 .bs_map = ifpga_bs_map,
71 .bs_unmap = ifpga_bs_unmap,
72 .bs_subregion = ifpga_bs_subregion,
73
74 /* allocation/deallocation */
75 .bs_alloc = ifpga_bs_alloc,
76 .bs_free = ifpga_bs_free,
77
78 /* get kernel virtual address */
79 .bs_vaddr = ifpga_bs_vaddr,
80
81 /* mmap */
82 .bs_mmap = bs_notimpl_bs_mmap,
83
84 /* barrier */
85 .bs_barrier = ifpga_bs_barrier,
86
87 /* read (single) */
88 .bs_r_1 = generic_bs_r_1,
89 .bs_r_2 = generic_armv4_bs_r_2,
90 .bs_r_4 = generic_bs_r_4,
91 .bs_r_8 = bs_notimpl_bs_r_8,
92
93 /* read multiple */
94 .bs_rm_1 = generic_bs_rm_1,
95 .bs_rm_2 = generic_armv4_bs_rm_2,
96 .bs_rm_4 = generic_bs_rm_4,
97 .bs_rm_8 = bs_notimpl_bs_rm_8,
98
99 /* read region */
100 .bs_rr_1 = bs_notimpl_bs_rr_1,
101 .bs_rr_2 = generic_armv4_bs_rr_2,
102 .bs_rr_4 = generic_bs_rr_4,
103 .bs_rr_8 = bs_notimpl_bs_rr_8,
104
105 /* write (single) */
106 .bs_w_1 = generic_bs_w_1,
107 .bs_w_2 = generic_armv4_bs_w_2,
108 .bs_w_4 = generic_bs_w_4,
109 .bs_w_8 = bs_notimpl_bs_w_8,
110
111 /* write multiple */
112 .bs_wm_1 = generic_bs_wm_1,
113 .bs_wm_2 = generic_armv4_bs_wm_2,
114 .bs_wm_4 = generic_bs_wm_4,
115 .bs_wm_8 = bs_notimpl_bs_wm_8,
116
117 /* write region */
118 .bs_wr_1 = bs_notimpl_bs_wr_1,
119 .bs_wr_2 = generic_armv4_bs_wr_2,
120 .bs_wr_4 = generic_bs_wr_4,
121 .bs_wr_8 = bs_notimpl_bs_wr_8,
122
123 /* set multiple */
124 .bs_sm_1 = bs_notimpl_bs_sm_1,
125 .bs_sm_2 = bs_notimpl_bs_sm_2,
126 .bs_sm_4 = bs_notimpl_bs_sm_4,
127 .bs_sm_8 = bs_notimpl_bs_sm_8,
128
129 /* set region */
130 .bs_sr_1 = bs_notimpl_bs_sr_1,
131 .bs_sr_2 = generic_armv4_bs_sr_2,
132 .bs_sr_4 = bs_notimpl_bs_sr_4,
133 .bs_sr_8 = bs_notimpl_bs_sr_8,
134
135 /* copy */
136 .bs_c_1 = bs_notimpl_bs_c_1,
137 .bs_c_2 = generic_armv4_bs_c_2,
138 .bs_c_4 = bs_notimpl_bs_c_4,
139 .bs_c_8 = bs_notimpl_bs_c_8,
140 };
141
142 /* This is a preinitialized version of ifpga_bs_tag */
143
144 struct bus_space ifpga_common_bs_tag = {
145 /* cookie */
146 .bs_cookie = (void *) IFPGA_IO_BASE, /* Physical base address */
147
148 /* mapping/unmapping */
149 .bs_map = ifpga_mem_bs_map,
150 .bs_unmap = ifpga_mem_bs_unmap,
151 .bs_subregion = ifpga_bs_subregion,
152
153 /* allocation/deallocation */
154 .bs_alloc = ifpga_bs_alloc,
155 .bs_free = ifpga_bs_free,
156
157 /* get kernel virtual address */
158 .bs_vaddr = ifpga_bs_vaddr,
159
160 /* mmap */
161 .bs_mmap = bs_notimpl_bs_mmap,
162
163 /* barrier */
164 .bs_barrier = ifpga_bs_barrier,
165
166 /* read (single) */
167 .bs_r_1 = generic_bs_r_1,
168 .bs_r_2 = generic_armv4_bs_r_2,
169 .bs_r_4 = generic_bs_r_4,
170 .bs_r_8 = bs_notimpl_bs_r_8,
171
172 /* read multiple */
173 .bs_rm_1 = generic_bs_rm_1,
174 .bs_rm_2 = generic_armv4_bs_rm_2,
175 .bs_rm_4 = generic_bs_rm_4,
176 .bs_rm_8 = bs_notimpl_bs_rm_8,
177
178 /* read region */
179 .bs_rr_1 = bs_notimpl_bs_rr_1,
180 .bs_rr_2 = generic_armv4_bs_rr_2,
181 .bs_rr_4 = generic_bs_rr_4,
182 .bs_rr_8 = bs_notimpl_bs_rr_8,
183
184 /* write (single) */
185 .bs_w_1 = generic_bs_w_1,
186 .bs_w_2 = generic_armv4_bs_w_2,
187 .bs_w_4 = generic_bs_w_4,
188 .bs_w_8 = bs_notimpl_bs_w_8,
189
190 /* write multiple */
191 .bs_wm_1 = generic_bs_wm_1,
192 .bs_wm_2 = generic_armv4_bs_wm_2,
193 .bs_wm_4 = generic_bs_wm_4,
194 .bs_wm_8 = bs_notimpl_bs_wm_8,
195
196 /* write region */
197 .bs_wr_1 = bs_notimpl_bs_wr_1,
198 .bs_wr_2 = generic_armv4_bs_wr_2,
199 .bs_wr_4 = generic_bs_wr_4,
200 .bs_wr_8 = bs_notimpl_bs_wr_8,
201
202 /* set multiple */
203 .bs_sm_1 = bs_notimpl_bs_sm_1,
204 .bs_sm_2 = bs_notimpl_bs_sm_2,
205 .bs_sm_4 = bs_notimpl_bs_sm_4,
206 .bs_sm_8 = bs_notimpl_bs_sm_8,
207
208 /* set region */
209 .bs_sr_1 = bs_notimpl_bs_sr_1,
210 .bs_sr_2 = generic_armv4_bs_sr_2,
211 .bs_sr_4 = bs_notimpl_bs_sr_4,
212 .bs_sr_8 = bs_notimpl_bs_sr_8,
213
214 /* copy */
215 .bs_c_1 = bs_notimpl_bs_c_1,
216 .bs_c_2 = generic_armv4_bs_c_2,
217 .bs_c_4 = bs_notimpl_bs_c_4,
218 .bs_c_8 = bs_notimpl_bs_c_8,
219 };
220
221 void
ifpga_create_io_bs_tag(struct bus_space * t,void * cookie)222 ifpga_create_io_bs_tag(struct bus_space *t, void *cookie)
223 {
224 *t = ifpga_bs_tag;
225 t->bs_cookie = cookie;
226 }
227
228 void
ifpga_create_mem_bs_tag(struct bus_space * t,void * cookie)229 ifpga_create_mem_bs_tag(struct bus_space *t, void *cookie)
230 {
231 *t = ifpga_bs_tag;
232 t->bs_map = ifpga_mem_bs_map;
233 t->bs_unmap = ifpga_mem_bs_unmap;
234 t->bs_cookie = cookie;
235 }
236
237 /* bus space functions */
238
239 int
ifpga_bs_map(void * t,bus_addr_t bpa,bus_size_t size,int cacheable,bus_space_handle_t * bshp)240 ifpga_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
241 {
242 /* The cookie is the base address for the I/O area */
243 *bshp = bpa + (bus_addr_t)t;
244 return 0;
245 }
246
247 int
ifpga_mem_bs_map(void * t,bus_addr_t bpa,bus_size_t size,int cacheable,bus_space_handle_t * bshp)248 ifpga_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int cacheable, bus_space_handle_t *bshp)
249 {
250 bus_addr_t startpa, endpa;
251 vaddr_t va;
252 const struct pmap_devmap *pd;
253 bus_addr_t pa = bpa + (bus_addr_t) t;
254
255 if ((pd = pmap_devmap_find_pa(pa, size)) != NULL) {
256 /* Device was statically mapped. */
257 *bshp = pd->pd_va + (pa - pd->pd_pa);
258 return 0;
259 }
260
261 /* Round the allocation to page boundaries */
262 startpa = trunc_page(bpa);
263 endpa = round_page(bpa + size);
264
265 /* Get some VM. */
266 va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
267 UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
268 if (va == 0)
269 return ENOMEM;
270
271 /* Store the bus space handle */
272 *bshp = va + (bpa & PGOFSET);
273
274 /* Now map the pages */
275 /* The cookie is the physical base address for the I/O area */
276 while (startpa < endpa) {
277 /* XXX pmap_kenter_pa maps pages cacheable -- not what
278 we want. */
279 pmap_enter(pmap_kernel(), va, (bus_addr_t)t + startpa,
280 VM_PROT_READ | VM_PROT_WRITE, 0);
281 va += PAGE_SIZE;
282 startpa += PAGE_SIZE;
283 }
284 pmap_update(pmap_kernel());
285
286 return 0;
287 }
288
289 int
ifpga_bs_alloc(void * t,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t alignment,bus_size_t boundary,int cacheable,bus_addr_t * bpap,bus_space_handle_t * bshp)290 ifpga_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend, bus_size_t size,
291 bus_size_t alignment, bus_size_t boundary, int cacheable,
292 bus_addr_t *bpap, bus_space_handle_t *bshp)
293 {
294 panic("ifpga_alloc(): Help!");
295 }
296
297
298 void
ifpga_bs_unmap(void * t,bus_space_handle_t bsh,bus_size_t size)299 ifpga_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
300 {
301 /* Nothing to do for an io map. */
302 }
303
304 void
ifpga_mem_bs_unmap(void * t,bus_space_handle_t bsh,bus_size_t size)305 ifpga_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
306 {
307 vaddr_t startva, endva;
308
309 if (pmap_devmap_find_va(bsh, size) != NULL) {
310 /* Device was statically mapped; nothing to do. */
311 return;
312 }
313
314 startva = trunc_page(bsh);
315 endva = round_page(bsh + size);
316
317 pmap_remove(pmap_kernel(), startva, endva);
318 pmap_update(pmap_kernel());
319 uvm_km_free(kernel_map, startva, endva - startva, UVM_KMF_VAONLY);
320 }
321
322 void
ifpga_bs_free(void * t,bus_space_handle_t bsh,bus_size_t size)323 ifpga_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
324 {
325
326 panic("ifpga_free(): Help!");
327 /* ifpga_bs_unmap() does all that we need to do. */
328 /* ifpga_bs_unmap(t, bsh, size);*/
329 }
330
331 int
ifpga_bs_subregion(void * t,bus_space_handle_t bsh,bus_size_t offset,bus_size_t size,bus_space_handle_t * nbshp)332 ifpga_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
333 {
334
335 *nbshp = bsh + (offset << ((int)t));
336 return (0);
337 }
338
339 void *
ifpga_bs_vaddr(void * t,bus_space_handle_t bsh)340 ifpga_bs_vaddr(void *t, bus_space_handle_t bsh)
341 {
342
343 return ((void *)bsh);
344 }
345
346 void
ifpga_bs_barrier(void * t,bus_space_handle_t bsh,bus_size_t offset,bus_size_t len,int flags)347 ifpga_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset, bus_size_t len, int flags)
348 {
349 }
350