1 /* $NetBSD: if_ie_mbmem.c,v 1.13 2021/10/24 20:00:11 andvar Exp $ */
2
3 /*
4 * Copyright (c) 1995 Charles D. Cranor
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*
29 * Converted to SUN ie driver by Charles D. Cranor,
30 * October 1994, January 1995.
31 */
32
33 /*
34 * The i82586 is a very painful chip, found in sun2's, sun3's, sun-4/100's
35 * sun-4/200's, and VME based suns. The byte order is all wrong for a
36 * SUN, making life difficult. Programming this chip is mostly the same,
37 * but certain details differ from system to system. This driver is
38 * written so that different "ie" interfaces can be controlled by the same
39 * driver.
40 */
41
42 /*
43 * programming notes:
44 *
45 * the ie chip operates in a 24 bit address space.
46 *
47 * most ie interfaces appear to be divided into two parts:
48 * - generic 586 stuff
49 * - board specific
50 *
51 * generic:
52 * the generic stuff of the ie chip is all done with data structures
53 * that live in the chip's memory address space. the chip expects
54 * its main data structure (the sys conf ptr -- SCP) to be at a fixed
55 * address in its 24 bit space: 0xfffff4
56 *
57 * the SCP points to another structure called the ISCP.
58 * the ISCP points to another structure called the SCB.
59 * the SCB has a status field, a linked list of "commands", and
60 * a linked list of "receive buffers". these are data structures that
61 * live in memory, not registers.
62 *
63 * board:
64 * to get the chip to do anything, you first put a command in the
65 * command data structure list. then you have to signal "attention"
66 * to the chip to get it to look at the command. how you
67 * signal attention depends on what board you have... on PC's
68 * there is an i/o port number to do this, on sun's there is a
69 * register bit you toggle.
70 *
71 * to get data from the chip you program it to interrupt...
72 *
73 *
74 * sun issues:
75 *
76 * there are 3 kinds of sun "ie" interfaces:
77 * 1 - a VME/multibus card
78 * 2 - an on-board interface (sun3's, sun-4/100's, and sun-4/200's)
79 * 3 - another VME board called the 3E
80 *
81 * the VME boards lives in vme16 space. only 16 and 8 bit accesses
82 * are allowed, so functions that copy data must be aware of this.
83 *
84 * the chip is an intel chip. this means that the byte order
85 * on all the "short"s in the chip's data structures is wrong.
86 * so, constants described in the intel docs are swapped for the sun.
87 * that means that any buffer pointers you give the chip must be
88 * swapped to intel format. yuck.
89 *
90 * VME/multibus interface:
91 * for the multibus interface the board ignores the top 4 bits
92 * of the chip address. the multibus interface has its own
93 * MMU like page map (without protections or valid bits, etc).
94 * there are 256 pages of physical memory on the board (each page
95 * is 1024 bytes). There are 1024 slots in the page map. so,
96 * a 1024 byte page takes up 10 bits of address for the offset,
97 * and if there are 1024 slots in the page that is another 10 bits
98 * of the address. That makes a 20 bit address, and as stated
99 * earlier the board ignores the top 4 bits, so that accounts
100 * for all 24 bits of address.
101 *
102 * Note that the last entry of the page map maps the top of the
103 * 24 bit address space and that the SCP is supposed to be at
104 * 0xfffff4 (taking into account alignment). so,
105 * for multibus, that entry in the page map has to be used for the SCP.
106 *
107 * The page map effects BOTH how the ie chip sees the
108 * memory, and how the host sees it.
109 *
110 * The page map is part of the "register" area of the board
111 *
112 * The page map to control where ram appears in the address space.
113 * We choose to have RAM start at 0 in the 24 bit address space.
114 *
115 * to get the physical address of the board's RAM you must take the
116 * top 12 bits of the physical address of the register address and
117 * or in the 4 bits from the status word as bits 17-20 (remember that
118 * the board ignores the chip's top 4 address lines). For example:
119 * if the register is @ 0xffe88000, then the top 12 bits are 0xffe00000.
120 * to get the 4 bits from the status word just do status & IEMBMEM_HADDR.
121 * suppose the value is "4". Then just shift it left 16 bits to get
122 * it into bits 17-20 (e.g. 0x40000). Then or it to get the
123 * address of RAM (in our example: 0xffe40000). see the attach routine!
124 *
125 *
126 * on-board interface:
127 *
128 * on the onboard ie interface the 24 bit address space is hardwired
129 * to be 0xff000000 -> 0xffffffff of KVA. this means that sc_iobase
130 * will be 0xff000000. sc_maddr will be where ever we allocate RAM
131 * in KVA. note that since the SCP is at a fixed address it means
132 * that we have to allocate a fixed KVA for the SCP.
133 * <fill in useful info later>
134 *
135 *
136 * VME3E interface:
137 *
138 * <fill in useful info later>
139 *
140 */
141
142 #include <sys/cdefs.h>
143 __KERNEL_RCSID(0, "$NetBSD: if_ie_mbmem.c,v 1.13 2021/10/24 20:00:11 andvar Exp $");
144
145 #include <sys/param.h>
146 #include <sys/systm.h>
147 #include <sys/errno.h>
148 #include <sys/device.h>
149 #include <sys/protosw.h>
150 #include <sys/socket.h>
151
152 #include <net/if.h>
153 #include <net/if_types.h>
154 #include <net/if_dl.h>
155 #include <net/if_media.h>
156 #include <net/if_ether.h>
157
158 #include <machine/autoconf.h>
159 #include <machine/idprom.h>
160 #include <machine/bus.h>
161 #include <machine/intr.h>
162 #include <machine/cpu.h>
163
164 #include <dev/ic/i82586reg.h>
165 #include <dev/ic/i82586var.h>
166
167 #include "locators.h"
168
169 /*
170 * VME/multibus definitions
171 */
172 #define IEMBMEM_PAGESIZE 1024 /* bytes */
173 #define IEMBMEM_PAGSHIFT 10 /* bits */
174 #define IEMBMEM_NPAGES 256 /* number of pages on chip */
175 #define IEMBMEM_MAPSZ 1024 /* number of entries in the map */
176
177 /*
178 * PTE for the page map
179 */
180 #define IEMBMEM_SBORDR 0x8000 /* sun byte order */
181 #define IEMBMEM_IBORDR 0x0000 /* intel byte order */
182
183 #define IEMBMEM_P2MEM 0x2000 /* memory is on P2 */
184 #define IEMBMEM_OBMEM 0x0000 /* memory is on board */
185
186 #define IEMBMEM_PGMASK 0x0fff /* gives the physical page frame number */
187
188 struct iembmem {
189 uint16_t pgmap[IEMBMEM_MAPSZ];
190 uint16_t xxx[32]; /* prom */
191 uint16_t status; /* see below for bits */
192 uint16_t xxx2; /* filler */
193 uint16_t pectrl; /* parity control (see below) */
194 uint16_t peaddr; /* low 16 bits of address */
195 };
196
197 /*
198 * status bits
199 */
200 #define IEMBMEM_RESET 0x8000 /* reset board */
201 #define IEMBMEM_ONAIR 0x4000 /* go out of loopback 'on-air' */
202 #define IEMBMEM_ATTEN 0x2000 /* attention */
203 #define IEMBMEM_IENAB 0x1000 /* interrupt enable */
204 #define IEMBMEM_PEINT 0x0800 /* parity error interrupt enable */
205 #define IEMBMEM_PERR 0x0200 /* parity error flag */
206 #define IEMBMEM_INT 0x0100 /* interrupt flag */
207 #define IEMBMEM_P2EN 0x0020 /* enable p2 bus */
208 #define IEMBMEM_256K 0x0010 /* 256kb rams */
209 #define IEMBMEM_HADDR 0x000f /* mask for bits 17-20 of address */
210
211 /*
212 * parity control
213 */
214 #define IEMBMEM_PARACK 0x0100 /* parity error ack */
215 #define IEMBMEM_PARSRC 0x0080 /* parity error source */
216 #define IEMBMEM_PAREND 0x0040 /* which end of the data got the error */
217 #define IEMBMEM_PARADR 0x000f /* mask to get bits 17-20 of parity address */
218
219 /* Supported media */
220 static int media[] = {
221 IFM_ETHER | IFM_10_2,
222 };
223 #define NMEDIA __arraycount(media)
224
225 /*
226 * the 3E board not supported (yet?)
227 */
228
229
230 static void ie_mbmemreset(struct ie_softc *, int);
231 static void ie_mbmemattend(struct ie_softc *, int);
232 static void ie_mbmemrun(struct ie_softc *);
233 static int ie_mbmemintr(struct ie_softc *, int);
234
235 int ie_mbmem_match(device_t, cfdata_t, void *);
236 void ie_mbmem_attach(device_t, device_t, void *);
237
238 struct ie_mbmem_softc {
239 struct ie_softc ie;
240 bus_space_tag_t ievt;
241 bus_space_handle_t ievh;
242 };
243
244 CFATTACH_DECL_NEW(ie_mbmem, sizeof(struct ie_mbmem_softc),
245 ie_mbmem_match, ie_mbmem_attach, NULL, NULL);
246
247 #define read_iev(sc, reg) \
248 bus_space_read_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg))
249 #define write_iev(sc, reg, val) \
250 bus_space_write_2(sc->ievt, sc->ievh, offsetof(struct iembmem, reg), val)
251
252 /*
253 * MULTIBUS support routines
254 */
255 void
ie_mbmemreset(struct ie_softc * sc,int what)256 ie_mbmemreset(struct ie_softc *sc, int what)
257 {
258 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
259 write_iev(vsc, status, IEMBMEM_RESET);
260 delay(100); /* XXX could be shorter? */
261 write_iev(vsc, status, 0);
262 }
263
264 void
ie_mbmemattend(struct ie_softc * sc,int why)265 ie_mbmemattend(struct ie_softc *sc, int why)
266 {
267 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
268
269 /* Flag! */
270 write_iev(vsc, status, read_iev(vsc, status) | IEMBMEM_ATTEN);
271 /* Down. */
272 write_iev(vsc, status, read_iev(vsc, status) & ~IEMBMEM_ATTEN);
273 }
274
275 void
ie_mbmemrun(struct ie_softc * sc)276 ie_mbmemrun(struct ie_softc *sc)
277 {
278 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
279
280 write_iev(vsc, status, read_iev(vsc, status)
281 | IEMBMEM_ONAIR | IEMBMEM_IENAB | IEMBMEM_PEINT);
282 }
283
284 int
ie_mbmemintr(struct ie_softc * sc,int where)285 ie_mbmemintr(struct ie_softc *sc, int where)
286 {
287 struct ie_mbmem_softc *vsc = (struct ie_mbmem_softc *)sc;
288
289 if (where != INTR_ENTER)
290 return 0;
291
292 /* check for parity error */
293 if (read_iev(vsc, status) & IEMBMEM_PERR) {
294 printf("%s: parity error (ctrl 0x%x @ 0x%02x%04x)\n",
295 device_xname(sc->sc_dev), read_iev(vsc, pectrl),
296 read_iev(vsc, pectrl) & IEMBMEM_HADDR,
297 read_iev(vsc, peaddr));
298 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK);
299 }
300 return 0;
301 }
302
303 void ie_mbmemcopyin(struct ie_softc *, void *, int, size_t);
304 void ie_mbmemcopyout(struct ie_softc *, const void *, int, size_t);
305
306 /*
307 * Copy board memory to kernel.
308 */
309 void
ie_mbmemcopyin(struct ie_softc * sc,void * p,int offset,size_t size)310 ie_mbmemcopyin(struct ie_softc *sc, void *p, int offset, size_t size)
311 {
312
313 bus_space_copyin(sc->bt, sc->bh, offset, p, size);
314 }
315
316 /*
317 * Copy from kernel space to board memory.
318 */
319 void
ie_mbmemcopyout(struct ie_softc * sc,const void * p,int offset,size_t size)320 ie_mbmemcopyout(struct ie_softc *sc, const void *p, int offset, size_t size)
321 {
322
323 bus_space_copyout(sc->bt, sc->bh, offset, p, size);
324 }
325
326 /* Read a 16-bit value at BH offset */
327 uint16_t ie_mbmem_read16(struct ie_softc *, int offset);
328 /* Write a 16-bit value at BH offset */
329 void ie_mbmem_write16(struct ie_softc *, int offset, uint16_t value);
330 void ie_mbmem_write24(struct ie_softc *, int offset, int addr);
331
332 uint16_t
ie_mbmem_read16(struct ie_softc * sc,int offset)333 ie_mbmem_read16(struct ie_softc *sc, int offset)
334 {
335 uint16_t v;
336
337 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_READ);
338 v = bus_space_read_2(sc->bt, sc->bh, offset);
339 return (((v&0xff)<<8) | ((v>>8)&0xff));
340 }
341
342 void
ie_mbmem_write16(struct ie_softc * sc,int offset,uint16_t v)343 ie_mbmem_write16(struct ie_softc *sc, int offset, uint16_t v)
344 {
345 int v0 = ((((v)&0xff)<<8) | (((v)>>8)&0xff));
346
347 bus_space_write_2(sc->bt, sc->bh, offset, v0);
348 bus_space_barrier(sc->bt, sc->bh, offset, 2, BUS_SPACE_BARRIER_WRITE);
349 }
350
351 void
ie_mbmem_write24(struct ie_softc * sc,int offset,int addr)352 ie_mbmem_write24(struct ie_softc *sc, int offset, int addr)
353 {
354 u_char *f = (u_char *)&addr;
355 uint16_t v0, v1;
356 u_char *t;
357
358 t = (u_char *)&v0;
359 t[0] = f[3]; t[1] = f[2];
360 bus_space_write_2(sc->bt, sc->bh, offset, v0);
361
362 t = (u_char *)&v1;
363 t[0] = f[1]; t[1] = 0;
364 bus_space_write_2(sc->bt, sc->bh, offset+2, v1);
365
366 bus_space_barrier(sc->bt, sc->bh, offset, 4, BUS_SPACE_BARRIER_WRITE);
367 }
368
369 int
ie_mbmem_match(device_t parent,cfdata_t cf,void * aux)370 ie_mbmem_match(device_t parent, cfdata_t cf, void *aux)
371 {
372 struct mbmem_attach_args *mbma = aux;
373 bus_space_handle_t bh;
374 int matched;
375
376 /* No default Multibus address. */
377 if (mbma->mbma_paddr == -1)
378 return 0;
379
380 /* Make sure there is something there... */
381 if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr,
382 sizeof(struct iembmem), 0, &bh))
383 return 0;
384 matched = (bus_space_peek_2(mbma->mbma_bustag, bh, 0, NULL) == 0);
385 bus_space_unmap(mbma->mbma_bustag, bh, sizeof(struct iembmem));
386 if (!matched)
387 return 0;
388
389 /* Default interrupt priority. */
390 if (mbma->mbma_pri == -1)
391 mbma->mbma_pri = 3;
392
393 return 1;
394 }
395
396 void
ie_mbmem_attach(device_t parent,device_t self,void * aux)397 ie_mbmem_attach(device_t parent, device_t self, void *aux)
398 {
399 uint8_t myaddr[ETHER_ADDR_LEN];
400 struct ie_mbmem_softc *vsc = device_private(self);
401 struct mbmem_attach_args *mbma = aux;
402 struct ie_softc *sc;
403 bus_size_t memsize;
404 bus_addr_t rampaddr;
405 int lcv;
406
407 sc = &vsc->ie;
408 sc->sc_dev = self;
409
410 sc->hwreset = ie_mbmemreset;
411 sc->hwinit = ie_mbmemrun;
412 sc->chan_attn = ie_mbmemattend;
413 sc->intrhook = ie_mbmemintr;
414 sc->memcopyout = ie_mbmemcopyout;
415 sc->memcopyin = ie_mbmemcopyin;
416
417 sc->ie_bus_barrier = NULL;
418 sc->ie_bus_read16 = ie_mbmem_read16;
419 sc->ie_bus_write16 = ie_mbmem_write16;
420 sc->ie_bus_write24 = ie_mbmem_write24;
421
422 /*
423 * There is 64K of memory on the Multibus board.
424 * (determined by hardware - NOT configurable!)
425 */
426 memsize = 0x10000; /* MEMSIZE 64K */
427
428 /* Map in the board control regs. */
429 vsc->ievt = mbma->mbma_bustag;
430 if (bus_space_map(mbma->mbma_bustag, mbma->mbma_paddr,
431 sizeof(struct iembmem), 0, &vsc->ievh))
432 panic("ie_mbmem_attach: can't map regs");
433
434 /*
435 * Find and map in the board memory.
436 */
437 /* top 12 bits */
438 rampaddr = mbma->mbma_paddr & 0xfff00000;
439 /* 4 more */
440 rampaddr = rampaddr | ((read_iev(vsc, status) & IEMBMEM_HADDR) << 16);
441 sc->bt = mbma->mbma_bustag;
442 if (bus_space_map(mbma->mbma_bustag, rampaddr, memsize, 0, &sc->bh))
443 panic("ie_mbmem_attach: can't map mem");
444
445 write_iev(vsc, pectrl, read_iev(vsc, pectrl) | IEMBMEM_PARACK);
446
447 /*
448 * Set up mappings, direct map except for last page
449 * which is mapped at zero and at high address (for scp)
450 */
451 for (lcv = 0; lcv < IEMBMEM_MAPSZ - 1; lcv++)
452 write_iev(vsc, pgmap[lcv],
453 IEMBMEM_SBORDR | IEMBMEM_OBMEM | lcv);
454 write_iev(vsc, pgmap[IEMBMEM_MAPSZ - 1],
455 IEMBMEM_SBORDR | IEMBMEM_OBMEM | 0);
456
457 /* Clear all ram */
458 bus_space_set_region_2(sc->bt, sc->bh, 0, 0, memsize/2);
459
460 /*
461 * We use the first page to set up SCP, ICSP and SCB data
462 * structures. The remaining pages become the buffer area
463 * (managed in i82586.c).
464 * SCP is in double-mapped page, so the 586 can see it at
465 * the mandatory magic address (IE_SCP_ADDR).
466 */
467 sc->scp = (IE_SCP_ADDR & (IEMBMEM_PAGESIZE - 1));
468
469 /* iscp at location zero */
470 sc->iscp = 0;
471
472 /* scb follows iscp */
473 sc->scb = IE_ISCP_SZ;
474
475 ie_mbmem_write16(sc, IE_ISCP_SCB((long)sc->iscp), sc->scb);
476 ie_mbmem_write16(sc, IE_ISCP_BASE((u_long)sc->iscp), 0);
477 ie_mbmem_write24(sc, IE_SCP_ISCP((u_long)sc->scp), 0);
478
479 if (i82586_proberam(sc) == 0) {
480 printf(": memory probe failed\n");
481 return;
482 }
483
484 /* Rest of first page is unused; rest of ram for buffers. */
485 sc->buf_area = IEMBMEM_PAGESIZE;
486 sc->buf_area_sz = memsize - IEMBMEM_PAGESIZE;
487
488 sc->do_xmitnopchain = 0;
489
490 printf("\n%s:", device_xname(self));
491
492 /* Set the ethernet address. */
493 idprom_etheraddr(myaddr);
494
495 i82586_attach(sc, "multibus", myaddr, media, NMEDIA, media[0]);
496
497 bus_intr_establish(mbma->mbma_bustag, mbma->mbma_pri, IPL_NET, 0,
498 i82586_intr, sc);
499 }
500