1 /* $NetBSD: i80312.c,v 1.26 2021/08/07 16:18:46 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Autoconfiguration support for the Intel i80312 Companion I/O chip.
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: i80312.c,v 1.26 2021/08/07 16:18:46 thorpej Exp $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/device.h>
48
49 #define _ARM32_BUS_DMA_PRIVATE
50 #include <sys/bus.h>
51
52 #include <arm/xscale/i80312reg.h>
53 #include <arm/xscale/i80312var.h>
54
55 #include <dev/pci/ppbreg.h>
56
57 /*
58 * Statically-allocated bus_space structure used to access the
59 * i80312's own registers.
60 */
61 struct bus_space i80312_bs_tag;
62
63 /*
64 * There can be only one i80312, so we keep a global pointer to
65 * the softc, so board-specific code can use features of the
66 * i80312 without having to have a handle on the softc itself.
67 */
68 struct i80312_softc *i80312_softc;
69
70 static void i80312_pci_dma_init(struct i80312_softc *);
71 static void i80312_local_dma_init(struct i80312_softc *);
72
73 static int i80312_iopxs_print(void *, const char *);
74
75 /* Built-in devices. */
76 static const struct iopxs_device {
77 const char *id_name;
78 bus_addr_t id_offset;
79 bus_size_t id_size;
80 } iopxs_devices[] = {
81 /* { "iopaau", I80312_AAU_BASE, I80312_AAU_SIZE }, */
82 /* { "iopdma", I80312_DMA_BASE0, I80312_DMA_SIZE }, */
83 /* { "iopdma", I80312_DMA_BASE1, I80312_DMA_SIZE }, */
84 { "iopiic", I80312_IIC_BASE, I80312_IIC_SIZE },
85 /* { "iopmu", I80312_MSG_BASE, I80312_MU_SIZE }, */
86 { NULL, 0, 0 }
87 };
88
89 /*
90 * i80312_attach:
91 *
92 * Board-independent attach routine for the i80312.
93 */
94 void
i80312_attach(struct i80312_softc * sc)95 i80312_attach(struct i80312_softc *sc)
96 {
97 struct pcibus_attach_args pba;
98 const struct iopxs_device *id;
99 struct iopxs_attach_args ia;
100 uint32_t atucr;
101 pcireg_t preg;
102
103 i80312_softc = sc;
104
105 /*
106 * Slice off some useful subregion handles.
107 */
108
109 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_PPB_BASE,
110 I80312_PPB_SIZE, &sc->sc_ppb_sh))
111 panic("%s: unable to subregion PPB registers",
112 device_xname(sc->sc_dev));
113
114 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_ATU_BASE,
115 I80312_ATU_SIZE, &sc->sc_atu_sh))
116 panic("%s: unable to subregion ATU registers",
117 device_xname(sc->sc_dev));
118
119 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_INTC_BASE,
120 I80312_INTC_SIZE, &sc->sc_intc_sh))
121 panic("%s: unable to subregion INTC registers",
122 device_xname(sc->sc_dev));
123
124 /* We expect the Memory Controller to be already sliced off. */
125
126 /*
127 * Disable the private space decode.
128 */
129 sc->sc_sder = bus_space_read_1(sc->sc_st, sc->sc_ppb_sh,
130 I80312_PPB_SDER);
131 sc->sc_sder &= ~PPB_SDER_PMSE;
132 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh,
133 I80312_PPB_SDER, sc->sc_sder);
134
135 /*
136 * Program the Secondary ID Select register.
137 */
138 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh,
139 I80312_PPB_SISR, sc->sc_sisr);
140
141 /*
142 * Program the private secondary bus spaces.
143 */
144 if (sc->sc_privmem_size && sc->sc_privio_size) {
145 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOBR,
146 (sc->sc_privio_base >> 12) << 4);
147 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SIOLR,
148 ((sc->sc_privio_base + sc->sc_privio_size - 1)
149 >> 12) << 4);
150
151 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMBR,
152 (sc->sc_privmem_base >> 20) << 4);
153 bus_space_write_2(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SMLR,
154 ((sc->sc_privmem_base + sc->sc_privmem_size - 1)
155 >> 20) << 4);
156
157 sc->sc_sder |= PPB_SDER_PMSE;
158 bus_space_write_1(sc->sc_st, sc->sc_ppb_sh, I80312_PPB_SDER,
159 sc->sc_sder);
160 } else if (sc->sc_privmem_size || sc->sc_privio_size) {
161 printf("%s: WARNING: privmem_size 0x%08x privio_size 0x%08x\n",
162 device_xname(sc->sc_dev), sc->sc_privmem_size,
163 sc->sc_privio_size);
164 printf("%s: private bus spaces not enabled\n",
165 device_xname(sc->sc_dev));
166 }
167
168 /*
169 * Program the Primary Inbound window.
170 */
171 if (sc->sc_is_host)
172 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
173 PCI_MAPREG_START, sc->sc_pin_base);
174 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
175 I80312_ATU_PIAL, ATU_LIMIT(sc->sc_pin_size));
176 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
177 I80312_ATU_PIATV, sc->sc_pin_xlate);
178
179 /*
180 * Program the Secondary Inbound window.
181 */
182 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
183 I80312_ATU_SIAM, sc->sc_sin_base);
184 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
185 I80312_ATU_SIAL, ATU_LIMIT(sc->sc_sin_size));
186 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
187 I80312_ATU_SIATV, sc->sc_sin_xlate);
188
189 /*
190 * Mask (disable) the ATU interrupt sources.
191 * XXX May want to revisit this if we encounter
192 * XXX an application that wants it.
193 */
194 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
195 I80312_ATU_PAIM,
196 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM |
197 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM |
198 ATU_AIM_PSTIM);
199 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
200 I80312_ATU_SAIM,
201 ATU_AIM_MPEIM | ATU_AIM_TATIM | ATU_AIM_TAMIM |
202 ATU_AIM_MAIM | ATU_AIM_SAIM | ATU_AIM_DPEIM);
203
204 /*
205 * Clear:
206 *
207 * Primary Outbound ATU Enable
208 * Secondary Outbound ATU Enable
209 * Secondary Direct Addressing Select
210 * Direct Addressing Enable
211 */
212 atucr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR);
213 atucr &= ~(ATU_ACR_POAE|ATU_ACR_SOAE|ATU_ACR_SDAS|ATU_ACR_DAE);
214
215 /*
216 * Program the Primary Outbound windows.
217 */
218 if (sc->sc_pmemout_size)
219 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
220 I80312_ATU_POMWV, sc->sc_pmemout_base);
221 if (sc->sc_pioout_size)
222 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
223 I80312_ATU_POIOWV, sc->sc_pioout_base);
224 if (sc->sc_pmemout_size || sc->sc_pioout_size)
225 atucr |= ATU_ACR_POAE;
226
227 /*
228 * Program the Secondary Outbound windows.
229 */
230 if (sc->sc_smemout_size)
231 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
232 I80312_ATU_SOMWV, sc->sc_smemout_base);
233 if (sc->sc_sioout_size)
234 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
235 I80312_ATU_SOIOWV, sc->sc_sioout_base);
236 if (sc->sc_smemout_size || sc->sc_sioout_size)
237 atucr |= ATU_ACR_SOAE;
238
239 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, I80312_ATU_ACR, atucr);
240
241 /*
242 * Enable bus mastering, memory access, SERR, and parity
243 * checking on the ATU.
244 */
245 if (sc->sc_is_host) {
246 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
247 PCI_COMMAND_STATUS_REG);
248 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
249 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
250 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
251 PCI_COMMAND_STATUS_REG, preg);
252 }
253 preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
254 I80312_ATU_SACS);
255 preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
256 PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
257 bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
258 I80312_ATU_SACS, preg);
259
260 /*
261 * Configure the bridge. If we're a host, set the primary
262 * bus to bus #0 and the secondary bus to bus #1. We also
263 * set the PPB's subordinate bus # to 1. It will be fixed
264 * up later when we fully configure the bus.
265 *
266 * If we're a slave, just use the bus #'s that the host
267 * provides.
268 */
269 if (sc->sc_is_host) {
270 bus_space_write_4(sc->sc_st, sc->sc_ppb_sh,
271 PCI_BRIDGE_BUS_REG,
272 __SHIFTIN(0, PCI_BRIDGE_BUS_PRIMARY) |
273 __SHIFTIN(1, PCI_BRIDGE_BUS_SECONDARY) |
274 __SHIFTIN(1, PCI_BRIDGE_BUS_SUBORDINATE));
275 }
276
277 /* Initialize the bus space tags. */
278 i80312_io_bs_init(&sc->sc_pci_iot, sc);
279 i80312_mem_bs_init(&sc->sc_pci_memt, sc);
280
281 /* Initialize the PCI chipset tag. */
282 i80312_pci_init(&sc->sc_pci_chipset, sc);
283
284 /* Initialize the DMA tags. */
285 i80312_pci_dma_init(sc);
286 i80312_local_dma_init(sc);
287
288 /*
289 * Attach all the IOP built-ins.
290 */
291 for (id = iopxs_devices; id->id_name != NULL; id++) {
292 ia.ia_name = id->id_name;
293 ia.ia_st = sc->sc_st;
294 ia.ia_sh = sc->sc_sh;
295 ia.ia_dmat = &sc->sc_local_dmat;
296 ia.ia_offset = id->id_offset;
297 ia.ia_size = id->id_size;
298
299 config_found(sc->sc_dev, &ia, i80312_iopxs_print,
300 CFARGS(.iattr = "iopxs"));
301 }
302
303 /*
304 * Attach the PCI bus.
305 *
306 * Note: We only probe the Secondary PCI bus, since that
307 * is the only bus on which we can have a private device
308 * space.
309 */
310 preg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
311 pba.pba_iot = &sc->sc_pci_iot;
312 pba.pba_memt = &sc->sc_pci_memt;
313 pba.pba_dmat = &sc->sc_pci_dmat;
314 pba.pba_dmat64 = NULL;
315 pba.pba_pc = &sc->sc_pci_chipset;
316 pba.pba_bus = PCI_BRIDGE_BUS_NUM_SECONDARY(preg);
317 pba.pba_bridgetag = NULL;
318 pba.pba_intrswiz = 3;
319 pba.pba_intrtag = 0;
320 /* XXX MRL/MRM/MWI seem to have problems, at the moment. */
321 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY /* |
322 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY */;
323 config_found(sc->sc_dev, &pba, pcibusprint,
324 CFARGS(.iattr = "pcibus"));
325 }
326
327 /*
328 * i80312_iopxs_print:
329 *
330 * Autoconfiguration cfprint routine when attaching
331 * to the "iopxs" device.
332 */
333 static int
i80312_iopxs_print(void * aux,const char * pnp)334 i80312_iopxs_print(void *aux, const char *pnp)
335 {
336
337 return (QUIET);
338 }
339
340 /*
341 * i80312_pci_dma_init:
342 *
343 * Initialize the PCI DMA tag.
344 */
345 static void
i80312_pci_dma_init(struct i80312_softc * sc)346 i80312_pci_dma_init(struct i80312_softc *sc)
347 {
348 bus_dma_tag_t dmat = &sc->sc_pci_dmat;
349 struct arm32_dma_range *dr = &sc->sc_pci_dma_range;
350
351 dr->dr_sysbase = sc->sc_sin_xlate;
352 dr->dr_busbase = sc->sc_sin_base;
353 dr->dr_len = sc->sc_sin_size;
354
355 dmat->_ranges = dr;
356 dmat->_nranges = 1;
357
358 dmat->_dmamap_create = _bus_dmamap_create;
359 dmat->_dmamap_destroy = _bus_dmamap_destroy;
360 dmat->_dmamap_load = _bus_dmamap_load;
361 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
362 dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
363 dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
364 dmat->_dmamap_unload = _bus_dmamap_unload;
365 dmat->_dmamap_sync_pre = _bus_dmamap_sync;
366 dmat->_dmamap_sync_post = NULL;
367
368 dmat->_dmamem_alloc = _bus_dmamem_alloc;
369 dmat->_dmamem_free = _bus_dmamem_free;
370 dmat->_dmamem_map = _bus_dmamem_map;
371 dmat->_dmamem_unmap = _bus_dmamem_unmap;
372 dmat->_dmamem_mmap = _bus_dmamem_mmap;
373
374 dmat->_dmatag_subregion = _bus_dmatag_subregion;
375 dmat->_dmatag_destroy = _bus_dmatag_destroy;
376 }
377
378 /*
379 * i80312_local_dma_init:
380 *
381 * Initialize the local DMA tag.
382 */
383 static void
i80312_local_dma_init(struct i80312_softc * sc)384 i80312_local_dma_init(struct i80312_softc *sc)
385 {
386 bus_dma_tag_t dmat = &sc->sc_local_dmat;
387
388 dmat->_ranges = NULL;
389 dmat->_nranges = 0;
390
391 dmat->_dmamap_create = _bus_dmamap_create;
392 dmat->_dmamap_destroy = _bus_dmamap_destroy;
393 dmat->_dmamap_load = _bus_dmamap_load;
394 dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
395 dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
396 dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
397 dmat->_dmamap_unload = _bus_dmamap_unload;
398 dmat->_dmamap_sync_pre = _bus_dmamap_sync;
399 dmat->_dmamap_sync_post = NULL;
400
401 dmat->_dmamem_alloc = _bus_dmamem_alloc;
402 dmat->_dmamem_free = _bus_dmamem_free;
403 dmat->_dmamem_map = _bus_dmamem_map;
404 dmat->_dmamem_unmap = _bus_dmamem_unmap;
405 dmat->_dmamem_mmap = _bus_dmamem_mmap;
406 }
407