1 /* $NetBSD: pim.h,v 1.3 2024/01/22 07:10:54 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matthew Fredette. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * This describes the Processor Internal Memory data for various checks. 34 * 35 * References: 36 * 37 * "PA/RISC 1.1 I/O Firmware Architecture Reference Specification", 38 * Version 1.0, August 22, 2001. 39 * 40 * "PA/RISC 2.0 I/O Firmware Architecture Reference Specification", 41 * Version 1.0, August 22, 2001. 42 */ 43 44 /* The PIM data for HPMC and TOC contains these register arrays. */ 45 struct hppa_pim_regs { 46 47 /* The general registers. */ 48 uint32_t pim_regs_r0; 49 uint32_t pim_regs_r1; 50 uint32_t pim_regs_r2; 51 uint32_t pim_regs_r3; 52 uint32_t pim_regs_r4; 53 uint32_t pim_regs_r5; 54 uint32_t pim_regs_r6; 55 uint32_t pim_regs_r7; 56 uint32_t pim_regs_r8; 57 uint32_t pim_regs_r9; 58 uint32_t pim_regs_r10; 59 uint32_t pim_regs_r11; 60 uint32_t pim_regs_r12; 61 uint32_t pim_regs_r13; 62 uint32_t pim_regs_r14; 63 uint32_t pim_regs_r15; 64 uint32_t pim_regs_r16; 65 uint32_t pim_regs_r17; 66 uint32_t pim_regs_r18; 67 uint32_t pim_regs_r19; 68 uint32_t pim_regs_r20; 69 uint32_t pim_regs_r21; 70 uint32_t pim_regs_r22; 71 uint32_t pim_regs_r23; 72 uint32_t pim_regs_r24; 73 uint32_t pim_regs_r25; 74 uint32_t pim_regs_r26; 75 uint32_t pim_regs_r27; 76 uint32_t pim_regs_r28; 77 uint32_t pim_regs_r29; 78 uint32_t pim_regs_r30; 79 uint32_t pim_regs_r31; 80 81 /* The control registers. */ 82 uint32_t pim_regs_cr0; 83 uint32_t pim_regs_cr1; 84 uint32_t pim_regs_cr2; 85 uint32_t pim_regs_cr3; 86 uint32_t pim_regs_cr4; 87 uint32_t pim_regs_cr5; 88 uint32_t pim_regs_cr6; 89 uint32_t pim_regs_cr7; 90 uint32_t pim_regs_cr8; 91 uint32_t pim_regs_cr9; 92 uint32_t pim_regs_cr10; 93 uint32_t pim_regs_cr11; 94 uint32_t pim_regs_cr12; 95 uint32_t pim_regs_cr13; 96 uint32_t pim_regs_cr14; 97 uint32_t pim_regs_cr15; 98 uint32_t pim_regs_cr16; 99 uint32_t pim_regs_cr17; 100 uint32_t pim_regs_cr18; 101 uint32_t pim_regs_cr19; 102 uint32_t pim_regs_cr20; 103 uint32_t pim_regs_cr21; 104 uint32_t pim_regs_cr22; 105 uint32_t pim_regs_cr23; 106 uint32_t pim_regs_cr24; 107 uint32_t pim_regs_cr25; 108 uint32_t pim_regs_cr26; 109 uint32_t pim_regs_cr27; 110 uint32_t pim_regs_cr28; 111 uint32_t pim_regs_cr29; 112 uint32_t pim_regs_cr30; 113 uint32_t pim_regs_cr31; 114 115 /* The space registers. */ 116 uint32_t pim_regs_sr0; 117 uint32_t pim_regs_sr1; 118 uint32_t pim_regs_sr2; 119 uint32_t pim_regs_sr3; 120 uint32_t pim_regs_sr4; 121 uint32_t pim_regs_sr5; 122 uint32_t pim_regs_sr6; 123 uint32_t pim_regs_sr7; 124 125 /* The back entries of the instruction address queues. */ 126 uint32_t pim_regs_iisq_tail; 127 uint32_t pim_regs_iioq_tail; 128 }; 129 130 /* The PIM data for HPMC and LPMC contains this check information. */ 131 struct hppa_pim_checks { 132 133 /* The Check Type. */ 134 uint32_t pim_check_type; 135 #define PIM_CHECK_CACHE (1 << 31) 136 #define PIM_CHECK_TLB (1 << 30) 137 #define PIM_CHECK_BUS (1 << 29) 138 #define PIM_CHECK_ASSISTS (1 << 28) 139 #define PIM_CHECK_BITS \ 140 "\177\020" /* New bitmask format */ \ 141 "b\037cache\0" /* bit 31 */ \ 142 "b\036tlb\0" /* bit 30 */ \ 143 "b\035bus\0" /* bit 29 */ \ 144 "b\034assists\0" /* bit 28 */ 145 146 /* 147 * The CPU State. In addition to the common PIM_CPU_ 148 * bits defined below, some fields are HPMC-specific. 149 */ 150 uint32_t pim_check_cpu_state; 151 #define PIM_CPU_IQV (1 << 31) 152 #define PIM_CPU_IQF (1 << 30) 153 #define PIM_CPU_IPV (1 << 29) 154 #define PIM_CPU_GRV (1 << 28) 155 #define PIM_CPU_CRV (1 << 27) 156 #define PIM_CPU_SRV (1 << 26) 157 #define PIM_CPU_TRV (1 << 25) 158 #define PIM_CPU_BITS \ 159 "\177\020" /* New bitmask format */ \ 160 "b\037iqv\0" /* bit 31 */ \ 161 "b\036iqf\0" /* bit 30 */ \ 162 "b\035ipv\0" /* bit 29 */ \ 163 "b\034grv\0" /* bit 28 */ \ 164 "b\033crv\0" /* bit 27 */ \ 165 "b\032srv\0" /* bit 26 */ \ 166 "b\031trv\0" /* bit 25 */ 167 #define PIM_CPU_HPMC_TL(cs) (((cs) >> 4) & 0x3) 168 #define PIM_CPU_HPMC_HD (1 << 3) 169 #define PIM_CPU_HPMC_SIS (1 << 2) 170 #define PIM_CPU_HPMC_CS(cs) ((cs) & 0x3) 171 #define PIM_CPU_HPMC_BITS \ 172 PIM_CPU_BITS \ 173 "f\004\002tl\0" /* bit 4 .. 5 */ \ 174 "b\003hd\0" /* bit 3 */ \ 175 "b\002sis\0" /* bit 2 */ \ 176 "f\000\002cs\0" /* bit 0 .. 1 */ 177 178 uint32_t pim_check_reserved_0; 179 180 /* The Cache Check word. */ 181 uint32_t pim_check_cache; 182 #define PIM_CACHE_ICC (1 << 31) 183 #define PIM_CACHE_DCC (1 << 30) 184 #define PIM_CACHE_TC (1 << 29) 185 #define PIM_CACHE_DC (1 << 28) 186 #define PIM_CACHE_CRG (1 << 27) 187 #define PIM_CACHE_LC (1 << 26) 188 #define PIM_CACHE_RCC (1 << 25) 189 #define PIM_CACHE_PADD(cc) ((cc) & 0x000fffff) 190 #define PIM_CACHE_BITS \ 191 "\177\020" /* New bitmask format */ \ 192 "b\037icc\0" /* bit 31 */ \ 193 "b\036dcc\0" /* bit 30 */ \ 194 "b\035tc\0" /* bit 29 */ \ 195 "b\034dc\0" /* bit 28 */ \ 196 "b\033crg\0" /* bit 27 */ \ 197 "b\032lc\0" /* bit 26 */ \ 198 "b\031rcc\0" /* bit 25 */ \ 199 "f\000\030paddr\0" /* bit 0 .. 23 */ 200 201 /* The TLB Check word. */ 202 uint32_t pim_check_tlb; 203 #define PIM_TLB_ITC (1 << 31) 204 #define PIM_TLB_DTC (1 << 30) 205 #define PIM_TLB_TRG (1 << 29) 206 #define PIM_TLB_TUC (1 << 28) 207 #define PIM_TLB_TNF (1 << 27) 208 #define PIM_TLB_BITS \ 209 "\177\020" /* New bitmask format */ \ 210 "b\037itc\0" /* bit 31 */ \ 211 "b\036dtc\0" /* bit 30 */ \ 212 "b\035trg\0" /* bit 29 */ \ 213 "b\034tuc\0" /* bit 28 */ \ 214 "b\033tnf\0" /* bit 27 */ \ 215 216 /* The Bus Check word. */ 217 uint32_t pim_check_bus; 218 #define PIM_BUS_RSV (1 << 21) 219 #define PIM_BUS_RQV (1 << 20) 220 #define PIM_BUS_VAR(bc) (((bc) >> 16) & 0xf) 221 #define PIM_BUS_TYPE(bc) (((bc) >> 12) & 0xf) 222 #define PIM_BUS_SIZE(bc) (((bc) >> 8) & 0xf) 223 #define PIM_BUS_PIV (1 << 7) 224 #define PIM_BUS_BSV (1 << 6) 225 #define PIM_BUS_STAT(bc) ((bc) & 0x3f) 226 #define PIM_BUS_BITS \ 227 "\177\020" /* New bitmask format */ \ 228 "b\025rsv\0" /* bit 21 */ \ 229 "b\024rqv\0" /* bit 20 */ \ 230 "f\020\004var\0" /* bit 16 .. 19 */ \ 231 "f\014\004type\0" /* bit 12 .. 15 */ \ 232 "f\010\004size\0" /* bit 8 .. 11 */ \ 233 "b\007piv\0" /* bit 7 */ \ 234 "b\006bsv\0" /* bit 6 */ \ 235 "f\000\006stat\0" /* bit 0 .. 5 */ 236 237 /* The Assist Check word. */ 238 uint32_t pim_check_assist; 239 #define PIM_ASSIST_COC (1 << 31) 240 #define PIM_ASSIST_SC (1 << 30) 241 #define PIM_ASSIST_BITS "\020\037COC\036SC" 242 243 uint32_t pim_check_reserved_1; 244 245 /* Additional information about the check. */ 246 uint32_t pim_check_assist_state; 247 uint32_t pim_check_responder; 248 uint32_t pim_check_requestor; 249 uint32_t pim_check_path_info; 250 }; 251 252 /* The PIM data for HPMC and LPMC contains this register array. */ 253 struct hppa_pim_fpregs { 254 255 /* The FPU state. */ 256 uint64_t pim_fpregs_fp0; 257 uint64_t pim_fpregs_fp1; 258 uint64_t pim_fpregs_fp2; 259 uint64_t pim_fpregs_fp3; 260 uint64_t pim_fpregs_fp4; 261 uint64_t pim_fpregs_fp5; 262 uint64_t pim_fpregs_fp6; 263 uint64_t pim_fpregs_fp7; 264 uint64_t pim_fpregs_fp8; 265 uint64_t pim_fpregs_fp9; 266 uint64_t pim_fpregs_fp10; 267 uint64_t pim_fpregs_fp11; 268 uint64_t pim_fpregs_fp12; 269 uint64_t pim_fpregs_fp13; 270 uint64_t pim_fpregs_fp14; 271 uint64_t pim_fpregs_fp15; 272 uint64_t pim_fpregs_fp16; 273 uint64_t pim_fpregs_fp17; 274 uint64_t pim_fpregs_fp18; 275 uint64_t pim_fpregs_fp19; 276 uint64_t pim_fpregs_fp20; 277 uint64_t pim_fpregs_fp21; 278 uint64_t pim_fpregs_fp22; 279 uint64_t pim_fpregs_fp23; 280 uint64_t pim_fpregs_fp24; 281 uint64_t pim_fpregs_fp25; 282 uint64_t pim_fpregs_fp26; 283 uint64_t pim_fpregs_fp27; 284 uint64_t pim_fpregs_fp28; 285 uint64_t pim_fpregs_fp29; 286 uint64_t pim_fpregs_fp30; 287 uint64_t pim_fpregs_fp31; 288 }; 289 290 /* The HPMC PIM data. */ 291 struct hppa_pim_hpmc { 292 struct hppa_pim_regs pim_hpmc_regs; 293 struct hppa_pim_checks pim_hpmc_checks; 294 struct hppa_pim_fpregs pim_hpmc_fpregs; 295 }; 296 297 /* The LPMC PIM data. */ 298 struct hppa_pim_lpmc { 299 uint32_t pim_lpmc_hversion_dep[74]; 300 struct hppa_pim_checks pim_lpmc_checks; 301 struct hppa_pim_fpregs pim_lpmc_fpregs; 302 }; 303 304 /* The TOC PIM data. */ 305 struct hppa_pim_toc { 306 struct hppa_pim_regs pim_toc_regs; 307 uint32_t pim_toc_hversion_dep; 308 uint32_t pim_toc_cpu_state; 309 }; 310 311 struct hppa_pim64_regs { 312 313 /* The general registers. */ 314 uint64_t pim_regs_r0; 315 uint64_t pim_regs_r1; 316 uint64_t pim_regs_r2; 317 uint64_t pim_regs_r3; 318 uint64_t pim_regs_r4; 319 uint64_t pim_regs_r5; 320 uint64_t pim_regs_r6; 321 uint64_t pim_regs_r7; 322 uint64_t pim_regs_r8; 323 uint64_t pim_regs_r9; 324 uint64_t pim_regs_r10; 325 uint64_t pim_regs_r11; 326 uint64_t pim_regs_r12; 327 uint64_t pim_regs_r13; 328 uint64_t pim_regs_r14; 329 uint64_t pim_regs_r15; 330 uint64_t pim_regs_r16; 331 uint64_t pim_regs_r17; 332 uint64_t pim_regs_r18; 333 uint64_t pim_regs_r19; 334 uint64_t pim_regs_r20; 335 uint64_t pim_regs_r21; 336 uint64_t pim_regs_r22; 337 uint64_t pim_regs_r23; 338 uint64_t pim_regs_r24; 339 uint64_t pim_regs_r25; 340 uint64_t pim_regs_r26; 341 uint64_t pim_regs_r27; 342 uint64_t pim_regs_r28; 343 uint64_t pim_regs_r29; 344 uint64_t pim_regs_r30; 345 uint64_t pim_regs_r31; 346 347 /* The control registers. */ 348 uint64_t pim_regs_cr0; 349 uint64_t pim_regs_cr1; 350 uint64_t pim_regs_cr2; 351 uint64_t pim_regs_cr3; 352 uint64_t pim_regs_cr4; 353 uint64_t pim_regs_cr5; 354 uint64_t pim_regs_cr6; 355 uint64_t pim_regs_cr7; 356 uint64_t pim_regs_cr8; 357 uint64_t pim_regs_cr9; 358 uint64_t pim_regs_cr10; 359 uint64_t pim_regs_cr11; 360 uint64_t pim_regs_cr12; 361 uint64_t pim_regs_cr13; 362 uint64_t pim_regs_cr14; 363 uint64_t pim_regs_cr15; 364 uint64_t pim_regs_cr16; 365 uint64_t pim_regs_cr17; 366 uint64_t pim_regs_cr18; 367 uint64_t pim_regs_cr19; 368 uint64_t pim_regs_cr20; 369 uint64_t pim_regs_cr21; 370 uint64_t pim_regs_cr22; 371 uint64_t pim_regs_cr23; 372 uint64_t pim_regs_cr24; 373 uint64_t pim_regs_cr25; 374 uint64_t pim_regs_cr26; 375 uint64_t pim_regs_cr27; 376 uint64_t pim_regs_cr28; 377 uint64_t pim_regs_cr29; 378 uint64_t pim_regs_cr30; 379 uint64_t pim_regs_cr31; 380 381 /* The space registers. */ 382 uint64_t pim_regs_sr0; 383 uint64_t pim_regs_sr1; 384 uint64_t pim_regs_sr2; 385 uint64_t pim_regs_sr3; 386 uint64_t pim_regs_sr4; 387 uint64_t pim_regs_sr5; 388 uint64_t pim_regs_sr6; 389 uint64_t pim_regs_sr7; 390 391 /* The back entries of the instruction address queues. */ 392 uint64_t pim_regs_iisq_tail; 393 uint64_t pim_regs_iioq_tail; 394 }; 395 396 struct hppa_pim64_checks { 397 /* The Check Type. */ 398 uint32_t pim_check_type; 399 400 /* 401 * The CPU State. In addition to the common PIM_CPU_ 402 * bits defined below, some fields are HPMC-specific. 403 */ 404 uint32_t pim_check_cpu_state; 405 406 /* The Cache Check word. */ 407 uint32_t pim_check_cache; 408 409 /* The TLB Check word. */ 410 uint32_t pim_check_tlb; 411 412 /* The Bus Check word. */ 413 uint32_t pim_check_bus; 414 415 /* The Assist Check word. */ 416 uint32_t pim_check_assist; 417 418 /* Additional information about the check. */ 419 uint32_t pim_check_assist_state; 420 uint32_t pim_check_path_info; 421 uint64_t pim_check_responder; 422 uint64_t pim_check_requestor; 423 }; 424 425 /* The PARISC 2.0 HPMC PIM data. */ 426 struct hppa_pim64_hpmc { 427 struct hppa_pim64_regs pim_hpmc_regs; 428 struct hppa_pim64_checks pim_hpmc_checks; 429 struct hppa_pim_fpregs pim_hpmc_fpregs; 430 }; 431 432 /* The PARISC 2.0 LPMC PIM data. */ 433 struct hppa_pim64_lpmc { 434 uint64_t pim_lmpc_hversion_dep[74]; 435 struct hppa_pim64_checks pim_lpmc_checks; 436 struct hppa_pim_fpregs pim_lpmc_fpregs; 437 }; 438 439 /* The PARISC 2.0 TOC PIM data. */ 440 struct hppa_pim64_toc { 441 struct hppa_pim64_regs pim_toc_regs; 442 uint32_t pim_toc_hversion_dep; 443 uint32_t pim_toc_cpu_state; 444 }; 445