xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/hpd_regs.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: hpd_regs.h,v 1.2 2021/12/18 23:45:04 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2012-16 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 
28 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_
29 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_
30 
31 #include "gpio_regs.h"
32 
33 #define ONE_MORE_0 1
34 #define ONE_MORE_1 2
35 #define ONE_MORE_2 3
36 #define ONE_MORE_3 4
37 #define ONE_MORE_4 5
38 #define ONE_MORE_5 6
39 
40 
41 #define HPD_GPIO_REG_LIST_ENTRY(type,cd,id) \
42 	.type ## _reg =  REG(DC_GPIO_HPD_## type),\
43 	.type ## _mask =  DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\
44 	.type ## _shift = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## __SHIFT
45 
46 #define HPD_GPIO_REG_LIST(id) \
47 	{\
48 	HPD_GPIO_REG_LIST_ENTRY(MASK,cd,id),\
49 	HPD_GPIO_REG_LIST_ENTRY(A,cd,id),\
50 	HPD_GPIO_REG_LIST_ENTRY(EN,cd,id),\
51 	HPD_GPIO_REG_LIST_ENTRY(Y,cd,id)\
52 	}
53 
54 #define HPD_REG_LIST(id) \
55 	HPD_GPIO_REG_LIST(ONE_MORE_ ## id), \
56 	.int_status = REGI(DC_HPD_INT_STATUS, HPD, id),\
57 	.toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id)
58 
59  #define HPD_MASK_SH_LIST(mask_sh) \
60 		SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED, mask_sh),\
61 		SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE, mask_sh),\
62 		SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, mask_sh),\
63 		SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, mask_sh)
64 
65 struct hpd_registers {
66 	struct gpio_registers gpio;
67 	uint32_t int_status;
68 	uint32_t toggle_filt_cntl;
69 };
70 
71 struct hpd_sh_mask {
72 	/* int_status */
73 	uint32_t DC_HPD_SENSE_DELAYED;
74 	uint32_t DC_HPD_SENSE;
75 	/* toggle_filt_cntl */
76 	uint32_t DC_HPD_CONNECT_INT_DELAY;
77 	uint32_t DC_HPD_DISCONNECT_INT_DELAY;
78 };
79 
80 
81 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ */
82