1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef HNS3_DCB_H 6 #define HNS3_DCB_H 7 8 #include <stdint.h> 9 10 #include <ethdev_driver.h> 11 #include <rte_ethdev.h> 12 13 #include "hns3_cmd.h" 14 #include "hns3_ethdev.h" 15 16 #define HNS3_ETHER_MAX_RATE 100000 17 18 /* MAC Pause */ 19 #define HNS3_TX_MAC_PAUSE_EN_MSK BIT(0) 20 #define HNS3_RX_MAC_PAUSE_EN_MSK BIT(1) 21 22 #define HNS3_DEFAULT_PAUSE_TRANS_GAP 0x18 23 #define HNS3_DEFAULT_PAUSE_TRANS_TIME 0xFFFF 24 25 /* SP or DWRR */ 26 #define HNS3_DCB_TX_SCHD_DWRR_MSK BIT(0) 27 #define HNS3_DCB_TX_SCHD_SP_MSK 0xFE 28 29 enum hns3_shap_bucket { 30 HNS3_DCB_SHAP_C_BUCKET = 0, 31 HNS3_DCB_SHAP_P_BUCKET, 32 }; 33 34 struct hns3_priority_weight_cmd { 35 uint8_t pri_id; 36 uint8_t dwrr; 37 uint8_t rsvd[22]; 38 }; 39 40 struct hns3_qs_weight_cmd { 41 uint16_t qs_id; 42 uint8_t dwrr; 43 uint8_t rsvd[21]; 44 }; 45 46 struct hns3_pg_weight_cmd { 47 uint8_t pg_id; 48 uint8_t dwrr; 49 uint8_t rsvd[22]; 50 }; 51 52 struct hns3_ets_tc_weight_cmd { 53 uint8_t tc_weight[HNS3_MAX_TC_NUM]; 54 uint8_t weight_offset; 55 uint8_t rsvd[15]; 56 }; 57 58 struct hns3_qs_to_pri_link_cmd { 59 uint16_t qs_id; 60 uint16_t rsvd; 61 uint8_t priority; 62 #define HNS3_DCB_QS_PRI_LINK_VLD_MSK BIT(0) 63 #define HNS3_DCB_QS_ID_L_MSK GENMASK(9, 0) 64 #define HNS3_DCB_QS_ID_L_S 0 65 #define HNS3_DCB_QS_ID_H_MSK GENMASK(14, 10) 66 #define HNS3_DCB_QS_ID_H_S 10 67 #define HNS3_DCB_QS_ID_H_EXT_S 11 68 #define HNS3_DCB_QS_ID_H_EXT_MSK GENMASK(15, 11) 69 uint8_t link_vld; 70 uint8_t rsvd1[18]; 71 }; 72 73 struct hns3_nq_to_qs_link_cmd { 74 uint16_t nq_id; 75 uint16_t rsvd; 76 #define HNS3_DCB_Q_QS_LINK_VLD_MSK BIT(10) 77 uint16_t qset_id; 78 uint8_t rsvd1[18]; 79 }; 80 81 #define HNS3_DCB_SHAP_IR_B_MSK GENMASK(7, 0) 82 #define HNS3_DCB_SHAP_IR_B_LSH 0 83 #define HNS3_DCB_SHAP_IR_U_MSK GENMASK(11, 8) 84 #define HNS3_DCB_SHAP_IR_U_LSH 8 85 #define HNS3_DCB_SHAP_IR_S_MSK GENMASK(15, 12) 86 #define HNS3_DCB_SHAP_IR_S_LSH 12 87 #define HNS3_DCB_SHAP_BS_B_MSK GENMASK(20, 16) 88 #define HNS3_DCB_SHAP_BS_B_LSH 16 89 #define HNS3_DCB_SHAP_BS_S_MSK GENMASK(25, 21) 90 #define HNS3_DCB_SHAP_BS_S_LSH 21 91 92 /* 93 * For more flexible selection of shapping algorithm in different network 94 * engine, the algorithm calculating shapping parameter is moved to firmware to 95 * execute. Bit HNS3_TM_RATE_VLD_B of flag field in hns3_pri_shapping_cmd, 96 * hns3_pg_shapping_cmd or hns3_port_shapping_cmd is set to 1 to require 97 * firmware to recalculate shapping parameters. However, whether the parameters 98 * are recalculated depends on the firmware version. If firmware doesn't support 99 * the calculation of shapping parameters, such as on network engine with 100 * revision id 0x21, the value driver calculated will be used to configure to 101 * hardware. On the contrary, firmware ignores configuration of driver 102 * and recalculates the parameter. 103 */ 104 #define HNS3_TM_RATE_VLD_B 0 105 106 struct hns3_pri_shapping_cmd { 107 uint8_t pri_id; 108 uint8_t rsvd[3]; 109 uint32_t pri_shapping_para; 110 uint8_t flag; 111 uint8_t rsvd1[3]; 112 uint32_t pri_rate; /* Unit Mbps */ 113 uint8_t rsvd2[8]; 114 }; 115 116 struct hns3_pg_shapping_cmd { 117 uint8_t pg_id; 118 uint8_t rsvd[3]; 119 uint32_t pg_shapping_para; 120 uint8_t flag; 121 uint8_t rsvd1[3]; 122 uint32_t pg_rate; /* Unit Mbps */ 123 uint8_t rsvd2[8]; 124 }; 125 126 struct hns3_port_shapping_cmd { 127 uint32_t port_shapping_para; 128 uint8_t flag; 129 uint8_t rsvd[3]; 130 uint32_t port_rate; /* Unit Mbps */ 131 uint8_t rsvd1[12]; 132 }; 133 134 #define HNS3_BP_GRP_NUM 32 135 #define HNS3_BP_SUB_GRP_ID_S 0 136 #define HNS3_BP_SUB_GRP_ID_M GENMASK(4, 0) 137 #define HNS3_BP_GRP_ID_S 5 138 #define HNS3_BP_GRP_ID_M GENMASK(9, 5) 139 140 struct hns3_bp_to_qs_map_cmd { 141 uint8_t tc_id; 142 uint8_t rsvd[2]; 143 uint8_t qs_group_id; 144 uint32_t qs_bit_map; 145 uint32_t rsvd1[4]; 146 }; 147 148 struct hns3_pfc_en_cmd { 149 uint8_t tx_rx_en_bitmap; 150 uint8_t pri_en_bitmap; 151 uint8_t rsvd[22]; 152 }; 153 154 struct hns3_cfg_pause_param_cmd { 155 uint8_t mac_addr[RTE_ETHER_ADDR_LEN]; 156 uint8_t pause_trans_gap; 157 uint8_t rsvd; 158 uint16_t pause_trans_time; 159 uint8_t rsvd1[6]; 160 /* extra mac address to do double check for pause frame */ 161 uint8_t mac_addr_extra[RTE_ETHER_ADDR_LEN]; 162 uint16_t rsvd2; 163 }; 164 165 struct hns3_pg_to_pri_link_cmd { 166 uint8_t pg_id; 167 uint8_t rsvd1[3]; 168 uint8_t pri_bit_map; 169 uint8_t rsvd2[19]; 170 }; 171 172 enum hns3_shaper_level { 173 HNS3_SHAPER_LVL_PRI = 0, 174 HNS3_SHAPER_LVL_PG = 1, 175 HNS3_SHAPER_LVL_PORT = 2, 176 HNS3_SHAPER_LVL_QSET = 3, 177 HNS3_SHAPER_LVL_CNT = 4, 178 HNS3_SHAPER_LVL_VF = 0, 179 HNS3_SHAPER_LVL_PF = 1, 180 }; 181 182 struct hns3_shaper_parameter { 183 uint32_t ir_b; /* IR_B parameter of IR shaper */ 184 uint32_t ir_u; /* IR_U parameter of IR shaper */ 185 uint32_t ir_s; /* IR_S parameter of IR shaper */ 186 }; 187 188 #define hns3_dcb_set_field(dest, string, val) \ 189 hns3_set_field((dest), \ 190 (HNS3_DCB_SHAP_##string##_MSK), \ 191 (HNS3_DCB_SHAP_##string##_LSH), val) 192 #define hns3_dcb_get_field(src, string) \ 193 hns3_get_field((src), (HNS3_DCB_SHAP_##string##_MSK), \ 194 (HNS3_DCB_SHAP_##string##_LSH)) 195 196 int hns3_pause_addr_cfg(struct hns3_hw *hw, const uint8_t *mac_addr); 197 198 int hns3_dcb_configure(struct hns3_adapter *hns); 199 200 int hns3_dcb_init(struct hns3_hw *hw); 201 202 int hns3_dcb_init_hw(struct hns3_hw *hw); 203 204 int hns3_dcb_info_init(struct hns3_hw *hw); 205 206 int hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); 207 208 int hns3_dcb_pfc_enable(struct rte_eth_dev *dev, 209 struct rte_eth_pfc_conf *pfc_conf); 210 211 int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q, 212 uint16_t nb_tx_q); 213 214 int hns3_update_queue_map_configure(struct hns3_adapter *hns); 215 int hns3_port_shaper_update(struct hns3_hw *hw, uint32_t speed); 216 uint8_t hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no); 217 218 #endif /* HNS3_DCB_H */ 219