1 /* $NetBSD: gdium_intr.c,v 1.10 2020/11/21 15:36:36 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Platform-specific interrupt support for the Algorithmics P-6032.
34 *
35 * The Algorithmics P-6032's interrupts are wired to GPIO pins
36 * on the BONITO system controller.
37 */
38
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.10 2020/11/21 15:36:36 thorpej Exp $");
41
42 #define __INTR_PRIVATE
43
44
45 #include "opt_ddb.h"
46
47 #include <sys/param.h>
48 #include <sys/bus.h>
49 #include <sys/cpu.h>
50 #include <sys/device.h>
51 #include <sys/intr.h>
52 #include <sys/kernel.h>
53 #include <sys/kmem.h>
54 #include <sys/systm.h>
55
56 #include <mips/locore.h>
57
58 #include <mips/bonito/bonitoreg.h>
59 #include <evbmips/gdium/gdiumvar.h>
60
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcivar.h>
63
64 /*
65 * The GDIUM interrupts are wired up in the following way:
66 *
67 * GPIN0 ISA_NMI (in)
68 * GPIN1 ISA_INTR (in)
69 * GPIN2 ETH_INT~ (in)
70 * GPIN3 BONIDE_INT (in)
71 *
72 * PCI_INTA
73 * GPIN4 ISA IRQ3 (in, also on piix4)
74 * GPIN5 ISA IRQ4 (in, also on piix4)
75 *
76 * GPIO0 PIRQ A~ (in)
77 * GPIO1 PIRQ B~ (in)
78 * GPIO2 PIRQ C~ (in)
79 * GPIO3 PIRQ D~ (in)
80 */
81
82 struct gdium_irqmap {
83 const char *name;
84 uint8_t irqidx;
85 uint8_t flags;
86 };
87
88 #define IRQ_F_INVERT 0x80 /* invert polarity */
89 #define IRQ_F_EDGE 0x40 /* edge trigger */
90 #define IRQ_F_INT0 0x00 /* INT0 */
91 #define IRQ_F_INT1 0x01 /* INT1 */
92 #define IRQ_F_INT2 0x02 /* INT2 */
93 #define IRQ_F_INT3 0x03 /* INT3 */
94 #define IRQ_F_INTMASK 0x07 /* INT mask */
95
96 const struct gdium_irqmap gdium_irqmap[] = {
97 { "gpio0", GDIUM_IRQ_GPIO0, IRQ_F_INT0 },
98 { "gpio1", GDIUM_IRQ_GPIO1, IRQ_F_INT0 },
99 { "gpio2", GDIUM_IRQ_GPIO2, IRQ_F_INT0 },
100 { "gpio3", GDIUM_IRQ_GPIO3, IRQ_F_INT0 },
101
102 { "pci inta", GDIUM_IRQ_PCI_INTA, IRQ_F_INT0 },
103 { "pci intb", GDIUM_IRQ_PCI_INTB, IRQ_F_INT0 },
104 { "pci intc", GDIUM_IRQ_PCI_INTC, IRQ_F_INT0 },
105 { "pci intd", GDIUM_IRQ_PCI_INTD, IRQ_F_INT0 },
106
107 { "pci perr", GDIUM_IRQ_PCI_PERR, IRQ_F_EDGE|IRQ_F_INT1 },
108 { "pci serr", GDIUM_IRQ_PCI_SERR, IRQ_F_EDGE|IRQ_F_INT1 },
109
110 { "denali", GDIUM_IRQ_DENALI, IRQ_F_INT1 },
111
112 { "mips int0", GDIUM_IRQ_INT0, IRQ_F_INT0 },
113 { "mips int1", GDIUM_IRQ_INT1, IRQ_F_INT1 },
114 { "mips int2", GDIUM_IRQ_INT2, IRQ_F_INT2 },
115 { "mips int3", GDIUM_IRQ_INT3, IRQ_F_INT3 },
116 };
117
118 struct gdium_intrhead {
119 struct evcnt intr_count;
120 int intr_refcnt;
121 };
122 struct gdium_intrhead gdium_intrtab[__arraycount(gdium_irqmap)];
123
124 #define NINTRS 2 /* MIPS INT0 - INT1 */
125
126 struct gdium_cpuintr {
127 LIST_HEAD(, evbmips_intrhand) cintr_list;
128 struct evcnt cintr_count;
129 int cintr_refcnt;
130 };
131
132 struct gdium_cpuintr gdium_cpuintrs[NINTRS];
133 const char * const gdium_cpuintrnames[NINTRS] = {
134 "int 0 (pci)",
135 "int 1 (errors)",
136 };
137
138 /*
139 * This is a mask of bits to clear in the SR when we go to a
140 * given hardware interrupt priority level.
141 */
142 static const struct ipl_sr_map gdium_ipl_sr_map = {
143 .sr_bits = {
144 [IPL_NONE] = 0,
145 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
146 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
147 [IPL_VM] =
148 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
149 MIPS_INT_MASK_0 |
150 MIPS_INT_MASK_1 |
151 MIPS_INT_MASK_2 |
152 MIPS_INT_MASK_3 |
153 MIPS_INT_MASK_4,
154 [IPL_SCHED] =
155 MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
156 MIPS_INT_MASK_0 |
157 MIPS_INT_MASK_1 |
158 MIPS_INT_MASK_2 |
159 MIPS_INT_MASK_3 |
160 MIPS_INT_MASK_4 |
161 MIPS_INT_MASK_5,
162 [IPL_DDB] = MIPS_INT_MASK,
163 [IPL_HIGH] = MIPS_INT_MASK,
164 },
165 };
166
167 int gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
168 const char *gdium_pci_intr_string(void *, pci_intr_handle_t, char *, size_t);
169 const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t);
170 void *gdium_pci_intr_establish(void *, pci_intr_handle_t, int,
171 int (*)(void *), void *);
172 void gdium_pci_intr_disestablish(void *, void *);
173 void gdium_pci_conf_interrupt(void *, int, int, int, int, int *);
174
175 void
evbmips_intr_init(void)176 evbmips_intr_init(void)
177 {
178 struct gdium_config * const gc = &gdium_configuration;
179 struct bonito_config *bc = &gc->gc_bonito;
180 const struct gdium_irqmap *irqmap;
181 uint32_t intbit;
182 size_t i;
183
184 ipl_sr_map = gdium_ipl_sr_map;
185
186 for (i = 0; i < NINTRS; i++) {
187 LIST_INIT(&gdium_cpuintrs[i].cintr_list);
188 evcnt_attach_dynamic(&gdium_cpuintrs[i].cintr_count,
189 EVCNT_TYPE_INTR, NULL, "mips", gdium_cpuintrnames[i]);
190 }
191 //evcnt_attach_static(&mips_int5_evcnt);
192
193 for (i = 0; i < __arraycount(gdium_irqmap); i++) {
194 irqmap = &gdium_irqmap[i];
195 intbit = 1 << irqmap->irqidx;
196
197 evcnt_attach_dynamic(&gdium_intrtab[i].intr_count,
198 EVCNT_TYPE_INTR, NULL, "bonito", irqmap->name);
199
200 if (irqmap->irqidx < 4)
201 bc->bc_gpioIE |= intbit;
202 if (irqmap->flags & IRQ_F_INVERT)
203 bc->bc_intPol |= intbit;
204 if (irqmap->flags & IRQ_F_EDGE)
205 bc->bc_intEdge |= intbit;
206 if ((irqmap->flags & IRQ_F_INTMASK) == IRQ_F_INT1)
207 bc->bc_intSteer |= intbit;
208
209 REGVAL(BONITO_INTENCLR) = intbit;
210 }
211
212 REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE;
213 REGVAL(BONITO_INTEDGE) = bc->bc_intEdge;
214 REGVAL(BONITO_INTSTEER) = bc->bc_intSteer;
215 REGVAL(BONITO_INTPOL) = bc->bc_intPol;
216
217 gc->gc_pc.pc_intr_v = NULL;
218 gc->gc_pc.pc_intr_map = gdium_pci_intr_map;
219 gc->gc_pc.pc_intr_string = gdium_pci_intr_string;
220 gc->gc_pc.pc_intr_evcnt = gdium_pci_intr_evcnt;
221 gc->gc_pc.pc_intr_establish = gdium_pci_intr_establish;
222 gc->gc_pc.pc_intr_disestablish = gdium_pci_intr_disestablish;
223 gc->gc_pc.pc_conf_interrupt = gdium_pci_conf_interrupt;
224
225 /* We let the PCI-ISA bridge code handle this. */
226 gc->gc_pc.pc_pciide_compat_intr_establish = NULL;
227 }
228
229 void *
evbmips_intr_establish(int irq,int (* func)(void *),void * arg)230 evbmips_intr_establish(int irq, int (*func)(void *), void *arg)
231 {
232 const struct gdium_irqmap *irqmap;
233 struct evbmips_intrhand *ih;
234 int level;
235 int s;
236
237 irqmap = &gdium_irqmap[irq];
238 KASSERT(irq < __arraycount(gdium_irqmap));
239
240 KASSERT(irq == irqmap->irqidx);
241
242 ih = kmem_zalloc(sizeof(*ih), KM_SLEEP);
243 ih->ih_func = func;
244 ih->ih_arg = arg;
245 ih->ih_irq = irq;
246
247 s = splhigh();
248
249 /*
250 * First, link it into the tables.
251 */
252 level = (irqmap->flags & IRQ_F_INT1) != 0;
253 LIST_INSERT_HEAD(&gdium_cpuintrs[level].cintr_list, ih, ih_q);
254 gdium_cpuintrs[level].cintr_refcnt++;
255
256 /*
257 * Now enable it.
258 */
259 if (gdium_intrtab[ih->ih_irq].intr_refcnt++ == 0)
260 REGVAL(BONITO_INTENSET) = (1 << ih->ih_irq);
261
262 splx(s);
263
264 return (ih);
265 }
266
267 void
evbmips_intr_disestablish(void * cookie)268 evbmips_intr_disestablish(void *cookie)
269 {
270 const struct gdium_irqmap *irqmap;
271 struct evbmips_intrhand *ih = cookie;
272 int s;
273
274 irqmap = &gdium_irqmap[ih->ih_irq];
275
276 s = splhigh();
277
278 /*
279 * First, remove it from the table.
280 */
281 LIST_REMOVE(ih, ih_q);
282 gdium_cpuintrs[(irqmap->flags & IRQ_F_INT1) != 0].cintr_refcnt--;
283
284 /*
285 * Now, disable it, if there is nothing remaining on the
286 * list.
287 */
288 if (gdium_intrtab[ih->ih_irq].intr_refcnt-- == 1)
289 REGVAL(BONITO_INTENCLR) = (1 << ih->ih_irq);
290
291 splx(s);
292
293 kmem_free(ih, sizeof(*ih));
294 }
295
296 void
evbmips_iointr(int ipl,uint32_t ipending,struct clockframe * cf)297 evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
298 {
299 struct evbmips_intrhand *ih;
300 int level;
301 uint32_t isr;
302
303 /*
304 * Read the interrupt pending registers, mask them with the
305 * ones we have enabled, and service them in order of decreasing
306 * priority.
307 */
308 isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN);
309 for (level = 1; level >= 0; level--) {
310 if ((ipending & (MIPS_INT_MASK_4 << level)) == 0)
311 continue;
312 gdium_cpuintrs[level].cintr_count.ev_count++;
313 LIST_FOREACH (ih, &gdium_cpuintrs[level].cintr_list, ih_q) {
314 if (isr & (1 << ih->ih_irq)) {
315 gdium_intrtab[ih->ih_irq].intr_count.ev_count++;
316 (*ih->ih_func)(ih->ih_arg);
317 }
318 }
319 }
320 }
321
322 /*****************************************************************************
323 * PCI interrupt support
324 *****************************************************************************/
325
326 int
gdium_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)327 gdium_pci_intr_map(const struct pci_attach_args *pa,
328 pci_intr_handle_t *ihp)
329 {
330 static const int8_t pciirqmap[5/*device*/] = {
331 GDIUM_IRQ_PCI_INTC, /* 13: PCI 802.11 */
332 GDIUM_IRQ_PCI_INTA, /* 14: SM501 */
333 GDIUM_IRQ_PCI_INTB, /* 15: NEC USB (2 func) */
334 GDIUM_IRQ_PCI_INTD, /* 16: Ethernet */
335 GDIUM_IRQ_PCI_INTC, /* 17: NEC USB (2 func) */
336 };
337 pcitag_t bustag = pa->pa_intrtag;
338 int buspin = pa->pa_intrpin;
339 pci_chipset_tag_t pc = pa->pa_pc;
340 int device;
341
342 if (buspin == 0) {
343 /* No IRQ used. */
344 return (1);
345 }
346
347 if (buspin > 4) {
348 printf("gdium_pci_intr_map: bad interrupt pin %d\n",
349 buspin);
350 return (1);
351 }
352
353 pci_decompose_tag(pc, bustag, NULL, &device, NULL);
354 if (device < 13 || device > 17) {
355 printf("gdium_pci_intr_map: bad device %d\n",
356 device);
357 return (1);
358 }
359
360 *ihp = pciirqmap[device - 13];
361 return (0);
362 }
363
364 const char *
gdium_pci_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)365 gdium_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
366 {
367
368 if (ih >= __arraycount(gdium_irqmap))
369 panic("gdium_intr_string: bogus IRQ %ld", ih);
370
371 strlcpy(buf, gdium_irqmap[ih].name, len);
372 return buf;
373 }
374
375 const struct evcnt *
gdium_pci_intr_evcnt(void * v,pci_intr_handle_t ih)376 gdium_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
377 {
378
379 return &gdium_intrtab[ih].intr_count;
380 }
381
382 void *
gdium_pci_intr_establish(void * v,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg)383 gdium_pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
384 int (*func)(void *), void *arg)
385 {
386
387 if (ih >= __arraycount(gdium_irqmap))
388 panic("gdium_pci_intr_establish: bogus IRQ %ld", ih);
389
390 return evbmips_intr_establish(ih, func, arg);
391 }
392
393 void
gdium_pci_intr_disestablish(void * v,void * cookie)394 gdium_pci_intr_disestablish(void *v, void *cookie)
395 {
396
397 return (evbmips_intr_disestablish(cookie));
398 }
399
400 void
gdium_pci_conf_interrupt(void * v,int bus,int dev,int pin,int swiz,int * iline)401 gdium_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
402 int *iline)
403 {
404
405 /*
406 * We actually don't need to do anything; everything is handled
407 * in pci_intr_map().
408 */
409 *iline = 0;
410 }
411