1/* List of supported core and tune info for RISC-V. 2 Copyright (C) 2020-2022 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, but 12 WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20/* This is a list of cores that implement RISC-V. 21 22 Before using #include to read this file, define a macro: 23 24 RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO) 25 26 The CORE_NAME is the name of the core, represented as a string. 27 The ARCH is the default arch of the core, represented as a string, 28 can be NULL if no default arch. 29 The MICRO_ARCH is the name of the core for which scheduling decisions 30 will be made, represented as an identifier. 31 The TUNE_INFO is the detail cost model for this core, represented as an 32 identifier, reference to riscv-tunes.def. */ 33 34RISCV_CORE("sifive-e20", "rv32imc", "rocket") 35RISCV_CORE("sifive-e21", "rv32imac", "rocket") 36RISCV_CORE("sifive-e24", "rv32imafc", "rocket") 37RISCV_CORE("sifive-e31", "rv32imac", "sifive-3-series") 38RISCV_CORE("sifive-e34", "rv32imafc", "sifive-3-series") 39RISCV_CORE("sifive-e76", "rv32imafc", "sifive-7-series") 40 41RISCV_CORE("sifive-s21", "rv64imac", "rocket") 42RISCV_CORE("sifive-s51", "rv64imac", "sifive-5-series") 43RISCV_CORE("sifive-s54", "rv64imafdc", "sifive-5-series") 44RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") 45 46RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") 47RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") 48 49#undef RISCV_CORE 50