1 /* Subroutines used for macro/preprocessor support on the ia-32.
2 Copyright (C) 2008-2022 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #define IN_TARGET_CODE 1
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "target.h"
26 #include "c-family/c-common.h"
27 #include "memmodel.h"
28 #include "tm_p.h"
29 #include "c-family/c-pragma.h"
30
31 static bool ix86_pragma_target_parse (tree, tree);
32 static void ix86_target_macros_internal
33 (HOST_WIDE_INT, HOST_WIDE_INT, enum processor_type, enum processor_type, enum fpmath_unit,
34 void (*def_or_undef) (cpp_reader *, const char *));
35
36 /* Internal function to either define or undef the appropriate system
37 macros. */
38 static void
ix86_target_macros_internal(HOST_WIDE_INT isa_flag,HOST_WIDE_INT isa_flag2,enum processor_type arch,enum processor_type tune,enum fpmath_unit fpmath,void (* def_or_undef)(cpp_reader *,const char *))39 ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
40 HOST_WIDE_INT isa_flag2,
41 enum processor_type arch,
42 enum processor_type tune,
43 enum fpmath_unit fpmath,
44 void (*def_or_undef) (cpp_reader *,
45 const char *))
46 {
47 /* For some of the k6/pentium varients there weren't separate ISA bits to
48 identify which tune/arch flag was passed, so figure it out here. */
49 size_t arch_len = strlen (ix86_arch_string);
50 size_t tune_len = strlen (ix86_tune_string);
51 int last_arch_char = ix86_arch_string[arch_len - 1];
52 int last_tune_char = ix86_tune_string[tune_len - 1];
53
54 /* Built-ins based on -march=. */
55 switch (arch)
56 {
57 case PROCESSOR_I386:
58 break;
59 case PROCESSOR_I486:
60 def_or_undef (parse_in, "__i486");
61 def_or_undef (parse_in, "__i486__");
62 break;
63 case PROCESSOR_LAKEMONT:
64 /* Intel MCU is based on Intel Pentium CPU. */
65 case PROCESSOR_PENTIUM:
66 def_or_undef (parse_in, "__i586");
67 def_or_undef (parse_in, "__i586__");
68 def_or_undef (parse_in, "__pentium");
69 def_or_undef (parse_in, "__pentium__");
70 if (isa_flag & OPTION_MASK_ISA_MMX)
71 def_or_undef (parse_in, "__pentium_mmx__");
72 break;
73 case PROCESSOR_PENTIUMPRO:
74 def_or_undef (parse_in, "__i686");
75 def_or_undef (parse_in, "__i686__");
76 def_or_undef (parse_in, "__pentiumpro");
77 def_or_undef (parse_in, "__pentiumpro__");
78 break;
79 case PROCESSOR_GEODE:
80 def_or_undef (parse_in, "__geode");
81 def_or_undef (parse_in, "__geode__");
82 break;
83 case PROCESSOR_K6:
84 def_or_undef (parse_in, "__k6");
85 def_or_undef (parse_in, "__k6__");
86 if (last_arch_char == '2')
87 def_or_undef (parse_in, "__k6_2__");
88 else if (last_arch_char == '3')
89 def_or_undef (parse_in, "__k6_3__");
90 else if (isa_flag & OPTION_MASK_ISA_3DNOW)
91 def_or_undef (parse_in, "__k6_3__");
92 break;
93 case PROCESSOR_ATHLON:
94 def_or_undef (parse_in, "__athlon");
95 def_or_undef (parse_in, "__athlon__");
96 if (isa_flag & OPTION_MASK_ISA_SSE)
97 def_or_undef (parse_in, "__athlon_sse__");
98 break;
99 case PROCESSOR_K8:
100 def_or_undef (parse_in, "__k8");
101 def_or_undef (parse_in, "__k8__");
102 break;
103 case PROCESSOR_AMDFAM10:
104 def_or_undef (parse_in, "__amdfam10");
105 def_or_undef (parse_in, "__amdfam10__");
106 break;
107 case PROCESSOR_BDVER1:
108 def_or_undef (parse_in, "__bdver1");
109 def_or_undef (parse_in, "__bdver1__");
110 break;
111 case PROCESSOR_BDVER2:
112 def_or_undef (parse_in, "__bdver2");
113 def_or_undef (parse_in, "__bdver2__");
114 break;
115 case PROCESSOR_BDVER3:
116 def_or_undef (parse_in, "__bdver3");
117 def_or_undef (parse_in, "__bdver3__");
118 break;
119 case PROCESSOR_BDVER4:
120 def_or_undef (parse_in, "__bdver4");
121 def_or_undef (parse_in, "__bdver4__");
122 break;
123 case PROCESSOR_ZNVER1:
124 def_or_undef (parse_in, "__znver1");
125 def_or_undef (parse_in, "__znver1__");
126 break;
127 case PROCESSOR_ZNVER2:
128 def_or_undef (parse_in, "__znver2");
129 def_or_undef (parse_in, "__znver2__");
130 break;
131 case PROCESSOR_ZNVER3:
132 def_or_undef (parse_in, "__znver3");
133 def_or_undef (parse_in, "__znver3__");
134 break;
135 case PROCESSOR_ZNVER4:
136 def_or_undef (parse_in, "__znver4");
137 def_or_undef (parse_in, "__znver4__");
138 break;
139 case PROCESSOR_BTVER1:
140 def_or_undef (parse_in, "__btver1");
141 def_or_undef (parse_in, "__btver1__");
142 break;
143 case PROCESSOR_BTVER2:
144 def_or_undef (parse_in, "__btver2");
145 def_or_undef (parse_in, "__btver2__");
146 break;
147 case PROCESSOR_PENTIUM4:
148 def_or_undef (parse_in, "__pentium4");
149 def_or_undef (parse_in, "__pentium4__");
150 break;
151 case PROCESSOR_NOCONA:
152 def_or_undef (parse_in, "__nocona");
153 def_or_undef (parse_in, "__nocona__");
154 break;
155 case PROCESSOR_CORE2:
156 def_or_undef (parse_in, "__core2");
157 def_or_undef (parse_in, "__core2__");
158 break;
159 case PROCESSOR_NEHALEM:
160 def_or_undef (parse_in, "__corei7");
161 def_or_undef (parse_in, "__corei7__");
162 def_or_undef (parse_in, "__nehalem");
163 def_or_undef (parse_in, "__nehalem__");
164 break;
165 case PROCESSOR_SANDYBRIDGE:
166 def_or_undef (parse_in, "__corei7_avx");
167 def_or_undef (parse_in, "__corei7_avx__");
168 def_or_undef (parse_in, "__sandybridge");
169 def_or_undef (parse_in, "__sandybridge__");
170 break;
171 case PROCESSOR_HASWELL:
172 def_or_undef (parse_in, "__core_avx2");
173 def_or_undef (parse_in, "__core_avx2__");
174 def_or_undef (parse_in, "__haswell");
175 def_or_undef (parse_in, "__haswell__");
176 break;
177 case PROCESSOR_BONNELL:
178 def_or_undef (parse_in, "__atom");
179 def_or_undef (parse_in, "__atom__");
180 def_or_undef (parse_in, "__bonnell");
181 def_or_undef (parse_in, "__bonnell__");
182 break;
183 case PROCESSOR_SILVERMONT:
184 def_or_undef (parse_in, "__slm");
185 def_or_undef (parse_in, "__slm__");
186 def_or_undef (parse_in, "__silvermont");
187 def_or_undef (parse_in, "__silvermont__");
188 break;
189 case PROCESSOR_GOLDMONT:
190 def_or_undef (parse_in, "__goldmont");
191 def_or_undef (parse_in, "__goldmont__");
192 break;
193 case PROCESSOR_GOLDMONT_PLUS:
194 def_or_undef (parse_in, "__goldmont_plus");
195 def_or_undef (parse_in, "__goldmont_plus__");
196 break;
197 case PROCESSOR_TREMONT:
198 def_or_undef (parse_in, "__tremont");
199 def_or_undef (parse_in, "__tremont__");
200 break;
201 case PROCESSOR_KNL:
202 def_or_undef (parse_in, "__knl");
203 def_or_undef (parse_in, "__knl__");
204 break;
205 case PROCESSOR_KNM:
206 def_or_undef (parse_in, "__knm");
207 def_or_undef (parse_in, "__knm__");
208 break;
209 case PROCESSOR_SKYLAKE:
210 def_or_undef (parse_in, "__skylake");
211 def_or_undef (parse_in, "__skylake__");
212 break;
213 case PROCESSOR_SKYLAKE_AVX512:
214 def_or_undef (parse_in, "__skylake_avx512");
215 def_or_undef (parse_in, "__skylake_avx512__");
216 break;
217 case PROCESSOR_CANNONLAKE:
218 def_or_undef (parse_in, "__cannonlake");
219 def_or_undef (parse_in, "__cannonlake__");
220 break;
221 case PROCESSOR_ICELAKE_CLIENT:
222 def_or_undef (parse_in, "__icelake_client");
223 def_or_undef (parse_in, "__icelake_client__");
224 break;
225 case PROCESSOR_ICELAKE_SERVER:
226 def_or_undef (parse_in, "__icelake_server");
227 def_or_undef (parse_in, "__icelake_server__");
228 break;
229 case PROCESSOR_CASCADELAKE:
230 def_or_undef (parse_in, "__cascadelake");
231 def_or_undef (parse_in, "__cascadelake__");
232 break;
233 case PROCESSOR_TIGERLAKE:
234 def_or_undef (parse_in, "__tigerlake");
235 def_or_undef (parse_in, "__tigerlake__");
236 break;
237 case PROCESSOR_COOPERLAKE:
238 def_or_undef (parse_in, "__cooperlake");
239 def_or_undef (parse_in, "__cooperlake__");
240 break;
241 case PROCESSOR_SAPPHIRERAPIDS:
242 def_or_undef (parse_in, "__sapphirerapids");
243 def_or_undef (parse_in, "__sapphirerapids__");
244 break;
245 case PROCESSOR_ALDERLAKE:
246 def_or_undef (parse_in, "__alderlake");
247 def_or_undef (parse_in, "__alderlake__");
248 break;
249 case PROCESSOR_ROCKETLAKE:
250 def_or_undef (parse_in, "__rocketlake");
251 def_or_undef (parse_in, "__rocketlake__");
252 break;
253 /* use PROCESSOR_max to not set/unset the arch macro. */
254 case PROCESSOR_max:
255 break;
256 case PROCESSOR_INTEL:
257 case PROCESSOR_GENERIC:
258 gcc_unreachable ();
259 }
260
261 /* Built-ins based on -mtune=. */
262 switch (tune)
263 {
264 case PROCESSOR_I386:
265 def_or_undef (parse_in, "__tune_i386__");
266 break;
267 case PROCESSOR_I486:
268 def_or_undef (parse_in, "__tune_i486__");
269 break;
270 case PROCESSOR_PENTIUM:
271 def_or_undef (parse_in, "__tune_i586__");
272 def_or_undef (parse_in, "__tune_pentium__");
273 if (last_tune_char == 'x')
274 def_or_undef (parse_in, "__tune_pentium_mmx__");
275 break;
276 case PROCESSOR_PENTIUMPRO:
277 def_or_undef (parse_in, "__tune_i686__");
278 def_or_undef (parse_in, "__tune_pentiumpro__");
279 switch (last_tune_char)
280 {
281 case '3':
282 def_or_undef (parse_in, "__tune_pentium3__");
283 /* FALLTHRU */
284 case '2':
285 def_or_undef (parse_in, "__tune_pentium2__");
286 break;
287 }
288 break;
289 case PROCESSOR_GEODE:
290 def_or_undef (parse_in, "__tune_geode__");
291 break;
292 case PROCESSOR_K6:
293 def_or_undef (parse_in, "__tune_k6__");
294 if (last_tune_char == '2')
295 def_or_undef (parse_in, "__tune_k6_2__");
296 else if (last_tune_char == '3')
297 def_or_undef (parse_in, "__tune_k6_3__");
298 else if (isa_flag & OPTION_MASK_ISA_3DNOW)
299 def_or_undef (parse_in, "__tune_k6_3__");
300 break;
301 case PROCESSOR_ATHLON:
302 def_or_undef (parse_in, "__tune_athlon__");
303 if (isa_flag & OPTION_MASK_ISA_SSE)
304 def_or_undef (parse_in, "__tune_athlon_sse__");
305 break;
306 case PROCESSOR_K8:
307 def_or_undef (parse_in, "__tune_k8__");
308 break;
309 case PROCESSOR_AMDFAM10:
310 def_or_undef (parse_in, "__tune_amdfam10__");
311 break;
312 case PROCESSOR_BDVER1:
313 def_or_undef (parse_in, "__tune_bdver1__");
314 break;
315 case PROCESSOR_BDVER2:
316 def_or_undef (parse_in, "__tune_bdver2__");
317 break;
318 case PROCESSOR_BDVER3:
319 def_or_undef (parse_in, "__tune_bdver3__");
320 break;
321 case PROCESSOR_BDVER4:
322 def_or_undef (parse_in, "__tune_bdver4__");
323 break;
324 case PROCESSOR_ZNVER1:
325 def_or_undef (parse_in, "__tune_znver1__");
326 break;
327 case PROCESSOR_ZNVER2:
328 def_or_undef (parse_in, "__tune_znver2__");
329 break;
330 case PROCESSOR_ZNVER3:
331 def_or_undef (parse_in, "__tune_znver3__");
332 break;
333 case PROCESSOR_ZNVER4:
334 def_or_undef (parse_in, "__tune_znver4__");
335 break;
336 case PROCESSOR_BTVER1:
337 def_or_undef (parse_in, "__tune_btver1__");
338 break;
339 case PROCESSOR_BTVER2:
340 def_or_undef (parse_in, "__tune_btver2__");
341 break;
342 case PROCESSOR_PENTIUM4:
343 def_or_undef (parse_in, "__tune_pentium4__");
344 break;
345 case PROCESSOR_NOCONA:
346 def_or_undef (parse_in, "__tune_nocona__");
347 break;
348 case PROCESSOR_CORE2:
349 def_or_undef (parse_in, "__tune_core2__");
350 break;
351 case PROCESSOR_NEHALEM:
352 def_or_undef (parse_in, "__tune_corei7__");
353 def_or_undef (parse_in, "__tune_nehalem__");
354 break;
355 case PROCESSOR_SANDYBRIDGE:
356 def_or_undef (parse_in, "__tune_corei7_avx__");
357 def_or_undef (parse_in, "__tune_sandybridge__");
358 break;
359 case PROCESSOR_HASWELL:
360 def_or_undef (parse_in, "__tune_core_avx2__");
361 def_or_undef (parse_in, "__tune_haswell__");
362 break;
363 case PROCESSOR_BONNELL:
364 def_or_undef (parse_in, "__tune_atom__");
365 def_or_undef (parse_in, "__tune_bonnell__");
366 break;
367 case PROCESSOR_SILVERMONT:
368 def_or_undef (parse_in, "__tune_slm__");
369 def_or_undef (parse_in, "__tune_silvermont__");
370 break;
371 case PROCESSOR_GOLDMONT:
372 def_or_undef (parse_in, "__tune_goldmont__");
373 break;
374 case PROCESSOR_GOLDMONT_PLUS:
375 def_or_undef (parse_in, "__tune_goldmont_plus__");
376 break;
377 case PROCESSOR_TREMONT:
378 def_or_undef (parse_in, "__tune_tremont__");
379 break;
380 case PROCESSOR_KNL:
381 def_or_undef (parse_in, "__tune_knl__");
382 break;
383 case PROCESSOR_KNM:
384 def_or_undef (parse_in, "__tune_knm__");
385 break;
386 case PROCESSOR_SKYLAKE:
387 def_or_undef (parse_in, "__tune_skylake__");
388 break;
389 case PROCESSOR_SKYLAKE_AVX512:
390 def_or_undef (parse_in, "__tune_skylake_avx512__");
391 break;
392 case PROCESSOR_CANNONLAKE:
393 def_or_undef (parse_in, "__tune_cannonlake__");
394 break;
395 case PROCESSOR_ICELAKE_CLIENT:
396 def_or_undef (parse_in, "__tune_icelake_client__");
397 break;
398 case PROCESSOR_ICELAKE_SERVER:
399 def_or_undef (parse_in, "__tune_icelake_server__");
400 break;
401 case PROCESSOR_LAKEMONT:
402 def_or_undef (parse_in, "__tune_lakemont__");
403 break;
404 case PROCESSOR_CASCADELAKE:
405 def_or_undef (parse_in, "__tune_cascadelake__");
406 break;
407 case PROCESSOR_TIGERLAKE:
408 def_or_undef (parse_in, "__tune_tigerlake__");
409 break;
410 case PROCESSOR_COOPERLAKE:
411 def_or_undef (parse_in, "__tune_cooperlake__");
412 break;
413 case PROCESSOR_SAPPHIRERAPIDS:
414 def_or_undef (parse_in, "__tune_sapphirerapids__");
415 break;
416 case PROCESSOR_ALDERLAKE:
417 def_or_undef (parse_in, "__tune_alderlake__");
418 break;
419 case PROCESSOR_ROCKETLAKE:
420 def_or_undef (parse_in, "__tune_rocketlake__");
421 break;
422 case PROCESSOR_INTEL:
423 case PROCESSOR_GENERIC:
424 break;
425 /* use PROCESSOR_max to not set/unset the tune macro. */
426 case PROCESSOR_max:
427 break;
428 }
429
430 switch (ix86_cmodel)
431 {
432 case CM_SMALL:
433 case CM_SMALL_PIC:
434 def_or_undef (parse_in, "__code_model_small__");
435 break;
436 case CM_MEDIUM:
437 case CM_MEDIUM_PIC:
438 def_or_undef (parse_in, "__code_model_medium__");
439 break;
440 case CM_LARGE:
441 case CM_LARGE_PIC:
442 def_or_undef (parse_in, "__code_model_large__");
443 break;
444 case CM_32:
445 def_or_undef (parse_in, "__code_model_32__");
446 break;
447 case CM_KERNEL:
448 def_or_undef (parse_in, "__code_model_kernel__");
449 break;
450 default:
451 ;
452 }
453
454 if (isa_flag2 & OPTION_MASK_ISA2_WBNOINVD)
455 def_or_undef (parse_in, "__WBNOINVD__");
456 if (isa_flag2 & OPTION_MASK_ISA2_AVX512VP2INTERSECT)
457 def_or_undef (parse_in, "__AVX512VP2INTERSECT__");
458 if (isa_flag & OPTION_MASK_ISA_MMX)
459 def_or_undef (parse_in, "__MMX__");
460 if (isa_flag & OPTION_MASK_ISA_3DNOW)
461 def_or_undef (parse_in, "__3dNOW__");
462 if (isa_flag & OPTION_MASK_ISA_3DNOW_A)
463 def_or_undef (parse_in, "__3dNOW_A__");
464 if (isa_flag & OPTION_MASK_ISA_SSE)
465 def_or_undef (parse_in, "__SSE__");
466 if (isa_flag & OPTION_MASK_ISA_SSE2)
467 def_or_undef (parse_in, "__SSE2__");
468 if (isa_flag & OPTION_MASK_ISA_SSE3)
469 def_or_undef (parse_in, "__SSE3__");
470 if (isa_flag & OPTION_MASK_ISA_SSSE3)
471 def_or_undef (parse_in, "__SSSE3__");
472 if (isa_flag & OPTION_MASK_ISA_SSE4_1)
473 def_or_undef (parse_in, "__SSE4_1__");
474 if (isa_flag & OPTION_MASK_ISA_SSE4_2)
475 def_or_undef (parse_in, "__SSE4_2__");
476 if (isa_flag & OPTION_MASK_ISA_AES)
477 def_or_undef (parse_in, "__AES__");
478 if (isa_flag & OPTION_MASK_ISA_SHA)
479 def_or_undef (parse_in, "__SHA__");
480 if (isa_flag & OPTION_MASK_ISA_PCLMUL)
481 def_or_undef (parse_in, "__PCLMUL__");
482 if (isa_flag & OPTION_MASK_ISA_AVX)
483 def_or_undef (parse_in, "__AVX__");
484 if (isa_flag & OPTION_MASK_ISA_AVX2)
485 def_or_undef (parse_in, "__AVX2__");
486 if (isa_flag & OPTION_MASK_ISA_AVX512F)
487 def_or_undef (parse_in, "__AVX512F__");
488 if (isa_flag & OPTION_MASK_ISA_AVX512ER)
489 def_or_undef (parse_in, "__AVX512ER__");
490 if (isa_flag & OPTION_MASK_ISA_AVX512CD)
491 def_or_undef (parse_in, "__AVX512CD__");
492 if (isa_flag & OPTION_MASK_ISA_AVX512PF)
493 def_or_undef (parse_in, "__AVX512PF__");
494 if (isa_flag & OPTION_MASK_ISA_AVX512DQ)
495 def_or_undef (parse_in, "__AVX512DQ__");
496 if (isa_flag & OPTION_MASK_ISA_AVX512BW)
497 def_or_undef (parse_in, "__AVX512BW__");
498 if (isa_flag & OPTION_MASK_ISA_AVX512VL)
499 def_or_undef (parse_in, "__AVX512VL__");
500 if (isa_flag & OPTION_MASK_ISA_AVX512VBMI)
501 def_or_undef (parse_in, "__AVX512VBMI__");
502 if (isa_flag & OPTION_MASK_ISA_AVX512IFMA)
503 def_or_undef (parse_in, "__AVX512IFMA__");
504 if (isa_flag2 & OPTION_MASK_ISA2_AVX5124VNNIW)
505 def_or_undef (parse_in, "__AVX5124VNNIW__");
506 if (isa_flag & OPTION_MASK_ISA_AVX512VBMI2)
507 def_or_undef (parse_in, "__AVX512VBMI2__");
508 if (isa_flag & OPTION_MASK_ISA_AVX512VNNI)
509 def_or_undef (parse_in, "__AVX512VNNI__");
510 if (isa_flag2 & OPTION_MASK_ISA2_PCONFIG)
511 def_or_undef (parse_in, "__PCONFIG__");
512 if (isa_flag2 & OPTION_MASK_ISA2_SGX)
513 def_or_undef (parse_in, "__SGX__");
514 if (isa_flag2 & OPTION_MASK_ISA2_AVX5124FMAPS)
515 def_or_undef (parse_in, "__AVX5124FMAPS__");
516 if (isa_flag & OPTION_MASK_ISA_AVX512BITALG)
517 def_or_undef (parse_in, "__AVX512BITALG__");
518 if (isa_flag & OPTION_MASK_ISA_AVX512VPOPCNTDQ)
519 def_or_undef (parse_in, "__AVX512VPOPCNTDQ__");
520 if (isa_flag & OPTION_MASK_ISA_FMA)
521 def_or_undef (parse_in, "__FMA__");
522 if (isa_flag & OPTION_MASK_ISA_RTM)
523 def_or_undef (parse_in, "__RTM__");
524 if (isa_flag & OPTION_MASK_ISA_SSE4A)
525 def_or_undef (parse_in, "__SSE4A__");
526 if (isa_flag & OPTION_MASK_ISA_FMA4)
527 def_or_undef (parse_in, "__FMA4__");
528 if (isa_flag & OPTION_MASK_ISA_XOP)
529 def_or_undef (parse_in, "__XOP__");
530 if (isa_flag & OPTION_MASK_ISA_LWP)
531 def_or_undef (parse_in, "__LWP__");
532 if (isa_flag & OPTION_MASK_ISA_ABM)
533 def_or_undef (parse_in, "__ABM__");
534 if (isa_flag & OPTION_MASK_ISA_BMI)
535 def_or_undef (parse_in, "__BMI__");
536 if (isa_flag & OPTION_MASK_ISA_BMI2)
537 def_or_undef (parse_in, "__BMI2__");
538 if (isa_flag & OPTION_MASK_ISA_LZCNT)
539 def_or_undef (parse_in, "__LZCNT__");
540 if (isa_flag & OPTION_MASK_ISA_TBM)
541 def_or_undef (parse_in, "__TBM__");
542 if (isa_flag & OPTION_MASK_ISA_CRC32)
543 def_or_undef (parse_in, "__CRC32__");
544 if (isa_flag & OPTION_MASK_ISA_POPCNT)
545 def_or_undef (parse_in, "__POPCNT__");
546 if (isa_flag & OPTION_MASK_ISA_FSGSBASE)
547 def_or_undef (parse_in, "__FSGSBASE__");
548 if (isa_flag & OPTION_MASK_ISA_RDRND)
549 def_or_undef (parse_in, "__RDRND__");
550 if (isa_flag & OPTION_MASK_ISA_F16C)
551 def_or_undef (parse_in, "__F16C__");
552 if (isa_flag & OPTION_MASK_ISA_RDSEED)
553 def_or_undef (parse_in, "__RDSEED__");
554 if (isa_flag & OPTION_MASK_ISA_PRFCHW)
555 def_or_undef (parse_in, "__PRFCHW__");
556 if (isa_flag & OPTION_MASK_ISA_ADX)
557 def_or_undef (parse_in, "__ADX__");
558 if (isa_flag & OPTION_MASK_ISA_FXSR)
559 def_or_undef (parse_in, "__FXSR__");
560 if (isa_flag & OPTION_MASK_ISA_XSAVE)
561 def_or_undef (parse_in, "__XSAVE__");
562 if (isa_flag & OPTION_MASK_ISA_XSAVEOPT)
563 def_or_undef (parse_in, "__XSAVEOPT__");
564 if (isa_flag & OPTION_MASK_ISA_PREFETCHWT1)
565 def_or_undef (parse_in, "__PREFETCHWT1__");
566 if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
567 def_or_undef (parse_in, "__SSE_MATH__");
568 if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
569 def_or_undef (parse_in, "__SSE2_MATH__");
570 if (isa_flag & OPTION_MASK_ISA_CLFLUSHOPT)
571 def_or_undef (parse_in, "__CLFLUSHOPT__");
572 if (isa_flag2 & OPTION_MASK_ISA2_CLZERO)
573 def_or_undef (parse_in, "__CLZERO__");
574 if (isa_flag & OPTION_MASK_ISA_XSAVEC)
575 def_or_undef (parse_in, "__XSAVEC__");
576 if (isa_flag & OPTION_MASK_ISA_XSAVES)
577 def_or_undef (parse_in, "__XSAVES__");
578 if (isa_flag & OPTION_MASK_ISA_CLWB)
579 def_or_undef (parse_in, "__CLWB__");
580 if (isa_flag2 & OPTION_MASK_ISA2_MWAITX)
581 def_or_undef (parse_in, "__MWAITX__");
582 if (isa_flag & OPTION_MASK_ISA_PKU)
583 def_or_undef (parse_in, "__PKU__");
584 if (isa_flag2 & OPTION_MASK_ISA2_RDPID)
585 def_or_undef (parse_in, "__RDPID__");
586 if (isa_flag & OPTION_MASK_ISA_GFNI)
587 def_or_undef (parse_in, "__GFNI__");
588 if ((isa_flag & OPTION_MASK_ISA_SHSTK))
589 def_or_undef (parse_in, "__SHSTK__");
590 if (isa_flag2 & OPTION_MASK_ISA2_VAES)
591 def_or_undef (parse_in, "__VAES__");
592 if (isa_flag & OPTION_MASK_ISA_VPCLMULQDQ)
593 def_or_undef (parse_in, "__VPCLMULQDQ__");
594 if (isa_flag & OPTION_MASK_ISA_MOVDIRI)
595 def_or_undef (parse_in, "__MOVDIRI__");
596 if (isa_flag2 & OPTION_MASK_ISA2_MOVDIR64B)
597 def_or_undef (parse_in, "__MOVDIR64B__");
598 if (isa_flag2 & OPTION_MASK_ISA2_WAITPKG)
599 def_or_undef (parse_in, "__WAITPKG__");
600 if (isa_flag2 & OPTION_MASK_ISA2_CLDEMOTE)
601 def_or_undef (parse_in, "__CLDEMOTE__");
602 if (isa_flag2 & OPTION_MASK_ISA2_SERIALIZE)
603 def_or_undef (parse_in, "__SERIALIZE__");
604 if (isa_flag2 & OPTION_MASK_ISA2_PTWRITE)
605 def_or_undef (parse_in, "__PTWRITE__");
606 if (isa_flag2 & OPTION_MASK_ISA2_AVX512BF16)
607 def_or_undef (parse_in, "__AVX512BF16__");
608 if (isa_flag2 & OPTION_MASK_ISA2_AVX512FP16)
609 def_or_undef (parse_in, "__AVX512FP16__");
610 if (TARGET_MMX_WITH_SSE)
611 def_or_undef (parse_in, "__MMX_WITH_SSE__");
612 if (isa_flag2 & OPTION_MASK_ISA2_ENQCMD)
613 def_or_undef (parse_in, "__ENQCMD__");
614 if (isa_flag2 & OPTION_MASK_ISA2_TSXLDTRK)
615 def_or_undef (parse_in, "__TSXLDTRK__");
616 if (isa_flag2 & OPTION_MASK_ISA2_AMX_TILE)
617 def_or_undef (parse_in, "__AMX_TILE__");
618 if (isa_flag2 & OPTION_MASK_ISA2_AMX_INT8)
619 def_or_undef (parse_in, "__AMX_INT8__");
620 if (isa_flag2 & OPTION_MASK_ISA2_AMX_BF16)
621 def_or_undef (parse_in, "__AMX_BF16__");
622 if (isa_flag & OPTION_MASK_ISA_SAHF)
623 def_or_undef (parse_in, "__LAHF_SAHF__");
624 if (isa_flag2 & OPTION_MASK_ISA2_MOVBE)
625 def_or_undef (parse_in, "__MOVBE__");
626 if (isa_flag2 & OPTION_MASK_ISA2_UINTR)
627 def_or_undef (parse_in, "__UINTR__");
628 if (isa_flag2 & OPTION_MASK_ISA2_HRESET)
629 def_or_undef (parse_in, "__HRESET__");
630 if (isa_flag2 & OPTION_MASK_ISA2_KL)
631 def_or_undef (parse_in, "__KL__");
632 if (isa_flag2 & OPTION_MASK_ISA2_WIDEKL)
633 def_or_undef (parse_in, "__WIDEKL__");
634 if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNI)
635 def_or_undef (parse_in, "__AVXVNNI__");
636 if (TARGET_IAMCU)
637 {
638 def_or_undef (parse_in, "__iamcu");
639 def_or_undef (parse_in, "__iamcu__");
640 }
641 }
642
643
644 /* Hook to validate the current #pragma GCC target and set the state, and
645 update the macros based on what was changed. If ARGS is NULL, then
646 POP_TARGET is used to reset the options. */
647
648 static bool
ix86_pragma_target_parse(tree args,tree pop_target)649 ix86_pragma_target_parse (tree args, tree pop_target)
650 {
651 tree prev_tree
652 = build_target_option_node (&global_options, &global_options_set);
653 tree cur_tree;
654 struct cl_target_option *prev_opt;
655 struct cl_target_option *cur_opt;
656 HOST_WIDE_INT prev_isa;
657 HOST_WIDE_INT cur_isa;
658 HOST_WIDE_INT diff_isa;
659 HOST_WIDE_INT prev_isa2;
660 HOST_WIDE_INT cur_isa2;
661 HOST_WIDE_INT diff_isa2;
662 enum processor_type prev_arch;
663 enum processor_type prev_tune;
664 enum processor_type cur_arch;
665 enum processor_type cur_tune;
666
667 if (! args)
668 {
669 cur_tree = (pop_target ? pop_target : target_option_default_node);
670 cl_target_option_restore (&global_options, &global_options_set,
671 TREE_TARGET_OPTION (cur_tree));
672 }
673 else
674 {
675 cur_tree = ix86_valid_target_attribute_tree (NULL_TREE, args,
676 &global_options,
677 &global_options_set, 0);
678 if (!cur_tree || cur_tree == error_mark_node)
679 {
680 cl_target_option_restore (&global_options, &global_options_set,
681 TREE_TARGET_OPTION (prev_tree));
682 return false;
683 }
684 }
685
686 target_option_current_node = cur_tree;
687 ix86_reset_previous_fndecl ();
688
689 /* Figure out the previous/current isa, arch, tune and the differences. */
690 prev_opt = TREE_TARGET_OPTION (prev_tree);
691 cur_opt = TREE_TARGET_OPTION (cur_tree);
692 prev_isa = prev_opt->x_ix86_isa_flags;
693 cur_isa = cur_opt->x_ix86_isa_flags;
694 diff_isa = (prev_isa ^ cur_isa);
695 prev_isa2 = prev_opt->x_ix86_isa_flags2;
696 cur_isa2 = cur_opt->x_ix86_isa_flags2;
697 diff_isa2 = (prev_isa2 ^ cur_isa2);
698 prev_arch = (enum processor_type) prev_opt->arch;
699 prev_tune = (enum processor_type) prev_opt->tune;
700 cur_arch = (enum processor_type) cur_opt->arch;
701 cur_tune = (enum processor_type) cur_opt->tune;
702
703 /* If the same processor is used for both previous and current options, don't
704 change the macros. */
705 if (cur_arch == prev_arch)
706 cur_arch = prev_arch = PROCESSOR_max;
707
708 if (cur_tune == prev_tune)
709 cur_tune = prev_tune = PROCESSOR_max;
710
711 /* Undef all of the macros for that are no longer current. */
712 cpp_force_token_locations (parse_in, BUILTINS_LOCATION);
713 ix86_target_macros_internal (prev_isa & diff_isa,
714 prev_isa2 & diff_isa2,
715 prev_arch,
716 prev_tune,
717 (enum fpmath_unit) prev_opt->x_ix86_fpmath,
718 cpp_undef);
719 cpp_stop_forcing_token_locations (parse_in);
720
721 /* For the definitions, ensure all newly defined macros are considered
722 as used for -Wunused-macros. There is no point warning about the
723 compiler predefined macros. */
724 cpp_options *cpp_opts = cpp_get_options (parse_in);
725 unsigned char saved_warn_unused_macros = cpp_opts->warn_unused_macros;
726 cpp_opts->warn_unused_macros = 0;
727
728 /* Define all of the macros for new options that were just turned on. */
729 cpp_force_token_locations (parse_in, BUILTINS_LOCATION);
730 ix86_target_macros_internal (cur_isa & diff_isa,
731 cur_isa2 & diff_isa2,
732 cur_arch,
733 cur_tune,
734 (enum fpmath_unit) cur_opt->x_ix86_fpmath,
735 cpp_define);
736 cpp_stop_forcing_token_locations (parse_in);
737
738 cpp_opts->warn_unused_macros = saved_warn_unused_macros;
739
740 return true;
741 }
742
743 /* Function to tell the preprocessor about the defines for the current target. */
744
745 void
ix86_target_macros(void)746 ix86_target_macros (void)
747 {
748 /* 32/64-bit won't change with target specific options, so do the assert and
749 builtin_define_std calls here. */
750 if (TARGET_64BIT)
751 {
752 cpp_assert (parse_in, "cpu=x86_64");
753 cpp_assert (parse_in, "machine=x86_64");
754 cpp_define (parse_in, "__amd64");
755 cpp_define (parse_in, "__amd64__");
756 cpp_define (parse_in, "__x86_64");
757 cpp_define (parse_in, "__x86_64__");
758 if (TARGET_X32)
759 {
760 cpp_define (parse_in, "_ILP32");
761 cpp_define (parse_in, "__ILP32__");
762 }
763 }
764 else
765 {
766 cpp_assert (parse_in, "cpu=i386");
767 cpp_assert (parse_in, "machine=i386");
768 builtin_define_std ("i386");
769 cpp_define (parse_in, "_ILP32");
770 cpp_define (parse_in, "__ILP32__");
771 }
772
773 if (!TARGET_80387)
774 cpp_define (parse_in, "_SOFT_FLOAT");
775
776 if (TARGET_LONG_DOUBLE_64)
777 cpp_define (parse_in, "__LONG_DOUBLE_64__");
778
779 if (TARGET_LONG_DOUBLE_128)
780 cpp_define (parse_in, "__LONG_DOUBLE_128__");
781
782 cpp_define_formatted (parse_in, "__SIZEOF_FLOAT80__=%d",
783 GET_MODE_SIZE (XFmode));
784
785 cpp_define (parse_in, "__SIZEOF_FLOAT128__=16");
786
787 cpp_define_formatted (parse_in, "__ATOMIC_HLE_ACQUIRE=%d", IX86_HLE_ACQUIRE);
788 cpp_define_formatted (parse_in, "__ATOMIC_HLE_RELEASE=%d", IX86_HLE_RELEASE);
789
790 cpp_define (parse_in, "__GCC_ASM_FLAG_OUTPUTS__");
791
792 ix86_target_macros_internal (ix86_isa_flags,
793 ix86_isa_flags2,
794 ix86_arch,
795 ix86_tune,
796 ix86_fpmath,
797 cpp_define);
798
799 cpp_define (parse_in, "__SEG_FS");
800 cpp_define (parse_in, "__SEG_GS");
801
802 if (flag_cf_protection != CF_NONE)
803 cpp_define_formatted (parse_in, "__CET__=%d", flag_cf_protection & ~CF_SET);
804 }
805
806
807 /* Register target pragmas. We need to add the hook for parsing #pragma GCC
808 option here rather than in i386.cc since it will pull in various preprocessor
809 functions, and those are not present in languages like fortran without a
810 preprocessor. */
811
812 void
ix86_register_pragmas(void)813 ix86_register_pragmas (void)
814 {
815 /* Update pragma hook to allow parsing #pragma GCC target. */
816 targetm.target_option.pragma_parse = ix86_pragma_target_parse;
817
818 c_register_addr_space ("__seg_fs", ADDR_SPACE_SEG_FS);
819 c_register_addr_space ("__seg_gs", ADDR_SPACE_SEG_GS);
820
821 #ifdef REGISTER_SUBTARGET_PRAGMAS
822 REGISTER_SUBTARGET_PRAGMAS ();
823 #endif
824 }
825