1;; ----------------------------------------------------------------- 2;; COMBINE PATTERNS 3;; ----------------------------------------------------------------- 4 5;; insv:SI 6 7(define_insn_and_split "*insv_si_1_n" 8 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 9 (const_int 1) 10 (match_operand:SI 1 "const_int_operand" "n")) 11 (match_operand:SI 2 "register_operand" "r"))] 12 "INTVAL (operands[1]) < 16" 13 "#" 14 "&& reload_completed" 15 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)) 16 (match_dup 2)) 17 (clobber (reg:CC CC_REG))])]) 18 19(define_insn "*insv_si_1_n_clobber_flags" 20 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 21 (const_int 1) 22 (match_operand:SI 1 "const_int_operand" "n")) 23 (match_operand:SI 2 "register_operand" "r")) 24 (clobber (reg:CC CC_REG))] 25 "INTVAL (operands[1]) < 16" 26 "bld\\t#0,%w2\;bst\\t%Z1,%Y0" 27 [(set_attr "length" "4")]) 28 29(define_insn_and_split "*insv_si_1_n_lshiftrt" 30 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 31 (const_int 1) 32 (match_operand:SI 1 "const_int_operand" "n")) 33 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 34 (match_operand:SI 3 "const_int_operand" "n")))] 35 "INTVAL (operands[1]) < 16 && INTVAL (operands[3]) < 16" 36 "#" 37 "&& reload_completed" 38 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)) 39 (lshiftrt:SI (match_dup 2) (match_dup 3))) 40 (clobber (reg:CC CC_REG))])]) 41 42(define_insn "*insv_si_1_n_lshiftrt_clobber_flags" 43 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 44 (const_int 1) 45 (match_operand:SI 1 "const_int_operand" "n")) 46 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 47 (match_operand:SI 3 "const_int_operand" "n"))) 48 (clobber (reg:CC CC_REG))] 49 "INTVAL (operands[1]) < 16 && INTVAL (operands[3]) < 16" 50 "bld\\t%Z3,%Y2\;bst\\t%Z1,%Y0" 51 [(set_attr "length" "4")]) 52 53(define_insn_and_split "*insv_si_1_n_lshiftrt_16" 54 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 55 (const_int 1) 56 (match_operand:SI 1 "const_int_operand" "n")) 57 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 58 (const_int 16)))] 59 "INTVAL (operands[1]) < 16" 60 "#" 61 "&& reload_completed" 62 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)) 63 (lshiftrt:SI (match_dup 2) (const_int 16))) 64 (clobber (reg:CC CC_REG))])]) 65 66(define_insn "*insv_si_1_n_lshiftrt_16_clobber_flags" 67 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 68 (const_int 1) 69 (match_operand:SI 1 "const_int_operand" "n")) 70 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 71 (const_int 16))) 72 (clobber (reg:CC CC_REG))] 73 "INTVAL (operands[1]) < 16" 74 "rotr.w\\t%e2\;rotl.w\\t%e2\;bst\\t%Z1,%Y0" 75 [(set_attr "length" "6")]) 76 77(define_insn_and_split "*insv_si_8_8" 78 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 79 (const_int 8) 80 (const_int 8)) 81 (match_operand:SI 1 "register_operand" "r"))] 82 "" 83 "#" 84 "&& reload_completed" 85 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) 86 (match_dup 1)) 87 (clobber (reg:CC CC_REG))])]) 88 89(define_insn "*insv_si_8_8_clobber_flags" 90 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 91 (const_int 8) 92 (const_int 8)) 93 (match_operand:SI 1 "register_operand" "r")) 94 (clobber (reg:CC CC_REG))] 95 "" 96 "mov.b\\t%w1,%x0" 97 [(set_attr "length" "2")]) 98 99(define_insn_and_split "*insv_si_8_8_lshiftrt_8" 100 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 101 (const_int 8) 102 (const_int 8)) 103 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 104 (const_int 8)))] 105 "" 106 "#" 107 "&& reload_completed" 108 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) 109 (lshiftrt:SI (match_dup 1) (const_int 8))) 110 (clobber (reg:CC CC_REG))])]) 111 112(define_insn "*insv_si_8_8_lshiftrt_8_clobber_flags" 113 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 114 (const_int 8) 115 (const_int 8)) 116 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 117 (const_int 8))) 118 (clobber (reg:CC CC_REG))] 119 "" 120 "mov.b\\t%x1,%x0" 121 [(set_attr "length" "2")]) 122 123;; extzv:SI 124 125(define_insn_and_split "*extzv_8_8" 126 [(set (match_operand:SI 0 "register_operand" "=r,r") 127 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r") 128 (const_int 8) 129 (const_int 8)))] 130 "" 131 "#" 132 "&& reload_completed" 133 [(parallel [(set (match_dup 0) 134 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))) 135 (clobber (reg:CC CC_REG))])]) 136 137(define_insn "*extzv_8_8_clobber_flags" 138 [(set (match_operand:SI 0 "register_operand" "=r,r") 139 (zero_extract:SI (match_operand:SI 1 "register_operand" "?0,r") 140 (const_int 8) 141 (const_int 8))) 142 (clobber (reg:CC CC_REG))] 143 "" 144 "@ 145 mov.b\\t%x1,%w0\;extu.w\\t%f0\;extu.l\\t%S0 146 sub.l\\t%S0,%S0\;mov.b\\t%x1,%w0" 147 [(set_attr "length" "6,4")]) 148 149(define_insn_and_split "*extzv_8_16" 150 [(set (match_operand:SI 0 "register_operand" "=r") 151 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 152 (const_int 8) 153 (const_int 16)))] 154 "" 155 "#" 156 "&& reload_completed" 157 [(parallel [(set (match_dup 0) 158 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 16))) 159 (clobber (reg:CC CC_REG))])]) 160 161(define_insn "*extzv_8_16_clobber_flags" 162 [(set (match_operand:SI 0 "register_operand" "=r") 163 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 164 (const_int 8) 165 (const_int 16))) 166 (clobber (reg:CC CC_REG))] 167 "" 168 "mov.w\\t%e1,%f0\;extu.w\\t%f0\;extu.l\\t%S0" 169 [(set_attr "length" "6")]) 170 171(define_insn_and_split "*extzv_16_8" 172 [(set (match_operand:SI 0 "register_operand" "=r") 173 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 174 (const_int 16) 175 (const_int 8))) 176 (clobber (match_scratch:SI 2 "=&r"))] 177 "TARGET_H8300H" 178 "#" 179 "&& reload_completed" 180 [(parallel [(set (match_dup 0) 181 (zero_extract:SI (match_dup 1) (const_int 16) (const_int 8))) 182 (clobber (reg:CC CC_REG))])]) 183 184(define_insn "*extzv_16_8_clobber_flags" 185 [(set (match_operand:SI 0 "register_operand" "=r") 186 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 187 (const_int 16) 188 (const_int 8))) 189 (clobber (match_scratch:SI 2 "=&r")) 190 (clobber (reg:CC CC_REG))] 191 "TARGET_H8300H" 192 "mov.w\\t%e1,%f2\;mov.b\\t%x1,%w0\;mov.b\\t%w2,%x0\;extu.l\\t%S0" 193 [(set_attr "length" "8")]) 194 195;; Extract the exponent of a float. 196 197(define_insn_and_split "*extzv_8_23" 198 [(set (match_operand:SI 0 "register_operand" "=r") 199 (zero_extract:SI (match_operand:SI 1 "register_operand" "0") 200 (const_int 8) 201 (const_int 23)))] 202 "" 203 "#" 204 "&& reload_completed" 205 [(parallel [(set (match_dup 0) 206 (ashift:SI (match_dup 0) 207 (const_int 1))) 208 (clobber (scratch:QI)) 209 (clobber (reg:CC CC_REG))]) 210 (parallel [(set (match_dup 0) 211 (lshiftrt:SI (match_dup 0) 212 (const_int 24))) 213 (clobber (scratch:QI)) 214 (clobber (reg:CC CC_REG))])]) 215 216;; and:SI 217 218;; ((SImode) HImode) << 15 219 220(define_insn_and_split "*twoshifts_l16_r1" 221 [(set (match_operand:SI 0 "register_operand" "=r") 222 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 223 (const_int 15)) 224 (const_int 2147450880)))] 225 "" 226 "#" 227 "&& reload_completed" 228 [(parallel [(set (match_dup 0) 229 (ashift:SI (match_dup 0) 230 (const_int 16))) 231 (clobber (scratch:QI)) 232 (clobber (reg:CC CC_REG))]) 233 (parallel [(set (match_dup 0) 234 (lshiftrt:SI (match_dup 0) 235 (const_int 1))) 236 (clobber (scratch:QI)) 237 (clobber (reg:CC CC_REG))])]) 238 239;; Transform (SImode << B) & 0xffff into (SImode) (HImode << B). 240 241(define_insn_and_split "*andsi3_ashift_n_lower" 242 [(set (match_operand:SI 0 "register_operand" "=r,r") 243 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0,0") 244 (match_operand:QI 2 "const_int_operand" "S,n")) 245 (match_operand:SI 3 "const_int_operand" "n,n"))) 246 (clobber (match_scratch:QI 4 "=X,&r"))] 247 "INTVAL (operands[2]) <= 15 248 && UINTVAL (operands[3]) == ((HOST_WIDE_INT_M1U << INTVAL (operands[2])) 249 & 0xffff)" 250 "#" 251 "&& reload_completed" 252 [(parallel [(set (match_dup 5) 253 (ashift:HI (match_dup 5) 254 (match_dup 2))) 255 (clobber (match_dup 4)) 256 (clobber (reg:CC CC_REG))]) 257 (parallel [(set (match_dup 0) 258 (zero_extend:SI (match_dup 5))) 259 (clobber (reg:CC CC_REG))])] 260 { 261 operands[5] = gen_rtx_REG (HImode, REGNO (operands[0])); 262 }) 263 264;; Accept (A >> 30) & 2 and the like. 265 266(define_insn_and_split "*andsi3_lshiftrt_n_sb" 267 [(set (match_operand:SI 0 "register_operand" "=r") 268 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 269 (match_operand:SI 2 "const_int_operand" "n")) 270 (match_operand:SI 3 "single_one_operand" "n")))] 271 "exact_log2 (INTVAL (operands[3])) < 16 272 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31" 273 "#" 274 "&& reload_completed" 275 [(parallel [(set (match_dup 0) 276 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) 277 (match_dup 3))) 278 (clobber (reg:CC CC_REG))])]) 279 280(define_insn "*andsi3_lshiftrt_n_sb" 281 [(set (match_operand:SI 0 "register_operand" "=r") 282 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 283 (match_operand:SI 2 "const_int_operand" "n")) 284 (match_operand:SI 3 "single_one_operand" "n"))) 285 (clobber (reg:CC CC_REG))] 286 "exact_log2 (INTVAL (operands[3])) < 16 287 && INTVAL (operands[2]) + exact_log2 (INTVAL (operands[3])) == 31" 288{ 289 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); 290 return "shll.l\\t%S0\;xor.l\\t%S0,%S0\;bst\\t%Z3,%Y0"; 291} 292 [(set_attr "length" "8")]) 293 294(define_insn_and_split "*andsi3_lshiftrt_9_sb" 295 [(set (match_operand:SI 0 "register_operand" "=r") 296 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 297 (const_int 9)) 298 (const_int 4194304)))] 299 "" 300 "#" 301 "&& reload_completed" 302 [(parallel [(set (match_dup 0) 303 (and:SI (lshiftrt:SI (match_dup 0) (const_int 25)) 304 (const_int 64))) 305 (clobber (reg:CC CC_REG))]) 306 (parallel [(set (match_dup 0) 307 (ashift:SI (match_dup 0) 308 (const_int 16))) 309 (clobber (scratch:QI)) 310 (clobber (reg:CC CC_REG))])]) 311 312;; plus:SI 313 314(define_insn_and_split "*addsi3_upper" 315 [(set (match_operand:SI 0 "register_operand" "=r") 316 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") 317 (const_int 65536)) 318 (match_operand:SI 2 "register_operand" "0")))] 319 "" 320 "#" 321 "&& reload_completed" 322 [(parallel [(set (match_dup 0) 323 (plus:SI (mult:SI (match_dup 1) (const_int 65536)) 324 (match_dup 2))) 325 (clobber (reg:CC CC_REG))])]) 326 327(define_insn "*addsi3_upper_clobber_regs" 328 [(set (match_operand:SI 0 "register_operand" "=r") 329 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") 330 (const_int 65536)) 331 (match_operand:SI 2 "register_operand" "0"))) 332 (clobber (reg:CC CC_REG))] 333 "" 334 "add.w\\t%f1,%e0" 335 [(set_attr "length" "2")]) 336 337(define_insn_and_split "*addsi3_lshiftrt_16_zexthi" 338 [(set (match_operand:SI 0 "register_operand" "=r") 339 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 340 (const_int 16)) 341 (zero_extend:SI (match_operand:HI 2 "register_operand" "0"))))] 342 "" 343 "#" 344 "&& reload_completed" 345 [(parallel [(set (match_dup 0) 346 (plus:SI (lshiftrt:SI (match_dup 1) (const_int 16)) 347 (zero_extend:SI (match_dup 2)))) 348 (clobber (reg:CC CC_REG))])]) 349 350(define_insn "*addsi3_lshiftrt_16_zexthi_clobber_flags" 351 [(set (match_operand:SI 0 "register_operand" "=r") 352 (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 353 (const_int 16)) 354 (zero_extend:SI (match_operand:HI 2 "register_operand" "0")))) 355 (clobber (reg:CC CC_REG))] 356 "" 357 "add.w\\t%e1,%f0\;xor.w\\t%e0,%e0\;rotxl.w\\t%e0" 358 [(set_attr "length" "6")]) 359 360;;(define_insn_and_split "*addsi3_and_r_1" 361;; [(set (match_operand:SI 0 "register_operand" "=r") 362;; (plus:SI (and:SI (match_operand:SI 1 "register_operand" "r") 363;; (const_int 1)) 364;; (match_operand:SI 2 "register_operand" "0")))] 365;; "" 366;; "#" 367;; "&& reload_completed" 368;; [(set (cc0) (compare (zero_extract:SI (match_dup 1) 369;; (const_int 1) 370;; (const_int 0)) 371;; (const_int 0))) 372;; (set (pc) 373;; (if_then_else (eq (cc0) 374;; (const_int 0)) 375;; (label_ref (match_dup 3)) 376;; (pc))) 377;; (set (match_dup 2) 378;; (plus:SI (match_dup 2) 379;; (const_int 1))) 380;; (match_dup 3)] 381;; { 382;; operands[3] = gen_label_rtx (); 383;; }) 384 385;;(define_insn_and_split "*addsi3_and_not_r_1" 386;; [(set (match_operand:SI 0 "register_operand" "=r") 387;; (plus:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "r")) 388;; (const_int 1)) 389;; (match_operand:SI 2 "register_operand" "0")))] 390;; "" 391;; "#" 392;; "&& reload_completed" 393;; [(set (cc0) (compare (zero_extract:SI (match_dup 1) 394;; (const_int 1) 395;; (const_int 0)) 396;; (const_int 0))) 397;; (set (pc) 398;; (if_then_else (ne (cc0) 399;; (const_int 0)) 400;; (label_ref (match_dup 3)) 401;; (pc))) 402;; (set (match_dup 2) 403;; (plus:SI (match_dup 2) 404;; (const_int 1))) 405;; (match_dup 3)] 406;; { 407;; operands[3] = gen_label_rtx (); 408;; }) 409 410;; [ix]or:HI 411 412(define_insn_and_split "*ixorhi3_zext" 413 [(set (match_operand:HI 0 "register_operand" "=r") 414 (match_operator:HI 1 "iorxor_operator" 415 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r")) 416 (match_operand:HI 3 "register_operand" "0")]))] 417 "" 418 "#" 419 "&& reload_completed" 420 [(parallel [(set (match_dup 0) 421 (match_op_dup 1 [(zero_extend:HI (match_dup 2)) 422 (match_dup 3)])) 423 (clobber (reg:CC CC_REG))])]) 424 425 426(define_insn "*ixorhi3_zext_clobber_flags" 427 [(set (match_operand:HI 0 "register_operand" "=r") 428 (match_operator:HI 1 "iorxor_operator" 429 [(zero_extend:HI (match_operand:QI 2 "register_operand" "r")) 430 (match_operand:HI 3 "register_operand" "0")])) 431 (clobber (reg:CC CC_REG))] 432 "" 433 "%c1.b\\t%X2,%s0" 434 [(set_attr "length" "2")]) 435 436;; [ix]or:SI 437 438(define_insn_and_split "*ixorsi3_zext_qi" 439 [(set (match_operand:SI 0 "register_operand" "=r") 440 (match_operator:SI 1 "iorxor_operator" 441 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r")) 442 (match_operand:SI 3 "register_operand" "0")]))] 443 "" 444 "#" 445 "&& reload_completed" 446 [(parallel [(set (match_dup 0) 447 (match_op_dup 1 [(zero_extend:SI (match_dup 2)) 448 (match_dup 3)])) 449 (clobber (reg:CC CC_REG))])]) 450 451(define_insn "*ixorsi3_zext_qi_clobber_flags" 452 [(set (match_operand:SI 0 "register_operand" "=r") 453 (match_operator:SI 1 "iorxor_operator" 454 [(zero_extend:SI (match_operand:QI 2 "register_operand" "r")) 455 (match_operand:SI 3 "register_operand" "0")])) 456 (clobber (reg:CC CC_REG))] 457 "" 458 "%c1.b\\t%X2,%w0" 459 [(set_attr "length" "2")]) 460 461(define_insn_and_split "*ixorsi3_zext_hi" 462 [(set (match_operand:SI 0 "register_operand" "=r") 463 (match_operator:SI 1 "iorxor_operator" 464 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r")) 465 (match_operand:SI 3 "register_operand" "0")]))] 466 "" 467 "#" 468 "&& reload_completed" 469 [(parallel [(set (match_dup 0) 470 (match_op_dup 1 [(zero_extend:SI (match_dup 2)) 471 (match_dup 3)])) 472 (clobber (reg:CC CC_REG))])]) 473 474(define_insn "*ixorsi3_zext_hi_clobber_flags" 475 [(set (match_operand:SI 0 "register_operand" "=r") 476 (match_operator:SI 1 "iorxor_operator" 477 [(zero_extend:SI (match_operand:HI 2 "register_operand" "r")) 478 (match_operand:SI 3 "register_operand" "0")])) 479 (clobber (reg:CC CC_REG))] 480 "" 481 "%c1.w\\t%T2,%f0" 482 [(set_attr "length" "2")]) 483 484(define_insn_and_split "*ixorsi3_ashift_16" 485 [(set (match_operand:SI 0 "register_operand" "=r") 486 (match_operator:SI 1 "iorxor_operator" 487 [(ashift:SI (match_operand:SI 2 "register_operand" "r") 488 (const_int 16)) 489 (match_operand:SI 3 "register_operand" "0")]))] 490 "" 491 "#" 492 "&& reload_completed" 493 [(parallel [(set (match_dup 0) 494 (match_op_dup 1 [(ashift:SI (match_dup 2) (const_int 16)) 495 (match_dup 3)])) 496 (clobber (reg:CC CC_REG))])]) 497 498(define_insn "*ixorsi3_ashift_16_clobber_flags" 499 [(set (match_operand:SI 0 "register_operand" "=r") 500 (match_operator:SI 1 "iorxor_operator" 501 [(ashift:SI (match_operand:SI 2 "register_operand" "r") 502 (const_int 16)) 503 (match_operand:SI 3 "register_operand" "0")])) 504 (clobber (reg:CC CC_REG))] 505 "" 506 "%c1.w\\t%f2,%e0" 507 [(set_attr "length" "2")]) 508 509(define_insn_and_split "*ixorsi3_lshiftrt_16" 510 [(set (match_operand:SI 0 "register_operand" "=r") 511 (match_operator:SI 1 "iorxor_operator" 512 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 513 (const_int 16)) 514 (match_operand:SI 3 "register_operand" "0")]))] 515 "" 516 "#" 517 "&& reload_completed" 518 [(parallel [(set (match_dup 0) 519 (match_op_dup 1 [(lshiftrt:SI (match_dup 2) (const_int 16)) 520 (match_dup 3)])) 521 (clobber (reg:CC CC_REG))])]) 522 523(define_insn "*ixorsi3_lshiftrt_16_clobber_flags" 524 [(set (match_operand:SI 0 "register_operand" "=r") 525 (match_operator:SI 1 "iorxor_operator" 526 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 527 (const_int 16)) 528 (match_operand:SI 3 "register_operand" "0")])) 529 (clobber (reg:CC CC_REG))] 530 "" 531 "%c1.w\\t%e2,%f0" 532 [(set_attr "length" "2")]) 533 534;; ior:HI 535 536(define_insn_and_split "*iorhi3_ashift_8" 537 [(set (match_operand:HI 0 "register_operand" "=r") 538 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r") 539 (const_int 8)) 540 (match_operand:HI 2 "register_operand" "0")))] 541 "" 542 "#" 543 "&& reload_completed" 544 [(parallel [(set (match_dup 0) 545 (ior:HI (ashift:HI (match_dup 1) (const_int 8)) 546 (match_dup 2))) 547 (clobber (reg:CC CC_REG))])]) 548 549(define_insn "*iorhi3_ashift_8_clobber_flags" 550 [(set (match_operand:HI 0 "register_operand" "=r") 551 (ior:HI (ashift:HI (match_operand:HI 1 "register_operand" "r") 552 (const_int 8)) 553 (match_operand:HI 2 "register_operand" "0"))) 554 (clobber (reg:CC CC_REG))] 555 "" 556 "or.b\\t%s1,%t0" 557 [(set_attr "length" "2")]) 558 559(define_insn_and_split "*iorhi3_lshiftrt_8" 560 [(set (match_operand:HI 0 "register_operand" "=r") 561 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") 562 (const_int 8)) 563 (match_operand:HI 2 "register_operand" "0")))] 564 "" 565 "#" 566 "&& reload_completed" 567 [(parallel [(set (match_dup 0) 568 (ior:HI (lshiftrt:HI (match_dup 1) (const_int 8)) 569 (match_dup 2))) 570 (clobber (reg:CC CC_REG))])]) 571 572(define_insn "*iorhi3_lshiftrt_8_clobber_flags" 573 [(set (match_operand:HI 0 "register_operand" "=r") 574 (ior:HI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") 575 (const_int 8)) 576 (match_operand:HI 2 "register_operand" "0"))) 577 (clobber (reg:CC CC_REG))] 578 "" 579 "or.b\\t%t1,%s0" 580 [(set_attr "length" "2")]) 581 582(define_insn_and_split "*iorhi3_two_qi" 583 [(set (match_operand:HI 0 "register_operand" "=r") 584 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0")) 585 (ashift:HI (match_operand:HI 2 "register_operand" "r") 586 (const_int 8))))] 587 "" 588 "#" 589 "&& reload_completed" 590 [(parallel [(set (match_dup 0) 591 (ior:HI (zero_extend:HI (match_dup 1)) 592 (ashift:HI (match_dup 2) (const_int 8)))) 593 (clobber (reg:CC CC_REG))])]) 594 595(define_insn "*iorhi3_two_qi_clobber_flags" 596 [(set (match_operand:HI 0 "register_operand" "=r") 597 (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0")) 598 (ashift:HI (match_operand:HI 2 "register_operand" "r") 599 (const_int 8)))) 600 (clobber (reg:CC CC_REG))] 601 "" 602 "mov.b\\t%s2,%t0" 603 [(set_attr "length" "2")]) 604 605(define_insn_and_split "*iorhi3_two_qi_mem" 606 [(set (match_operand:HI 0 "register_operand" "=&r") 607 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")) 608 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0) 609 (const_int 8))))] 610 "" 611 "#" 612 "&& reload_completed" 613 [(parallel [(set (match_dup 0) 614 (ior:HI (zero_extend:HI (match_dup 1)) 615 (ashift:HI (subreg:HI (match_dup 2) 0) 616 (const_int 8)))) 617 (clobber (reg:CC CC_REG))])]) 618 619(define_insn "*iorhi3_two_qi_mem_clobber_flags" 620 [(set (match_operand:HI 0 "register_operand" "=&r") 621 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")) 622 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "m") 0) 623 (const_int 8)))) 624 (clobber (reg:CC CC_REG))] 625 "" 626 "mov.b\\t%X2,%t0\;mov.b\\t%X1,%s0" 627 [(set_attr "length" "16")]) 628 629(define_split 630 [(set (match_operand:HI 0 "register_operand" "") 631 (ior:HI (zero_extend:HI (match_operand:QI 1 "memory_operand" "")) 632 (ashift:HI (subreg:HI (match_operand:QI 2 "memory_operand" "") 0) 633 (const_int 8))))] 634 "reload_completed 635 && byte_accesses_mergeable_p (XEXP (operands[2], 0), XEXP (operands[1], 0))" 636 [(parallel [(set (match_dup 0) (match_dup 3)) 637 (clobber (reg:CC CC_REG))])] 638 { 639 operands[3] = gen_rtx_MEM (HImode, XEXP (operands[2], 0)); 640 }) 641 642;; ior:SI 643 644(define_insn_and_split "*iorsi3_two_hi" 645 [(set (match_operand:SI 0 "register_operand" "=r") 646 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0")) 647 (ashift:SI (match_operand:SI 2 "register_operand" "r") 648 (const_int 16))))] 649 "" 650 "#" 651 "&& reload_completed" 652 [(parallel [(set (match_dup 0) 653 (ior:SI (zero_extend:SI (match_dup 1)) 654 (ashift:SI (match_dup 2) (const_int 16)))) 655 (clobber (reg:CC CC_REG))])]) 656 657(define_insn "*iorsi3_two_hi_clobber_flags" 658 [(set (match_operand:SI 0 "register_operand" "=r") 659 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0")) 660 (ashift:SI (match_operand:SI 2 "register_operand" "r") 661 (const_int 16)))) 662 (clobber (reg:CC CC_REG))] 663 "" 664 "mov.w\\t%f2,%e0" 665 [(set_attr "length" "2")]) 666 667(define_insn_and_split "*iorsi3_two_qi_zext" 668 [(set (match_operand:SI 0 "register_operand" "=&r") 669 (ior:SI (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")) 670 (and:SI (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) 671 (const_int 8)) 672 (const_int 65280))))] 673 "" 674 "#" 675 "&& reload_completed" 676 [(parallel [(set (match_dup 3) 677 (ior:HI (zero_extend:HI (match_dup 1)) 678 (ashift:HI (subreg:HI (match_dup 2) 0) 679 (const_int 8)))) 680 (clobber (reg:CC CC_REG))]) 681 (parallel [(set (match_dup 0) (zero_extend:SI (match_dup 3))) 682 (clobber (reg:CC CC_REG))])] 683 { 684 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 685 }) 686 687(define_insn_and_split "*iorsi3_e2f" 688 [(set (match_operand:SI 0 "register_operand" "=r") 689 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") 690 (const_int -65536)) 691 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 692 (const_int 16))))] 693 "" 694 "#" 695 "&& reload_completed" 696 [(parallel [(set (match_dup 0) 697 (ior:SI (and:SI (match_dup 1) (const_int -65536)) 698 (lshiftrt:SI (match_dup 2) (const_int 16)))) 699 (clobber (reg:CC CC_REG))])]) 700 701(define_insn "*iorsi3_e2f_clobber_flags" 702 [(set (match_operand:SI 0 "register_operand" "=r") 703 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") 704 (const_int -65536)) 705 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") 706 (const_int 16)))) 707 (clobber (reg:CC CC_REG))] 708 "" 709 "mov.w\\t%e2,%f0" 710 [(set_attr "length" "2")]) 711 712(define_insn_and_split "*iorsi3_two_qi_sext" 713 [(set (match_operand:SI 0 "register_operand" "=r") 714 (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0")) 715 (ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r")) 716 (const_int 8))))] 717 "" 718 "#" 719 "&& reload_completed" 720 [(parallel [(set (match_dup 3) 721 (ior:HI (zero_extend:HI (match_dup 1)) 722 (ashift:HI (match_dup 4) (const_int 8)))) 723 (clobber (reg:CC CC_REG))]) 724 (parallel [(set (match_dup 0) (sign_extend:SI (match_dup 3))) 725 (clobber (reg:CC CC_REG))])] 726 { 727 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 728 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); 729 }) 730 731(define_insn_and_split "*iorsi3_w" 732 [(set (match_operand:SI 0 "register_operand" "=r,&r") 733 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0") 734 (const_int -256)) 735 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>"))))] 736 "" 737 "#" 738 "&& reload_completed" 739 [(parallel [(set (match_dup 0) 740 (ior:SI (and:SI (match_dup 1) (const_int -256)) 741 (zero_extend:SI (match_dup 2)))) 742 (clobber (reg:CC CC_REG))])]) 743 744(define_insn "*iorsi3_w_clobber_flags" 745 [(set (match_operand:SI 0 "register_operand" "=r,&r") 746 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0,0") 747 (const_int -256)) 748 (zero_extend:SI (match_operand:QI 2 "general_operand_src" "r,g>")))) 749 (clobber (reg:CC CC_REG))] 750 "" 751 "mov.b\\t%X2,%w0" 752 [(set_attr "length" "2,8")]) 753 754(define_insn_and_split "*iorsi3_ashift_31" 755 [(set (match_operand:SI 0 "register_operand" "=&r") 756 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 757 (const_int 31)) 758 (match_operand:SI 2 "register_operand" "0")))] 759 "" 760 "#" 761 "&& reload_completed" 762 [(parallel [(set (match_dup 0) 763 (ior:SI (ashift:SI (match_dup 1) (const_int 31)) 764 (match_dup 2))) 765 (clobber (reg:CC CC_REG))])]) 766 767(define_insn "*iorsi3_ashift_31_clobber_flags" 768 [(set (match_operand:SI 0 "register_operand" "=&r") 769 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 770 (const_int 31)) 771 (match_operand:SI 2 "register_operand" "0"))) 772 (clobber (reg:CC CC_REG))] 773 "" 774 "rotxl.l\\t%S0\;bor\\t#0,%w1\;rotxr.l\\t%S0" 775 [(set_attr "length" "6")]) 776 777(define_insn_and_split "*iorsi3_and_ashift" 778 [(set (match_operand:SI 0 "register_operand" "=r") 779 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 780 (match_operand:SI 2 "const_int_operand" "n")) 781 (match_operand:SI 3 "single_one_operand" "n")) 782 (match_operand:SI 4 "register_operand" "0")))] 783 "(INTVAL (operands[3]) & ~0xffff) == 0" 784 "#" 785 "&& reload_completed" 786 [(parallel [(set (match_dup 0) 787 (ior:SI (and:SI (ashift:SI (match_dup 1) (match_dup 2)) 788 (match_dup 3)) 789 (match_dup 4))) 790 (clobber (reg:CC CC_REG))])]) 791 792(define_insn "*iorsi3_and_ashift_clobber_flags" 793 [(set (match_operand:SI 0 "register_operand" "=r") 794 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 795 (match_operand:SI 2 "const_int_operand" "n")) 796 (match_operand:SI 3 "single_one_operand" "n")) 797 (match_operand:SI 4 "register_operand" "0"))) 798 (clobber (reg:CC CC_REG))] 799 "(INTVAL (operands[3]) & ~0xffff) == 0" 800{ 801 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) 802 - INTVAL (operands[2])); 803 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3]))); 804 operands[2] = srcpos; 805 operands[3] = dstpos; 806 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0"; 807} 808 [(set_attr "length" "6")]) 809 810(define_insn_and_split "*iorsi3_and_lshiftrt" 811 [(set (match_operand:SI 0 "register_operand" "=r") 812 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 813 (match_operand:SI 2 "const_int_operand" "n")) 814 (match_operand:SI 3 "single_one_operand" "n")) 815 (match_operand:SI 4 "register_operand" "0")))] 816 "((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0" 817 "#" 818 "&& reload_completed" 819 [(parallel [(set (match_dup 0) 820 (ior:SI (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) 821 (match_dup 3)) 822 (match_dup 4))) 823 (clobber (reg:CC CC_REG))])]) 824 825(define_insn "*iorsi3_and_lshiftrt_clobber_flags" 826 [(set (match_operand:SI 0 "register_operand" "=r") 827 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 828 (match_operand:SI 2 "const_int_operand" "n")) 829 (match_operand:SI 3 "single_one_operand" "n")) 830 (match_operand:SI 4 "register_operand" "0"))) 831 (clobber (reg:CC CC_REG))] 832 "((INTVAL (operands[3]) << INTVAL (operands[2])) & ~0xffff) == 0" 833{ 834 rtx srcpos = GEN_INT (exact_log2 (INTVAL (operands[3])) 835 + INTVAL (operands[2])); 836 rtx dstpos = GEN_INT (exact_log2 (INTVAL (operands[3]))); 837 operands[2] = srcpos; 838 operands[3] = dstpos; 839 return "bld\\t%Z2,%Y1\;bor\\t%Z3,%Y0\;bst\\t%Z3,%Y0"; 840} 841 [(set_attr "length" "6")]) 842 843(define_insn_and_split "*iorsi3_zero_extract" 844 [(set (match_operand:SI 0 "register_operand" "=r") 845 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 846 (const_int 1) 847 (match_operand:SI 2 "const_int_operand" "n")) 848 (match_operand:SI 3 "register_operand" "0")))] 849 "INTVAL (operands[2]) < 16" 850 "#" 851 "&& reload_completed" 852 [(parallel [(set (match_dup 0) 853 (ior:SI (zero_extract:SI (match_dup 1) 854 (const_int 1) 855 (match_dup 2)) 856 (match_dup 3))) 857 (clobber (reg:CC CC_REG))])]) 858 859(define_insn "*iorsi3_zero_extract_clobber_flags" 860 [(set (match_operand:SI 0 "register_operand" "=r") 861 (ior:SI (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 862 (const_int 1) 863 (match_operand:SI 2 "const_int_operand" "n")) 864 (match_operand:SI 3 "register_operand" "0"))) 865 (clobber (reg:CC CC_REG))] 866 "INTVAL (operands[2]) < 16" 867 "bld\\t%Z2,%Y1\;bor\\t#0,%w0\;bst\\t#0,%w0" 868 [(set_attr "length" "6")]) 869 870(define_insn_and_split "*iorsi3_and_lshiftrt_n_sb" 871 [(set (match_operand:SI 0 "register_operand" "=r") 872 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 873 (const_int 30)) 874 (const_int 2)) 875 (match_operand:SI 2 "register_operand" "0")))] 876 "" 877 "#" 878 "&& reload_completed" 879 [(parallel [(set (match_dup 0) 880 (ior:SI (and:SI (lshiftrt:SI (match_dup 1) (const_int 30)) 881 (const_int 2)) 882 (match_dup 2))) 883 (clobber (reg:CC CC_REG))])]) 884 885(define_insn "*iorsi3_and_lshiftrt_n_sb_clobber_flags" 886 [(set (match_operand:SI 0 "register_operand" "=r") 887 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 888 (const_int 30)) 889 (const_int 2)) 890 (match_operand:SI 2 "register_operand" "0"))) 891 (clobber (reg:CC CC_REG))] 892 "" 893 "rotl.l\\t%S1\;rotr.l\\t%S1\;bor\\t#1,%w0\;bst\\t#1,%w0" 894 [(set_attr "length" "8")]) 895 896(define_insn_and_split "*iorsi3_and_lshiftrt_9_sb" 897 [(set (match_operand:SI 0 "register_operand" "=r") 898 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 899 (const_int 9)) 900 (const_int 4194304)) 901 (match_operand:SI 2 "register_operand" "0"))) 902 (clobber (match_scratch:HI 3 "=&r"))] 903 "" 904 "#" 905 "&& reload_completed" 906 [(parallel [(set (match_dup 0) 907 (ior:SI (and:SI (lshiftrt:SI (match_dup 1) (const_int 9)) 908 (const_int 4194304)) 909 (match_dup 2))) 910 (clobber (match_dup 3)) 911 (clobber (reg:CC CC_REG))])]) 912 913 914(define_insn "*iorsi3_and_lshiftrt_9_sb_clobber_flags" 915 [(set (match_operand:SI 0 "register_operand" "=r") 916 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 917 (const_int 9)) 918 (const_int 4194304)) 919 (match_operand:SI 2 "register_operand" "0"))) 920 (clobber (match_scratch:HI 3 "=&r")) 921 (clobber (reg:CC CC_REG))] 922 "" 923{ 924 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) 925 return "shll.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0"; 926 else 927 return "rotl.l\\t%S1\;rotr.l\\t%S1\;xor.w\\t%T3,%T3\;bst\\t#6,%s3\;or.w\\t%T3,%e0"; 928} 929 [(set_attr "length" "10")]) 930 931;; Used to OR the exponent of a float. 932 933(define_insn "*iorsi3_shift" 934 [(set (match_operand:SI 0 "register_operand" "=r") 935 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 936 (const_int 23)) 937 (match_operand:SI 2 "register_operand" "0"))) 938 (clobber (match_scratch:SI 3 "=&r"))] 939 "" 940 "#") 941 942(define_split 943 [(set (match_operand:SI 0 "register_operand" "") 944 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "") 945 (const_int 23)) 946 (match_dup 0))) 947 (clobber (match_operand:SI 2 "register_operand" ""))] 948 "epilogue_completed 949 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 950 && REGNO (operands[0]) != REGNO (operands[1])" 951 [(parallel [(set (match_dup 3) 952 (ashift:HI (match_dup 3) 953 (const_int 7))) 954 (clobber (scratch:QI)) 955 (clobber (reg:CC CC_REG))]) 956 (parallel [(set (match_dup 0) 957 (ior:SI (ashift:SI (match_dup 1) (const_int 16)) 958 (match_dup 0))) 959 (clobber (reg:CC CC_REG))])] 960 { 961 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1])); 962 }) 963 964(define_split 965 [(set (match_operand:SI 0 "register_operand" "") 966 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "") 967 (const_int 23)) 968 (match_dup 0))) 969 (clobber (match_operand:SI 2 "register_operand" ""))] 970 "epilogue_completed 971 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 972 && REGNO (operands[0]) != REGNO (operands[1]))" 973 [(parallel [(set (match_dup 2) (match_dup 1)) 974 (clobber (reg:CC CC_REG))]) 975 (parallel [(set (match_dup 3) 976 (ashift:HI (match_dup 3) 977 (const_int 7))) 978 (clobber (scratch:QI)) 979 (clobber (reg:CC CC_REG))]) 980 (parallel [(set (match_dup 0) 981 (ior:SI (ashift:SI (match_dup 2) (const_int 16)) 982 (match_dup 0))) 983 (clobber (reg:CC CC_REG))])] 984 { 985 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2])); 986 }) 987 988(define_insn_and_split "*iorsi2_and_1_lshiftrt_1" 989 [(set (match_operand:SI 0 "register_operand" "=r") 990 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") 991 (const_int 1)) 992 (lshiftrt:SI (match_dup 1) 993 (const_int 1))))] 994 "" 995 "#" 996 "&& reload_completed" 997 [(parallel [(set (match_dup 0) 998 (ior:SI (and:SI (match_dup 1) (const_int 1)) 999 (lshiftrt:SI (match_dup 1) (const_int 1)))) 1000 (clobber (reg:CC CC_REG))])]) 1001 1002(define_insn "*iorsi2_and_1_lshiftrt_1_clobber_flags" 1003 [(set (match_operand:SI 0 "register_operand" "=r") 1004 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") 1005 (const_int 1)) 1006 (lshiftrt:SI (match_dup 1) 1007 (const_int 1)))) 1008 (clobber (reg:CC CC_REG))] 1009 "" 1010 "shlr.l\\t%S0\;bor\\t#0,%w0\;bst\\t#0,%w0" 1011 [(set_attr "length" "6")]) 1012 1013(define_insn_and_split "*iorsi3_ashift_16_ashift_24" 1014 [(set (match_operand:SI 0 "register_operand" "=r") 1015 (ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 1016 (const_int 16)) 1017 (ashift:SI (match_operand:SI 2 "register_operand" "r") 1018 (const_int 24))))] 1019 "" 1020 "#" 1021 "&& reload_completed" 1022 [(parallel [(set (match_dup 3) 1023 (ior:HI (ashift:HI (match_dup 4) (const_int 8)) 1024 (match_dup 3))) 1025 (clobber (reg:CC CC_REG))]) 1026 (parallel [(set (match_dup 0) 1027 (ashift:SI (match_dup 0) 1028 (const_int 16))) 1029 (clobber (scratch:QI)) 1030 (clobber (reg:CC CC_REG))])] 1031 { 1032 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 1033 operands[4] = gen_rtx_REG (HImode, REGNO (operands[2])); 1034 }) 1035 1036(define_insn_and_split "*iorsi3_ashift_16_ashift_24_mem" 1037 [(set (match_operand:SI 0 "register_operand" "=&r") 1038 (ior:SI (and:SI (ashift:SI (subreg:SI (match_operand:QI 1 "memory_operand" "m") 0) 1039 (const_int 16)) 1040 (const_int 16711680)) 1041 (ashift:SI (subreg:SI (match_operand:QI 2 "memory_operand" "m") 0) 1042 (const_int 24))))] 1043 "" 1044 "#" 1045 "&& reload_completed" 1046 [(parallel [(set (match_dup 3) 1047 (ior:HI (zero_extend:HI (match_dup 1)) 1048 (ashift:HI (subreg:HI (match_dup 2) 0) 1049 (const_int 8)))) 1050 (clobber (reg:CC CC_REG))]) 1051 (parallel [(set (match_dup 0) 1052 (ashift:SI (match_dup 0) 1053 (const_int 16))) 1054 (clobber (scratch:QI)) 1055 (clobber (reg:CC CC_REG))])] 1056 { 1057 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0])); 1058 }) 1059 1060;; Used to add the exponent of a float. 1061 1062(define_insn "*addsi3_shift" 1063 [(set (match_operand:SI 0 "register_operand" "=r") 1064 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") 1065 (const_int 8388608)) 1066 (match_operand:SI 2 "register_operand" "0"))) 1067 (clobber (match_scratch:SI 3 "=&r"))] 1068 "" 1069 "#") 1070 1071(define_split 1072 [(set (match_operand:SI 0 "register_operand" "") 1073 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "") 1074 (const_int 8388608)) 1075 (match_dup 0))) 1076 (clobber (match_operand:SI 2 "register_operand" ""))] 1077 "epilogue_completed 1078 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 1079 && REGNO (operands[0]) != REGNO (operands[1])" 1080 [(parallel [(set (match_dup 3) 1081 (ashift:HI (match_dup 3) 1082 (const_int 7))) 1083 (clobber (scratch:QI)) 1084 (clobber (reg:CC CC_REG))]) 1085 (parallel [(set (match_dup 0) 1086 (plus:SI (mult:SI (match_dup 1) (const_int 65536)) 1087 (match_dup 0))) 1088 (clobber (reg:CC CC_REG))])] 1089 { 1090 operands[3] = gen_rtx_REG (HImode, REGNO (operands[1])); 1091 }) 1092 1093(define_split 1094 [(set (match_operand:SI 0 "register_operand" "") 1095 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "") 1096 (const_int 8388608)) 1097 (match_dup 0))) 1098 (clobber (match_operand:SI 2 "register_operand" ""))] 1099 "epilogue_completed 1100 && !(find_regno_note (insn, REG_DEAD, REGNO (operands[1])) 1101 && REGNO (operands[0]) != REGNO (operands[1]))" 1102 [(parallel [(set (match_dup 2) (match_dup 1)) 1103 (clobber (reg:CC CC_REG))]) 1104 (parallel [(set (match_dup 3) 1105 (ashift:HI (match_dup 3) 1106 (const_int 7))) 1107 (clobber (scratch:QI)) 1108 (clobber (reg:CC CC_REG))]) 1109 (parallel [(set (match_dup 0) 1110 (plus:SI (mult:SI (match_dup 2) (const_int 65536)) 1111 (match_dup 0))) 1112 (clobber (reg:CC CC_REG))])] 1113 { 1114 operands[3] = gen_rtx_REG (HImode, REGNO (operands[2])); 1115 }) 1116 1117;; ashift:SI 1118 1119(define_insn_and_split "*ashiftsi_sextqi_7" 1120 [(set (match_operand:SI 0 "register_operand" "=r") 1121 (ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0")) 1122 (const_int 7)))] 1123 "" 1124 "#" 1125 "&& reload_completed" 1126 [(parallel [(set (match_dup 2) 1127 (ashift:HI (match_dup 2) 1128 (const_int 8))) 1129 (clobber (scratch:QI)) 1130 (clobber (reg:CC CC_REG))]) 1131 (parallel [(set (match_dup 0) (sign_extend:SI (match_dup 2))) 1132 (clobber (reg:CC CC_REG))]) 1133 (parallel [(set (match_dup 0) 1134 (ashiftrt:SI (match_dup 0) 1135 (const_int 1))) 1136 (clobber (scratch:QI)) 1137 (clobber (reg:CC CC_REG))])] 1138 { 1139 operands[2] = gen_rtx_REG (HImode, REGNO (operands[0])); 1140 }) 1141 1142;; Storing a part of HImode to QImode. 1143 1144(define_insn_and_split "" 1145 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1146 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") 1147 (const_int 8)) 1))] 1148 "" 1149 "#" 1150 "&& reload_completed" 1151 [(parallel [(set (match_dup 0) (subreg:QI (lshiftrt:HI (match_dup 1) 1152 (const_int 8)) 1)) 1153 (clobber (reg:CC CC_REG))])]) 1154 1155(define_insn "" 1156 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1157 (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") 1158 (const_int 8)) 1)) 1159 (clobber (reg:CC CC_REG))] 1160 "" 1161 "mov.b\\t%t1,%R0" 1162 [(set_attr "length" "8")]) 1163 1164;; Storing a part of SImode to QImode. 1165 1166(define_insn_and_split "" 1167 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1168 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 1169 (const_int 8)) 3))] 1170 "" 1171 "#" 1172 "&& reload_completed" 1173 [(parallel [(set (match_dup 0) 1174 (subreg:QI (lshiftrt:SI (match_dup 1) (const_int 8)) 3)) 1175 (clobber (reg:CC CC_REG))])]) 1176 1177(define_insn "" 1178 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1179 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 1180 (const_int 8)) 3)) 1181 (clobber (reg:CC CC_REG))] 1182 "" 1183 "mov.b\\t%x1,%R0" 1184 [(set_attr "length" "8")]) 1185 1186(define_insn_and_split "" 1187 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1188 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 1189 (const_int 16)) 3)) 1190 (clobber (match_scratch:SI 2 "=&r"))] 1191 "" 1192 "#" 1193 "&& reload_completed" 1194 [(parallel [(set (match_dup 0) 1195 (subreg:QI (lshiftrt:SI (match_dup 1) (const_int 16)) 3)) 1196 (clobber (match_dup 2)) 1197 (clobber (reg:CC CC_REG))])]) 1198 1199(define_insn "" 1200 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1201 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 1202 (const_int 16)) 3)) 1203 (clobber (match_scratch:SI 2 "=&r")) 1204 (clobber (reg:CC CC_REG))] 1205 "" 1206 "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0" 1207 [(set_attr "length" "10")]) 1208 1209(define_insn_and_split "" 1210 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1211 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 1212 (const_int 24)) 3)) 1213 (clobber (match_scratch:SI 2 "=&r"))] 1214 "" 1215 "#" 1216 "&& reload_completed" 1217 [(parallel [(set (match_dup 0) 1218 (subreg:QI (lshiftrt:SI (match_dup 1) (const_int 24)) 3)) 1219 (clobber (match_dup 2)) 1220 (clobber (reg:CC CC_REG))])]) 1221 1222(define_insn "" 1223 [(set (match_operand:QI 0 "general_operand_dst" "=rm<") 1224 (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") 1225 (const_int 24)) 3)) 1226 (clobber (match_scratch:SI 2 "=&r")) 1227 (clobber (reg:CC CC_REG))] 1228 "" 1229 "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0" 1230 [(set_attr "length" "10")]) 1231 1232;;(define_insn_and_split "" 1233;; [(set (pc) 1234;; (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0) 1235;; (const_int 1) 1236;; (const_int 7)) 1237;; (const_int 0)) 1238;; (label_ref (match_operand 1 "" "")) 1239;; (pc)))] 1240;; "" 1241;; "#" 1242;; "" 1243;; [(set (cc0) (compare (match_dup 0) 1244;; (const_int 0))) 1245;; (set (pc) 1246;; (if_then_else (ge (cc0) 1247;; (const_int 0)) 1248;; (label_ref (match_dup 1)) 1249;; (pc)))] 1250;; "") 1251;; 1252;; (define_insn_and_split "" 1253;; [(set (pc) 1254;; (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0) 1255;; (const_int 1) 1256;; (const_int 7)) 1257;; (const_int 0)) 1258;; (label_ref (match_operand 1 "" "")) 1259;; (pc)))] 1260;; "" 1261;; "#" 1262;; "" 1263;; [(set (cc0) (compare (match_dup 0) 1264;; (const_int 0))) 1265;; (set (pc) 1266;; (if_then_else (lt (cc0) 1267;; (const_int 0)) 1268;; (label_ref (match_dup 1)) 1269;; (pc)))] 1270;; "") 1271