1 /* IA-32 common hooks.
2 Copyright (C) 1988-2022 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS
82 #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET
86 #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16
87 #define OPTION_MASK_ISA_AVX512VNNI_SET \
88 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
89 #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI
90 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
91 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
92 #define OPTION_MASK_ISA_AVX512BITALG_SET \
93 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
94 #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16
95 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
96 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
97 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
98 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
99 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
100 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
101 #define OPTION_MASK_ISA_XSAVES_SET \
102 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
103 #define OPTION_MASK_ISA_XSAVEC_SET \
104 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
105 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
106 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT
107 #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE
108 #define OPTION_MASK_ISA2_AMX_INT8_SET OPTION_MASK_ISA2_AMX_INT8
109 #define OPTION_MASK_ISA2_AMX_BF16_SET OPTION_MASK_ISA2_AMX_BF16
110
111 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
112 as -msse4.2. */
113 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
114
115 #define OPTION_MASK_ISA_SSE4A_SET \
116 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
117 #define OPTION_MASK_ISA_FMA4_SET \
118 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
119 | OPTION_MASK_ISA_AVX_SET)
120 #define OPTION_MASK_ISA_XOP_SET \
121 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
122 #define OPTION_MASK_ISA_LWP_SET \
123 OPTION_MASK_ISA_LWP
124
125 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
126 #define OPTION_MASK_ISA_AES_SET \
127 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
128 #define OPTION_MASK_ISA_SHA_SET \
129 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
130 #define OPTION_MASK_ISA_PCLMUL_SET \
131 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
132
133 #define OPTION_MASK_ISA_ABM_SET \
134 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
135
136 #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG
137 #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD
138 #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX
139 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
140 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
141 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
142 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
143 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
144 #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16
145 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
146 #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE
147 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
148
149 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
150 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
151 #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE
152 #define OPTION_MASK_ISA_F16C_SET \
153 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
154 #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX
155 #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT
156 #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO
157 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
158 #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID
159 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
160 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
161 #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES
162 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
163 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
164 #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B
165 #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG
166 #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE
167 #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD
168 #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE
169 #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK
170 #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR
171 #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET
172 #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL
173 #define OPTION_MASK_ISA2_WIDEKL_SET \
174 (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET)
175
176 /* Define a set of ISAs which aren't available when a given ISA is
177 disabled. MMX and SSE ISAs are handled separately. */
178
179 #define OPTION_MASK_ISA_MMX_UNSET \
180 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
181 #define OPTION_MASK_ISA_3DNOW_UNSET \
182 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
183 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
184
185 #define OPTION_MASK_ISA_SSE_UNSET \
186 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
187 #define OPTION_MASK_ISA_SSE2_UNSET \
188 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
189 #define OPTION_MASK_ISA_SSE3_UNSET \
190 (OPTION_MASK_ISA_SSE3 \
191 | OPTION_MASK_ISA_SSSE3_UNSET \
192 | OPTION_MASK_ISA_SSE4A_UNSET )
193 #define OPTION_MASK_ISA_SSSE3_UNSET \
194 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
195 #define OPTION_MASK_ISA_SSE4_1_UNSET \
196 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
197 #define OPTION_MASK_ISA_SSE4_2_UNSET \
198 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
199 #define OPTION_MASK_ISA_AVX_UNSET \
200 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
201 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
202 | OPTION_MASK_ISA_AVX2_UNSET )
203 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
204 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
205 #define OPTION_MASK_ISA_XSAVE_UNSET \
206 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
207 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \
208 | OPTION_MASK_ISA_AVX_UNSET)
209 #define OPTION_MASK_ISA2_XSAVE_UNSET \
210 (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET)
211 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
212 #define OPTION_MASK_ISA_AVX2_UNSET \
213 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
214 #define OPTION_MASK_ISA2_AVX2_UNSET \
215 (OPTION_MASK_ISA2_AVXVNNI_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
216 #define OPTION_MASK_ISA_AVX512F_UNSET \
217 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
218 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
219 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
220 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
221 | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
222 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
223 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
224 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
225 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
226 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
227 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
228 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
229 #define OPTION_MASK_ISA_AVX512BW_UNSET \
230 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
231 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
232 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
233 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
234 #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS
235 #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW
236 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
237 #define OPTION_MASK_ISA_AVX512FP16_UNSET OPTION_MASK_ISA_AVX512BW_UNSET
238 #define OPTION_MASK_ISA2_AVX512FP16_UNSET OPTION_MASK_ISA2_AVX512FP16
239 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
240 #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI
241 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
242 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
243 #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16
244 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
245 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
246 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
247 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
248 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
249 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
250 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
251 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
252 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
253 #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX
254 #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT
255 #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO
256 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
257 #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID
258 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
259 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
260 #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES
261 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
262 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
263 #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B
264 #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG
265 #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE
266 #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD
267 #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE
268 #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT
269 #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK
270 #define OPTION_MASK_ISA2_AMX_TILE_UNSET OPTION_MASK_ISA2_AMX_TILE
271 #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8
272 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16
273 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR
274 #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET
275 #define OPTION_MASK_ISA2_KL_UNSET \
276 (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET)
277 #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL
278
279 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
280 as -mno-sse4.1. */
281 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
282
283 #define OPTION_MASK_ISA_SSE4A_UNSET \
284 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
285
286 #define OPTION_MASK_ISA_FMA4_UNSET \
287 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
288 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
289 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
290
291 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
292 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
293 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
294 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
295 #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG
296 #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD
297 #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX
298 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
299 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
300 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
301 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
302 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
303 #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16
304 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
305 #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE
306 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
307
308 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
309 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
310 #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE
311 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
312
313 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
314 (OPTION_MASK_ISA_MMX_UNSET \
315 | OPTION_MASK_ISA_SSE_UNSET)
316
317 #define OPTION_MASK_ISA2_AVX512F_UNSET \
318 (OPTION_MASK_ISA2_AVX512BF16_UNSET \
319 | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \
320 | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \
321 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
322 | OPTION_MASK_ISA2_AVX512FP16_UNSET)
323 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
324 OPTION_MASK_ISA2_SSE_UNSET
325 #define OPTION_MASK_ISA2_AVX_UNSET OPTION_MASK_ISA2_AVX2_UNSET
326 #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
327 #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
328 #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
329 #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
330 #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET
331 #define OPTION_MASK_ISA2_SSE2_UNSET \
332 (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET)
333 #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET
334
335 #define OPTION_MASK_ISA2_AVX512BW_UNSET \
336 (OPTION_MASK_ISA2_AVX512BF16_UNSET \
337 | OPTION_MASK_ISA2_AVX512FP16_UNSET)
338
339 /* Set 1 << value as value of -malign-FLAG option. */
340
341 static void
set_malign_value(const char ** flag,unsigned value)342 set_malign_value (const char **flag, unsigned value)
343 {
344 char *r = XNEWVEC (char, 6);
345 sprintf (r, "%d", 1 << value);
346 *flag = r;
347 }
348
349 /* Implement TARGET_HANDLE_OPTION. */
350
351 bool
ix86_handle_option(struct gcc_options * opts,struct gcc_options * opts_set ATTRIBUTE_UNUSED,const struct cl_decoded_option * decoded,location_t loc)352 ix86_handle_option (struct gcc_options *opts,
353 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
354 const struct cl_decoded_option *decoded,
355 location_t loc)
356 {
357 size_t code = decoded->opt_index;
358 int value = decoded->value;
359
360 switch (code)
361 {
362 case OPT_mgeneral_regs_only:
363 if (value)
364 {
365 HOST_WIDE_INT general_regs_only_flags = 0;
366 HOST_WIDE_INT general_regs_only_flags2 = 0;
367
368 /* NB: Enable the GPR only instructions which are enabled
369 implicitly by SSE ISAs unless they have been disabled
370 explicitly. */
371 if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
372 {
373 if (!TARGET_EXPLICIT_CRC32_P (opts))
374 general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
375 if (!TARGET_EXPLICIT_POPCNT_P (opts))
376 general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
377 }
378 if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
379 {
380 if (!TARGET_EXPLICIT_MWAIT_P (opts))
381 general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
382 }
383
384 /* Disable MMX, SSE and x87 instructions if only
385 general registers are allowed. */
386 opts->x_ix86_isa_flags
387 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
388 opts->x_ix86_isa_flags2
389 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
390 opts->x_ix86_isa_flags |= general_regs_only_flags;
391 opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
392 opts->x_ix86_isa_flags_explicit
393 |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
394 | general_regs_only_flags);
395 opts->x_ix86_isa_flags2_explicit
396 |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
397 | general_regs_only_flags2);
398
399 opts->x_target_flags &= ~MASK_80387;
400 }
401 else
402 gcc_unreachable ();
403 return true;
404
405 case OPT_mmmx:
406 if (value)
407 {
408 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
409 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
410 }
411 else
412 {
413 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
414 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
415 }
416 return true;
417
418 case OPT_m3dnow:
419 if (value)
420 {
421 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
422 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
423 }
424 else
425 {
426 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
427 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
428 }
429 return true;
430
431 case OPT_m3dnowa:
432 if (value)
433 {
434 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
435 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
436 }
437 else
438 {
439 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
440 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
441 }
442 return true;
443
444 case OPT_msse:
445 if (value)
446 {
447 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
448 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
449 }
450 else
451 {
452 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
453 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
454 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET;
455 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET;
456 }
457 return true;
458
459 case OPT_msse2:
460 if (value)
461 {
462 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
463 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
464 }
465 else
466 {
467 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
468 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
469 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET;
470 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET;
471 }
472 return true;
473
474 case OPT_msse3:
475 if (value)
476 {
477 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
478 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
479 }
480 else
481 {
482 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
483 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
484 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET;
485 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET;
486 }
487 return true;
488
489 case OPT_mssse3:
490 if (value)
491 {
492 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
493 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
494 }
495 else
496 {
497 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
498 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
499 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET;
500 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET;
501 }
502 return true;
503
504 case OPT_msse4_1:
505 if (value)
506 {
507 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
508 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
509 }
510 else
511 {
512 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
513 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
514 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET;
515 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET;
516 }
517 return true;
518
519 case OPT_msse4_2:
520 if (value)
521 {
522 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
523 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
524 }
525 else
526 {
527 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
528 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
529 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET;
530 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET;
531 }
532 return true;
533
534 case OPT_mavx:
535 if (value)
536 {
537 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
538 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
539 }
540 else
541 {
542 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
543 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
544 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET;
545 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET;
546 }
547 return true;
548
549 case OPT_mavx2:
550 if (value)
551 {
552 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
553 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
554 }
555 else
556 {
557 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
558 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
559 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET;
560 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET;
561 }
562 return true;
563
564 case OPT_mavx512f:
565 if (value)
566 {
567 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
568 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
569 }
570 else
571 {
572 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
573 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
574 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
575 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
576 }
577 return true;
578
579 case OPT_mavx512cd:
580 if (value)
581 {
582 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
583 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
584 }
585 else
586 {
587 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
588 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
589 }
590 return true;
591
592 case OPT_mavx512pf:
593 if (value)
594 {
595 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
596 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
597 }
598 else
599 {
600 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
601 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
602 }
603 return true;
604
605 case OPT_mavx512er:
606 if (value)
607 {
608 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
609 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
610 }
611 else
612 {
613 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
614 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
615 }
616 return true;
617
618 case OPT_mrdpid:
619 if (value)
620 {
621 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET;
622 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET;
623 }
624 else
625 {
626 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET;
627 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET;
628 }
629 return true;
630
631 case OPT_mgfni:
632 if (value)
633 {
634 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
635 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
636 }
637 else
638 {
639 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
640 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
641 }
642 return true;
643
644 case OPT_mshstk:
645 if (value)
646 {
647 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
648 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
649 }
650 else
651 {
652 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
653 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
654 }
655 return true;
656
657 case OPT_mvaes:
658 if (value)
659 {
660 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET;
661 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET;
662 }
663 else
664 {
665 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET;
666 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET;
667 }
668 return true;
669
670 case OPT_mvpclmulqdq:
671 if (value)
672 {
673 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
674 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
675 }
676 else
677 {
678 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
679 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
680 }
681 return true;
682
683 case OPT_mmovdiri:
684 if (value)
685 {
686 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
687 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
688 }
689 else
690 {
691 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
692 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
693 }
694 return true;
695
696 case OPT_mmovdir64b:
697 if (value)
698 {
699 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET;
700 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET;
701 }
702 else
703 {
704 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET;
705 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET;
706 }
707 return true;
708
709 case OPT_mcldemote:
710 if (value)
711 {
712 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET;
713 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET;
714 }
715 else
716 {
717 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET;
718 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET;
719 }
720 return true;
721
722 case OPT_mwaitpkg:
723 if (value)
724 {
725 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET;
726 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET;
727 }
728 else
729 {
730 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET;
731 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET;
732 }
733 return true;
734
735 case OPT_menqcmd:
736 if (value)
737 {
738 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET;
739 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET;
740 }
741 else
742 {
743 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET;
744 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET;
745 }
746 return true;
747
748 case OPT_mkl:
749 if (value)
750 {
751 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET;
752 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET;
753
754 /* The Keylocker instructions need XMM registers from SSE2. */
755 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
756 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
757 }
758 else
759 {
760 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET;
761 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET;
762 }
763 return true;
764
765 case OPT_mwidekl:
766 if (value)
767 {
768 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET;
769 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET;
770
771 /* The Widekl instructions need XMM registers from SSE2. */
772 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
773 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
774 }
775 else
776 {
777 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET;
778 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET;
779 }
780 return true;
781
782 case OPT_mserialize:
783 if (value)
784 {
785 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET;
786 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET;
787 }
788 else
789 {
790 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET;
791 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET;
792 }
793 return true;
794
795 case OPT_muintr:
796 if (value)
797 {
798 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET;
799 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET;
800 }
801 else
802 {
803 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET;
804 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET;
805 }
806 return true;
807
808 case OPT_mhreset:
809 if (value)
810 {
811 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET;
812 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET;
813 }
814 else
815 {
816 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET;
817 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET;
818 }
819 return true;
820
821 case OPT_mavx5124fmaps:
822 if (value)
823 {
824 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
825 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET;
826 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
827 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
828 }
829 else
830 {
831 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
832 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET;
833 }
834 return true;
835
836 case OPT_mavx5124vnniw:
837 if (value)
838 {
839 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
840 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET;
841 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
842 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
843 }
844 else
845 {
846 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
847 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET;
848 }
849 return true;
850
851 case OPT_mavx512vbmi2:
852 if (value)
853 {
854 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
855 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
856 }
857 else
858 {
859 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
860 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
861 }
862 return true;
863
864 case OPT_mavx512fp16:
865 if (value)
866 {
867 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET;
868 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET;
869 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET;
870 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET;
871 }
872 else
873 {
874 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
875 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
876 }
877 return true;
878
879 case OPT_mavx512vnni:
880 if (value)
881 {
882 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
883 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
884 }
885 else
886 {
887 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
888 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
889 }
890 return true;
891
892 case OPT_mavx512vpopcntdq:
893 if (value)
894 {
895 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
896 opts->x_ix86_isa_flags_explicit
897 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
898 }
899 else
900 {
901 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
902 opts->x_ix86_isa_flags_explicit
903 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
904 }
905 return true;
906
907 case OPT_mavx512bitalg:
908 if (value)
909 {
910 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
911 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
912 }
913 else
914 {
915 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
916 opts->x_ix86_isa_flags_explicit
917 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
918 }
919 return true;
920
921 case OPT_mavx512bf16:
922 if (value)
923 {
924 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET;
925 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET;
926 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
927 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
928 }
929 else
930 {
931 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
932 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
933 }
934 return true;
935
936 case OPT_mavxvnni:
937 if (value)
938 {
939 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET;
940 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET;
941 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
942 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
943 }
944 else
945 {
946 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET;
947 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET;
948 }
949 return true;
950
951 case OPT_msgx:
952 if (value)
953 {
954 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET;
955 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET;
956 }
957 else
958 {
959 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET;
960 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET;
961 }
962 return true;
963
964 case OPT_mpconfig:
965 if (value)
966 {
967 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET;
968 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET;
969 }
970 else
971 {
972 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET;
973 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET;
974 }
975 return true;
976
977 case OPT_mwbnoinvd:
978 if (value)
979 {
980 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET;
981 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET;
982 }
983 else
984 {
985 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET;
986 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET;
987 }
988 return true;
989
990 case OPT_mavx512dq:
991 if (value)
992 {
993 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
994 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
995 }
996 else
997 {
998 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
999 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
1000 }
1001 return true;
1002
1003 case OPT_mavx512bw:
1004 if (value)
1005 {
1006 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
1007 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
1008 }
1009 else
1010 {
1011 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
1012 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
1013 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
1014 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
1015 }
1016 return true;
1017
1018 case OPT_mavx512vl:
1019 if (value)
1020 {
1021 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
1022 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
1023 }
1024 else
1025 {
1026 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
1027 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
1028 }
1029 return true;
1030
1031 case OPT_mavx512ifma:
1032 if (value)
1033 {
1034 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
1035 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
1036 }
1037 else
1038 {
1039 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
1040 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
1041 }
1042 return true;
1043
1044 case OPT_mavx512vbmi:
1045 if (value)
1046 {
1047 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
1048 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
1049 }
1050 else
1051 {
1052 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
1053 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
1054 }
1055 return true;
1056
1057 case OPT_mavx512vp2intersect:
1058 if (value)
1059 {
1060 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1061 opts->x_ix86_isa_flags2_explicit |=
1062 OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET;
1063 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
1064 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
1065 }
1066 else
1067 {
1068 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1069 opts->x_ix86_isa_flags2_explicit |=
1070 OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET;
1071 }
1072 return true;
1073
1074 case OPT_mtsxldtrk:
1075 if (value)
1076 {
1077 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1078 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET;
1079 }
1080 else
1081 {
1082 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1083 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET;
1084 }
1085 return true;
1086
1087 case OPT_mamx_tile:
1088 if (value)
1089 {
1090 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET;
1091 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET;
1092 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1093 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1094 }
1095 else
1096 {
1097 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET;
1098 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET;
1099 }
1100 return true;
1101
1102 case OPT_mamx_int8:
1103 if (value)
1104 {
1105 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET;
1106 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET;
1107 }
1108 else
1109 {
1110 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET;
1111 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET;
1112 }
1113 return true;
1114
1115 case OPT_mamx_bf16:
1116 if (value)
1117 {
1118 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET;
1119 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET;
1120 }
1121 else
1122 {
1123 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET;
1124 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET;
1125 }
1126 return true;
1127
1128 case OPT_mfma:
1129 if (value)
1130 {
1131 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
1132 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
1133 }
1134 else
1135 {
1136 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
1137 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
1138 }
1139 return true;
1140
1141 case OPT_mrtm:
1142 if (value)
1143 {
1144 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
1145 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
1146 }
1147 else
1148 {
1149 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
1150 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
1151 }
1152 return true;
1153
1154 case OPT_msse4:
1155 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1156 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1157 return true;
1158
1159 case OPT_mno_sse4:
1160 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1161 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1162 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET;
1163 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET;
1164 return true;
1165
1166 case OPT_msse4a:
1167 if (value)
1168 {
1169 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1170 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1171 }
1172 else
1173 {
1174 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1175 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1176 }
1177 return true;
1178
1179 case OPT_mfma4:
1180 if (value)
1181 {
1182 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
1183 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
1184 }
1185 else
1186 {
1187 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
1188 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
1189 }
1190 return true;
1191
1192 case OPT_mxop:
1193 if (value)
1194 {
1195 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
1196 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
1197 }
1198 else
1199 {
1200 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
1201 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
1202 }
1203 return true;
1204
1205 case OPT_mlwp:
1206 if (value)
1207 {
1208 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
1209 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
1210 }
1211 else
1212 {
1213 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
1214 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
1215 }
1216 return true;
1217
1218 case OPT_mabm:
1219 if (value)
1220 {
1221 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
1222 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
1223 }
1224 else
1225 {
1226 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
1227 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
1228 }
1229 return true;
1230
1231 case OPT_mbmi:
1232 if (value)
1233 {
1234 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
1235 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
1236 }
1237 else
1238 {
1239 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
1240 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
1241 }
1242 return true;
1243
1244 case OPT_mbmi2:
1245 if (value)
1246 {
1247 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1248 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1249 }
1250 else
1251 {
1252 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1253 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1254 }
1255 return true;
1256
1257 case OPT_mlzcnt:
1258 if (value)
1259 {
1260 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1261 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1262 }
1263 else
1264 {
1265 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1266 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1267 }
1268 return true;
1269
1270 case OPT_mtbm:
1271 if (value)
1272 {
1273 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1274 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1275 }
1276 else
1277 {
1278 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1279 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1280 }
1281 return true;
1282
1283 case OPT_mpopcnt:
1284 if (value)
1285 {
1286 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1287 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1288 }
1289 else
1290 {
1291 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1292 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1293 }
1294 return true;
1295
1296 case OPT_msahf:
1297 if (value)
1298 {
1299 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1300 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1301 }
1302 else
1303 {
1304 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1305 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1306 }
1307 return true;
1308
1309 case OPT_mcx16:
1310 if (value)
1311 {
1312 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET;
1313 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET;
1314 }
1315 else
1316 {
1317 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET;
1318 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET;
1319 }
1320 return true;
1321
1322 case OPT_mmovbe:
1323 if (value)
1324 {
1325 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET;
1326 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET;
1327 }
1328 else
1329 {
1330 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET;
1331 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET;
1332 }
1333 return true;
1334
1335 case OPT_mcrc32:
1336 if (value)
1337 {
1338 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1339 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1340 }
1341 else
1342 {
1343 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1344 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1345 }
1346 return true;
1347
1348 case OPT_maes:
1349 if (value)
1350 {
1351 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1352 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1353 }
1354 else
1355 {
1356 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1357 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1358 }
1359 return true;
1360
1361 case OPT_msha:
1362 if (value)
1363 {
1364 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1365 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1366 }
1367 else
1368 {
1369 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1370 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1371 }
1372 return true;
1373
1374 case OPT_mpclmul:
1375 if (value)
1376 {
1377 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1378 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1379 }
1380 else
1381 {
1382 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1383 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1384 }
1385 return true;
1386
1387 case OPT_mfsgsbase:
1388 if (value)
1389 {
1390 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1391 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1392 }
1393 else
1394 {
1395 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1396 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1397 }
1398 return true;
1399
1400 case OPT_mrdrnd:
1401 if (value)
1402 {
1403 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1404 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1405 }
1406 else
1407 {
1408 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1409 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1410 }
1411 return true;
1412
1413 case OPT_mptwrite:
1414 if (value)
1415 {
1416 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET;
1417 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET;
1418 }
1419 else
1420 {
1421 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET;
1422 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET;
1423 }
1424 return true;
1425
1426 case OPT_mf16c:
1427 if (value)
1428 {
1429 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1430 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1431 }
1432 else
1433 {
1434 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1435 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1436 }
1437 return true;
1438
1439 case OPT_mfxsr:
1440 if (value)
1441 {
1442 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1443 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1444 }
1445 else
1446 {
1447 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1448 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1449 }
1450 return true;
1451
1452 case OPT_mxsave:
1453 if (value)
1454 {
1455 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1456 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1457 }
1458 else
1459 {
1460 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1461 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1462 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET;
1463 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET;
1464 }
1465 return true;
1466
1467 case OPT_mxsaveopt:
1468 if (value)
1469 {
1470 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1471 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1472 }
1473 else
1474 {
1475 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1476 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1477 }
1478 return true;
1479
1480 case OPT_mxsavec:
1481 if (value)
1482 {
1483 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1484 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1485 }
1486 else
1487 {
1488 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1489 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1490 }
1491 return true;
1492
1493 case OPT_mxsaves:
1494 if (value)
1495 {
1496 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1497 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1498 }
1499 else
1500 {
1501 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1502 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1503 }
1504 return true;
1505
1506 case OPT_mrdseed:
1507 if (value)
1508 {
1509 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1510 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1511 }
1512 else
1513 {
1514 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1515 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1516 }
1517 return true;
1518
1519 case OPT_mprfchw:
1520 if (value)
1521 {
1522 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1523 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1524 }
1525 else
1526 {
1527 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1528 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1529 }
1530 return true;
1531
1532 case OPT_madx:
1533 if (value)
1534 {
1535 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1536 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1537 }
1538 else
1539 {
1540 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1541 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1542 }
1543 return true;
1544
1545 case OPT_mprefetchwt1:
1546 if (value)
1547 {
1548 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1549 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1550 }
1551 else
1552 {
1553 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1554 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1555 }
1556 return true;
1557
1558 case OPT_mclflushopt:
1559 if (value)
1560 {
1561 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1562 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1563 }
1564 else
1565 {
1566 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1567 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1568 }
1569 return true;
1570
1571 case OPT_mclwb:
1572 if (value)
1573 {
1574 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1575 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1576 }
1577 else
1578 {
1579 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1580 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1581 }
1582 return true;
1583
1584 case OPT_mmwaitx:
1585 if (value)
1586 {
1587 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET;
1588 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET;
1589 }
1590 else
1591 {
1592 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET;
1593 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET;
1594 }
1595 return true;
1596
1597 case OPT_mmwait:
1598 if (value)
1599 {
1600 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET;
1601 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET;
1602 }
1603 else
1604 {
1605 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET;
1606 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET;
1607 }
1608 return true;
1609
1610 case OPT_mclzero:
1611 if (value)
1612 {
1613 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET;
1614 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET;
1615 }
1616 else
1617 {
1618 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET;
1619 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET;
1620 }
1621 return true;
1622
1623 case OPT_mpku:
1624 if (value)
1625 {
1626 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1627 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1628 }
1629 else
1630 {
1631 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1632 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1633 }
1634 return true;
1635
1636
1637 case OPT_malign_loops_:
1638 warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1639 "use %<-falign-loops%>");
1640 if (value > MAX_CODE_ALIGN)
1641 error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1642 value, MAX_CODE_ALIGN);
1643 else
1644 set_malign_value (&opts->x_str_align_loops, value);
1645 return true;
1646
1647 case OPT_malign_jumps_:
1648 warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
1649 "use %<-falign-jumps%>");
1650 if (value > MAX_CODE_ALIGN)
1651 error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
1652 value, MAX_CODE_ALIGN);
1653 else
1654 set_malign_value (&opts->x_str_align_jumps, value);
1655 return true;
1656
1657 case OPT_malign_functions_:
1658 warning_at (loc, 0,
1659 "%<-malign-functions%> is obsolete, "
1660 "use %<-falign-functions%>");
1661 if (value > MAX_CODE_ALIGN)
1662 error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
1663 value, MAX_CODE_ALIGN);
1664 else
1665 set_malign_value (&opts->x_str_align_functions, value);
1666 return true;
1667
1668 case OPT_mbranch_cost_:
1669 if (value > 5)
1670 {
1671 error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
1672 opts->x_ix86_branch_cost = 5;
1673 }
1674 return true;
1675
1676 default:
1677 return true;
1678 }
1679 }
1680
1681 static const struct default_options ix86_option_optimization_table[] =
1682 {
1683 /* Enable redundant extension instructions removal at -O2 and higher. */
1684 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1685 /* Enable function splitting at -O2 and higher. */
1686 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1687 /* The STC algorithm produces the smallest code at -Os, for x86. */
1688 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1689 REORDER_BLOCKS_ALGORITHM_STC },
1690 /* Turn off -fschedule-insns by default. It tends to make the
1691 problem with not enough registers even worse. */
1692 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1693
1694 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1695 SUBTARGET_OPTIMIZATION_OPTIONS,
1696 #endif
1697 { OPT_LEVELS_NONE, 0, NULL, 0 }
1698 };
1699
1700 /* Implement TARGET_OPTION_INIT_STRUCT. */
1701
1702 static void
ix86_option_init_struct(struct gcc_options * opts)1703 ix86_option_init_struct (struct gcc_options *opts)
1704 {
1705 if (TARGET_MACHO)
1706 /* The Darwin libraries never set errno, so we might as well
1707 avoid calling them when that's the only reason we would. */
1708 opts->x_flag_errno_math = 0;
1709
1710 opts->x_flag_pcc_struct_return = 2;
1711 opts->x_flag_asynchronous_unwind_tables = 2;
1712 }
1713
1714 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1715 field in the TCB, so they cannot be used together. */
1716
1717 static bool
ix86_supports_split_stack(bool report,struct gcc_options * opts ATTRIBUTE_UNUSED)1718 ix86_supports_split_stack (bool report,
1719 struct gcc_options *opts ATTRIBUTE_UNUSED)
1720 {
1721 #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P)
1722 if (!OPTION_GLIBC_P (opts))
1723 #endif
1724 {
1725 if (report)
1726 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1727 return false;
1728 }
1729
1730 bool ret = true;
1731
1732 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
1733 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1734 {
1735 if (report)
1736 error ("%<-fsplit-stack%> requires "
1737 "assembler support for CFI directives");
1738 ret = false;
1739 }
1740 #endif
1741
1742 return ret;
1743 }
1744
1745 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1746
1747 static enum unwind_info_type
i386_except_unwind_info(struct gcc_options * opts)1748 i386_except_unwind_info (struct gcc_options *opts)
1749 {
1750 /* Honor the --enable-sjlj-exceptions configure switch. */
1751 #ifdef CONFIG_SJLJ_EXCEPTIONS
1752 if (CONFIG_SJLJ_EXCEPTIONS)
1753 return UI_SJLJ;
1754 #endif
1755
1756 /* On windows 64, prefer SEH exceptions over anything else. */
1757 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1758 return UI_SEH;
1759
1760 if (DWARF2_UNWIND_INFO)
1761 return UI_DWARF2;
1762
1763 return UI_SJLJ;
1764 }
1765
1766 #undef TARGET_EXCEPT_UNWIND_INFO
1767 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1768
1769 #undef TARGET_DEFAULT_TARGET_FLAGS
1770 #define TARGET_DEFAULT_TARGET_FLAGS \
1771 (TARGET_DEFAULT \
1772 | TARGET_SUBTARGET_DEFAULT \
1773 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1774
1775 #undef TARGET_HANDLE_OPTION
1776 #define TARGET_HANDLE_OPTION ix86_handle_option
1777
1778 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1779 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1780 #undef TARGET_OPTION_INIT_STRUCT
1781 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1782
1783 #undef TARGET_SUPPORTS_SPLIT_STACK
1784 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1785
1786 /* This table must be in sync with enum processor_type in i386.h. */
1787 const char *const processor_names[] =
1788 {
1789 "generic",
1790 "i386",
1791 "i486",
1792 "pentium",
1793 "lakemont",
1794 "pentiumpro",
1795 "pentium4",
1796 "nocona",
1797 "core2",
1798 "nehalem",
1799 "sandybridge",
1800 "haswell",
1801 "bonnell",
1802 "silvermont",
1803 "goldmont",
1804 "goldmont-plus",
1805 "tremont",
1806 "knl",
1807 "knm",
1808 "skylake",
1809 "skylake-avx512",
1810 "cannonlake",
1811 "icelake-client",
1812 "icelake-server",
1813 "cascadelake",
1814 "tigerlake",
1815 "cooperlake",
1816 "sapphirerapids",
1817 "alderlake",
1818 "rocketlake",
1819 "intel",
1820 "geode",
1821 "k6",
1822 "athlon",
1823 "k8",
1824 "amdfam10",
1825 "bdver1",
1826 "bdver2",
1827 "bdver3",
1828 "bdver4",
1829 "btver1",
1830 "btver2",
1831 "znver1",
1832 "znver2",
1833 "znver3",
1834 "znver4"
1835 };
1836
1837 /* Guarantee that the array is aligned with enum processor_type. */
1838 STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
1839
1840 const pta processor_alias_table[] =
1841 {
1842 {"i386", PROCESSOR_I386, CPU_NONE, 0, 0, P_NONE},
1843 {"i486", PROCESSOR_I486, CPU_NONE, 0, 0, P_NONE},
1844 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
1845 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0, P_NONE},
1846 {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387,
1847 0, P_NONE},
1848 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0, P_NONE},
1849 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0, P_NONE},
1850 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
1851 0, P_NONE},
1852 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0, P_NONE},
1853 {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW,
1854 0, P_NONE},
1855 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1856 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1857 {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1858 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1859 {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1860 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1861 {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1862 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1863 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
1864 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0, P_NONE},
1865 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR,
1866 0, P_NONE},
1867 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1868 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1869 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1870 PTA_MMX | PTA_SSE | PTA_FXSR, 0, P_NONE},
1871 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1872 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
1873 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
1874 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
1875 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
1876 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0, P_NONE},
1877 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
1878 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0, P_NONE},
1879 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
1880 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1881 | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
1882 {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2,
1883 M_CPU_TYPE (INTEL_CORE2), P_PROC_SSSE3},
1884 {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
1885 M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), P_PROC_DYNAMIC},
1886 {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM,
1887 M_CPU_TYPE (INTEL_COREI7), P_PROC_DYNAMIC},
1888 {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE,
1889 M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), P_PROC_DYNAMIC},
1890 {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1891 PTA_SANDYBRIDGE,
1892 M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), P_PROC_DYNAMIC},
1893 {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1894 PTA_SANDYBRIDGE, 0, P_PROC_DYNAMIC},
1895 {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1896 PTA_IVYBRIDGE,
1897 M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), P_PROC_DYNAMIC},
1898 {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1899 PTA_IVYBRIDGE, 0, P_PROC_DYNAMIC},
1900 {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
1901 M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), P_PROC_DYNAMIC},
1902 {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL,
1903 0, P_PROC_DYNAMIC},
1904 {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL,
1905 M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), P_PROC_DYNAMIC},
1906 {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE,
1907 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), P_PROC_AVX2},
1908 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
1909 PTA_SKYLAKE_AVX512,
1910 M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), P_PROC_AVX512F},
1911 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE,
1912 M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), P_PROC_AVX512F},
1913 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
1914 PTA_ICELAKE_CLIENT,
1915 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), P_PROC_AVX512F},
1916 {"rocketlake", PROCESSOR_ROCKETLAKE, CPU_HASWELL,
1917 PTA_ROCKETLAKE,
1918 M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), P_PROC_AVX512F},
1919 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
1920 PTA_ICELAKE_SERVER,
1921 M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), P_PROC_AVX512F},
1922 {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
1923 PTA_CASCADELAKE,
1924 M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), P_PROC_AVX512F},
1925 {"tigerlake", PROCESSOR_TIGERLAKE, CPU_HASWELL, PTA_TIGERLAKE,
1926 M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), P_PROC_AVX512F},
1927 {"cooperlake", PROCESSOR_COOPERLAKE, CPU_HASWELL, PTA_COOPERLAKE,
1928 M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), P_PROC_AVX512F},
1929 {"sapphirerapids", PROCESSOR_SAPPHIRERAPIDS, CPU_HASWELL, PTA_SAPPHIRERAPIDS,
1930 M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), P_PROC_AVX512F},
1931 {"alderlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
1932 M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
1933 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
1934 M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
1935 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
1936 M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
1937 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
1938 M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
1939 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT,
1940 M_CPU_TYPE (INTEL_SILVERMONT), P_PROC_SSE4_2},
1941 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT,
1942 M_CPU_TYPE (INTEL_GOLDMONT), P_PROC_SSE4_2},
1943 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS,
1944 M_CPU_TYPE (INTEL_GOLDMONT_PLUS), P_PROC_SSE4_2},
1945 {"tremont", PROCESSOR_TREMONT, CPU_HASWELL, PTA_TREMONT,
1946 M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2},
1947 {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL,
1948 M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F},
1949 {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM,
1950 M_CPU_TYPE (INTEL_KNM), P_PROC_AVX512F},
1951 {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM,
1952 M_VENDOR (VENDOR_INTEL), P_NONE},
1953 {"geode", PROCESSOR_GEODE, CPU_GEODE,
1954 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
1955 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0, P_NONE},
1956 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
1957 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0, P_NONE},
1958 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
1959 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
1960 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
1961 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0, P_NONE},
1962 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
1963 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
1964 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
1965 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
1966 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
1967 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0, P_NONE},
1968 {"x86-64", PROCESSOR_K8, CPU_K8, PTA_X86_64_BASELINE, 0, P_NONE},
1969 {"x86-64-v2", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V2 | PTA_NO_TUNE,
1970 0, P_NONE},
1971 {"x86-64-v3", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V3 | PTA_NO_TUNE,
1972 0, P_NONE},
1973 {"x86-64-v4", PROCESSOR_K8, CPU_GENERIC, PTA_X86_64_V4 | PTA_NO_TUNE,
1974 0, P_NONE},
1975 {"eden-x2", PROCESSOR_K8, CPU_K8,
1976 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR,
1977 0, P_NONE},
1978 {"nano", PROCESSOR_K8, CPU_K8,
1979 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1980 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
1981 {"nano-1000", PROCESSOR_K8, CPU_K8,
1982 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1983 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
1984 {"nano-2000", PROCESSOR_K8, CPU_K8,
1985 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1986 | PTA_SSSE3 | PTA_FXSR, 0, P_NONE},
1987 {"nano-3000", PROCESSOR_K8, CPU_K8,
1988 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1989 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1990 {"nano-x2", PROCESSOR_K8, CPU_K8,
1991 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1992 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1993 {"eden-x4", PROCESSOR_K8, CPU_K8,
1994 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1995 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1996 {"nano-x4", PROCESSOR_K8, CPU_K8,
1997 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1998 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0, P_NONE},
1999 {"k8", PROCESSOR_K8, CPU_K8,
2000 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2001 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2002 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2003 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2004 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2005 {"opteron", PROCESSOR_K8, CPU_K8,
2006 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2007 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2008 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2009 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2010 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2011 {"athlon64", PROCESSOR_K8, CPU_K8,
2012 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2013 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2014 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2015 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2016 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2017 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2018 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2019 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0, P_NONE},
2020 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2021 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2022 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2023 0, P_PROC_DYNAMIC},
2024 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2025 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
2026 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
2027 M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), P_PROC_DYNAMIC},
2028 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
2029 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2030 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2031 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2032 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
2033 M_CPU_TYPE (AMDFAM15H_BDVER1), P_PROC_XOP},
2034 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
2035 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2036 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2037 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2038 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
2039 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE,
2040 M_CPU_TYPE (AMDFAM15H_BDVER2), P_PROC_FMA},
2041 {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
2042 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2043 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2044 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
2045 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
2046 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
2047 | PTA_XSAVEOPT | PTA_FSGSBASE,
2048 M_CPU_SUBTYPE (AMDFAM15H_BDVER3), P_PROC_FMA},
2049 {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
2050 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2051 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
2052 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
2053 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
2054 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
2055 | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
2056 | PTA_MOVBE | PTA_MWAITX,
2057 M_CPU_SUBTYPE (AMDFAM15H_BDVER4), P_PROC_AVX2},
2058 {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
2059 PTA_ZNVER1,
2060 M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), P_PROC_AVX2},
2061 {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER2,
2062 PTA_ZNVER2,
2063 M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), P_PROC_AVX2},
2064 {"znver3", PROCESSOR_ZNVER3, CPU_ZNVER3,
2065 PTA_ZNVER3,
2066 M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), P_PROC_AVX2},
2067 {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
2068 PTA_ZNVER4,
2069 M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
2070 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
2071 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2072 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
2073 | PTA_FXSR | PTA_XSAVE,
2074 M_CPU_SUBTYPE (AMDFAM15H_BDVER1), P_PROC_SSE4_A},
2075 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
2076 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2077 | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1
2078 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
2079 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
2080 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT,
2081 M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
2082
2083 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
2084 PTA_64BIT
2085 | PTA_HLE /* flags are only used for -march switch. */,
2086 0, P_NONE},
2087
2088 {"amd", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2089 M_VENDOR (VENDOR_AMD), P_NONE},
2090 {"amdfam10h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2091 M_CPU_TYPE (AMDFAM10H), P_NONE},
2092 {"amdfam15h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2093 M_CPU_TYPE (AMDFAM15H), P_NONE},
2094 {"amdfam17h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2095 M_CPU_TYPE (AMDFAM17H), P_NONE},
2096 {"amdfam19h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2097 M_CPU_TYPE (AMDFAM19H), P_NONE},
2098 {"shanghai", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2099 M_CPU_TYPE (AMDFAM10H_SHANGHAI), P_NONE},
2100 {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
2101 M_CPU_TYPE (AMDFAM10H_ISTANBUL), P_NONE},
2102 };
2103
2104 /* NB: processor_alias_table stops at the "generic" entry. */
2105 unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;
2106 unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
2107
2108 /* Provide valid option values for -march and -mtune options. */
2109
2110 vec<const char *>
ix86_get_valid_option_values(int option_code,const char * prefix ATTRIBUTE_UNUSED)2111 ix86_get_valid_option_values (int option_code,
2112 const char *prefix ATTRIBUTE_UNUSED)
2113 {
2114 vec<const char *> v;
2115 v.create (0);
2116 opt_code opt = (opt_code) option_code;
2117
2118 switch (opt)
2119 {
2120 case OPT_march_:
2121 for (unsigned i = 0; i < pta_size; i++)
2122 {
2123 const char *name = processor_alias_table[i].name;
2124 gcc_checking_assert (name != NULL);
2125 v.safe_push (name);
2126 }
2127 #ifdef HAVE_LOCAL_CPU_DETECT
2128 /* Add also "native" as possible value. */
2129 v.safe_push ("native");
2130 #endif
2131
2132 break;
2133 case OPT_mtune_:
2134 for (unsigned i = 0; i < PROCESSOR_max; i++)
2135 {
2136 const char *name = processor_names[i];
2137 gcc_checking_assert (name != NULL);
2138 v.safe_push (name);
2139 }
2140 break;
2141 default:
2142 break;
2143 }
2144
2145 return v;
2146 }
2147
2148 #undef TARGET_GET_VALID_OPTION_VALUES
2149 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
2150
2151 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
2152