xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/gfx_7_2_enum.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1) 
1 /*	$NetBSD: gfx_7_2_enum.h,v 1.3 2021/12/18 23:45:14 riastradh Exp $	*/
2 
3 /*
4  * GFX_7_2 Register documentation
5  *
6  * Copyright (C) 2014  Advanced Micro Devices, Inc.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included
16  * in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
22  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 #ifndef GFX_7_2_ENUM_H
27 #define GFX_7_2_ENUM_H
28 
29 typedef enum SurfaceNumber {
30 	NUMBER_UNORM                                     = 0x0,
31 	NUMBER_SNORM                                     = 0x1,
32 	NUMBER_USCALED                                   = 0x2,
33 	NUMBER_SSCALED                                   = 0x3,
34 	NUMBER_UINT                                      = 0x4,
35 	NUMBER_SINT                                      = 0x5,
36 	NUMBER_SRGB                                      = 0x6,
37 	NUMBER_FLOAT                                     = 0x7,
38 } SurfaceNumber;
39 typedef enum SurfaceSwap {
40 	SWAP_STD                                         = 0x0,
41 	SWAP_ALT                                         = 0x1,
42 	SWAP_STD_REV                                     = 0x2,
43 	SWAP_ALT_REV                                     = 0x3,
44 } SurfaceSwap;
45 typedef enum CBMode {
46 	CB_DISABLE                                       = 0x0,
47 	CB_NORMAL                                        = 0x1,
48 	CB_ELIMINATE_FAST_CLEAR                          = 0x2,
49 	CB_RESOLVE                                       = 0x3,
50 	CB_DECOMPRESS                                    = 0x4,
51 	CB_FMASK_DECOMPRESS                              = 0x5,
52 } CBMode;
53 typedef enum RoundMode {
54 	ROUND_BY_HALF                                    = 0x0,
55 	ROUND_TRUNCATE                                   = 0x1,
56 } RoundMode;
57 typedef enum SourceFormat {
58 	EXPORT_4C_32BPC                                  = 0x0,
59 	EXPORT_4C_16BPC                                  = 0x1,
60 	EXPORT_2C_32BPC_GR                               = 0x2,
61 	EXPORT_2C_32BPC_AR                               = 0x3,
62 } SourceFormat;
63 typedef enum BlendOp {
64 	BLEND_ZERO                                       = 0x0,
65 	BLEND_ONE                                        = 0x1,
66 	BLEND_SRC_COLOR                                  = 0x2,
67 	BLEND_ONE_MINUS_SRC_COLOR                        = 0x3,
68 	BLEND_SRC_ALPHA                                  = 0x4,
69 	BLEND_ONE_MINUS_SRC_ALPHA                        = 0x5,
70 	BLEND_DST_ALPHA                                  = 0x6,
71 	BLEND_ONE_MINUS_DST_ALPHA                        = 0x7,
72 	BLEND_DST_COLOR                                  = 0x8,
73 	BLEND_ONE_MINUS_DST_COLOR                        = 0x9,
74 	BLEND_SRC_ALPHA_SATURATE                         = 0xa,
75 	BLEND_BOTH_SRC_ALPHA                             = 0xb,
76 	BLEND_BOTH_INV_SRC_ALPHA                         = 0xc,
77 	BLEND_CONSTANT_COLOR                             = 0xd,
78 	BLEND_ONE_MINUS_CONSTANT_COLOR                   = 0xe,
79 	BLEND_SRC1_COLOR                                 = 0xf,
80 	BLEND_INV_SRC1_COLOR                             = 0x10,
81 	BLEND_SRC1_ALPHA                                 = 0x11,
82 	BLEND_INV_SRC1_ALPHA                             = 0x12,
83 	BLEND_CONSTANT_ALPHA                             = 0x13,
84 	BLEND_ONE_MINUS_CONSTANT_ALPHA                   = 0x14,
85 } BlendOp;
86 typedef enum CombFunc {
87 	COMB_DST_PLUS_SRC                                = 0x0,
88 	COMB_SRC_MINUS_DST                               = 0x1,
89 	COMB_MIN_DST_SRC                                 = 0x2,
90 	COMB_MAX_DST_SRC                                 = 0x3,
91 	COMB_DST_MINUS_SRC                               = 0x4,
92 } CombFunc;
93 typedef enum BlendOpt {
94 	FORCE_OPT_AUTO                                   = 0x0,
95 	FORCE_OPT_DISABLE                                = 0x1,
96 	FORCE_OPT_ENABLE_IF_SRC_A_0                      = 0x2,
97 	FORCE_OPT_ENABLE_IF_SRC_RGB_0                    = 0x3,
98 	FORCE_OPT_ENABLE_IF_SRC_ARGB_0                   = 0x4,
99 	FORCE_OPT_ENABLE_IF_SRC_A_1                      = 0x5,
100 	FORCE_OPT_ENABLE_IF_SRC_RGB_1                    = 0x6,
101 	FORCE_OPT_ENABLE_IF_SRC_ARGB_1                   = 0x7,
102 } BlendOpt;
103 typedef enum CmaskCode {
104 	CMASK_CLR00_F0                                   = 0x0,
105 	CMASK_CLR00_F1                                   = 0x1,
106 	CMASK_CLR00_F2                                   = 0x2,
107 	CMASK_CLR00_FX                                   = 0x3,
108 	CMASK_CLR01_F0                                   = 0x4,
109 	CMASK_CLR01_F1                                   = 0x5,
110 	CMASK_CLR01_F2                                   = 0x6,
111 	CMASK_CLR01_FX                                   = 0x7,
112 	CMASK_CLR10_F0                                   = 0x8,
113 	CMASK_CLR10_F1                                   = 0x9,
114 	CMASK_CLR10_F2                                   = 0xa,
115 	CMASK_CLR10_FX                                   = 0xb,
116 	CMASK_CLR11_F0                                   = 0xc,
117 	CMASK_CLR11_F1                                   = 0xd,
118 	CMASK_CLR11_F2                                   = 0xe,
119 	CMASK_CLR11_FX                                   = 0xf,
120 } CmaskCode;
121 typedef enum CBPerfSel {
122 	CB_PERF_SEL_NONE                                 = 0x0,
123 	CB_PERF_SEL_BUSY                                 = 0x1,
124 	CB_PERF_SEL_CORE_SCLK_VLD                        = 0x2,
125 	CB_PERF_SEL_REG_SCLK0_VLD                        = 0x3,
126 	CB_PERF_SEL_REG_SCLK1_VLD                        = 0x4,
127 	CB_PERF_SEL_DRAWN_QUAD                           = 0x5,
128 	CB_PERF_SEL_DRAWN_PIXEL                          = 0x6,
129 	CB_PERF_SEL_DRAWN_QUAD_FRAGMENT                  = 0x7,
130 	CB_PERF_SEL_DRAWN_TILE                           = 0x8,
131 	CB_PERF_SEL_DB_CB_TILE_VALID_READY               = 0x9,
132 	CB_PERF_SEL_DB_CB_TILE_VALID_READYB              = 0xa,
133 	CB_PERF_SEL_DB_CB_TILE_VALIDB_READY              = 0xb,
134 	CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB             = 0xc,
135 	CB_PERF_SEL_CM_FC_TILE_VALID_READY               = 0xd,
136 	CB_PERF_SEL_CM_FC_TILE_VALID_READYB              = 0xe,
137 	CB_PERF_SEL_CM_FC_TILE_VALIDB_READY              = 0xf,
138 	CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB             = 0x10,
139 	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY          = 0x11,
140 	CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB         = 0x12,
141 	CB_PERF_SEL_DB_CB_LQUAD_VALID_READY              = 0x13,
142 	CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB             = 0x14,
143 	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY             = 0x15,
144 	CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB            = 0x16,
145 	CB_PERF_SEL_LQUAD_NO_TILE                        = 0x17,
146 	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R          = 0x18,
147 	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR         = 0x19,
148 	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR         = 0x1a,
149 	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR       = 0x1b,
150 	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR     = 0x1c,
151 	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d,
152 	CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e,
153 	CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT    = 0x1f,
154 	CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID         = 0x20,
155 	CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21,
156 	CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK      = 0x22,
157 	CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL         = 0x23,
158 	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY            = 0x24,
159 	CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB           = 0x25,
160 	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY           = 0x26,
161 	CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB          = 0x27,
162 	CB_PERF_SEL_FOP_IN_VALID_READY                   = 0x28,
163 	CB_PERF_SEL_FOP_IN_VALID_READYB                  = 0x29,
164 	CB_PERF_SEL_FOP_IN_VALIDB_READY                  = 0x2a,
165 	CB_PERF_SEL_FOP_IN_VALIDB_READYB                 = 0x2b,
166 	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY           = 0x2c,
167 	CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB          = 0x2d,
168 	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY          = 0x2e,
169 	CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB         = 0x2f,
170 	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY            = 0x30,
171 	CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB           = 0x31,
172 	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY           = 0x32,
173 	CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB          = 0x33,
174 	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY            = 0x34,
175 	CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB           = 0x35,
176 	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY           = 0x36,
177 	CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB          = 0x37,
178 	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY        = 0x38,
179 	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB       = 0x39,
180 	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY       = 0x3a,
181 	CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB      = 0x3b,
182 	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY         = 0x3c,
183 	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB        = 0x3d,
184 	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY        = 0x3e,
185 	CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB       = 0x3f,
186 	CB_PERF_SEL_CC_BC_CS_FRAG_VALID                  = 0x40,
187 	CB_PERF_SEL_CM_CACHE_HIT                         = 0x41,
188 	CB_PERF_SEL_CM_CACHE_TAG_MISS                    = 0x42,
189 	CB_PERF_SEL_CM_CACHE_SECTOR_MISS                 = 0x43,
190 	CB_PERF_SEL_CM_CACHE_REEVICTION_STALL            = 0x44,
191 	CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45,
192 	CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46,
193 	CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47,
194 	CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL           = 0x48,
195 	CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL          = 0x49,
196 	CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL            = 0x4a,
197 	CB_PERF_SEL_CM_CACHE_STALL                       = 0x4b,
198 	CB_PERF_SEL_CM_CACHE_FLUSH                       = 0x4c,
199 	CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED                = 0x4d,
200 	CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED             = 0x4e,
201 	CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED       = 0x4f,
202 	CB_PERF_SEL_FC_CACHE_HIT                         = 0x50,
203 	CB_PERF_SEL_FC_CACHE_TAG_MISS                    = 0x51,
204 	CB_PERF_SEL_FC_CACHE_SECTOR_MISS                 = 0x52,
205 	CB_PERF_SEL_FC_CACHE_REEVICTION_STALL            = 0x53,
206 	CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54,
207 	CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55,
208 	CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56,
209 	CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL           = 0x57,
210 	CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL          = 0x58,
211 	CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL            = 0x59,
212 	CB_PERF_SEL_FC_CACHE_STALL                       = 0x5a,
213 	CB_PERF_SEL_FC_CACHE_FLUSH                       = 0x5b,
214 	CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED                = 0x5c,
215 	CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED             = 0x5d,
216 	CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x5e,
217 	CB_PERF_SEL_CC_CACHE_HIT                         = 0x5f,
218 	CB_PERF_SEL_CC_CACHE_TAG_MISS                    = 0x60,
219 	CB_PERF_SEL_CC_CACHE_SECTOR_MISS                 = 0x61,
220 	CB_PERF_SEL_CC_CACHE_REEVICTION_STALL            = 0x62,
221 	CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63,
222 	CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64,
223 	CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65,
224 	CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL           = 0x66,
225 	CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL          = 0x67,
226 	CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL            = 0x68,
227 	CB_PERF_SEL_CC_CACHE_STALL                       = 0x69,
228 	CB_PERF_SEL_CC_CACHE_FLUSH                       = 0x6a,
229 	CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED                = 0x6b,
230 	CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED             = 0x6c,
231 	CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED       = 0x6d,
232 	CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION        = 0x6e,
233 	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY             = 0x6f,
234 	CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB            = 0x70,
235 	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY            = 0x71,
236 	CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB           = 0x72,
237 	CB_PERF_SEL_CM_MC_WRITE_REQUEST                  = 0x73,
238 	CB_PERF_SEL_FC_MC_WRITE_REQUEST                  = 0x74,
239 	CB_PERF_SEL_CC_MC_WRITE_REQUEST                  = 0x75,
240 	CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x76,
241 	CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x77,
242 	CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT       = 0x78,
243 	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY             = 0x79,
244 	CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB            = 0x7a,
245 	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY            = 0x7b,
246 	CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB           = 0x7c,
247 	CB_PERF_SEL_CM_MC_READ_REQUEST                   = 0x7d,
248 	CB_PERF_SEL_FC_MC_READ_REQUEST                   = 0x7e,
249 	CB_PERF_SEL_CC_MC_READ_REQUEST                   = 0x7f,
250 	CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT        = 0x80,
251 	CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT        = 0x81,
252 	CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT        = 0x82,
253 	CB_PERF_SEL_CM_TQ_FULL                           = 0x83,
254 	CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL      = 0x84,
255 	CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL              = 0x85,
256 	CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL              = 0x86,
257 	CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL   = 0x87,
258 	CB_PERF_SEL_FOP_FMASK_RAW_STALL                  = 0x88,
259 	CB_PERF_SEL_FOP_FMASK_BYPASS_STALL               = 0x89,
260 	CB_PERF_SEL_CC_SF_FULL                           = 0x8a,
261 	CB_PERF_SEL_CC_RB_FULL                           = 0x8b,
262 	CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL     = 0x8c,
263 	CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL      = 0x8d,
264 	CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL             = 0x8e,
265 	CB_PERF_SEL_EVENT                                = 0x8f,
266 	CB_PERF_SEL_EVENT_CACHE_FLUSH_TS                 = 0x90,
267 	CB_PERF_SEL_EVENT_CONTEXT_DONE                   = 0x91,
268 	CB_PERF_SEL_EVENT_CACHE_FLUSH                    = 0x92,
269 	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT   = 0x93,
270 	CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT      = 0x94,
271 	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS       = 0x95,
272 	CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META          = 0x96,
273 	CB_PERF_SEL_CC_SURFACE_SYNC                      = 0x97,
274 	CB_PERF_SEL_CMASK_READ_DATA_0xC                  = 0x98,
275 	CB_PERF_SEL_CMASK_READ_DATA_0xD                  = 0x99,
276 	CB_PERF_SEL_CMASK_READ_DATA_0xE                  = 0x9a,
277 	CB_PERF_SEL_CMASK_READ_DATA_0xF                  = 0x9b,
278 	CB_PERF_SEL_CMASK_WRITE_DATA_0xC                 = 0x9c,
279 	CB_PERF_SEL_CMASK_WRITE_DATA_0xD                 = 0x9d,
280 	CB_PERF_SEL_CMASK_WRITE_DATA_0xE                 = 0x9e,
281 	CB_PERF_SEL_CMASK_WRITE_DATA_0xF                 = 0x9f,
282 	CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT              = 0xa0,
283 	CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT         = 0xa1,
284 	CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT      = 0xa2,
285 	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE    = 0xa3,
286 	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE   = 0xa4,
287 	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE   = 0xa5,
288 	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE   = 0xa6,
289 	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE   = 0xa7,
290 	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE   = 0xa8,
291 	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE   = 0xa9,
292 	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE   = 0xaa,
293 	CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE     = 0xab,
294 	CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE    = 0xac,
295 	CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE    = 0xad,
296 	CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE    = 0xae,
297 	CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE    = 0xaf,
298 	CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE    = 0xb0,
299 	CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE    = 0xb1,
300 	CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE    = 0xb2,
301 	CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT                = 0xb3,
302 	CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS               = 0xb4,
303 	CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS               = 0xb5,
304 	CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS               = 0xb6,
305 	CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS               = 0xb7,
306 	CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS               = 0xb8,
307 	CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS               = 0xb9,
308 	CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT              = 0xba,
309 	CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS             = 0xbb,
310 	CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS             = 0xbc,
311 	CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS             = 0xbd,
312 	CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS             = 0xbe,
313 	CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS             = 0xbf,
314 	CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS             = 0xc0,
315 	CB_PERF_SEL_QUAD_READS_FRAGMENT_0                = 0xc1,
316 	CB_PERF_SEL_QUAD_READS_FRAGMENT_1                = 0xc2,
317 	CB_PERF_SEL_QUAD_READS_FRAGMENT_2                = 0xc3,
318 	CB_PERF_SEL_QUAD_READS_FRAGMENT_3                = 0xc4,
319 	CB_PERF_SEL_QUAD_READS_FRAGMENT_4                = 0xc5,
320 	CB_PERF_SEL_QUAD_READS_FRAGMENT_5                = 0xc6,
321 	CB_PERF_SEL_QUAD_READS_FRAGMENT_6                = 0xc7,
322 	CB_PERF_SEL_QUAD_READS_FRAGMENT_7                = 0xc8,
323 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0               = 0xc9,
324 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1               = 0xca,
325 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2               = 0xcb,
326 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3               = 0xcc,
327 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4               = 0xcd,
328 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5               = 0xce,
329 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6               = 0xcf,
330 	CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7               = 0xd0,
331 	CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST         = 0xd1,
332 	CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS          = 0xd2,
333 	CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS        = 0xd3,
334 	CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd4,
335 	CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd5,
336 	CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED       = 0xd6,
337 	CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST      = 0xd7,
338 	CB_PERF_SEL_DRAWN_BUSY                           = 0xd8,
339 	CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY              = 0xd9,
340 	CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY               = 0xda,
341 	CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY               = 0xdb,
342 	CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY               = 0xdc,
343 	CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xdd,
344 	CB_PERF_SEL_FC_SEQUENCER_CLEAR                   = 0xde,
345 	CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR    = 0xdf,
346 	CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS        = 0xe0,
347 	CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe1,
348 } CBPerfSel;
349 typedef enum CBPerfOpFilterSel {
350 	CB_PERF_OP_FILTER_SEL_WRITE_ONLY                 = 0x0,
351 	CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION          = 0x1,
352 	CB_PERF_OP_FILTER_SEL_RESOLVE                    = 0x2,
353 	CB_PERF_OP_FILTER_SEL_DECOMPRESS                 = 0x3,
354 	CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS           = 0x4,
355 	CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR       = 0x5,
356 } CBPerfOpFilterSel;
357 typedef enum CBPerfClearFilterSel {
358 	CB_PERF_CLEAR_FILTER_SEL_NONCLEAR                = 0x0,
359 	CB_PERF_CLEAR_FILTER_SEL_CLEAR                   = 0x1,
360 } CBPerfClearFilterSel;
361 typedef enum CP_RING_ID {
362 	RINGID0                                          = 0x0,
363 	RINGID1                                          = 0x1,
364 	RINGID2                                          = 0x2,
365 	RINGID3                                          = 0x3,
366 } CP_RING_ID;
367 typedef enum CP_PIPE_ID {
368 	PIPE_ID0                                         = 0x0,
369 	PIPE_ID1                                         = 0x1,
370 	PIPE_ID2                                         = 0x2,
371 	PIPE_ID3                                         = 0x3,
372 } CP_PIPE_ID;
373 typedef enum CP_ME_ID {
374 	ME_ID0                                           = 0x0,
375 	ME_ID1                                           = 0x1,
376 	ME_ID2                                           = 0x2,
377 	ME_ID3                                           = 0x3,
378 } CP_ME_ID;
379 typedef enum SPM_PERFMON_STATE {
380 	STRM_PERFMON_STATE_DISABLE_AND_RESET             = 0x0,
381 	STRM_PERFMON_STATE_START_COUNTING                = 0x1,
382 	STRM_PERFMON_STATE_STOP_COUNTING                 = 0x2,
383 	STRM_PERFMON_STATE_RESERVED_3                    = 0x3,
384 	STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM     = 0x4,
385 	STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM        = 0x5,
386 } SPM_PERFMON_STATE;
387 typedef enum CP_PERFMON_STATE {
388 	CP_PERFMON_STATE_DISABLE_AND_RESET               = 0x0,
389 	CP_PERFMON_STATE_START_COUNTING                  = 0x1,
390 	CP_PERFMON_STATE_STOP_COUNTING                   = 0x2,
391 	CP_PERFMON_STATE_RESERVED_3                      = 0x3,
392 	CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM       = 0x4,
393 	CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM          = 0x5,
394 } CP_PERFMON_STATE;
395 typedef enum CP_PERFMON_ENABLE_MODE {
396 	CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT              = 0x0,
397 	CP_PERFMON_ENABLE_MODE_RESERVED_1                = 0x1,
398 	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE        = 0x2,
399 	CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE       = 0x3,
400 } CP_PERFMON_ENABLE_MODE;
401 typedef enum CPG_PERFCOUNT_SEL {
402 	CPG_PERF_SEL_ALWAYS_COUNT                        = 0x0,
403 	CPG_PERF_SEL_RBIU_FIFO_FULL                      = 0x1,
404 	CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR             = 0x2,
405 	CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL          = 0x3,
406 	CPG_PERF_SEL_CP_GRBM_DWORDS_SENT                 = 0x4,
407 	CPG_PERF_SEL_ME_PARSER_BUSY                      = 0x5,
408 	CPG_PERF_SEL_COUNT_TYPE0_PACKETS                 = 0x6,
409 	CPG_PERF_SEL_COUNT_TYPE3_PACKETS                 = 0x7,
410 	CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0x8,
411 	CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS              = 0x9,
412 	CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS          = 0xa,
413 	CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS          = 0xb,
414 	CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ             = 0xc,
415 	CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ            = 0xd,
416 	CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX          = 0xe,
417 	CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS        = 0xf,
418 	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE        = 0x10,
419 	CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM   = 0x11,
420 	CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY            = 0x12,
421 	CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY            = 0x13,
422 	CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY           = 0x14,
423 	CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ       = 0x15,
424 	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP        = 0x16,
425 	CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ        = 0x17,
426 	CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX     = 0x18,
427 	CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU          = 0x19,
428 	CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS        = 0x1a,
429 	CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH         = 0x1b,
430 	CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER               = 0x1c,
431 	CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER             = 0x1d,
432 	CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS     = 0x1e,
433 	CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY       = 0x1f,
434 	CPG_PERF_SEL_DYNAMIC_CLK_VALID                   = 0x20,
435 	CPG_PERF_SEL_REGISTER_CLK_VALID                  = 0x21,
436 	CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT              = 0x22,
437 	CPG_PERF_SEL_MIU_READ_REQUEST_SENT               = 0x23,
438 	CPG_PERF_SEL_CE_STALL_RAM_DUMP                   = 0x24,
439 	CPG_PERF_SEL_CE_STALL_RAM_WRITE                  = 0x25,
440 	CPG_PERF_SEL_CE_STALL_ON_INC_FIFO                = 0x26,
441 	CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO             = 0x27,
442 	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU           = 0x28,
443 	CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ           = 0x29,
444 	CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG          = 0x2a,
445 	CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER              = 0x2b,
446 	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x2c,
447 	CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS             = 0x2d,
448 } CPG_PERFCOUNT_SEL;
449 typedef enum CPF_PERFCOUNT_SEL {
450 	CPF_PERF_SEL_ALWAYS_COUNT                        = 0x0,
451 	CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE      = 0x1,
452 	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE        = 0x2,
453 	CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS        = 0x3,
454 	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING          = 0x4,
455 	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1           = 0x5,
456 	CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2           = 0x6,
457 	CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE         = 0x7,
458 	CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS       = 0x8,
459 	CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR                 = 0x9,
460 	CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR              = 0xa,
461 	CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS            = 0xb,
462 	CPF_PERF_SEL_GRBM_DWORDS_SENT                    = 0xc,
463 	CPF_PERF_SEL_DYNAMIC_CLOCK_VALID                 = 0xd,
464 	CPF_PERF_SEL_REGISTER_CLOCK_VALID                = 0xe,
465 	CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND              = 0xf,
466 	CPF_PERF_SEL_MIU_READ_REQUEST_SEND               = 0x10,
467 } CPF_PERFCOUNT_SEL;
468 typedef enum CPC_PERFCOUNT_SEL {
469 	CPC_PERF_SEL_ALWAYS_COUNT                        = 0x0,
470 	CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE             = 0x1,
471 	CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION           = 0x2,
472 	CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE             = 0x3,
473 	CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE             = 0x4,
474 	CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE             = 0x5,
475 	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY        = 0x6,
476 	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF   = 0x7,
477 	CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ         = 0x8,
478 	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ          = 0x9,
479 	CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE         = 0xa,
480 	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ          = 0xb,
481 	CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF     = 0xc,
482 	CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE          = 0xd,
483 	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY        = 0xe,
484 	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF   = 0xf,
485 	CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ         = 0x10,
486 	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ          = 0x11,
487 	CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE         = 0x12,
488 	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ          = 0x13,
489 	CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF     = 0x14,
490 	CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE          = 0x15,
491 } CPC_PERFCOUNT_SEL;
492 typedef enum CP_ALPHA_TAG_RAM_SEL {
493 	CPG_TAG_RAM                                      = 0x0,
494 	CPC_TAG_RAM                                      = 0x1,
495 	CPF_TAG_RAM                                      = 0x2,
496 	RSV_TAG_RAM                                      = 0x3,
497 } CP_ALPHA_TAG_RAM_SEL;
498 #define SEM_ECC_ERROR                             0x0
499 #define SEM_RESERVED                              0x1
500 #define SEM_FAILED                                0x2
501 #define SEM_PASSED                                0x3
502 #define IQ_QUEUE_SLEEP                            0x0
503 #define IQ_OFFLOAD_RETRY                          0x1
504 #define IQ_SCH_WAVE_MSG                           0x2
505 #define IQ_SEM_REARM                              0x3
506 #define IQ_DEQUEUE_RETRY                          0x4
507 #define IQ_INTR_TYPE_PQ                           0x0
508 #define IQ_INTR_TYPE_IB                           0x1
509 #define IQ_INTR_TYPE_MQD                          0x2
510 #define VMID_SZ                                   0x4
511 #define CONFIG_SPACE_START                        0x2000
512 #define CONFIG_SPACE_END                          0x9fff
513 #define CONFIG_SPACE1_START                       0x2000
514 #define CONFIG_SPACE1_END                         0x2bff
515 #define CONFIG_SPACE2_START                       0x3000
516 #define CONFIG_SPACE2_END                         0x9fff
517 #define UCONFIG_SPACE_START                       0xc000
518 #define UCONFIG_SPACE_END                         0xffff
519 #define PERSISTENT_SPACE_START                    0x2c00
520 #define PERSISTENT_SPACE_END                      0x2fff
521 #define CONTEXT_SPACE_START                       0xa000
522 #define CONTEXT_SPACE_END                         0xbfff
523 typedef enum ForceControl {
524 	FORCE_OFF                                        = 0x0,
525 	FORCE_ENABLE                                     = 0x1,
526 	FORCE_DISABLE                                    = 0x2,
527 	FORCE_RESERVED                                   = 0x3,
528 } ForceControl;
529 typedef enum ZSamplePosition {
530 	Z_SAMPLE_CENTER                                  = 0x0,
531 	Z_SAMPLE_CENTROID                                = 0x1,
532 } ZSamplePosition;
533 typedef enum ZOrder {
534 	LATE_Z                                           = 0x0,
535 	EARLY_Z_THEN_LATE_Z                              = 0x1,
536 	RE_Z                                             = 0x2,
537 	EARLY_Z_THEN_RE_Z                                = 0x3,
538 } ZOrder;
539 typedef enum ZpassControl {
540 	ZPASS_DISABLE                                    = 0x0,
541 	ZPASS_SAMPLES                                    = 0x1,
542 	ZPASS_PIXELS                                     = 0x2,
543 } ZpassControl;
544 typedef enum ZModeForce {
545 	NO_FORCE                                         = 0x0,
546 	FORCE_EARLY_Z                                    = 0x1,
547 	FORCE_LATE_Z                                     = 0x2,
548 	FORCE_RE_Z                                       = 0x3,
549 } ZModeForce;
550 typedef enum ZLimitSumm {
551 	FORCE_SUMM_OFF                                   = 0x0,
552 	FORCE_SUMM_MINZ                                  = 0x1,
553 	FORCE_SUMM_MAXZ                                  = 0x2,
554 	FORCE_SUMM_BOTH                                  = 0x3,
555 } ZLimitSumm;
556 typedef enum CompareFrag {
557 	FRAG_NEVER                                       = 0x0,
558 	FRAG_LESS                                        = 0x1,
559 	FRAG_EQUAL                                       = 0x2,
560 	FRAG_LEQUAL                                      = 0x3,
561 	FRAG_GREATER                                     = 0x4,
562 	FRAG_NOTEQUAL                                    = 0x5,
563 	FRAG_GEQUAL                                      = 0x6,
564 	FRAG_ALWAYS                                      = 0x7,
565 } CompareFrag;
566 typedef enum StencilOp {
567 	STENCIL_KEEP                                     = 0x0,
568 	STENCIL_ZERO                                     = 0x1,
569 	STENCIL_ONES                                     = 0x2,
570 	STENCIL_REPLACE_TEST                             = 0x3,
571 	STENCIL_REPLACE_OP                               = 0x4,
572 	STENCIL_ADD_CLAMP                                = 0x5,
573 	STENCIL_SUB_CLAMP                                = 0x6,
574 	STENCIL_INVERT                                   = 0x7,
575 	STENCIL_ADD_WRAP                                 = 0x8,
576 	STENCIL_SUB_WRAP                                 = 0x9,
577 	STENCIL_AND                                      = 0xa,
578 	STENCIL_OR                                       = 0xb,
579 	STENCIL_XOR                                      = 0xc,
580 	STENCIL_NAND                                     = 0xd,
581 	STENCIL_NOR                                      = 0xe,
582 	STENCIL_XNOR                                     = 0xf,
583 } StencilOp;
584 typedef enum ConservativeZExport {
585 	EXPORT_ANY_Z                                     = 0x0,
586 	EXPORT_LESS_THAN_Z                               = 0x1,
587 	EXPORT_GREATER_THAN_Z                            = 0x2,
588 	EXPORT_RESERVED                                  = 0x3,
589 } ConservativeZExport;
590 typedef enum DbPSLControl {
591 	PSLC_AUTO                                        = 0x0,
592 	PSLC_ON_HANG_ONLY                                = 0x1,
593 	PSLC_ASAP                                        = 0x2,
594 	PSLC_COUNTDOWN                                   = 0x3,
595 } DbPSLControl;
596 typedef enum PerfCounter_Vals {
597 	DB_PERF_SEL_SC_DB_tile_sends                     = 0x0,
598 	DB_PERF_SEL_SC_DB_tile_busy                      = 0x1,
599 	DB_PERF_SEL_SC_DB_tile_stalls                    = 0x2,
600 	DB_PERF_SEL_SC_DB_tile_events                    = 0x3,
601 	DB_PERF_SEL_SC_DB_tile_tiles                     = 0x4,
602 	DB_PERF_SEL_SC_DB_tile_covered                   = 0x5,
603 	DB_PERF_SEL_hiz_tc_read_starved                  = 0x6,
604 	DB_PERF_SEL_hiz_tc_write_stall                   = 0x7,
605 	DB_PERF_SEL_hiz_qtiles_culled                    = 0x8,
606 	DB_PERF_SEL_his_qtiles_culled                    = 0x9,
607 	DB_PERF_SEL_DB_SC_tile_sends                     = 0xa,
608 	DB_PERF_SEL_DB_SC_tile_busy                      = 0xb,
609 	DB_PERF_SEL_DB_SC_tile_stalls                    = 0xc,
610 	DB_PERF_SEL_DB_SC_tile_df_stalls                 = 0xd,
611 	DB_PERF_SEL_DB_SC_tile_tiles                     = 0xe,
612 	DB_PERF_SEL_DB_SC_tile_culled                    = 0xf,
613 	DB_PERF_SEL_DB_SC_tile_hier_kill                 = 0x10,
614 	DB_PERF_SEL_DB_SC_tile_fast_ops                  = 0x11,
615 	DB_PERF_SEL_DB_SC_tile_no_ops                    = 0x12,
616 	DB_PERF_SEL_DB_SC_tile_tile_rate                 = 0x13,
617 	DB_PERF_SEL_DB_SC_tile_ssaa_kill                 = 0x14,
618 	DB_PERF_SEL_DB_SC_tile_fast_z_ops                = 0x15,
619 	DB_PERF_SEL_DB_SC_tile_fast_stencil_ops          = 0x16,
620 	DB_PERF_SEL_SC_DB_quad_sends                     = 0x17,
621 	DB_PERF_SEL_SC_DB_quad_busy                      = 0x18,
622 	DB_PERF_SEL_SC_DB_quad_squads                    = 0x19,
623 	DB_PERF_SEL_SC_DB_quad_tiles                     = 0x1a,
624 	DB_PERF_SEL_SC_DB_quad_pixels                    = 0x1b,
625 	DB_PERF_SEL_SC_DB_quad_killed_tiles              = 0x1c,
626 	DB_PERF_SEL_DB_SC_quad_sends                     = 0x1d,
627 	DB_PERF_SEL_DB_SC_quad_busy                      = 0x1e,
628 	DB_PERF_SEL_DB_SC_quad_stalls                    = 0x1f,
629 	DB_PERF_SEL_DB_SC_quad_tiles                     = 0x20,
630 	DB_PERF_SEL_DB_SC_quad_lit_quad                  = 0x21,
631 	DB_PERF_SEL_DB_CB_tile_sends                     = 0x22,
632 	DB_PERF_SEL_DB_CB_tile_busy                      = 0x23,
633 	DB_PERF_SEL_DB_CB_tile_stalls                    = 0x24,
634 	DB_PERF_SEL_SX_DB_quad_sends                     = 0x25,
635 	DB_PERF_SEL_SX_DB_quad_busy                      = 0x26,
636 	DB_PERF_SEL_SX_DB_quad_stalls                    = 0x27,
637 	DB_PERF_SEL_SX_DB_quad_quads                     = 0x28,
638 	DB_PERF_SEL_SX_DB_quad_pixels                    = 0x29,
639 	DB_PERF_SEL_SX_DB_quad_exports                   = 0x2a,
640 	DB_PERF_SEL_SH_quads_outstanding_sum             = 0x2b,
641 	DB_PERF_SEL_DB_CB_lquad_sends                    = 0x2c,
642 	DB_PERF_SEL_DB_CB_lquad_busy                     = 0x2d,
643 	DB_PERF_SEL_DB_CB_lquad_stalls                   = 0x2e,
644 	DB_PERF_SEL_DB_CB_lquad_quads                    = 0x2f,
645 	DB_PERF_SEL_tile_rd_sends                        = 0x30,
646 	DB_PERF_SEL_mi_tile_rd_outstanding_sum           = 0x31,
647 	DB_PERF_SEL_quad_rd_sends                        = 0x32,
648 	DB_PERF_SEL_quad_rd_busy                         = 0x33,
649 	DB_PERF_SEL_quad_rd_mi_stall                     = 0x34,
650 	DB_PERF_SEL_quad_rd_rw_collision                 = 0x35,
651 	DB_PERF_SEL_quad_rd_tag_stall                    = 0x36,
652 	DB_PERF_SEL_quad_rd_32byte_reqs                  = 0x37,
653 	DB_PERF_SEL_quad_rd_panic                        = 0x38,
654 	DB_PERF_SEL_mi_quad_rd_outstanding_sum           = 0x39,
655 	DB_PERF_SEL_quad_rdret_sends                     = 0x3a,
656 	DB_PERF_SEL_quad_rdret_busy                      = 0x3b,
657 	DB_PERF_SEL_tile_wr_sends                        = 0x3c,
658 	DB_PERF_SEL_tile_wr_acks                         = 0x3d,
659 	DB_PERF_SEL_mi_tile_wr_outstanding_sum           = 0x3e,
660 	DB_PERF_SEL_quad_wr_sends                        = 0x3f,
661 	DB_PERF_SEL_quad_wr_busy                         = 0x40,
662 	DB_PERF_SEL_quad_wr_mi_stall                     = 0x41,
663 	DB_PERF_SEL_quad_wr_coherency_stall              = 0x42,
664 	DB_PERF_SEL_quad_wr_acks                         = 0x43,
665 	DB_PERF_SEL_mi_quad_wr_outstanding_sum           = 0x44,
666 	DB_PERF_SEL_Tile_Cache_misses                    = 0x45,
667 	DB_PERF_SEL_Tile_Cache_hits                      = 0x46,
668 	DB_PERF_SEL_Tile_Cache_flushes                   = 0x47,
669 	DB_PERF_SEL_Tile_Cache_surface_stall             = 0x48,
670 	DB_PERF_SEL_Tile_Cache_starves                   = 0x49,
671 	DB_PERF_SEL_Tile_Cache_mem_return_starve         = 0x4a,
672 	DB_PERF_SEL_tcp_dispatcher_reads                 = 0x4b,
673 	DB_PERF_SEL_tcp_prefetcher_reads                 = 0x4c,
674 	DB_PERF_SEL_tcp_preloader_reads                  = 0x4d,
675 	DB_PERF_SEL_tcp_dispatcher_flushes               = 0x4e,
676 	DB_PERF_SEL_tcp_prefetcher_flushes               = 0x4f,
677 	DB_PERF_SEL_tcp_preloader_flushes                = 0x50,
678 	DB_PERF_SEL_Depth_Tile_Cache_sends               = 0x51,
679 	DB_PERF_SEL_Depth_Tile_Cache_busy                = 0x52,
680 	DB_PERF_SEL_Depth_Tile_Cache_starves             = 0x53,
681 	DB_PERF_SEL_Depth_Tile_Cache_dtile_locked        = 0x54,
682 	DB_PERF_SEL_Depth_Tile_Cache_alloc_stall         = 0x55,
683 	DB_PERF_SEL_Depth_Tile_Cache_misses              = 0x56,
684 	DB_PERF_SEL_Depth_Tile_Cache_hits                = 0x57,
685 	DB_PERF_SEL_Depth_Tile_Cache_flushes             = 0x58,
686 	DB_PERF_SEL_Depth_Tile_Cache_noop_tile           = 0x59,
687 	DB_PERF_SEL_Depth_Tile_Cache_detailed_noop       = 0x5a,
688 	DB_PERF_SEL_Depth_Tile_Cache_event               = 0x5b,
689 	DB_PERF_SEL_Depth_Tile_Cache_tile_frees          = 0x5c,
690 	DB_PERF_SEL_Depth_Tile_Cache_data_frees          = 0x5d,
691 	DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve   = 0x5e,
692 	DB_PERF_SEL_Stencil_Cache_misses                 = 0x5f,
693 	DB_PERF_SEL_Stencil_Cache_hits                   = 0x60,
694 	DB_PERF_SEL_Stencil_Cache_flushes                = 0x61,
695 	DB_PERF_SEL_Stencil_Cache_starves                = 0x62,
696 	DB_PERF_SEL_Stencil_Cache_frees                  = 0x63,
697 	DB_PERF_SEL_Z_Cache_separate_Z_misses            = 0x64,
698 	DB_PERF_SEL_Z_Cache_separate_Z_hits              = 0x65,
699 	DB_PERF_SEL_Z_Cache_separate_Z_flushes           = 0x66,
700 	DB_PERF_SEL_Z_Cache_separate_Z_starves           = 0x67,
701 	DB_PERF_SEL_Z_Cache_pmask_misses                 = 0x68,
702 	DB_PERF_SEL_Z_Cache_pmask_hits                   = 0x69,
703 	DB_PERF_SEL_Z_Cache_pmask_flushes                = 0x6a,
704 	DB_PERF_SEL_Z_Cache_pmask_starves                = 0x6b,
705 	DB_PERF_SEL_Z_Cache_frees                        = 0x6c,
706 	DB_PERF_SEL_Plane_Cache_misses                   = 0x6d,
707 	DB_PERF_SEL_Plane_Cache_hits                     = 0x6e,
708 	DB_PERF_SEL_Plane_Cache_flushes                  = 0x6f,
709 	DB_PERF_SEL_Plane_Cache_starves                  = 0x70,
710 	DB_PERF_SEL_Plane_Cache_frees                    = 0x71,
711 	DB_PERF_SEL_flush_expanded_stencil               = 0x72,
712 	DB_PERF_SEL_flush_compressed_stencil             = 0x73,
713 	DB_PERF_SEL_flush_single_stencil                 = 0x74,
714 	DB_PERF_SEL_planes_flushed                       = 0x75,
715 	DB_PERF_SEL_flush_1plane                         = 0x76,
716 	DB_PERF_SEL_flush_2plane                         = 0x77,
717 	DB_PERF_SEL_flush_3plane                         = 0x78,
718 	DB_PERF_SEL_flush_4plane                         = 0x79,
719 	DB_PERF_SEL_flush_5plane                         = 0x7a,
720 	DB_PERF_SEL_flush_6plane                         = 0x7b,
721 	DB_PERF_SEL_flush_7plane                         = 0x7c,
722 	DB_PERF_SEL_flush_8plane                         = 0x7d,
723 	DB_PERF_SEL_flush_9plane                         = 0x7e,
724 	DB_PERF_SEL_flush_10plane                        = 0x7f,
725 	DB_PERF_SEL_flush_11plane                        = 0x80,
726 	DB_PERF_SEL_flush_12plane                        = 0x81,
727 	DB_PERF_SEL_flush_13plane                        = 0x82,
728 	DB_PERF_SEL_flush_14plane                        = 0x83,
729 	DB_PERF_SEL_flush_15plane                        = 0x84,
730 	DB_PERF_SEL_flush_16plane                        = 0x85,
731 	DB_PERF_SEL_flush_expanded_z                     = 0x86,
732 	DB_PERF_SEL_earlyZ_waiting_for_postZ_done        = 0x87,
733 	DB_PERF_SEL_reZ_waiting_for_postZ_done           = 0x88,
734 	DB_PERF_SEL_dk_tile_sends                        = 0x89,
735 	DB_PERF_SEL_dk_tile_busy                         = 0x8a,
736 	DB_PERF_SEL_dk_tile_quad_starves                 = 0x8b,
737 	DB_PERF_SEL_dk_tile_stalls                       = 0x8c,
738 	DB_PERF_SEL_dk_squad_sends                       = 0x8d,
739 	DB_PERF_SEL_dk_squad_busy                        = 0x8e,
740 	DB_PERF_SEL_dk_squad_stalls                      = 0x8f,
741 	DB_PERF_SEL_Op_Pipe_Busy                         = 0x90,
742 	DB_PERF_SEL_Op_Pipe_MC_Read_stall                = 0x91,
743 	DB_PERF_SEL_qc_busy                              = 0x92,
744 	DB_PERF_SEL_qc_xfc                               = 0x93,
745 	DB_PERF_SEL_qc_conflicts                         = 0x94,
746 	DB_PERF_SEL_qc_full_stall                        = 0x95,
747 	DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ         = 0x96,
748 	DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ         = 0x97,
749 	DB_PERF_SEL_tsc_insert_summarize_stall           = 0x98,
750 	DB_PERF_SEL_tl_busy                              = 0x99,
751 	DB_PERF_SEL_tl_dtc_read_starved                  = 0x9a,
752 	DB_PERF_SEL_tl_z_fetch_stall                     = 0x9b,
753 	DB_PERF_SEL_tl_stencil_stall                     = 0x9c,
754 	DB_PERF_SEL_tl_z_decompress_stall                = 0x9d,
755 	DB_PERF_SEL_tl_stencil_locked_stall              = 0x9e,
756 	DB_PERF_SEL_tl_events                            = 0x9f,
757 	DB_PERF_SEL_tl_summarize_squads                  = 0xa0,
758 	DB_PERF_SEL_tl_flush_expand_squads               = 0xa1,
759 	DB_PERF_SEL_tl_expand_squads                     = 0xa2,
760 	DB_PERF_SEL_tl_preZ_squads                       = 0xa3,
761 	DB_PERF_SEL_tl_postZ_squads                      = 0xa4,
762 	DB_PERF_SEL_tl_preZ_noop_squads                  = 0xa5,
763 	DB_PERF_SEL_tl_postZ_noop_squads                 = 0xa6,
764 	DB_PERF_SEL_tl_tile_ops                          = 0xa7,
765 	DB_PERF_SEL_tl_in_xfc                            = 0xa8,
766 	DB_PERF_SEL_tl_in_single_stencil_expand_stall    = 0xa9,
767 	DB_PERF_SEL_tl_in_fast_z_stall                   = 0xaa,
768 	DB_PERF_SEL_tl_out_xfc                           = 0xab,
769 	DB_PERF_SEL_tl_out_squads                        = 0xac,
770 	DB_PERF_SEL_zf_plane_multicycle                  = 0xad,
771 	DB_PERF_SEL_PostZ_Samples_passing_Z              = 0xae,
772 	DB_PERF_SEL_PostZ_Samples_failing_Z              = 0xaf,
773 	DB_PERF_SEL_PostZ_Samples_failing_S              = 0xb0,
774 	DB_PERF_SEL_PreZ_Samples_passing_Z               = 0xb1,
775 	DB_PERF_SEL_PreZ_Samples_failing_Z               = 0xb2,
776 	DB_PERF_SEL_PreZ_Samples_failing_S               = 0xb3,
777 	DB_PERF_SEL_ts_tc_update_stall                   = 0xb4,
778 	DB_PERF_SEL_sc_kick_start                        = 0xb5,
779 	DB_PERF_SEL_sc_kick_end                          = 0xb6,
780 	DB_PERF_SEL_clock_reg_active                     = 0xb7,
781 	DB_PERF_SEL_clock_main_active                    = 0xb8,
782 	DB_PERF_SEL_clock_mem_export_active              = 0xb9,
783 	DB_PERF_SEL_esr_ps_out_busy                      = 0xba,
784 	DB_PERF_SEL_esr_ps_lqf_busy                      = 0xbb,
785 	DB_PERF_SEL_esr_ps_lqf_stall                     = 0xbc,
786 	DB_PERF_SEL_etr_out_send                         = 0xbd,
787 	DB_PERF_SEL_etr_out_busy                         = 0xbe,
788 	DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall  = 0xbf,
789 	DB_PERF_SEL_etr_out_cb_tile_stall                = 0xc0,
790 	DB_PERF_SEL_etr_out_esr_stall                    = 0xc1,
791 	DB_PERF_SEL_esr_ps_sqq_busy                      = 0xc2,
792 	DB_PERF_SEL_esr_ps_sqq_stall                     = 0xc3,
793 	DB_PERF_SEL_esr_eot_fwd_busy                     = 0xc4,
794 	DB_PERF_SEL_esr_eot_fwd_holding_squad            = 0xc5,
795 	DB_PERF_SEL_esr_eot_fwd_forward                  = 0xc6,
796 	DB_PERF_SEL_esr_sqq_zi_busy                      = 0xc7,
797 	DB_PERF_SEL_esr_sqq_zi_stall                     = 0xc8,
798 	DB_PERF_SEL_postzl_sq_pt_busy                    = 0xc9,
799 	DB_PERF_SEL_postzl_sq_pt_stall                   = 0xca,
800 	DB_PERF_SEL_postzl_se_busy                       = 0xcb,
801 	DB_PERF_SEL_postzl_se_stall                      = 0xcc,
802 	DB_PERF_SEL_postzl_partial_launch                = 0xcd,
803 	DB_PERF_SEL_postzl_full_launch                   = 0xce,
804 	DB_PERF_SEL_postzl_partial_waiting               = 0xcf,
805 	DB_PERF_SEL_postzl_tile_mem_stall                = 0xd0,
806 	DB_PERF_SEL_postzl_tile_init_stall               = 0xd1,
807 	DB_PEFF_SEL_prezl_tile_mem_stall                 = 0xd2,
808 	DB_PERF_SEL_prezl_tile_init_stall                = 0xd3,
809 	DB_PERF_SEL_dtt_sm_clash_stall                   = 0xd4,
810 	DB_PERF_SEL_dtt_sm_slot_stall                    = 0xd5,
811 	DB_PERF_SEL_dtt_sm_miss_stall                    = 0xd6,
812 	DB_PERF_SEL_mi_rdreq_busy                        = 0xd7,
813 	DB_PERF_SEL_mi_rdreq_stall                       = 0xd8,
814 	DB_PERF_SEL_mi_wrreq_busy                        = 0xd9,
815 	DB_PERF_SEL_mi_wrreq_stall                       = 0xda,
816 	DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop     = 0xdb,
817 	DB_PERF_SEL_dkg_tile_rate_tile                   = 0xdc,
818 	DB_PERF_SEL_prezl_src_in_sends                   = 0xdd,
819 	DB_PERF_SEL_prezl_src_in_stall                   = 0xde,
820 	DB_PERF_SEL_prezl_src_in_squads                  = 0xdf,
821 	DB_PERF_SEL_prezl_src_in_squads_unrolled         = 0xe0,
822 	DB_PERF_SEL_prezl_src_in_tile_rate               = 0xe1,
823 	DB_PERF_SEL_prezl_src_in_tile_rate_unrolled      = 0xe2,
824 	DB_PERF_SEL_prezl_src_out_stall                  = 0xe3,
825 	DB_PERF_SEL_postzl_src_in_sends                  = 0xe4,
826 	DB_PERF_SEL_postzl_src_in_stall                  = 0xe5,
827 	DB_PERF_SEL_postzl_src_in_squads                 = 0xe6,
828 	DB_PERF_SEL_postzl_src_in_squads_unrolled        = 0xe7,
829 	DB_PERF_SEL_postzl_src_in_tile_rate              = 0xe8,
830 	DB_PERF_SEL_postzl_src_in_tile_rate_unrolled     = 0xe9,
831 	DB_PERF_SEL_postzl_src_out_stall                 = 0xea,
832 	DB_PERF_SEL_esr_ps_src_in_sends                  = 0xeb,
833 	DB_PERF_SEL_esr_ps_src_in_stall                  = 0xec,
834 	DB_PERF_SEL_esr_ps_src_in_squads                 = 0xed,
835 	DB_PERF_SEL_esr_ps_src_in_squads_unrolled        = 0xee,
836 	DB_PERF_SEL_esr_ps_src_in_tile_rate              = 0xef,
837 	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled     = 0xf0,
838 	DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1,
839 	DB_PERF_SEL_esr_ps_src_out_stall                 = 0xf2,
840 	DB_PERF_SEL_depth_bounds_qtiles_culled           = 0xf3,
841 	DB_PERF_SEL_PreZ_Samples_failing_DB              = 0xf4,
842 	DB_PERF_SEL_PostZ_Samples_failing_DB             = 0xf5,
843 	DB_PERF_SEL_flush_compressed                     = 0xf6,
844 	DB_PERF_SEL_flush_plane_le4                      = 0xf7,
845 	DB_PERF_SEL_tiles_z_fully_summarized             = 0xf8,
846 	DB_PERF_SEL_tiles_stencil_fully_summarized       = 0xf9,
847 	DB_PERF_SEL_tiles_z_clear_on_expclear            = 0xfa,
848 	DB_PERF_SEL_tiles_s_clear_on_expclear            = 0xfb,
849 	DB_PERF_SEL_tiles_decomp_on_expclear             = 0xfc,
850 	DB_PERF_SEL_tiles_compressed_to_decompressed     = 0xfd,
851 	DB_PERF_SEL_Op_Pipe_Prez_Busy                    = 0xfe,
852 	DB_PERF_SEL_Op_Pipe_Postz_Busy                   = 0xff,
853 	DB_PERF_SEL_di_dt_stall                          = 0x100,
854 } PerfCounter_Vals;
855 typedef enum RingCounterControl {
856 	COUNTER_RING_SPLIT                               = 0x0,
857 	COUNTER_RING_0                                   = 0x1,
858 	COUNTER_RING_1                                   = 0x2,
859 } RingCounterControl;
860 typedef enum PixelPipeCounterId {
861 	PIXEL_PIPE_OCCLUSION_COUNT_0                     = 0x0,
862 	PIXEL_PIPE_OCCLUSION_COUNT_1                     = 0x1,
863 	PIXEL_PIPE_OCCLUSION_COUNT_2                     = 0x2,
864 	PIXEL_PIPE_OCCLUSION_COUNT_3                     = 0x3,
865 	PIXEL_PIPE_SCREEN_MIN_EXTENTS_0                  = 0x4,
866 	PIXEL_PIPE_SCREEN_MAX_EXTENTS_0                  = 0x5,
867 	PIXEL_PIPE_SCREEN_MIN_EXTENTS_1                  = 0x6,
868 	PIXEL_PIPE_SCREEN_MAX_EXTENTS_1                  = 0x7,
869 } PixelPipeCounterId;
870 typedef enum PixelPipeStride {
871 	PIXEL_PIPE_STRIDE_32_BITS                        = 0x0,
872 	PIXEL_PIPE_STRIDE_64_BITS                        = 0x1,
873 	PIXEL_PIPE_STRIDE_128_BITS                       = 0x2,
874 	PIXEL_PIPE_STRIDE_256_BITS                       = 0x3,
875 } PixelPipeStride;
876 typedef enum GB_EDC_DED_MODE {
877 	GB_EDC_DED_MODE_LOG                              = 0x0,
878 	GB_EDC_DED_MODE_HALT                             = 0x1,
879 	GB_EDC_DED_MODE_INT_HALT                         = 0x2,
880 } GB_EDC_DED_MODE;
881 #define GB_TILING_CONFIG_TABLE_SIZE               0x20
882 #define GB_TILING_CONFIG_MACROTABLE_SIZE          0x10
883 typedef enum GRBM_PERF_SEL {
884 	GRBM_PERF_SEL_COUNT                              = 0x0,
885 	GRBM_PERF_SEL_USER_DEFINED                       = 0x1,
886 	GRBM_PERF_SEL_GUI_ACTIVE                         = 0x2,
887 	GRBM_PERF_SEL_CP_BUSY                            = 0x3,
888 	GRBM_PERF_SEL_CP_COHER_BUSY                      = 0x4,
889 	GRBM_PERF_SEL_CP_DMA_BUSY                        = 0x5,
890 	GRBM_PERF_SEL_CB_BUSY                            = 0x6,
891 	GRBM_PERF_SEL_DB_BUSY                            = 0x7,
892 	GRBM_PERF_SEL_PA_BUSY                            = 0x8,
893 	GRBM_PERF_SEL_SC_BUSY                            = 0x9,
894 	GRBM_PERF_SEL_RESERVED_6                         = 0xa,
895 	GRBM_PERF_SEL_SPI_BUSY                           = 0xb,
896 	GRBM_PERF_SEL_SX_BUSY                            = 0xc,
897 	GRBM_PERF_SEL_TA_BUSY                            = 0xd,
898 	GRBM_PERF_SEL_CB_CLEAN                           = 0xe,
899 	GRBM_PERF_SEL_DB_CLEAN                           = 0xf,
900 	GRBM_PERF_SEL_RESERVED_5                         = 0x10,
901 	GRBM_PERF_SEL_VGT_BUSY                           = 0x11,
902 	GRBM_PERF_SEL_RESERVED_4                         = 0x12,
903 	GRBM_PERF_SEL_RESERVED_3                         = 0x13,
904 	GRBM_PERF_SEL_RESERVED_2                         = 0x14,
905 	GRBM_PERF_SEL_RESERVED_1                         = 0x15,
906 	GRBM_PERF_SEL_RESERVED_0                         = 0x16,
907 	GRBM_PERF_SEL_IA_BUSY                            = 0x17,
908 	GRBM_PERF_SEL_IA_NO_DMA_BUSY                     = 0x18,
909 	GRBM_PERF_SEL_GDS_BUSY                           = 0x19,
910 	GRBM_PERF_SEL_BCI_BUSY                           = 0x1a,
911 	GRBM_PERF_SEL_RLC_BUSY                           = 0x1b,
912 	GRBM_PERF_SEL_TC_BUSY                            = 0x1c,
913 	GRBM_PERF_SEL_CPG_BUSY                           = 0x1d,
914 	GRBM_PERF_SEL_CPC_BUSY                           = 0x1e,
915 	GRBM_PERF_SEL_CPF_BUSY                           = 0x1f,
916 	GRBM_PERF_SEL_WD_BUSY                            = 0x20,
917 	GRBM_PERF_SEL_WD_NO_DMA_BUSY                     = 0x21,
918 } GRBM_PERF_SEL;
919 typedef enum GRBM_SE0_PERF_SEL {
920 	GRBM_SE0_PERF_SEL_COUNT                          = 0x0,
921 	GRBM_SE0_PERF_SEL_USER_DEFINED                   = 0x1,
922 	GRBM_SE0_PERF_SEL_CB_BUSY                        = 0x2,
923 	GRBM_SE0_PERF_SEL_DB_BUSY                        = 0x3,
924 	GRBM_SE0_PERF_SEL_SC_BUSY                        = 0x4,
925 	GRBM_SE0_PERF_SEL_RESERVED_1                     = 0x5,
926 	GRBM_SE0_PERF_SEL_SPI_BUSY                       = 0x6,
927 	GRBM_SE0_PERF_SEL_SX_BUSY                        = 0x7,
928 	GRBM_SE0_PERF_SEL_TA_BUSY                        = 0x8,
929 	GRBM_SE0_PERF_SEL_CB_CLEAN                       = 0x9,
930 	GRBM_SE0_PERF_SEL_DB_CLEAN                       = 0xa,
931 	GRBM_SE0_PERF_SEL_RESERVED_0                     = 0xb,
932 	GRBM_SE0_PERF_SEL_PA_BUSY                        = 0xc,
933 	GRBM_SE0_PERF_SEL_VGT_BUSY                       = 0xd,
934 	GRBM_SE0_PERF_SEL_BCI_BUSY                       = 0xe,
935 } GRBM_SE0_PERF_SEL;
936 typedef enum GRBM_SE1_PERF_SEL {
937 	GRBM_SE1_PERF_SEL_COUNT                          = 0x0,
938 	GRBM_SE1_PERF_SEL_USER_DEFINED                   = 0x1,
939 	GRBM_SE1_PERF_SEL_CB_BUSY                        = 0x2,
940 	GRBM_SE1_PERF_SEL_DB_BUSY                        = 0x3,
941 	GRBM_SE1_PERF_SEL_SC_BUSY                        = 0x4,
942 	GRBM_SE1_PERF_SEL_RESERVED_1                     = 0x5,
943 	GRBM_SE1_PERF_SEL_SPI_BUSY                       = 0x6,
944 	GRBM_SE1_PERF_SEL_SX_BUSY                        = 0x7,
945 	GRBM_SE1_PERF_SEL_TA_BUSY                        = 0x8,
946 	GRBM_SE1_PERF_SEL_CB_CLEAN                       = 0x9,
947 	GRBM_SE1_PERF_SEL_DB_CLEAN                       = 0xa,
948 	GRBM_SE1_PERF_SEL_RESERVED_0                     = 0xb,
949 	GRBM_SE1_PERF_SEL_PA_BUSY                        = 0xc,
950 	GRBM_SE1_PERF_SEL_VGT_BUSY                       = 0xd,
951 	GRBM_SE1_PERF_SEL_BCI_BUSY                       = 0xe,
952 } GRBM_SE1_PERF_SEL;
953 typedef enum GRBM_SE2_PERF_SEL {
954 	GRBM_SE2_PERF_SEL_COUNT                          = 0x0,
955 	GRBM_SE2_PERF_SEL_USER_DEFINED                   = 0x1,
956 	GRBM_SE2_PERF_SEL_CB_BUSY                        = 0x2,
957 	GRBM_SE2_PERF_SEL_DB_BUSY                        = 0x3,
958 	GRBM_SE2_PERF_SEL_SC_BUSY                        = 0x4,
959 	GRBM_SE2_PERF_SEL_RESERVED_1                     = 0x5,
960 	GRBM_SE2_PERF_SEL_SPI_BUSY                       = 0x6,
961 	GRBM_SE2_PERF_SEL_SX_BUSY                        = 0x7,
962 	GRBM_SE2_PERF_SEL_TA_BUSY                        = 0x8,
963 	GRBM_SE2_PERF_SEL_CB_CLEAN                       = 0x9,
964 	GRBM_SE2_PERF_SEL_DB_CLEAN                       = 0xa,
965 	GRBM_SE2_PERF_SEL_RESERVED_0                     = 0xb,
966 	GRBM_SE2_PERF_SEL_PA_BUSY                        = 0xc,
967 	GRBM_SE2_PERF_SEL_VGT_BUSY                       = 0xd,
968 	GRBM_SE2_PERF_SEL_BCI_BUSY                       = 0xe,
969 } GRBM_SE2_PERF_SEL;
970 typedef enum GRBM_SE3_PERF_SEL {
971 	GRBM_SE3_PERF_SEL_COUNT                          = 0x0,
972 	GRBM_SE3_PERF_SEL_USER_DEFINED                   = 0x1,
973 	GRBM_SE3_PERF_SEL_CB_BUSY                        = 0x2,
974 	GRBM_SE3_PERF_SEL_DB_BUSY                        = 0x3,
975 	GRBM_SE3_PERF_SEL_SC_BUSY                        = 0x4,
976 	GRBM_SE3_PERF_SEL_RESERVED_1                     = 0x5,
977 	GRBM_SE3_PERF_SEL_SPI_BUSY                       = 0x6,
978 	GRBM_SE3_PERF_SEL_SX_BUSY                        = 0x7,
979 	GRBM_SE3_PERF_SEL_TA_BUSY                        = 0x8,
980 	GRBM_SE3_PERF_SEL_CB_CLEAN                       = 0x9,
981 	GRBM_SE3_PERF_SEL_DB_CLEAN                       = 0xa,
982 	GRBM_SE3_PERF_SEL_RESERVED_0                     = 0xb,
983 	GRBM_SE3_PERF_SEL_PA_BUSY                        = 0xc,
984 	GRBM_SE3_PERF_SEL_VGT_BUSY                       = 0xd,
985 	GRBM_SE3_PERF_SEL_BCI_BUSY                       = 0xe,
986 } GRBM_SE3_PERF_SEL;
987 typedef enum SU_PERFCNT_SEL {
988 	PERF_PAPC_PASX_REQ                               = 0x0,
989 	PERF_PAPC_PASX_DISABLE_PIPE                      = 0x1,
990 	PERF_PAPC_PASX_FIRST_VECTOR                      = 0x2,
991 	PERF_PAPC_PASX_SECOND_VECTOR                     = 0x3,
992 	PERF_PAPC_PASX_FIRST_DEAD                        = 0x4,
993 	PERF_PAPC_PASX_SECOND_DEAD                       = 0x5,
994 	PERF_PAPC_PASX_VTX_KILL_DISCARD                  = 0x6,
995 	PERF_PAPC_PASX_VTX_NAN_DISCARD                   = 0x7,
996 	PERF_PAPC_PA_INPUT_PRIM                          = 0x8,
997 	PERF_PAPC_PA_INPUT_NULL_PRIM                     = 0x9,
998 	PERF_PAPC_PA_INPUT_EVENT_FLAG                    = 0xa,
999 	PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT               = 0xb,
1000 	PERF_PAPC_PA_INPUT_END_OF_PACKET                 = 0xc,
1001 	PERF_PAPC_PA_INPUT_EXTENDED_EVENT                = 0xd,
1002 	PERF_PAPC_CLPR_CULL_PRIM                         = 0xe,
1003 	PERF_PAPC_CLPR_VVUCP_CULL_PRIM                   = 0xf,
1004 	PERF_PAPC_CLPR_VV_CULL_PRIM                      = 0x10,
1005 	PERF_PAPC_CLPR_UCP_CULL_PRIM                     = 0x11,
1006 	PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM                = 0x12,
1007 	PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM                 = 0x13,
1008 	PERF_PAPC_CLPR_CULL_TO_NULL_PRIM                 = 0x14,
1009 	PERF_PAPC_CLPR_VVUCP_CLIP_PRIM                   = 0x15,
1010 	PERF_PAPC_CLPR_VV_CLIP_PRIM                      = 0x16,
1011 	PERF_PAPC_CLPR_UCP_CLIP_PRIM                     = 0x17,
1012 	PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE              = 0x18,
1013 	PERF_PAPC_CLPR_CLIP_PLANE_CNT_1                  = 0x19,
1014 	PERF_PAPC_CLPR_CLIP_PLANE_CNT_2                  = 0x1a,
1015 	PERF_PAPC_CLPR_CLIP_PLANE_CNT_3                  = 0x1b,
1016 	PERF_PAPC_CLPR_CLIP_PLANE_CNT_4                  = 0x1c,
1017 	PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8                = 0x1d,
1018 	PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12               = 0x1e,
1019 	PERF_PAPC_CLPR_CLIP_PLANE_NEAR                   = 0x1f,
1020 	PERF_PAPC_CLPR_CLIP_PLANE_FAR                    = 0x20,
1021 	PERF_PAPC_CLPR_CLIP_PLANE_LEFT                   = 0x21,
1022 	PERF_PAPC_CLPR_CLIP_PLANE_RIGHT                  = 0x22,
1023 	PERF_PAPC_CLPR_CLIP_PLANE_TOP                    = 0x23,
1024 	PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM                 = 0x24,
1025 	PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM                = 0x25,
1026 	PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM             = 0x26,
1027 	PERF_PAPC_CLSM_NULL_PRIM                         = 0x27,
1028 	PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM              = 0x28,
1029 	PERF_PAPC_CLSM_CULL_TO_NULL_PRIM                 = 0x29,
1030 	PERF_PAPC_CLSM_OUT_PRIM_CNT_1                    = 0x2a,
1031 	PERF_PAPC_CLSM_OUT_PRIM_CNT_2                    = 0x2b,
1032 	PERF_PAPC_CLSM_OUT_PRIM_CNT_3                    = 0x2c,
1033 	PERF_PAPC_CLSM_OUT_PRIM_CNT_4                    = 0x2d,
1034 	PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8                  = 0x2e,
1035 	PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13                 = 0x2f,
1036 	PERF_PAPC_CLIPGA_VTE_KILL_PRIM                   = 0x30,
1037 	PERF_PAPC_SU_INPUT_PRIM                          = 0x31,
1038 	PERF_PAPC_SU_INPUT_CLIP_PRIM                     = 0x32,
1039 	PERF_PAPC_SU_INPUT_NULL_PRIM                     = 0x33,
1040 	PERF_PAPC_SU_INPUT_PRIM_DUAL                     = 0x34,
1041 	PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL                = 0x35,
1042 	PERF_PAPC_SU_ZERO_AREA_CULL_PRIM                 = 0x36,
1043 	PERF_PAPC_SU_BACK_FACE_CULL_PRIM                 = 0x37,
1044 	PERF_PAPC_SU_FRONT_FACE_CULL_PRIM                = 0x38,
1045 	PERF_PAPC_SU_POLYMODE_FACE_CULL                  = 0x39,
1046 	PERF_PAPC_SU_POLYMODE_BACK_CULL                  = 0x3a,
1047 	PERF_PAPC_SU_POLYMODE_FRONT_CULL                 = 0x3b,
1048 	PERF_PAPC_SU_POLYMODE_INVALID_FILL               = 0x3c,
1049 	PERF_PAPC_SU_OUTPUT_PRIM                         = 0x3d,
1050 	PERF_PAPC_SU_OUTPUT_CLIP_PRIM                    = 0x3e,
1051 	PERF_PAPC_SU_OUTPUT_NULL_PRIM                    = 0x3f,
1052 	PERF_PAPC_SU_OUTPUT_EVENT_FLAG                   = 0x40,
1053 	PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT              = 0x41,
1054 	PERF_PAPC_SU_OUTPUT_END_OF_PACKET                = 0x42,
1055 	PERF_PAPC_SU_OUTPUT_POLYMODE_FACE                = 0x43,
1056 	PERF_PAPC_SU_OUTPUT_POLYMODE_BACK                = 0x44,
1057 	PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT               = 0x45,
1058 	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE              = 0x46,
1059 	PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK              = 0x47,
1060 	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT             = 0x48,
1061 	PERF_PAPC_SU_OUTPUT_PRIM_DUAL                    = 0x49,
1062 	PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL               = 0x4a,
1063 	PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL                = 0x4b,
1064 	PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL           = 0x4c,
1065 	PERF_PAPC_PASX_REQ_IDLE                          = 0x4d,
1066 	PERF_PAPC_PASX_REQ_BUSY                          = 0x4e,
1067 	PERF_PAPC_PASX_REQ_STALLED                       = 0x4f,
1068 	PERF_PAPC_PASX_REC_IDLE                          = 0x50,
1069 	PERF_PAPC_PASX_REC_BUSY                          = 0x51,
1070 	PERF_PAPC_PASX_REC_STARVED_SX                    = 0x52,
1071 	PERF_PAPC_PASX_REC_STALLED                       = 0x53,
1072 	PERF_PAPC_PASX_REC_STALLED_POS_MEM               = 0x54,
1073 	PERF_PAPC_PASX_REC_STALLED_CCGSM_IN              = 0x55,
1074 	PERF_PAPC_CCGSM_IDLE                             = 0x56,
1075 	PERF_PAPC_CCGSM_BUSY                             = 0x57,
1076 	PERF_PAPC_CCGSM_STALLED                          = 0x58,
1077 	PERF_PAPC_CLPRIM_IDLE                            = 0x59,
1078 	PERF_PAPC_CLPRIM_BUSY                            = 0x5a,
1079 	PERF_PAPC_CLPRIM_STALLED                         = 0x5b,
1080 	PERF_PAPC_CLPRIM_STARVED_CCGSM                   = 0x5c,
1081 	PERF_PAPC_CLIPSM_IDLE                            = 0x5d,
1082 	PERF_PAPC_CLIPSM_BUSY                            = 0x5e,
1083 	PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH             = 0x5f,
1084 	PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ               = 0x60,
1085 	PERF_PAPC_CLIPSM_WAIT_CLIPGA                     = 0x61,
1086 	PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP             = 0x62,
1087 	PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM                 = 0x63,
1088 	PERF_PAPC_CLIPGA_IDLE                            = 0x64,
1089 	PERF_PAPC_CLIPGA_BUSY                            = 0x65,
1090 	PERF_PAPC_CLIPGA_STARVED_VTE_CLIP                = 0x66,
1091 	PERF_PAPC_CLIPGA_STALLED                         = 0x67,
1092 	PERF_PAPC_CLIP_IDLE                              = 0x68,
1093 	PERF_PAPC_CLIP_BUSY                              = 0x69,
1094 	PERF_PAPC_SU_IDLE                                = 0x6a,
1095 	PERF_PAPC_SU_BUSY                                = 0x6b,
1096 	PERF_PAPC_SU_STARVED_CLIP                        = 0x6c,
1097 	PERF_PAPC_SU_STALLED_SC                          = 0x6d,
1098 	PERF_PAPC_CL_DYN_SCLK_VLD                        = 0x6e,
1099 	PERF_PAPC_SU_DYN_SCLK_VLD                        = 0x6f,
1100 	PERF_PAPC_PA_REG_SCLK_VLD                        = 0x70,
1101 	PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL          = 0x71,
1102 	PERF_PAPC_PASX_SE0_REQ                           = 0x72,
1103 	PERF_PAPC_PASX_SE1_REQ                           = 0x73,
1104 	PERF_PAPC_PASX_SE0_FIRST_VECTOR                  = 0x74,
1105 	PERF_PAPC_PASX_SE0_SECOND_VECTOR                 = 0x75,
1106 	PERF_PAPC_PASX_SE1_FIRST_VECTOR                  = 0x76,
1107 	PERF_PAPC_PASX_SE1_SECOND_VECTOR                 = 0x77,
1108 	PERF_PAPC_SU_SE0_PRIM_FILTER_CULL                = 0x78,
1109 	PERF_PAPC_SU_SE1_PRIM_FILTER_CULL                = 0x79,
1110 	PERF_PAPC_SU_SE01_PRIM_FILTER_CULL               = 0x7a,
1111 	PERF_PAPC_SU_SE0_OUTPUT_PRIM                     = 0x7b,
1112 	PERF_PAPC_SU_SE1_OUTPUT_PRIM                     = 0x7c,
1113 	PERF_PAPC_SU_SE01_OUTPUT_PRIM                    = 0x7d,
1114 	PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM                = 0x7e,
1115 	PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM                = 0x7f,
1116 	PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM               = 0x80,
1117 	PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT          = 0x81,
1118 	PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT          = 0x82,
1119 	PERF_PAPC_SU_SE0_STALLED_SC                      = 0x83,
1120 	PERF_PAPC_SU_SE1_STALLED_SC                      = 0x84,
1121 	PERF_PAPC_SU_SE01_STALLED_SC                     = 0x85,
1122 	PERF_PAPC_CLSM_CLIPPING_PRIM                     = 0x86,
1123 	PERF_PAPC_SU_CULLED_PRIM                         = 0x87,
1124 	PERF_PAPC_SU_OUTPUT_EOPG                         = 0x88,
1125 	PERF_PAPC_SU_SE2_PRIM_FILTER_CULL                = 0x89,
1126 	PERF_PAPC_SU_SE3_PRIM_FILTER_CULL                = 0x8a,
1127 	PERF_PAPC_SU_SE2_OUTPUT_PRIM                     = 0x8b,
1128 	PERF_PAPC_SU_SE3_OUTPUT_PRIM                     = 0x8c,
1129 	PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM                = 0x8d,
1130 	PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM                = 0x8e,
1131 	PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET            = 0x8f,
1132 	PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET            = 0x90,
1133 	PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET            = 0x91,
1134 	PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET            = 0x92,
1135 	PERF_PAPC_SU_SE0_OUTPUT_EOPG                     = 0x93,
1136 	PERF_PAPC_SU_SE1_OUTPUT_EOPG                     = 0x94,
1137 	PERF_PAPC_SU_SE2_OUTPUT_EOPG                     = 0x95,
1138 	PERF_PAPC_SU_SE3_OUTPUT_EOPG                     = 0x96,
1139 	PERF_PAPC_SU_SE2_STALLED_SC                      = 0x97,
1140 	PERF_PAPC_SU_SE3_STALLED_SC                      = 0x98,
1141 } SU_PERFCNT_SEL;
1142 typedef enum SC_PERFCNT_SEL {
1143 	SC_SRPS_WINDOW_VALID                             = 0x0,
1144 	SC_PSSW_WINDOW_VALID                             = 0x1,
1145 	SC_TPQZ_WINDOW_VALID                             = 0x2,
1146 	SC_QZQP_WINDOW_VALID                             = 0x3,
1147 	SC_TRPK_WINDOW_VALID                             = 0x4,
1148 	SC_SRPS_WINDOW_VALID_BUSY                        = 0x5,
1149 	SC_PSSW_WINDOW_VALID_BUSY                        = 0x6,
1150 	SC_TPQZ_WINDOW_VALID_BUSY                        = 0x7,
1151 	SC_QZQP_WINDOW_VALID_BUSY                        = 0x8,
1152 	SC_TRPK_WINDOW_VALID_BUSY                        = 0x9,
1153 	SC_STARVED_BY_PA                                 = 0xa,
1154 	SC_STALLED_BY_PRIMFIFO                           = 0xb,
1155 	SC_STALLED_BY_DB_TILE                            = 0xc,
1156 	SC_STARVED_BY_DB_TILE                            = 0xd,
1157 	SC_STALLED_BY_TILEORDERFIFO                      = 0xe,
1158 	SC_STALLED_BY_TILEFIFO                           = 0xf,
1159 	SC_STALLED_BY_DB_QUAD                            = 0x10,
1160 	SC_STARVED_BY_DB_QUAD                            = 0x11,
1161 	SC_STALLED_BY_QUADFIFO                           = 0x12,
1162 	SC_STALLED_BY_BCI                                = 0x13,
1163 	SC_STALLED_BY_SPI                                = 0x14,
1164 	SC_SCISSOR_DISCARD                               = 0x15,
1165 	SC_BB_DISCARD                                    = 0x16,
1166 	SC_SUPERTILE_COUNT                               = 0x17,
1167 	SC_SUPERTILE_PER_PRIM_H0                         = 0x18,
1168 	SC_SUPERTILE_PER_PRIM_H1                         = 0x19,
1169 	SC_SUPERTILE_PER_PRIM_H2                         = 0x1a,
1170 	SC_SUPERTILE_PER_PRIM_H3                         = 0x1b,
1171 	SC_SUPERTILE_PER_PRIM_H4                         = 0x1c,
1172 	SC_SUPERTILE_PER_PRIM_H5                         = 0x1d,
1173 	SC_SUPERTILE_PER_PRIM_H6                         = 0x1e,
1174 	SC_SUPERTILE_PER_PRIM_H7                         = 0x1f,
1175 	SC_SUPERTILE_PER_PRIM_H8                         = 0x20,
1176 	SC_SUPERTILE_PER_PRIM_H9                         = 0x21,
1177 	SC_SUPERTILE_PER_PRIM_H10                        = 0x22,
1178 	SC_SUPERTILE_PER_PRIM_H11                        = 0x23,
1179 	SC_SUPERTILE_PER_PRIM_H12                        = 0x24,
1180 	SC_SUPERTILE_PER_PRIM_H13                        = 0x25,
1181 	SC_SUPERTILE_PER_PRIM_H14                        = 0x26,
1182 	SC_SUPERTILE_PER_PRIM_H15                        = 0x27,
1183 	SC_SUPERTILE_PER_PRIM_H16                        = 0x28,
1184 	SC_TILE_PER_PRIM_H0                              = 0x29,
1185 	SC_TILE_PER_PRIM_H1                              = 0x2a,
1186 	SC_TILE_PER_PRIM_H2                              = 0x2b,
1187 	SC_TILE_PER_PRIM_H3                              = 0x2c,
1188 	SC_TILE_PER_PRIM_H4                              = 0x2d,
1189 	SC_TILE_PER_PRIM_H5                              = 0x2e,
1190 	SC_TILE_PER_PRIM_H6                              = 0x2f,
1191 	SC_TILE_PER_PRIM_H7                              = 0x30,
1192 	SC_TILE_PER_PRIM_H8                              = 0x31,
1193 	SC_TILE_PER_PRIM_H9                              = 0x32,
1194 	SC_TILE_PER_PRIM_H10                             = 0x33,
1195 	SC_TILE_PER_PRIM_H11                             = 0x34,
1196 	SC_TILE_PER_PRIM_H12                             = 0x35,
1197 	SC_TILE_PER_PRIM_H13                             = 0x36,
1198 	SC_TILE_PER_PRIM_H14                             = 0x37,
1199 	SC_TILE_PER_PRIM_H15                             = 0x38,
1200 	SC_TILE_PER_PRIM_H16                             = 0x39,
1201 	SC_TILE_PER_SUPERTILE_H0                         = 0x3a,
1202 	SC_TILE_PER_SUPERTILE_H1                         = 0x3b,
1203 	SC_TILE_PER_SUPERTILE_H2                         = 0x3c,
1204 	SC_TILE_PER_SUPERTILE_H3                         = 0x3d,
1205 	SC_TILE_PER_SUPERTILE_H4                         = 0x3e,
1206 	SC_TILE_PER_SUPERTILE_H5                         = 0x3f,
1207 	SC_TILE_PER_SUPERTILE_H6                         = 0x40,
1208 	SC_TILE_PER_SUPERTILE_H7                         = 0x41,
1209 	SC_TILE_PER_SUPERTILE_H8                         = 0x42,
1210 	SC_TILE_PER_SUPERTILE_H9                         = 0x43,
1211 	SC_TILE_PER_SUPERTILE_H10                        = 0x44,
1212 	SC_TILE_PER_SUPERTILE_H11                        = 0x45,
1213 	SC_TILE_PER_SUPERTILE_H12                        = 0x46,
1214 	SC_TILE_PER_SUPERTILE_H13                        = 0x47,
1215 	SC_TILE_PER_SUPERTILE_H14                        = 0x48,
1216 	SC_TILE_PER_SUPERTILE_H15                        = 0x49,
1217 	SC_TILE_PER_SUPERTILE_H16                        = 0x4a,
1218 	SC_TILE_PICKED_H1                                = 0x4b,
1219 	SC_TILE_PICKED_H2                                = 0x4c,
1220 	SC_TILE_PICKED_H3                                = 0x4d,
1221 	SC_TILE_PICKED_H4                                = 0x4e,
1222 	SC_QZ0_MULTI_GPU_TILE_DISCARD                    = 0x4f,
1223 	SC_QZ1_MULTI_GPU_TILE_DISCARD                    = 0x50,
1224 	SC_QZ2_MULTI_GPU_TILE_DISCARD                    = 0x51,
1225 	SC_QZ3_MULTI_GPU_TILE_DISCARD                    = 0x52,
1226 	SC_QZ0_TILE_COUNT                                = 0x53,
1227 	SC_QZ1_TILE_COUNT                                = 0x54,
1228 	SC_QZ2_TILE_COUNT                                = 0x55,
1229 	SC_QZ3_TILE_COUNT                                = 0x56,
1230 	SC_QZ0_TILE_COVERED_COUNT                        = 0x57,
1231 	SC_QZ1_TILE_COVERED_COUNT                        = 0x58,
1232 	SC_QZ2_TILE_COVERED_COUNT                        = 0x59,
1233 	SC_QZ3_TILE_COVERED_COUNT                        = 0x5a,
1234 	SC_QZ0_TILE_NOT_COVERED_COUNT                    = 0x5b,
1235 	SC_QZ1_TILE_NOT_COVERED_COUNT                    = 0x5c,
1236 	SC_QZ2_TILE_NOT_COVERED_COUNT                    = 0x5d,
1237 	SC_QZ3_TILE_NOT_COVERED_COUNT                    = 0x5e,
1238 	SC_QZ0_QUAD_PER_TILE_H0                          = 0x5f,
1239 	SC_QZ0_QUAD_PER_TILE_H1                          = 0x60,
1240 	SC_QZ0_QUAD_PER_TILE_H2                          = 0x61,
1241 	SC_QZ0_QUAD_PER_TILE_H3                          = 0x62,
1242 	SC_QZ0_QUAD_PER_TILE_H4                          = 0x63,
1243 	SC_QZ0_QUAD_PER_TILE_H5                          = 0x64,
1244 	SC_QZ0_QUAD_PER_TILE_H6                          = 0x65,
1245 	SC_QZ0_QUAD_PER_TILE_H7                          = 0x66,
1246 	SC_QZ0_QUAD_PER_TILE_H8                          = 0x67,
1247 	SC_QZ0_QUAD_PER_TILE_H9                          = 0x68,
1248 	SC_QZ0_QUAD_PER_TILE_H10                         = 0x69,
1249 	SC_QZ0_QUAD_PER_TILE_H11                         = 0x6a,
1250 	SC_QZ0_QUAD_PER_TILE_H12                         = 0x6b,
1251 	SC_QZ0_QUAD_PER_TILE_H13                         = 0x6c,
1252 	SC_QZ0_QUAD_PER_TILE_H14                         = 0x6d,
1253 	SC_QZ0_QUAD_PER_TILE_H15                         = 0x6e,
1254 	SC_QZ0_QUAD_PER_TILE_H16                         = 0x6f,
1255 	SC_QZ1_QUAD_PER_TILE_H0                          = 0x70,
1256 	SC_QZ1_QUAD_PER_TILE_H1                          = 0x71,
1257 	SC_QZ1_QUAD_PER_TILE_H2                          = 0x72,
1258 	SC_QZ1_QUAD_PER_TILE_H3                          = 0x73,
1259 	SC_QZ1_QUAD_PER_TILE_H4                          = 0x74,
1260 	SC_QZ1_QUAD_PER_TILE_H5                          = 0x75,
1261 	SC_QZ1_QUAD_PER_TILE_H6                          = 0x76,
1262 	SC_QZ1_QUAD_PER_TILE_H7                          = 0x77,
1263 	SC_QZ1_QUAD_PER_TILE_H8                          = 0x78,
1264 	SC_QZ1_QUAD_PER_TILE_H9                          = 0x79,
1265 	SC_QZ1_QUAD_PER_TILE_H10                         = 0x7a,
1266 	SC_QZ1_QUAD_PER_TILE_H11                         = 0x7b,
1267 	SC_QZ1_QUAD_PER_TILE_H12                         = 0x7c,
1268 	SC_QZ1_QUAD_PER_TILE_H13                         = 0x7d,
1269 	SC_QZ1_QUAD_PER_TILE_H14                         = 0x7e,
1270 	SC_QZ1_QUAD_PER_TILE_H15                         = 0x7f,
1271 	SC_QZ1_QUAD_PER_TILE_H16                         = 0x80,
1272 	SC_QZ2_QUAD_PER_TILE_H0                          = 0x81,
1273 	SC_QZ2_QUAD_PER_TILE_H1                          = 0x82,
1274 	SC_QZ2_QUAD_PER_TILE_H2                          = 0x83,
1275 	SC_QZ2_QUAD_PER_TILE_H3                          = 0x84,
1276 	SC_QZ2_QUAD_PER_TILE_H4                          = 0x85,
1277 	SC_QZ2_QUAD_PER_TILE_H5                          = 0x86,
1278 	SC_QZ2_QUAD_PER_TILE_H6                          = 0x87,
1279 	SC_QZ2_QUAD_PER_TILE_H7                          = 0x88,
1280 	SC_QZ2_QUAD_PER_TILE_H8                          = 0x89,
1281 	SC_QZ2_QUAD_PER_TILE_H9                          = 0x8a,
1282 	SC_QZ2_QUAD_PER_TILE_H10                         = 0x8b,
1283 	SC_QZ2_QUAD_PER_TILE_H11                         = 0x8c,
1284 	SC_QZ2_QUAD_PER_TILE_H12                         = 0x8d,
1285 	SC_QZ2_QUAD_PER_TILE_H13                         = 0x8e,
1286 	SC_QZ2_QUAD_PER_TILE_H14                         = 0x8f,
1287 	SC_QZ2_QUAD_PER_TILE_H15                         = 0x90,
1288 	SC_QZ2_QUAD_PER_TILE_H16                         = 0x91,
1289 	SC_QZ3_QUAD_PER_TILE_H0                          = 0x92,
1290 	SC_QZ3_QUAD_PER_TILE_H1                          = 0x93,
1291 	SC_QZ3_QUAD_PER_TILE_H2                          = 0x94,
1292 	SC_QZ3_QUAD_PER_TILE_H3                          = 0x95,
1293 	SC_QZ3_QUAD_PER_TILE_H4                          = 0x96,
1294 	SC_QZ3_QUAD_PER_TILE_H5                          = 0x97,
1295 	SC_QZ3_QUAD_PER_TILE_H6                          = 0x98,
1296 	SC_QZ3_QUAD_PER_TILE_H7                          = 0x99,
1297 	SC_QZ3_QUAD_PER_TILE_H8                          = 0x9a,
1298 	SC_QZ3_QUAD_PER_TILE_H9                          = 0x9b,
1299 	SC_QZ3_QUAD_PER_TILE_H10                         = 0x9c,
1300 	SC_QZ3_QUAD_PER_TILE_H11                         = 0x9d,
1301 	SC_QZ3_QUAD_PER_TILE_H12                         = 0x9e,
1302 	SC_QZ3_QUAD_PER_TILE_H13                         = 0x9f,
1303 	SC_QZ3_QUAD_PER_TILE_H14                         = 0xa0,
1304 	SC_QZ3_QUAD_PER_TILE_H15                         = 0xa1,
1305 	SC_QZ3_QUAD_PER_TILE_H16                         = 0xa2,
1306 	SC_QZ0_QUAD_COUNT                                = 0xa3,
1307 	SC_QZ1_QUAD_COUNT                                = 0xa4,
1308 	SC_QZ2_QUAD_COUNT                                = 0xa5,
1309 	SC_QZ3_QUAD_COUNT                                = 0xa6,
1310 	SC_P0_HIZ_TILE_COUNT                             = 0xa7,
1311 	SC_P1_HIZ_TILE_COUNT                             = 0xa8,
1312 	SC_P2_HIZ_TILE_COUNT                             = 0xa9,
1313 	SC_P3_HIZ_TILE_COUNT                             = 0xaa,
1314 	SC_P0_HIZ_QUAD_PER_TILE_H0                       = 0xab,
1315 	SC_P0_HIZ_QUAD_PER_TILE_H1                       = 0xac,
1316 	SC_P0_HIZ_QUAD_PER_TILE_H2                       = 0xad,
1317 	SC_P0_HIZ_QUAD_PER_TILE_H3                       = 0xae,
1318 	SC_P0_HIZ_QUAD_PER_TILE_H4                       = 0xaf,
1319 	SC_P0_HIZ_QUAD_PER_TILE_H5                       = 0xb0,
1320 	SC_P0_HIZ_QUAD_PER_TILE_H6                       = 0xb1,
1321 	SC_P0_HIZ_QUAD_PER_TILE_H7                       = 0xb2,
1322 	SC_P0_HIZ_QUAD_PER_TILE_H8                       = 0xb3,
1323 	SC_P0_HIZ_QUAD_PER_TILE_H9                       = 0xb4,
1324 	SC_P0_HIZ_QUAD_PER_TILE_H10                      = 0xb5,
1325 	SC_P0_HIZ_QUAD_PER_TILE_H11                      = 0xb6,
1326 	SC_P0_HIZ_QUAD_PER_TILE_H12                      = 0xb7,
1327 	SC_P0_HIZ_QUAD_PER_TILE_H13                      = 0xb8,
1328 	SC_P0_HIZ_QUAD_PER_TILE_H14                      = 0xb9,
1329 	SC_P0_HIZ_QUAD_PER_TILE_H15                      = 0xba,
1330 	SC_P0_HIZ_QUAD_PER_TILE_H16                      = 0xbb,
1331 	SC_P1_HIZ_QUAD_PER_TILE_H0                       = 0xbc,
1332 	SC_P1_HIZ_QUAD_PER_TILE_H1                       = 0xbd,
1333 	SC_P1_HIZ_QUAD_PER_TILE_H2                       = 0xbe,
1334 	SC_P1_HIZ_QUAD_PER_TILE_H3                       = 0xbf,
1335 	SC_P1_HIZ_QUAD_PER_TILE_H4                       = 0xc0,
1336 	SC_P1_HIZ_QUAD_PER_TILE_H5                       = 0xc1,
1337 	SC_P1_HIZ_QUAD_PER_TILE_H6                       = 0xc2,
1338 	SC_P1_HIZ_QUAD_PER_TILE_H7                       = 0xc3,
1339 	SC_P1_HIZ_QUAD_PER_TILE_H8                       = 0xc4,
1340 	SC_P1_HIZ_QUAD_PER_TILE_H9                       = 0xc5,
1341 	SC_P1_HIZ_QUAD_PER_TILE_H10                      = 0xc6,
1342 	SC_P1_HIZ_QUAD_PER_TILE_H11                      = 0xc7,
1343 	SC_P1_HIZ_QUAD_PER_TILE_H12                      = 0xc8,
1344 	SC_P1_HIZ_QUAD_PER_TILE_H13                      = 0xc9,
1345 	SC_P1_HIZ_QUAD_PER_TILE_H14                      = 0xca,
1346 	SC_P1_HIZ_QUAD_PER_TILE_H15                      = 0xcb,
1347 	SC_P1_HIZ_QUAD_PER_TILE_H16                      = 0xcc,
1348 	SC_P2_HIZ_QUAD_PER_TILE_H0                       = 0xcd,
1349 	SC_P2_HIZ_QUAD_PER_TILE_H1                       = 0xce,
1350 	SC_P2_HIZ_QUAD_PER_TILE_H2                       = 0xcf,
1351 	SC_P2_HIZ_QUAD_PER_TILE_H3                       = 0xd0,
1352 	SC_P2_HIZ_QUAD_PER_TILE_H4                       = 0xd1,
1353 	SC_P2_HIZ_QUAD_PER_TILE_H5                       = 0xd2,
1354 	SC_P2_HIZ_QUAD_PER_TILE_H6                       = 0xd3,
1355 	SC_P2_HIZ_QUAD_PER_TILE_H7                       = 0xd4,
1356 	SC_P2_HIZ_QUAD_PER_TILE_H8                       = 0xd5,
1357 	SC_P2_HIZ_QUAD_PER_TILE_H9                       = 0xd6,
1358 	SC_P2_HIZ_QUAD_PER_TILE_H10                      = 0xd7,
1359 	SC_P2_HIZ_QUAD_PER_TILE_H11                      = 0xd8,
1360 	SC_P2_HIZ_QUAD_PER_TILE_H12                      = 0xd9,
1361 	SC_P2_HIZ_QUAD_PER_TILE_H13                      = 0xda,
1362 	SC_P2_HIZ_QUAD_PER_TILE_H14                      = 0xdb,
1363 	SC_P2_HIZ_QUAD_PER_TILE_H15                      = 0xdc,
1364 	SC_P2_HIZ_QUAD_PER_TILE_H16                      = 0xdd,
1365 	SC_P3_HIZ_QUAD_PER_TILE_H0                       = 0xde,
1366 	SC_P3_HIZ_QUAD_PER_TILE_H1                       = 0xdf,
1367 	SC_P3_HIZ_QUAD_PER_TILE_H2                       = 0xe0,
1368 	SC_P3_HIZ_QUAD_PER_TILE_H3                       = 0xe1,
1369 	SC_P3_HIZ_QUAD_PER_TILE_H4                       = 0xe2,
1370 	SC_P3_HIZ_QUAD_PER_TILE_H5                       = 0xe3,
1371 	SC_P3_HIZ_QUAD_PER_TILE_H6                       = 0xe4,
1372 	SC_P3_HIZ_QUAD_PER_TILE_H7                       = 0xe5,
1373 	SC_P3_HIZ_QUAD_PER_TILE_H8                       = 0xe6,
1374 	SC_P3_HIZ_QUAD_PER_TILE_H9                       = 0xe7,
1375 	SC_P3_HIZ_QUAD_PER_TILE_H10                      = 0xe8,
1376 	SC_P3_HIZ_QUAD_PER_TILE_H11                      = 0xe9,
1377 	SC_P3_HIZ_QUAD_PER_TILE_H12                      = 0xea,
1378 	SC_P3_HIZ_QUAD_PER_TILE_H13                      = 0xeb,
1379 	SC_P3_HIZ_QUAD_PER_TILE_H14                      = 0xec,
1380 	SC_P3_HIZ_QUAD_PER_TILE_H15                      = 0xed,
1381 	SC_P3_HIZ_QUAD_PER_TILE_H16                      = 0xee,
1382 	SC_P0_HIZ_QUAD_COUNT                             = 0xef,
1383 	SC_P1_HIZ_QUAD_COUNT                             = 0xf0,
1384 	SC_P2_HIZ_QUAD_COUNT                             = 0xf1,
1385 	SC_P3_HIZ_QUAD_COUNT                             = 0xf2,
1386 	SC_P0_DETAIL_QUAD_COUNT                          = 0xf3,
1387 	SC_P1_DETAIL_QUAD_COUNT                          = 0xf4,
1388 	SC_P2_DETAIL_QUAD_COUNT                          = 0xf5,
1389 	SC_P3_DETAIL_QUAD_COUNT                          = 0xf6,
1390 	SC_P0_DETAIL_QUAD_WITH_1_PIX                     = 0xf7,
1391 	SC_P0_DETAIL_QUAD_WITH_2_PIX                     = 0xf8,
1392 	SC_P0_DETAIL_QUAD_WITH_3_PIX                     = 0xf9,
1393 	SC_P0_DETAIL_QUAD_WITH_4_PIX                     = 0xfa,
1394 	SC_P1_DETAIL_QUAD_WITH_1_PIX                     = 0xfb,
1395 	SC_P1_DETAIL_QUAD_WITH_2_PIX                     = 0xfc,
1396 	SC_P1_DETAIL_QUAD_WITH_3_PIX                     = 0xfd,
1397 	SC_P1_DETAIL_QUAD_WITH_4_PIX                     = 0xfe,
1398 	SC_P2_DETAIL_QUAD_WITH_1_PIX                     = 0xff,
1399 	SC_P2_DETAIL_QUAD_WITH_2_PIX                     = 0x100,
1400 	SC_P2_DETAIL_QUAD_WITH_3_PIX                     = 0x101,
1401 	SC_P2_DETAIL_QUAD_WITH_4_PIX                     = 0x102,
1402 	SC_P3_DETAIL_QUAD_WITH_1_PIX                     = 0x103,
1403 	SC_P3_DETAIL_QUAD_WITH_2_PIX                     = 0x104,
1404 	SC_P3_DETAIL_QUAD_WITH_3_PIX                     = 0x105,
1405 	SC_P3_DETAIL_QUAD_WITH_4_PIX                     = 0x106,
1406 	SC_EARLYZ_QUAD_COUNT                             = 0x107,
1407 	SC_EARLYZ_QUAD_WITH_1_PIX                        = 0x108,
1408 	SC_EARLYZ_QUAD_WITH_2_PIX                        = 0x109,
1409 	SC_EARLYZ_QUAD_WITH_3_PIX                        = 0x10a,
1410 	SC_EARLYZ_QUAD_WITH_4_PIX                        = 0x10b,
1411 	SC_PKR_QUAD_PER_ROW_H1                           = 0x10c,
1412 	SC_PKR_QUAD_PER_ROW_H2                           = 0x10d,
1413 	SC_PKR_QUAD_PER_ROW_H3                           = 0x10e,
1414 	SC_PKR_QUAD_PER_ROW_H4                           = 0x10f,
1415 	SC_PKR_END_OF_VECTOR                             = 0x110,
1416 	SC_PKR_CONTROL_XFER                              = 0x111,
1417 	SC_PKR_DBHANG_FORCE_EOV                          = 0x112,
1418 	SC_REG_SCLK_BUSY                                 = 0x113,
1419 	SC_GRP0_DYN_SCLK_BUSY                            = 0x114,
1420 	SC_GRP1_DYN_SCLK_BUSY                            = 0x115,
1421 	SC_GRP2_DYN_SCLK_BUSY                            = 0x116,
1422 	SC_GRP3_DYN_SCLK_BUSY                            = 0x117,
1423 	SC_GRP4_DYN_SCLK_BUSY                            = 0x118,
1424 	SC_PA0_SC_DATA_FIFO_RD                           = 0x119,
1425 	SC_PA0_SC_DATA_FIFO_WE                           = 0x11a,
1426 	SC_PA1_SC_DATA_FIFO_RD                           = 0x11b,
1427 	SC_PA1_SC_DATA_FIFO_WE                           = 0x11c,
1428 	SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES           = 0x11d,
1429 	SC_PS_ARB_XFC_ONLY_PRIM_CYCLES                   = 0x11e,
1430 	SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM              = 0x11f,
1431 	SC_PS_ARB_STALLED_FROM_BELOW                     = 0x120,
1432 	SC_PS_ARB_STARVED_FROM_ABOVE                     = 0x121,
1433 	SC_PS_ARB_SC_BUSY                                = 0x122,
1434 	SC_PS_ARB_PA_SC_BUSY                             = 0x123,
1435 	SC_PA2_SC_DATA_FIFO_RD                           = 0x124,
1436 	SC_PA2_SC_DATA_FIFO_WE                           = 0x125,
1437 	SC_PA3_SC_DATA_FIFO_RD                           = 0x126,
1438 	SC_PA3_SC_DATA_FIFO_WE                           = 0x127,
1439 	SC_PA_SC_DEALLOC_0_0_WE                          = 0x128,
1440 	SC_PA_SC_DEALLOC_0_1_WE                          = 0x129,
1441 	SC_PA_SC_DEALLOC_1_0_WE                          = 0x12a,
1442 	SC_PA_SC_DEALLOC_1_1_WE                          = 0x12b,
1443 	SC_PA_SC_DEALLOC_2_0_WE                          = 0x12c,
1444 	SC_PA_SC_DEALLOC_2_1_WE                          = 0x12d,
1445 	SC_PA_SC_DEALLOC_3_0_WE                          = 0x12e,
1446 	SC_PA_SC_DEALLOC_3_1_WE                          = 0x12f,
1447 	SC_PA0_SC_EOP_WE                                 = 0x130,
1448 	SC_PA0_SC_EOPG_WE                                = 0x131,
1449 	SC_PA0_SC_EVENT_WE                               = 0x132,
1450 	SC_PA1_SC_EOP_WE                                 = 0x133,
1451 	SC_PA1_SC_EOPG_WE                                = 0x134,
1452 	SC_PA1_SC_EVENT_WE                               = 0x135,
1453 	SC_PA2_SC_EOP_WE                                 = 0x136,
1454 	SC_PA2_SC_EOPG_WE                                = 0x137,
1455 	SC_PA2_SC_EVENT_WE                               = 0x138,
1456 	SC_PA3_SC_EOP_WE                                 = 0x139,
1457 	SC_PA3_SC_EOPG_WE                                = 0x13a,
1458 	SC_PA3_SC_EVENT_WE                               = 0x13b,
1459 	SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO   = 0x13c,
1460 	SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH                  = 0x13d,
1461 	SC_PS_ARB_NULL_PRIM_BUBBLE_POP                   = 0x13e,
1462 	SC_PS_ARB_EOP_POP_SYNC_POP                       = 0x13f,
1463 	SC_PS_ARB_EVENT_SYNC_POP                         = 0x140,
1464 	SC_SC_PS_ENG_MULTICYCLE_BUBBLE                   = 0x141,
1465 	SC_PA0_SC_FPOV_WE                                = 0x142,
1466 	SC_PA1_SC_FPOV_WE                                = 0x143,
1467 	SC_PA2_SC_FPOV_WE                                = 0x144,
1468 	SC_PA3_SC_FPOV_WE                                = 0x145,
1469 	SC_PA0_SC_LPOV_WE                                = 0x146,
1470 	SC_PA1_SC_LPOV_WE                                = 0x147,
1471 	SC_PA2_SC_LPOV_WE                                = 0x148,
1472 	SC_PA3_SC_LPOV_WE                                = 0x149,
1473 	SC_SC_SPI_DEALLOC_0_0                            = 0x14a,
1474 	SC_SC_SPI_DEALLOC_0_1                            = 0x14b,
1475 	SC_SC_SPI_DEALLOC_0_2                            = 0x14c,
1476 	SC_SC_SPI_DEALLOC_1_0                            = 0x14d,
1477 	SC_SC_SPI_DEALLOC_1_1                            = 0x14e,
1478 	SC_SC_SPI_DEALLOC_1_2                            = 0x14f,
1479 	SC_SC_SPI_DEALLOC_2_0                            = 0x150,
1480 	SC_SC_SPI_DEALLOC_2_1                            = 0x151,
1481 	SC_SC_SPI_DEALLOC_2_2                            = 0x152,
1482 	SC_SC_SPI_DEALLOC_3_0                            = 0x153,
1483 	SC_SC_SPI_DEALLOC_3_1                            = 0x154,
1484 	SC_SC_SPI_DEALLOC_3_2                            = 0x155,
1485 	SC_SC_SPI_FPOV_0                                 = 0x156,
1486 	SC_SC_SPI_FPOV_1                                 = 0x157,
1487 	SC_SC_SPI_FPOV_2                                 = 0x158,
1488 	SC_SC_SPI_FPOV_3                                 = 0x159,
1489 	SC_SC_SPI_EVENT                                  = 0x15a,
1490 	SC_PS_TS_EVENT_FIFO_PUSH                         = 0x15b,
1491 	SC_PS_TS_EVENT_FIFO_POP                          = 0x15c,
1492 	SC_PS_CTX_DONE_FIFO_PUSH                         = 0x15d,
1493 	SC_PS_CTX_DONE_FIFO_POP                          = 0x15e,
1494 	SC_MULTICYCLE_BUBBLE_FREEZE                      = 0x15f,
1495 	SC_EOP_SYNC_WINDOW                               = 0x160,
1496 	SC_PA0_SC_NULL_WE                                = 0x161,
1497 	SC_PA0_SC_NULL_DEALLOC_WE                        = 0x162,
1498 	SC_PA0_SC_DATA_FIFO_EOPG_RD                      = 0x163,
1499 	SC_PA0_SC_DATA_FIFO_EOP_RD                       = 0x164,
1500 	SC_PA0_SC_DEALLOC_0_RD                           = 0x165,
1501 	SC_PA0_SC_DEALLOC_1_RD                           = 0x166,
1502 	SC_PA1_SC_DATA_FIFO_EOPG_RD                      = 0x167,
1503 	SC_PA1_SC_DATA_FIFO_EOP_RD                       = 0x168,
1504 	SC_PA1_SC_DEALLOC_0_RD                           = 0x169,
1505 	SC_PA1_SC_DEALLOC_1_RD                           = 0x16a,
1506 	SC_PA1_SC_NULL_WE                                = 0x16b,
1507 	SC_PA1_SC_NULL_DEALLOC_WE                        = 0x16c,
1508 	SC_PA2_SC_DATA_FIFO_EOPG_RD                      = 0x16d,
1509 	SC_PA2_SC_DATA_FIFO_EOP_RD                       = 0x16e,
1510 	SC_PA2_SC_DEALLOC_0_RD                           = 0x16f,
1511 	SC_PA2_SC_DEALLOC_1_RD                           = 0x170,
1512 	SC_PA2_SC_NULL_WE                                = 0x171,
1513 	SC_PA2_SC_NULL_DEALLOC_WE                        = 0x172,
1514 	SC_PA3_SC_DATA_FIFO_EOPG_RD                      = 0x173,
1515 	SC_PA3_SC_DATA_FIFO_EOP_RD                       = 0x174,
1516 	SC_PA3_SC_DEALLOC_0_RD                           = 0x175,
1517 	SC_PA3_SC_DEALLOC_1_RD                           = 0x176,
1518 	SC_PA3_SC_NULL_WE                                = 0x177,
1519 	SC_PA3_SC_NULL_DEALLOC_WE                        = 0x178,
1520 	SC_PS_PA0_SC_FIFO_EMPTY                          = 0x179,
1521 	SC_PS_PA0_SC_FIFO_FULL                           = 0x17a,
1522 	SC_PA0_PS_DATA_SEND                              = 0x17b,
1523 	SC_PS_PA1_SC_FIFO_EMPTY                          = 0x17c,
1524 	SC_PS_PA1_SC_FIFO_FULL                           = 0x17d,
1525 	SC_PA1_PS_DATA_SEND                              = 0x17e,
1526 	SC_PS_PA2_SC_FIFO_EMPTY                          = 0x17f,
1527 	SC_PS_PA2_SC_FIFO_FULL                           = 0x180,
1528 	SC_PA2_PS_DATA_SEND                              = 0x181,
1529 	SC_PS_PA3_SC_FIFO_EMPTY                          = 0x182,
1530 	SC_PS_PA3_SC_FIFO_FULL                           = 0x183,
1531 	SC_PA3_PS_DATA_SEND                              = 0x184,
1532 	SC_BUSY_PROCESSING_MULTICYCLE_PRIM               = 0x185,
1533 	SC_BUSY_CNT_NOT_ZERO                             = 0x186,
1534 	SC_BM_BUSY                                       = 0x187,
1535 	SC_BACKEND_BUSY                                  = 0x188,
1536 	SC_SCF_SCB_INTERFACE_BUSY                        = 0x189,
1537 	SC_SCB_BUSY                                      = 0x18a,
1538 } SC_PERFCNT_SEL;
1539 typedef enum SePairXsel {
1540 	RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE           = 0x0,
1541 	RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE          = 0x1,
1542 	RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE          = 0x2,
1543 	RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE          = 0x3,
1544 } SePairXsel;
1545 typedef enum SePairYsel {
1546 	RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE           = 0x0,
1547 	RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE          = 0x1,
1548 	RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE          = 0x2,
1549 	RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE          = 0x3,
1550 } SePairYsel;
1551 typedef enum SePairMap {
1552 	RASTER_CONFIG_SE_PAIR_MAP_0                      = 0x0,
1553 	RASTER_CONFIG_SE_PAIR_MAP_1                      = 0x1,
1554 	RASTER_CONFIG_SE_PAIR_MAP_2                      = 0x2,
1555 	RASTER_CONFIG_SE_PAIR_MAP_3                      = 0x3,
1556 } SePairMap;
1557 typedef enum SeXsel {
1558 	RASTER_CONFIG_SE_XSEL_8_WIDE_TILE                = 0x0,
1559 	RASTER_CONFIG_SE_XSEL_16_WIDE_TILE               = 0x1,
1560 	RASTER_CONFIG_SE_XSEL_32_WIDE_TILE               = 0x2,
1561 	RASTER_CONFIG_SE_XSEL_64_WIDE_TILE               = 0x3,
1562 } SeXsel;
1563 typedef enum SeYsel {
1564 	RASTER_CONFIG_SE_YSEL_8_WIDE_TILE                = 0x0,
1565 	RASTER_CONFIG_SE_YSEL_16_WIDE_TILE               = 0x1,
1566 	RASTER_CONFIG_SE_YSEL_32_WIDE_TILE               = 0x2,
1567 	RASTER_CONFIG_SE_YSEL_64_WIDE_TILE               = 0x3,
1568 } SeYsel;
1569 typedef enum SeMap {
1570 	RASTER_CONFIG_SE_MAP_0                           = 0x0,
1571 	RASTER_CONFIG_SE_MAP_1                           = 0x1,
1572 	RASTER_CONFIG_SE_MAP_2                           = 0x2,
1573 	RASTER_CONFIG_SE_MAP_3                           = 0x3,
1574 } SeMap;
1575 typedef enum ScXsel {
1576 	RASTER_CONFIG_SC_XSEL_8_WIDE_TILE                = 0x0,
1577 	RASTER_CONFIG_SC_XSEL_16_WIDE_TILE               = 0x1,
1578 	RASTER_CONFIG_SC_XSEL_32_WIDE_TILE               = 0x2,
1579 	RASTER_CONFIG_SC_XSEL_64_WIDE_TILE               = 0x3,
1580 } ScXsel;
1581 typedef enum ScYsel {
1582 	RASTER_CONFIG_SC_YSEL_8_WIDE_TILE                = 0x0,
1583 	RASTER_CONFIG_SC_YSEL_16_WIDE_TILE               = 0x1,
1584 	RASTER_CONFIG_SC_YSEL_32_WIDE_TILE               = 0x2,
1585 	RASTER_CONFIG_SC_YSEL_64_WIDE_TILE               = 0x3,
1586 } ScYsel;
1587 typedef enum ScMap {
1588 	RASTER_CONFIG_SC_MAP_0                           = 0x0,
1589 	RASTER_CONFIG_SC_MAP_1                           = 0x1,
1590 	RASTER_CONFIG_SC_MAP_2                           = 0x2,
1591 	RASTER_CONFIG_SC_MAP_3                           = 0x3,
1592 } ScMap;
1593 typedef enum PkrXsel2 {
1594 	RASTER_CONFIG_PKR_XSEL2_0                        = 0x0,
1595 	RASTER_CONFIG_PKR_XSEL2_1                        = 0x1,
1596 	RASTER_CONFIG_PKR_XSEL2_2                        = 0x2,
1597 	RASTER_CONFIG_PKR_XSEL2_3                        = 0x3,
1598 } PkrXsel2;
1599 typedef enum PkrXsel {
1600 	RASTER_CONFIG_PKR_XSEL_0                         = 0x0,
1601 	RASTER_CONFIG_PKR_XSEL_1                         = 0x1,
1602 	RASTER_CONFIG_PKR_XSEL_2                         = 0x2,
1603 	RASTER_CONFIG_PKR_XSEL_3                         = 0x3,
1604 } PkrXsel;
1605 typedef enum PkrYsel {
1606 	RASTER_CONFIG_PKR_YSEL_0                         = 0x0,
1607 	RASTER_CONFIG_PKR_YSEL_1                         = 0x1,
1608 	RASTER_CONFIG_PKR_YSEL_2                         = 0x2,
1609 	RASTER_CONFIG_PKR_YSEL_3                         = 0x3,
1610 } PkrYsel;
1611 typedef enum PkrMap {
1612 	RASTER_CONFIG_PKR_MAP_0                          = 0x0,
1613 	RASTER_CONFIG_PKR_MAP_1                          = 0x1,
1614 	RASTER_CONFIG_PKR_MAP_2                          = 0x2,
1615 	RASTER_CONFIG_PKR_MAP_3                          = 0x3,
1616 } PkrMap;
1617 typedef enum RbXsel {
1618 	RASTER_CONFIG_RB_XSEL_0                          = 0x0,
1619 	RASTER_CONFIG_RB_XSEL_1                          = 0x1,
1620 } RbXsel;
1621 typedef enum RbYsel {
1622 	RASTER_CONFIG_RB_YSEL_0                          = 0x0,
1623 	RASTER_CONFIG_RB_YSEL_1                          = 0x1,
1624 } RbYsel;
1625 typedef enum RbXsel2 {
1626 	RASTER_CONFIG_RB_XSEL2_0                         = 0x0,
1627 	RASTER_CONFIG_RB_XSEL2_1                         = 0x1,
1628 	RASTER_CONFIG_RB_XSEL2_2                         = 0x2,
1629 	RASTER_CONFIG_RB_XSEL2_3                         = 0x3,
1630 } RbXsel2;
1631 typedef enum RbMap {
1632 	RASTER_CONFIG_RB_MAP_0                           = 0x0,
1633 	RASTER_CONFIG_RB_MAP_1                           = 0x1,
1634 	RASTER_CONFIG_RB_MAP_2                           = 0x2,
1635 	RASTER_CONFIG_RB_MAP_3                           = 0x3,
1636 } RbMap;
1637 typedef enum CSDATA_TYPE {
1638 	CSDATA_TYPE_TG                                   = 0x0,
1639 	CSDATA_TYPE_STATE                                = 0x1,
1640 	CSDATA_TYPE_EVENT                                = 0x2,
1641 	CSDATA_TYPE_PRIVATE                              = 0x3,
1642 } CSDATA_TYPE;
1643 #define CSDATA_TYPE_WIDTH                         0x2
1644 #define CSDATA_ADDR_WIDTH                         0x7
1645 #define CSDATA_DATA_WIDTH                         0x20
1646 typedef enum SPI_SAMPLE_CNTL {
1647 	CENTROIDS_ONLY                                   = 0x0,
1648 	CENTERS_ONLY                                     = 0x1,
1649 	CENTROIDS_AND_CENTERS                            = 0x2,
1650 	UNDEF                                            = 0x3,
1651 } SPI_SAMPLE_CNTL;
1652 typedef enum SPI_FOG_MODE {
1653 	SPI_FOG_NONE                                     = 0x0,
1654 	SPI_FOG_EXP                                      = 0x1,
1655 	SPI_FOG_EXP2                                     = 0x2,
1656 	SPI_FOG_LINEAR                                   = 0x3,
1657 } SPI_FOG_MODE;
1658 typedef enum SPI_PNT_SPRITE_OVERRIDE {
1659 	SPI_PNT_SPRITE_SEL_0                             = 0x0,
1660 	SPI_PNT_SPRITE_SEL_1                             = 0x1,
1661 	SPI_PNT_SPRITE_SEL_S                             = 0x2,
1662 	SPI_PNT_SPRITE_SEL_T                             = 0x3,
1663 	SPI_PNT_SPRITE_SEL_NONE                          = 0x4,
1664 } SPI_PNT_SPRITE_OVERRIDE;
1665 typedef enum SPI_PERFCNT_SEL {
1666 	SPI_PERF_VS_WINDOW_VALID                         = 0x0,
1667 	SPI_PERF_VS_BUSY                                 = 0x1,
1668 	SPI_PERF_VS_FIRST_WAVE                           = 0x2,
1669 	SPI_PERF_VS_LAST_WAVE                            = 0x3,
1670 	SPI_PERF_VS_LSHS_DEALLOC                         = 0x4,
1671 	SPI_PERF_VS_PC_STALL                             = 0x5,
1672 	SPI_PERF_VS_POS0_STALL                           = 0x6,
1673 	SPI_PERF_VS_POS1_STALL                           = 0x7,
1674 	SPI_PERF_VS_CRAWLER_STALL                        = 0x8,
1675 	SPI_PERF_VS_EVENT_WAVE                           = 0x9,
1676 	SPI_PERF_VS_WAVE                                 = 0xa,
1677 	SPI_PERF_VS_PERS_UPD_FULL0                       = 0xb,
1678 	SPI_PERF_VS_PERS_UPD_FULL1                       = 0xc,
1679 	SPI_PERF_VS_LATE_ALLOC_FULL                      = 0xd,
1680 	SPI_PERF_VS_FIRST_SUBGRP                         = 0xe,
1681 	SPI_PERF_VS_LAST_SUBGRP                          = 0xf,
1682 	SPI_PERF_GS_WINDOW_VALID                         = 0x10,
1683 	SPI_PERF_GS_BUSY                                 = 0x11,
1684 	SPI_PERF_GS_CRAWLER_STALL                        = 0x12,
1685 	SPI_PERF_GS_EVENT_WAVE                           = 0x13,
1686 	SPI_PERF_GS_WAVE                                 = 0x14,
1687 	SPI_PERF_GS_PERS_UPD_FULL0                       = 0x15,
1688 	SPI_PERF_GS_PERS_UPD_FULL1                       = 0x16,
1689 	SPI_PERF_GS_FIRST_SUBGRP                         = 0x17,
1690 	SPI_PERF_GS_LAST_SUBGRP                          = 0x18,
1691 	SPI_PERF_ES_WINDOW_VALID                         = 0x19,
1692 	SPI_PERF_ES_BUSY                                 = 0x1a,
1693 	SPI_PERF_ES_CRAWLER_STALL                        = 0x1b,
1694 	SPI_PERF_ES_FIRST_WAVE                           = 0x1c,
1695 	SPI_PERF_ES_LAST_WAVE                            = 0x1d,
1696 	SPI_PERF_ES_LSHS_DEALLOC                         = 0x1e,
1697 	SPI_PERF_ES_EVENT_WAVE                           = 0x1f,
1698 	SPI_PERF_ES_WAVE                                 = 0x20,
1699 	SPI_PERF_ES_PERS_UPD_FULL0                       = 0x21,
1700 	SPI_PERF_ES_PERS_UPD_FULL1                       = 0x22,
1701 	SPI_PERF_ES_FIRST_SUBGRP                         = 0x23,
1702 	SPI_PERF_ES_LAST_SUBGRP                          = 0x24,
1703 	SPI_PERF_HS_WINDOW_VALID                         = 0x25,
1704 	SPI_PERF_HS_BUSY                                 = 0x26,
1705 	SPI_PERF_HS_CRAWLER_STALL                        = 0x27,
1706 	SPI_PERF_HS_FIRST_WAVE                           = 0x28,
1707 	SPI_PERF_HS_LAST_WAVE                            = 0x29,
1708 	SPI_PERF_HS_LSHS_DEALLOC                         = 0x2a,
1709 	SPI_PERF_HS_EVENT_WAVE                           = 0x2b,
1710 	SPI_PERF_HS_WAVE                                 = 0x2c,
1711 	SPI_PERF_HS_PERS_UPD_FULL0                       = 0x2d,
1712 	SPI_PERF_HS_PERS_UPD_FULL1                       = 0x2e,
1713 	SPI_PERF_LS_WINDOW_VALID                         = 0x2f,
1714 	SPI_PERF_LS_BUSY                                 = 0x30,
1715 	SPI_PERF_LS_CRAWLER_STALL                        = 0x31,
1716 	SPI_PERF_LS_FIRST_WAVE                           = 0x32,
1717 	SPI_PERF_LS_LAST_WAVE                            = 0x33,
1718 	SPI_PERF_OFFCHIP_LDS_STALL_LS                    = 0x34,
1719 	SPI_PERF_LS_EVENT_WAVE                           = 0x35,
1720 	SPI_PERF_LS_WAVE                                 = 0x36,
1721 	SPI_PERF_LS_PERS_UPD_FULL0                       = 0x37,
1722 	SPI_PERF_LS_PERS_UPD_FULL1                       = 0x38,
1723 	SPI_PERF_CSG_WINDOW_VALID                        = 0x39,
1724 	SPI_PERF_CSG_BUSY                                = 0x3a,
1725 	SPI_PERF_CSG_NUM_THREADGROUPS                    = 0x3b,
1726 	SPI_PERF_CSG_CRAWLER_STALL                       = 0x3c,
1727 	SPI_PERF_CSG_EVENT_WAVE                          = 0x3d,
1728 	SPI_PERF_CSG_WAVE                                = 0x3e,
1729 	SPI_PERF_CSN_WINDOW_VALID                        = 0x3f,
1730 	SPI_PERF_CSN_BUSY                                = 0x40,
1731 	SPI_PERF_CSN_NUM_THREADGROUPS                    = 0x41,
1732 	SPI_PERF_CSN_CRAWLER_STALL                       = 0x42,
1733 	SPI_PERF_CSN_EVENT_WAVE                          = 0x43,
1734 	SPI_PERF_CSN_WAVE                                = 0x44,
1735 	SPI_PERF_PS_CTL_WINDOW_VALID                     = 0x45,
1736 	SPI_PERF_PS_CTL_BUSY                             = 0x46,
1737 	SPI_PERF_PS_CTL_ACTIVE                           = 0x47,
1738 	SPI_PERF_PS_CTL_DEALLOC_BIN0                     = 0x48,
1739 	SPI_PERF_PS_CTL_FPOS_BIN1_STALL                  = 0x49,
1740 	SPI_PERF_PS_CTL_EVENT_WAVE                       = 0x4a,
1741 	SPI_PERF_PS_CTL_WAVE                             = 0x4b,
1742 	SPI_PERF_PS_CTL_OPT_WAVE                         = 0x4c,
1743 	SPI_PERF_PS_CTL_PASS_BIN0                        = 0x4d,
1744 	SPI_PERF_PS_CTL_PASS_BIN1                        = 0x4e,
1745 	SPI_PERF_PS_CTL_FPOS_BIN2                        = 0x4f,
1746 	SPI_PERF_PS_CTL_PRIM_BIN0                        = 0x50,
1747 	SPI_PERF_PS_CTL_PRIM_BIN1                        = 0x51,
1748 	SPI_PERF_PS_CTL_CNF_BIN2                         = 0x52,
1749 	SPI_PERF_PS_CTL_CNF_BIN3                         = 0x53,
1750 	SPI_PERF_PS_CTL_CRAWLER_STALL                    = 0x54,
1751 	SPI_PERF_PS_CTL_LDS_RES_FULL                     = 0x55,
1752 	SPI_PERF_PS_PERS_UPD_FULL0                       = 0x56,
1753 	SPI_PERF_PS_PERS_UPD_FULL1                       = 0x57,
1754 	SPI_PERF_PIX_ALLOC_PEND_CNT                      = 0x58,
1755 	SPI_PERF_PIX_ALLOC_SCB_STALL                     = 0x59,
1756 	SPI_PERF_PIX_ALLOC_DB0_STALL                     = 0x5a,
1757 	SPI_PERF_PIX_ALLOC_DB1_STALL                     = 0x5b,
1758 	SPI_PERF_PIX_ALLOC_DB2_STALL                     = 0x5c,
1759 	SPI_PERF_PIX_ALLOC_DB3_STALL                     = 0x5d,
1760 	SPI_PERF_LDS0_PC_VALID                           = 0x5e,
1761 	SPI_PERF_LDS1_PC_VALID                           = 0x5f,
1762 	SPI_PERF_RA_PIPE_REQ_BIN2                        = 0x60,
1763 	SPI_PERF_RA_TASK_REQ_BIN3                        = 0x61,
1764 	SPI_PERF_RA_WR_CTL_FULL                          = 0x62,
1765 	SPI_PERF_RA_REQ_NO_ALLOC                         = 0x63,
1766 	SPI_PERF_RA_REQ_NO_ALLOC_PS                      = 0x64,
1767 	SPI_PERF_RA_REQ_NO_ALLOC_VS                      = 0x65,
1768 	SPI_PERF_RA_REQ_NO_ALLOC_GS                      = 0x66,
1769 	SPI_PERF_RA_REQ_NO_ALLOC_ES                      = 0x67,
1770 	SPI_PERF_RA_REQ_NO_ALLOC_HS                      = 0x68,
1771 	SPI_PERF_RA_REQ_NO_ALLOC_LS                      = 0x69,
1772 	SPI_PERF_RA_REQ_NO_ALLOC_CSG                     = 0x6a,
1773 	SPI_PERF_RA_REQ_NO_ALLOC_CSN                     = 0x6b,
1774 	SPI_PERF_RA_RES_STALL_PS                         = 0x6c,
1775 	SPI_PERF_RA_RES_STALL_VS                         = 0x6d,
1776 	SPI_PERF_RA_RES_STALL_GS                         = 0x6e,
1777 	SPI_PERF_RA_RES_STALL_ES                         = 0x6f,
1778 	SPI_PERF_RA_RES_STALL_HS                         = 0x70,
1779 	SPI_PERF_RA_RES_STALL_LS                         = 0x71,
1780 	SPI_PERF_RA_RES_STALL_CSG                        = 0x72,
1781 	SPI_PERF_RA_RES_STALL_CSN                        = 0x73,
1782 	SPI_PERF_RA_TMP_STALL_PS                         = 0x74,
1783 	SPI_PERF_RA_TMP_STALL_VS                         = 0x75,
1784 	SPI_PERF_RA_TMP_STALL_GS                         = 0x76,
1785 	SPI_PERF_RA_TMP_STALL_ES                         = 0x77,
1786 	SPI_PERF_RA_TMP_STALL_HS                         = 0x78,
1787 	SPI_PERF_RA_TMP_STALL_LS                         = 0x79,
1788 	SPI_PERF_RA_TMP_STALL_CSG                        = 0x7a,
1789 	SPI_PERF_RA_TMP_STALL_CSN                        = 0x7b,
1790 	SPI_PERF_RA_WAVE_SIMD_FULL_PS                    = 0x7c,
1791 	SPI_PERF_RA_WAVE_SIMD_FULL_VS                    = 0x7d,
1792 	SPI_PERF_RA_WAVE_SIMD_FULL_GS                    = 0x7e,
1793 	SPI_PERF_RA_WAVE_SIMD_FULL_ES                    = 0x7f,
1794 	SPI_PERF_RA_WAVE_SIMD_FULL_HS                    = 0x80,
1795 	SPI_PERF_RA_WAVE_SIMD_FULL_LS                    = 0x81,
1796 	SPI_PERF_RA_WAVE_SIMD_FULL_CSG                   = 0x82,
1797 	SPI_PERF_RA_WAVE_SIMD_FULL_CSN                   = 0x83,
1798 	SPI_PERF_RA_VGPR_SIMD_FULL_PS                    = 0x84,
1799 	SPI_PERF_RA_VGPR_SIMD_FULL_VS                    = 0x85,
1800 	SPI_PERF_RA_VGPR_SIMD_FULL_GS                    = 0x86,
1801 	SPI_PERF_RA_VGPR_SIMD_FULL_ES                    = 0x87,
1802 	SPI_PERF_RA_VGPR_SIMD_FULL_HS                    = 0x88,
1803 	SPI_PERF_RA_VGPR_SIMD_FULL_LS                    = 0x89,
1804 	SPI_PERF_RA_VGPR_SIMD_FULL_CSG                   = 0x8a,
1805 	SPI_PERF_RA_VGPR_SIMD_FULL_CSN                   = 0x8b,
1806 	SPI_PERF_RA_SGPR_SIMD_FULL_PS                    = 0x8c,
1807 	SPI_PERF_RA_SGPR_SIMD_FULL_VS                    = 0x8d,
1808 	SPI_PERF_RA_SGPR_SIMD_FULL_GS                    = 0x8e,
1809 	SPI_PERF_RA_SGPR_SIMD_FULL_ES                    = 0x8f,
1810 	SPI_PERF_RA_SGPR_SIMD_FULL_HS                    = 0x90,
1811 	SPI_PERF_RA_SGPR_SIMD_FULL_LS                    = 0x91,
1812 	SPI_PERF_RA_SGPR_SIMD_FULL_CSG                   = 0x92,
1813 	SPI_PERF_RA_SGPR_SIMD_FULL_CSN                   = 0x93,
1814 	SPI_PERF_RA_LDS_CU_FULL_PS                       = 0x94,
1815 	SPI_PERF_RA_LDS_CU_FULL_LS                       = 0x95,
1816 	SPI_PERF_RA_LDS_CU_FULL_ES                       = 0x96,
1817 	SPI_PERF_RA_LDS_CU_FULL_CSG                      = 0x97,
1818 	SPI_PERF_RA_LDS_CU_FULL_CSN                      = 0x98,
1819 	SPI_PERF_RA_BAR_CU_FULL_HS                       = 0x99,
1820 	SPI_PERF_RA_BAR_CU_FULL_CSG                      = 0x9a,
1821 	SPI_PERF_RA_BAR_CU_FULL_CSN                      = 0x9b,
1822 	SPI_PERF_RA_BULKY_CU_FULL_CSG                    = 0x9c,
1823 	SPI_PERF_RA_BULKY_CU_FULL_CSN                    = 0x9d,
1824 	SPI_PERF_RA_TGLIM_CU_FULL_CSG                    = 0x9e,
1825 	SPI_PERF_RA_TGLIM_CU_FULL_CSN                    = 0x9f,
1826 	SPI_PERF_RA_WVLIM_STALL_PS                       = 0xa0,
1827 	SPI_PERF_RA_WVLIM_STALL_VS                       = 0xa1,
1828 	SPI_PERF_RA_WVLIM_STALL_GS                       = 0xa2,
1829 	SPI_PERF_RA_WVLIM_STALL_ES                       = 0xa3,
1830 	SPI_PERF_RA_WVLIM_STALL_HS                       = 0xa4,
1831 	SPI_PERF_RA_WVLIM_STALL_LS                       = 0xa5,
1832 	SPI_PERF_RA_WVLIM_STALL_CSG                      = 0xa6,
1833 	SPI_PERF_RA_WVLIM_STALL_CSN                      = 0xa7,
1834 	SPI_PERF_RA_PS_LOCK                              = 0xa8,
1835 	SPI_PERF_RA_VS_LOCK                              = 0xa9,
1836 	SPI_PERF_RA_GS_LOCK                              = 0xaa,
1837 	SPI_PERF_RA_ES_LOCK                              = 0xab,
1838 	SPI_PERF_RA_HS_LOCK                              = 0xac,
1839 	SPI_PERF_RA_LS_LOCK                              = 0xad,
1840 	SPI_PERF_RA_CSG_LOCK                             = 0xae,
1841 	SPI_PERF_RA_CSN_LOCK                             = 0xaf,
1842 	SPI_PERF_RA_RSV_UPD                              = 0xb0,
1843 	SPI_PERF_EXP_ARB_COL_CNT                         = 0xb1,
1844 	SPI_PERF_EXP_ARB_PAR_CNT                         = 0xb2,
1845 	SPI_PERF_EXP_ARB_POS_CNT                         = 0xb3,
1846 	SPI_PERF_EXP_ARB_GDS_CNT                         = 0xb4,
1847 	SPI_PERF_CLKGATE_BUSY_STALL                      = 0xb5,
1848 	SPI_PERF_CLKGATE_ACTIVE_STALL                    = 0xb6,
1849 	SPI_PERF_CLKGATE_ALL_CLOCKS_ON                   = 0xb7,
1850 	SPI_PERF_CLKGATE_CGTT_DYN_ON                     = 0xb8,
1851 	SPI_PERF_CLKGATE_CGTT_REG_ON                     = 0xb9,
1852 } SPI_PERFCNT_SEL;
1853 typedef enum SPI_SHADER_FORMAT {
1854 	SPI_SHADER_NONE                                  = 0x0,
1855 	SPI_SHADER_1COMP                                 = 0x1,
1856 	SPI_SHADER_2COMP                                 = 0x2,
1857 	SPI_SHADER_4COMPRESS                             = 0x3,
1858 	SPI_SHADER_4COMP                                 = 0x4,
1859 } SPI_SHADER_FORMAT;
1860 typedef enum SPI_SHADER_EX_FORMAT {
1861 	SPI_SHADER_ZERO                                  = 0x0,
1862 	SPI_SHADER_32_R                                  = 0x1,
1863 	SPI_SHADER_32_GR                                 = 0x2,
1864 	SPI_SHADER_32_AR                                 = 0x3,
1865 	SPI_SHADER_FP16_ABGR                             = 0x4,
1866 	SPI_SHADER_UNORM16_ABGR                          = 0x5,
1867 	SPI_SHADER_SNORM16_ABGR                          = 0x6,
1868 	SPI_SHADER_UINT16_ABGR                           = 0x7,
1869 	SPI_SHADER_SINT16_ABGR                           = 0x8,
1870 	SPI_SHADER_32_ABGR                               = 0x9,
1871 } SPI_SHADER_EX_FORMAT;
1872 typedef enum CLKGATE_SM_MODE {
1873 	ON_SEQ                                           = 0x0,
1874 	OFF_SEQ                                          = 0x1,
1875 	PROG_SEQ                                         = 0x2,
1876 	READ_SEQ                                         = 0x3,
1877 	SM_MODE_RESERVED                                 = 0x4,
1878 } CLKGATE_SM_MODE;
1879 typedef enum CLKGATE_BASE_MODE {
1880 	MULT_8                                           = 0x0,
1881 	MULT_16                                          = 0x1,
1882 } CLKGATE_BASE_MODE;
1883 typedef enum SQ_TEX_CLAMP {
1884 	SQ_TEX_WRAP                                      = 0x0,
1885 	SQ_TEX_MIRROR                                    = 0x1,
1886 	SQ_TEX_CLAMP_LAST_TEXEL                          = 0x2,
1887 	SQ_TEX_MIRROR_ONCE_LAST_TEXEL                    = 0x3,
1888 	SQ_TEX_CLAMP_HALF_BORDER                         = 0x4,
1889 	SQ_TEX_MIRROR_ONCE_HALF_BORDER                   = 0x5,
1890 	SQ_TEX_CLAMP_BORDER                              = 0x6,
1891 	SQ_TEX_MIRROR_ONCE_BORDER                        = 0x7,
1892 } SQ_TEX_CLAMP;
1893 typedef enum SQ_TEX_XY_FILTER {
1894 	SQ_TEX_XY_FILTER_POINT                           = 0x0,
1895 	SQ_TEX_XY_FILTER_BILINEAR                        = 0x1,
1896 	SQ_TEX_XY_FILTER_ANISO_POINT                     = 0x2,
1897 	SQ_TEX_XY_FILTER_ANISO_BILINEAR                  = 0x3,
1898 } SQ_TEX_XY_FILTER;
1899 typedef enum SQ_TEX_Z_FILTER {
1900 	SQ_TEX_Z_FILTER_NONE                             = 0x0,
1901 	SQ_TEX_Z_FILTER_POINT                            = 0x1,
1902 	SQ_TEX_Z_FILTER_LINEAR                           = 0x2,
1903 } SQ_TEX_Z_FILTER;
1904 typedef enum SQ_TEX_MIP_FILTER {
1905 	SQ_TEX_MIP_FILTER_NONE                           = 0x0,
1906 	SQ_TEX_MIP_FILTER_POINT                          = 0x1,
1907 	SQ_TEX_MIP_FILTER_LINEAR                         = 0x2,
1908 } SQ_TEX_MIP_FILTER;
1909 typedef enum SQ_TEX_ANISO_RATIO {
1910 	SQ_TEX_ANISO_RATIO_1                             = 0x0,
1911 	SQ_TEX_ANISO_RATIO_2                             = 0x1,
1912 	SQ_TEX_ANISO_RATIO_4                             = 0x2,
1913 	SQ_TEX_ANISO_RATIO_8                             = 0x3,
1914 	SQ_TEX_ANISO_RATIO_16                            = 0x4,
1915 } SQ_TEX_ANISO_RATIO;
1916 typedef enum SQ_TEX_DEPTH_COMPARE {
1917 	SQ_TEX_DEPTH_COMPARE_NEVER                       = 0x0,
1918 	SQ_TEX_DEPTH_COMPARE_LESS                        = 0x1,
1919 	SQ_TEX_DEPTH_COMPARE_EQUAL                       = 0x2,
1920 	SQ_TEX_DEPTH_COMPARE_LESSEQUAL                   = 0x3,
1921 	SQ_TEX_DEPTH_COMPARE_GREATER                     = 0x4,
1922 	SQ_TEX_DEPTH_COMPARE_NOTEQUAL                    = 0x5,
1923 	SQ_TEX_DEPTH_COMPARE_GREATEREQUAL                = 0x6,
1924 	SQ_TEX_DEPTH_COMPARE_ALWAYS                      = 0x7,
1925 } SQ_TEX_DEPTH_COMPARE;
1926 typedef enum SQ_TEX_BORDER_COLOR {
1927 	SQ_TEX_BORDER_COLOR_TRANS_BLACK                  = 0x0,
1928 	SQ_TEX_BORDER_COLOR_OPAQUE_BLACK                 = 0x1,
1929 	SQ_TEX_BORDER_COLOR_OPAQUE_WHITE                 = 0x2,
1930 	SQ_TEX_BORDER_COLOR_REGISTER                     = 0x3,
1931 } SQ_TEX_BORDER_COLOR;
1932 typedef enum SQ_RSRC_BUF_TYPE {
1933 	SQ_RSRC_BUF                                      = 0x0,
1934 	SQ_RSRC_BUF_RSVD_1                               = 0x1,
1935 	SQ_RSRC_BUF_RSVD_2                               = 0x2,
1936 	SQ_RSRC_BUF_RSVD_3                               = 0x3,
1937 } SQ_RSRC_BUF_TYPE;
1938 typedef enum SQ_RSRC_IMG_TYPE {
1939 	SQ_RSRC_IMG_RSVD_0                               = 0x0,
1940 	SQ_RSRC_IMG_RSVD_1                               = 0x1,
1941 	SQ_RSRC_IMG_RSVD_2                               = 0x2,
1942 	SQ_RSRC_IMG_RSVD_3                               = 0x3,
1943 	SQ_RSRC_IMG_RSVD_4                               = 0x4,
1944 	SQ_RSRC_IMG_RSVD_5                               = 0x5,
1945 	SQ_RSRC_IMG_RSVD_6                               = 0x6,
1946 	SQ_RSRC_IMG_RSVD_7                               = 0x7,
1947 	SQ_RSRC_IMG_1D                                   = 0x8,
1948 	SQ_RSRC_IMG_2D                                   = 0x9,
1949 	SQ_RSRC_IMG_3D                                   = 0xa,
1950 	SQ_RSRC_IMG_CUBE                                 = 0xb,
1951 	SQ_RSRC_IMG_1D_ARRAY                             = 0xc,
1952 	SQ_RSRC_IMG_2D_ARRAY                             = 0xd,
1953 	SQ_RSRC_IMG_2D_MSAA                              = 0xe,
1954 	SQ_RSRC_IMG_2D_MSAA_ARRAY                        = 0xf,
1955 } SQ_RSRC_IMG_TYPE;
1956 typedef enum SQ_RSRC_FLAT_TYPE {
1957 	SQ_RSRC_FLAT_RSVD_0                              = 0x0,
1958 	SQ_RSRC_FLAT                                     = 0x1,
1959 	SQ_RSRC_FLAT_RSVD_2                              = 0x2,
1960 	SQ_RSRC_FLAT_RSVD_3                              = 0x3,
1961 } SQ_RSRC_FLAT_TYPE;
1962 typedef enum SQ_IMG_FILTER_TYPE {
1963 	SQ_IMG_FILTER_MODE_BLEND                         = 0x0,
1964 	SQ_IMG_FILTER_MODE_MIN                           = 0x1,
1965 	SQ_IMG_FILTER_MODE_MAX                           = 0x2,
1966 } SQ_IMG_FILTER_TYPE;
1967 typedef enum SQ_SEL_XYZW01 {
1968 	SQ_SEL_0                                         = 0x0,
1969 	SQ_SEL_1                                         = 0x1,
1970 	SQ_SEL_RESERVED_0                                = 0x2,
1971 	SQ_SEL_RESERVED_1                                = 0x3,
1972 	SQ_SEL_X                                         = 0x4,
1973 	SQ_SEL_Y                                         = 0x5,
1974 	SQ_SEL_Z                                         = 0x6,
1975 	SQ_SEL_W                                         = 0x7,
1976 } SQ_SEL_XYZW01;
1977 typedef enum SQ_WAVE_TYPE {
1978 	SQ_WAVE_TYPE_PS                                  = 0x0,
1979 	SQ_WAVE_TYPE_VS                                  = 0x1,
1980 	SQ_WAVE_TYPE_GS                                  = 0x2,
1981 	SQ_WAVE_TYPE_ES                                  = 0x3,
1982 	SQ_WAVE_TYPE_HS                                  = 0x4,
1983 	SQ_WAVE_TYPE_LS                                  = 0x5,
1984 	SQ_WAVE_TYPE_CS                                  = 0x6,
1985 	SQ_WAVE_TYPE_PS1                                 = 0x7,
1986 } SQ_WAVE_TYPE;
1987 typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
1988 	SQ_THREAD_TRACE_TOKEN_MISC                       = 0x0,
1989 	SQ_THREAD_TRACE_TOKEN_TIMESTAMP                  = 0x1,
1990 	SQ_THREAD_TRACE_TOKEN_REG                        = 0x2,
1991 	SQ_THREAD_TRACE_TOKEN_WAVE_START                 = 0x3,
1992 	SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC                 = 0x4,
1993 	SQ_THREAD_TRACE_TOKEN_REG_CSPRIV                 = 0x5,
1994 	SQ_THREAD_TRACE_TOKEN_WAVE_END                   = 0x6,
1995 	SQ_THREAD_TRACE_TOKEN_EVENT                      = 0x7,
1996 	SQ_THREAD_TRACE_TOKEN_EVENT_CS                   = 0x8,
1997 	SQ_THREAD_TRACE_TOKEN_EVENT_GFX1                 = 0x9,
1998 	SQ_THREAD_TRACE_TOKEN_INST                       = 0xa,
1999 	SQ_THREAD_TRACE_TOKEN_INST_PC                    = 0xb,
2000 	SQ_THREAD_TRACE_TOKEN_INST_USERDATA              = 0xc,
2001 	SQ_THREAD_TRACE_TOKEN_ISSUE                      = 0xd,
2002 	SQ_THREAD_TRACE_TOKEN_PERF                       = 0xe,
2003 	SQ_THREAD_TRACE_TOKEN_REG_CS                     = 0xf,
2004 } SQ_THREAD_TRACE_TOKEN_TYPE;
2005 typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
2006 	SQ_THREAD_TRACE_MISC_TOKEN_TIME                  = 0x0,
2007 	SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET            = 0x1,
2008 	SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST           = 0x2,
2009 	SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC             = 0x3,
2010 	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN    = 0x4,
2011 	SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END      = 0x5,
2012 } SQ_THREAD_TRACE_MISC_TOKEN_TYPE;
2013 typedef enum SQ_THREAD_TRACE_INST_TYPE {
2014 	SQ_THREAD_TRACE_INST_TYPE_SMEM                   = 0x0,
2015 	SQ_THREAD_TRACE_INST_TYPE_SALU                   = 0x1,
2016 	SQ_THREAD_TRACE_INST_TYPE_VMEM_RD                = 0x2,
2017 	SQ_THREAD_TRACE_INST_TYPE_VMEM_WR                = 0x3,
2018 	SQ_THREAD_TRACE_INST_TYPE_FLAT_WR                = 0x4,
2019 	SQ_THREAD_TRACE_INST_TYPE_VALU                   = 0x5,
2020 	SQ_THREAD_TRACE_INST_TYPE_LDS                    = 0x6,
2021 	SQ_THREAD_TRACE_INST_TYPE_PC                     = 0x7,
2022 	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS             = 0x8,
2023 	SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX             = 0x9,
2024 	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL         = 0xa,
2025 	SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS         = 0xb,
2026 	SQ_THREAD_TRACE_INST_TYPE_JUMP                   = 0xc,
2027 	SQ_THREAD_TRACE_INST_TYPE_NEXT                   = 0xd,
2028 	SQ_THREAD_TRACE_INST_TYPE_FLAT_RD                = 0xe,
2029 	SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG              = 0xf,
2030 } SQ_THREAD_TRACE_INST_TYPE;
2031 typedef enum SQ_THREAD_TRACE_REG_TYPE {
2032 	SQ_THREAD_TRACE_REG_TYPE_EVENT                   = 0x0,
2033 	SQ_THREAD_TRACE_REG_TYPE_DRAW                    = 0x1,
2034 	SQ_THREAD_TRACE_REG_TYPE_DISPATCH                = 0x2,
2035 	SQ_THREAD_TRACE_REG_TYPE_USERDATA                = 0x3,
2036 	SQ_THREAD_TRACE_REG_TYPE_MARKER                  = 0x4,
2037 	SQ_THREAD_TRACE_REG_TYPE_GFXDEC                  = 0x5,
2038 	SQ_THREAD_TRACE_REG_TYPE_SHDEC                   = 0x6,
2039 	SQ_THREAD_TRACE_REG_TYPE_OTHER                   = 0x7,
2040 } SQ_THREAD_TRACE_REG_TYPE;
2041 typedef enum SQ_THREAD_TRACE_REG_OP {
2042 	SQ_THREAD_TRACE_REG_OP_READ                      = 0x0,
2043 	SQ_THREAD_TRACE_REG_OP_WRITE                     = 0x1,
2044 } SQ_THREAD_TRACE_REG_OP;
2045 typedef enum SQ_THREAD_TRACE_MODE_SEL {
2046 	SQ_THREAD_TRACE_MODE_OFF                         = 0x0,
2047 	SQ_THREAD_TRACE_MODE_ON                          = 0x1,
2048 	SQ_THREAD_TRACE_MODE_RANDOM                      = 0x2,
2049 } SQ_THREAD_TRACE_MODE_SEL;
2050 typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
2051 	SQ_THREAD_TRACE_CAPTURE_MODE_ALL                 = 0x0,
2052 	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT              = 0x1,
2053 	SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL       = 0x2,
2054 } SQ_THREAD_TRACE_CAPTURE_MODE;
2055 typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
2056 	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE                = 0x0,
2057 	SQ_THREAD_TRACE_VM_ID_MASK_ALL                   = 0x1,
2058 	SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL         = 0x2,
2059 } SQ_THREAD_TRACE_VM_ID_MASK;
2060 typedef enum SQ_THREAD_TRACE_WAVE_MASK {
2061 	SQ_THREAD_TRACE_WAVE_MASK_NONE                   = 0x0,
2062 	SQ_THREAD_TRACE_WAVE_MASK_ALL                    = 0x1,
2063 	SQ_THREAD_TRACE_WAVE_MASK_1_2                    = 0x2,
2064 	SQ_THREAD_TRACE_WAVE_MASK_1_4                    = 0x3,
2065 	SQ_THREAD_TRACE_WAVE_MASK_1_8                    = 0x4,
2066 	SQ_THREAD_TRACE_WAVE_MASK_1_16                   = 0x5,
2067 	SQ_THREAD_TRACE_WAVE_MASK_1_32                   = 0x6,
2068 	SQ_THREAD_TRACE_WAVE_MASK_1_64                   = 0x7,
2069 } SQ_THREAD_TRACE_WAVE_MASK;
2070 typedef enum SQ_THREAD_TRACE_ISSUE {
2071 	SQ_THREAD_TRACE_ISSUE_NULL                       = 0x0,
2072 	SQ_THREAD_TRACE_ISSUE_STALL                      = 0x1,
2073 	SQ_THREAD_TRACE_ISSUE_INST                       = 0x2,
2074 	SQ_THREAD_TRACE_ISSUE_IMMED                      = 0x3,
2075 } SQ_THREAD_TRACE_ISSUE;
2076 typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
2077 	SQ_THREAD_TRACE_ISSUE_MASK_ALL                   = 0x0,
2078 	SQ_THREAD_TRACE_ISSUE_MASK_STALLED               = 0x1,
2079 	SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED     = 0x2,
2080 	SQ_THREAD_TRACE_ISSUE_MASK_IMMED                 = 0x3,
2081 } SQ_THREAD_TRACE_ISSUE_MASK;
2082 typedef enum SQ_PERF_SEL {
2083 	SQ_PERF_SEL_NONE                                 = 0x0,
2084 	SQ_PERF_SEL_ACCUM_PREV                           = 0x1,
2085 	SQ_PERF_SEL_CYCLES                               = 0x2,
2086 	SQ_PERF_SEL_BUSY_CYCLES                          = 0x3,
2087 	SQ_PERF_SEL_WAVES                                = 0x4,
2088 	SQ_PERF_SEL_LEVEL_WAVES                          = 0x5,
2089 	SQ_PERF_SEL_WAVES_EQ_64                          = 0x6,
2090 	SQ_PERF_SEL_WAVES_LT_64                          = 0x7,
2091 	SQ_PERF_SEL_WAVES_LT_48                          = 0x8,
2092 	SQ_PERF_SEL_WAVES_LT_32                          = 0x9,
2093 	SQ_PERF_SEL_WAVES_LT_16                          = 0xa,
2094 	SQ_PERF_SEL_WAVES_CU                             = 0xb,
2095 	SQ_PERF_SEL_LEVEL_WAVES_CU                       = 0xc,
2096 	SQ_PERF_SEL_BUSY_CU_CYCLES                       = 0xd,
2097 	SQ_PERF_SEL_ITEMS                                = 0xe,
2098 	SQ_PERF_SEL_QUADS                                = 0xf,
2099 	SQ_PERF_SEL_EVENTS                               = 0x10,
2100 	SQ_PERF_SEL_SURF_SYNCS                           = 0x11,
2101 	SQ_PERF_SEL_TTRACE_REQS                          = 0x12,
2102 	SQ_PERF_SEL_TTRACE_INFLIGHT_REQS                 = 0x13,
2103 	SQ_PERF_SEL_TTRACE_STALL                         = 0x14,
2104 	SQ_PERF_SEL_MSG_CNTR                             = 0x15,
2105 	SQ_PERF_SEL_MSG_PERF                             = 0x16,
2106 	SQ_PERF_SEL_MSG_GSCNT                            = 0x17,
2107 	SQ_PERF_SEL_MSG_INTERRUPT                        = 0x18,
2108 	SQ_PERF_SEL_INSTS                                = 0x19,
2109 	SQ_PERF_SEL_INSTS_VALU                           = 0x1a,
2110 	SQ_PERF_SEL_INSTS_VMEM_WR                        = 0x1b,
2111 	SQ_PERF_SEL_INSTS_VMEM_RD                        = 0x1c,
2112 	SQ_PERF_SEL_INSTS_VMEM                           = 0x1d,
2113 	SQ_PERF_SEL_INSTS_SALU                           = 0x1e,
2114 	SQ_PERF_SEL_INSTS_SMEM                           = 0x1f,
2115 	SQ_PERF_SEL_INSTS_FLAT                           = 0x20,
2116 	SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY                  = 0x21,
2117 	SQ_PERF_SEL_INSTS_LDS                            = 0x22,
2118 	SQ_PERF_SEL_INSTS_GDS                            = 0x23,
2119 	SQ_PERF_SEL_INSTS_EXP                            = 0x24,
2120 	SQ_PERF_SEL_INSTS_EXP_GDS                        = 0x25,
2121 	SQ_PERF_SEL_INSTS_BRANCH                         = 0x26,
2122 	SQ_PERF_SEL_INSTS_SENDMSG                        = 0x27,
2123 	SQ_PERF_SEL_INSTS_VSKIPPED                       = 0x28,
2124 	SQ_PERF_SEL_INST_LEVEL_VMEM                      = 0x29,
2125 	SQ_PERF_SEL_INST_LEVEL_SMEM                      = 0x2a,
2126 	SQ_PERF_SEL_INST_LEVEL_LDS                       = 0x2b,
2127 	SQ_PERF_SEL_INST_LEVEL_GDS                       = 0x2c,
2128 	SQ_PERF_SEL_INST_LEVEL_EXP                       = 0x2d,
2129 	SQ_PERF_SEL_WAVE_CYCLES                          = 0x2e,
2130 	SQ_PERF_SEL_WAVE_READY                           = 0x2f,
2131 	SQ_PERF_SEL_WAIT_CNT_VM                          = 0x30,
2132 	SQ_PERF_SEL_WAIT_CNT_LGKM                        = 0x31,
2133 	SQ_PERF_SEL_WAIT_CNT_EXP                         = 0x32,
2134 	SQ_PERF_SEL_WAIT_CNT_ANY                         = 0x33,
2135 	SQ_PERF_SEL_WAIT_BARRIER                         = 0x34,
2136 	SQ_PERF_SEL_WAIT_EXP_ALLOC                       = 0x35,
2137 	SQ_PERF_SEL_WAIT_SLEEP                           = 0x36,
2138 	SQ_PERF_SEL_WAIT_OTHER                           = 0x37,
2139 	SQ_PERF_SEL_WAIT_ANY                             = 0x38,
2140 	SQ_PERF_SEL_WAIT_TTRACE                          = 0x39,
2141 	SQ_PERF_SEL_WAIT_IFETCH                          = 0x3a,
2142 	SQ_PERF_SEL_WAIT_INST_VMEM                       = 0x3b,
2143 	SQ_PERF_SEL_WAIT_INST_SCA                        = 0x3c,
2144 	SQ_PERF_SEL_WAIT_INST_LDS                        = 0x3d,
2145 	SQ_PERF_SEL_WAIT_INST_VALU                       = 0x3e,
2146 	SQ_PERF_SEL_WAIT_INST_EXP_GDS                    = 0x3f,
2147 	SQ_PERF_SEL_WAIT_INST_MISC                       = 0x40,
2148 	SQ_PERF_SEL_WAIT_INST_FLAT                       = 0x41,
2149 	SQ_PERF_SEL_ACTIVE_INST_ANY                      = 0x42,
2150 	SQ_PERF_SEL_ACTIVE_INST_VMEM                     = 0x43,
2151 	SQ_PERF_SEL_ACTIVE_INST_LDS                      = 0x44,
2152 	SQ_PERF_SEL_ACTIVE_INST_VALU                     = 0x45,
2153 	SQ_PERF_SEL_ACTIVE_INST_SCA                      = 0x46,
2154 	SQ_PERF_SEL_ACTIVE_INST_EXP_GDS                  = 0x47,
2155 	SQ_PERF_SEL_ACTIVE_INST_MISC                     = 0x48,
2156 	SQ_PERF_SEL_ACTIVE_INST_FLAT                     = 0x49,
2157 	SQ_PERF_SEL_INST_CYCLES_VMEM_WR                  = 0x4a,
2158 	SQ_PERF_SEL_INST_CYCLES_VMEM_RD                  = 0x4b,
2159 	SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR                = 0x4c,
2160 	SQ_PERF_SEL_INST_CYCLES_VMEM_DATA                = 0x4d,
2161 	SQ_PERF_SEL_INST_CYCLES_VMEM_CMD                 = 0x4e,
2162 	SQ_PERF_SEL_INST_CYCLES_VMEM                     = 0x4f,
2163 	SQ_PERF_SEL_INST_CYCLES_LDS                      = 0x50,
2164 	SQ_PERF_SEL_INST_CYCLES_VALU                     = 0x51,
2165 	SQ_PERF_SEL_INST_CYCLES_EXP                      = 0x52,
2166 	SQ_PERF_SEL_INST_CYCLES_GDS                      = 0x53,
2167 	SQ_PERF_SEL_INST_CYCLES_SCA                      = 0x54,
2168 	SQ_PERF_SEL_INST_CYCLES_SMEM                     = 0x55,
2169 	SQ_PERF_SEL_INST_CYCLES_SALU                     = 0x56,
2170 	SQ_PERF_SEL_INST_CYCLES_EXP_GDS                  = 0x57,
2171 	SQ_PERF_SEL_INST_CYCLES_MISC                     = 0x58,
2172 	SQ_PERF_SEL_THREAD_CYCLES_VALU                   = 0x59,
2173 	SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX               = 0x5a,
2174 	SQ_PERF_SEL_IFETCH                               = 0x5b,
2175 	SQ_PERF_SEL_IFETCH_LEVEL                         = 0x5c,
2176 	SQ_PERF_SEL_CBRANCH_FORK                         = 0x5d,
2177 	SQ_PERF_SEL_CBRANCH_FORK_SPLIT                   = 0x5e,
2178 	SQ_PERF_SEL_VALU_LDS_DIRECT_RD                   = 0x5f,
2179 	SQ_PERF_SEL_VALU_LDS_INTERP_OP                   = 0x60,
2180 	SQ_PERF_SEL_LDS_BANK_CONFLICT                    = 0x61,
2181 	SQ_PERF_SEL_LDS_ADDR_CONFLICT                    = 0x62,
2182 	SQ_PERF_SEL_LDS_UNALIGNED_STALL                  = 0x63,
2183 	SQ_PERF_SEL_LDS_MEM_VIOLATIONS                   = 0x64,
2184 	SQ_PERF_SEL_LDS_ATOMIC_RETURN                    = 0x65,
2185 	SQ_PERF_SEL_LDS_IDX_ACTIVE                       = 0x66,
2186 	SQ_PERF_SEL_VALU_DEP_STALL                       = 0x67,
2187 	SQ_PERF_SEL_VALU_STARVE                          = 0x68,
2188 	SQ_PERF_SEL_EXP_REQ_FIFO_FULL                    = 0x69,
2189 	SQ_PERF_SEL_LDS_BACK2BACK_STALL                  = 0x6a,
2190 	SQ_PERF_SEL_LDS_DATA_FIFO_FULL                   = 0x6b,
2191 	SQ_PERF_SEL_LDS_CMD_FIFO_FULL                    = 0x6c,
2192 	SQ_PERF_SEL_VMEM_BACK2BACK_STALL                 = 0x6d,
2193 	SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL               = 0x6e,
2194 	SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL                = 0x6f,
2195 	SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY                = 0x70,
2196 	SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL              = 0x71,
2197 	SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL            = 0x72,
2198 	SQ_PERF_SEL_VALU_SRC_C_CONFLICT                  = 0x73,
2199 	SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT              = 0x74,
2200 	SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT              = 0x75,
2201 	SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT                 = 0x76,
2202 	SQ_PERF_SEL_LDS_SRC_CD_CONFLICT                  = 0x77,
2203 	SQ_PERF_SEL_SRC_CD_BUSY                          = 0x78,
2204 	SQ_PERF_SEL_PT_POWER_STALL                       = 0x79,
2205 	SQ_PERF_SEL_USER0                                = 0x7a,
2206 	SQ_PERF_SEL_USER1                                = 0x7b,
2207 	SQ_PERF_SEL_USER2                                = 0x7c,
2208 	SQ_PERF_SEL_USER3                                = 0x7d,
2209 	SQ_PERF_SEL_USER4                                = 0x7e,
2210 	SQ_PERF_SEL_USER5                                = 0x7f,
2211 	SQ_PERF_SEL_USER6                                = 0x80,
2212 	SQ_PERF_SEL_USER7                                = 0x81,
2213 	SQ_PERF_SEL_USER8                                = 0x82,
2214 	SQ_PERF_SEL_USER9                                = 0x83,
2215 	SQ_PERF_SEL_USER10                               = 0x84,
2216 	SQ_PERF_SEL_USER11                               = 0x85,
2217 	SQ_PERF_SEL_USER12                               = 0x86,
2218 	SQ_PERF_SEL_USER13                               = 0x87,
2219 	SQ_PERF_SEL_USER14                               = 0x88,
2220 	SQ_PERF_SEL_USER15                               = 0x89,
2221 	SQ_PERF_SEL_USER_LEVEL0                          = 0x8a,
2222 	SQ_PERF_SEL_USER_LEVEL1                          = 0x8b,
2223 	SQ_PERF_SEL_USER_LEVEL2                          = 0x8c,
2224 	SQ_PERF_SEL_USER_LEVEL3                          = 0x8d,
2225 	SQ_PERF_SEL_USER_LEVEL4                          = 0x8e,
2226 	SQ_PERF_SEL_USER_LEVEL5                          = 0x8f,
2227 	SQ_PERF_SEL_USER_LEVEL6                          = 0x90,
2228 	SQ_PERF_SEL_USER_LEVEL7                          = 0x91,
2229 	SQ_PERF_SEL_USER_LEVEL8                          = 0x92,
2230 	SQ_PERF_SEL_USER_LEVEL9                          = 0x93,
2231 	SQ_PERF_SEL_USER_LEVEL10                         = 0x94,
2232 	SQ_PERF_SEL_USER_LEVEL11                         = 0x95,
2233 	SQ_PERF_SEL_USER_LEVEL12                         = 0x96,
2234 	SQ_PERF_SEL_USER_LEVEL13                         = 0x97,
2235 	SQ_PERF_SEL_USER_LEVEL14                         = 0x98,
2236 	SQ_PERF_SEL_USER_LEVEL15                         = 0x99,
2237 	SQ_PERF_SEL_POWER_VALU                           = 0x9a,
2238 	SQ_PERF_SEL_POWER_VALU0                          = 0x9b,
2239 	SQ_PERF_SEL_POWER_VALU1                          = 0x9c,
2240 	SQ_PERF_SEL_POWER_VALU2                          = 0x9d,
2241 	SQ_PERF_SEL_POWER_GPR_RD                         = 0x9e,
2242 	SQ_PERF_SEL_POWER_GPR_WR                         = 0x9f,
2243 	SQ_PERF_SEL_POWER_LDS_BUSY                       = 0xa0,
2244 	SQ_PERF_SEL_POWER_ALU_BUSY                       = 0xa1,
2245 	SQ_PERF_SEL_POWER_TEX_BUSY                       = 0xa2,
2246 	SQ_PERF_SEL_ACCUM_PREV_HIRES                     = 0xa3,
2247 	SQ_PERF_SEL_DUMMY_LAST                           = 0xa7,
2248 	SQC_PERF_SEL_ICACHE_INPUT_VALID_READY            = 0xa8,
2249 	SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB           = 0xa9,
2250 	SQC_PERF_SEL_ICACHE_INPUT_VALIDB                 = 0xaa,
2251 	SQC_PERF_SEL_DCACHE_INPUT_VALID_READY            = 0xab,
2252 	SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB           = 0xac,
2253 	SQC_PERF_SEL_DCACHE_INPUT_VALIDB                 = 0xad,
2254 	SQC_PERF_SEL_TC_REQ                              = 0xae,
2255 	SQC_PERF_SEL_TC_INST_REQ                         = 0xaf,
2256 	SQC_PERF_SEL_TC_DATA_REQ                         = 0xb0,
2257 	SQC_PERF_SEL_TC_STALL                            = 0xb1,
2258 	SQC_PERF_SEL_TC_STARVE                           = 0xb2,
2259 	SQC_PERF_SEL_ICACHE_BUSY_CYCLES                  = 0xb3,
2260 	SQC_PERF_SEL_ICACHE_REQ                          = 0xb4,
2261 	SQC_PERF_SEL_ICACHE_HITS                         = 0xb5,
2262 	SQC_PERF_SEL_ICACHE_MISSES                       = 0xb6,
2263 	SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE             = 0xb7,
2264 	SQC_PERF_SEL_ICACHE_UNCACHED                     = 0xb8,
2265 	SQC_PERF_SEL_ICACHE_VOLATILE                     = 0xb9,
2266 	SQC_PERF_SEL_ICACHE_INVAL_INST                   = 0xba,
2267 	SQC_PERF_SEL_ICACHE_INVAL_ASYNC                  = 0xbb,
2268 	SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_INST          = 0xbc,
2269 	SQC_PERF_SEL_ICACHE_INVAL_VOLATILE_ASYNC         = 0xbd,
2270 	SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT     = 0xbe,
2271 	SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB      = 0xbf,
2272 	SQC_PERF_SEL_ICACHE_CACHE_STALLED                = 0xc0,
2273 	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xc1,
2274 	SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX     = 0xc2,
2275 	SQC_PERF_SEL_ICACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xc3,
2276 	SQC_PERF_SEL_ICACHE_CACHE_STALL_UNCACHED_HIT     = 0xc4,
2277 	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT           = 0xc5,
2278 	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc6,
2279 	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xc7,
2280 	SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xc8,
2281 	SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xc9,
2282 	SQC_PERF_SEL_DCACHE_BUSY_CYCLES                  = 0xca,
2283 	SQC_PERF_SEL_DCACHE_REQ                          = 0xcb,
2284 	SQC_PERF_SEL_DCACHE_HITS                         = 0xcc,
2285 	SQC_PERF_SEL_DCACHE_MISSES                       = 0xcd,
2286 	SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE             = 0xce,
2287 	SQC_PERF_SEL_DCACHE_UNCACHED                     = 0xcf,
2288 	SQC_PERF_SEL_DCACHE_VOLATILE                     = 0xd0,
2289 	SQC_PERF_SEL_DCACHE_INVAL_INST                   = 0xd1,
2290 	SQC_PERF_SEL_DCACHE_INVAL_ASYNC                  = 0xd2,
2291 	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST          = 0xd3,
2292 	SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC         = 0xd4,
2293 	SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT     = 0xd5,
2294 	SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB      = 0xd6,
2295 	SQC_PERF_SEL_DCACHE_CACHE_STALLED                = 0xd7,
2296 	SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xd8,
2297 	SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX     = 0xd9,
2298 	SQC_PERF_SEL_DCACHE_CACHE_STALL_VOLATILE_MISMATCH= 0xda,
2299 	SQC_PERF_SEL_DCACHE_CACHE_STALL_UNCACHED_HIT     = 0xdb,
2300 	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT           = 0xdc,
2301 	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xdd,
2302 	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO  = 0xde,
2303 	SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF     = 0xdf,
2304 	SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT   = 0xe0,
2305 	SQC_PERF_SEL_DCACHE_REQ_1                        = 0xe1,
2306 	SQC_PERF_SEL_DCACHE_REQ_2                        = 0xe2,
2307 	SQC_PERF_SEL_DCACHE_REQ_4                        = 0xe3,
2308 	SQC_PERF_SEL_DCACHE_REQ_8                        = 0xe4,
2309 	SQC_PERF_SEL_DCACHE_REQ_16                       = 0xe5,
2310 	SQC_PERF_SEL_DCACHE_REQ_TIME                     = 0xe6,
2311 	SQC_PERF_SEL_SQ_DCACHE_REQS                      = 0xe7,
2312 	SQC_PERF_SEL_DCACHE_FLAT_REQ                     = 0xe8,
2313 	SQC_PERF_SEL_DCACHE_NONFLAT_REQ                  = 0xe9,
2314 	SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL               = 0xea,
2315 	SQC_PERF_SEL_ICACHE_PRE_CC_LEVEL                 = 0xeb,
2316 	SQC_PERF_SEL_ICACHE_POST_CC_LEVEL                = 0xec,
2317 	SQC_PERF_SEL_ICACHE_POST_CC_HIT_LEVEL            = 0xed,
2318 	SQC_PERF_SEL_ICACHE_POST_CC_MISS_LEVEL           = 0xee,
2319 	SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL               = 0xef,
2320 	SQC_PERF_SEL_DCACHE_PRE_CC_LEVEL                 = 0xf0,
2321 	SQC_PERF_SEL_DCACHE_POST_CC_LEVEL                = 0xf1,
2322 	SQC_PERF_SEL_DCACHE_POST_CC_HIT_LEVEL            = 0xf2,
2323 	SQC_PERF_SEL_DCACHE_POST_CC_MISS_LEVEL           = 0xf3,
2324 	SQC_PERF_SEL_TC_INFLIGHT_LEVEL                   = 0xf4,
2325 	SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL            = 0xf5,
2326 	SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL            = 0xf6,
2327 	SQC_PERF_SEL_ERR_DCACHE_REQ_2_GPR_ADDR_UNALIGNED = 0xf7,
2328 	SQC_PERF_SEL_ERR_DCACHE_REQ_4_GPR_ADDR_UNALIGNED = 0xf8,
2329 	SQC_PERF_SEL_ERR_DCACHE_REQ_8_GPR_ADDR_UNALIGNED = 0xf9,
2330 	SQC_PERF_SEL_ERR_DCACHE_REQ_16_GPR_ADDR_UNALIGNED= 0xfa,
2331 	SQC_PERF_SEL_DUMMY_LAST                          = 0xfb,
2332 } SQ_PERF_SEL;
2333 typedef enum SQC_DATA_CACHE_POLICIES {
2334 	SQC_DATA_CACHE_POLICY_HIT_LRU                    = 0x0,
2335 	SQC_DATA_CACHE_POLICY_MISS_EVICT                 = 0x1,
2336 } SQC_DATA_CACHE_POLICIES;
2337 typedef enum SQ_CAC_POWER_SEL {
2338 	SQ_CAC_POWER_VALU                                = 0x0,
2339 	SQ_CAC_POWER_VALU0                               = 0x1,
2340 	SQ_CAC_POWER_VALU1                               = 0x2,
2341 	SQ_CAC_POWER_VALU2                               = 0x3,
2342 	SQ_CAC_POWER_GPR_RD                              = 0x4,
2343 	SQ_CAC_POWER_GPR_WR                              = 0x5,
2344 	SQ_CAC_POWER_LDS_BUSY                            = 0x6,
2345 	SQ_CAC_POWER_ALU_BUSY                            = 0x7,
2346 	SQ_CAC_POWER_TEX_BUSY                            = 0x8,
2347 } SQ_CAC_POWER_SEL;
2348 typedef enum SQ_IND_CMD_CMD {
2349 	SQ_IND_CMD_CMD_NULL                              = 0x0,
2350 	SQ_IND_CMD_CMD_HALT                              = 0x1,
2351 	SQ_IND_CMD_CMD_RESUME                            = 0x2,
2352 	SQ_IND_CMD_CMD_KILL                              = 0x3,
2353 	SQ_IND_CMD_CMD_DEBUG                             = 0x4,
2354 	SQ_IND_CMD_CMD_TRAP                              = 0x5,
2355 } SQ_IND_CMD_CMD;
2356 typedef enum SQ_IND_CMD_MODE {
2357 	SQ_IND_CMD_MODE_SINGLE                           = 0x0,
2358 	SQ_IND_CMD_MODE_BROADCAST                        = 0x1,
2359 	SQ_IND_CMD_MODE_BROADCAST_QUEUE                  = 0x2,
2360 	SQ_IND_CMD_MODE_BROADCAST_PIPE                   = 0x3,
2361 	SQ_IND_CMD_MODE_BROADCAST_ME                     = 0x4,
2362 } SQ_IND_CMD_MODE;
2363 typedef enum SQ_DED_INFO_SOURCE {
2364 	SQ_DED_INFO_SOURCE_INVALID                       = 0x0,
2365 	SQ_DED_INFO_SOURCE_INST                          = 0x1,
2366 	SQ_DED_INFO_SOURCE_SGPR                          = 0x2,
2367 	SQ_DED_INFO_SOURCE_VGPR                          = 0x3,
2368 	SQ_DED_INFO_SOURCE_LDS                           = 0x4,
2369 	SQ_DED_INFO_SOURCE_GDS                           = 0x5,
2370 	SQ_DED_INFO_SOURCE_TA                            = 0x6,
2371 } SQ_DED_INFO_SOURCE;
2372 typedef enum SQ_ROUND_MODE {
2373 	SQ_ROUND_NEAREST_EVEN                            = 0x0,
2374 	SQ_ROUND_PLUS_INFINITY                           = 0x1,
2375 	SQ_ROUND_MINUS_INFINITY                          = 0x2,
2376 	SQ_ROUND_TO_ZERO                                 = 0x3,
2377 } SQ_ROUND_MODE;
2378 typedef enum SQ_INTERRUPT_WORD_ENCODING {
2379 	SQ_INTERRUPT_WORD_ENCODING_AUTO                  = 0x0,
2380 	SQ_INTERRUPT_WORD_ENCODING_INST                  = 0x1,
2381 	SQ_INTERRUPT_WORD_ENCODING_ERROR                 = 0x2,
2382 } SQ_INTERRUPT_WORD_ENCODING;
2383 typedef enum ENUM_SQ_EXPORT_RAT_INST {
2384 	SQ_EXPORT_RAT_INST_NOP                           = 0x0,
2385 	SQ_EXPORT_RAT_INST_STORE_TYPED                   = 0x1,
2386 	SQ_EXPORT_RAT_INST_STORE_RAW                     = 0x2,
2387 	SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM             = 0x3,
2388 	SQ_EXPORT_RAT_INST_CMPXCHG_INT                   = 0x4,
2389 	SQ_EXPORT_RAT_INST_CMPXCHG_FLT                   = 0x5,
2390 	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM               = 0x6,
2391 	SQ_EXPORT_RAT_INST_ADD                           = 0x7,
2392 	SQ_EXPORT_RAT_INST_SUB                           = 0x8,
2393 	SQ_EXPORT_RAT_INST_RSUB                          = 0x9,
2394 	SQ_EXPORT_RAT_INST_MIN_INT                       = 0xa,
2395 	SQ_EXPORT_RAT_INST_MIN_UINT                      = 0xb,
2396 	SQ_EXPORT_RAT_INST_MAX_INT                       = 0xc,
2397 	SQ_EXPORT_RAT_INST_MAX_UINT                      = 0xd,
2398 	SQ_EXPORT_RAT_INST_AND                           = 0xe,
2399 	SQ_EXPORT_RAT_INST_OR                            = 0xf,
2400 	SQ_EXPORT_RAT_INST_XOR                           = 0x10,
2401 	SQ_EXPORT_RAT_INST_MSKOR                         = 0x11,
2402 	SQ_EXPORT_RAT_INST_INC_UINT                      = 0x12,
2403 	SQ_EXPORT_RAT_INST_DEC_UINT                      = 0x13,
2404 	SQ_EXPORT_RAT_INST_STORE_DWORD                   = 0x14,
2405 	SQ_EXPORT_RAT_INST_STORE_SHORT                   = 0x15,
2406 	SQ_EXPORT_RAT_INST_STORE_BYTE                    = 0x16,
2407 	SQ_EXPORT_RAT_INST_NOP_RTN                       = 0x20,
2408 	SQ_EXPORT_RAT_INST_XCHG_RTN                      = 0x22,
2409 	SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN              = 0x23,
2410 	SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN               = 0x24,
2411 	SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN               = 0x25,
2412 	SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN           = 0x26,
2413 	SQ_EXPORT_RAT_INST_ADD_RTN                       = 0x27,
2414 	SQ_EXPORT_RAT_INST_SUB_RTN                       = 0x28,
2415 	SQ_EXPORT_RAT_INST_RSUB_RTN                      = 0x29,
2416 	SQ_EXPORT_RAT_INST_MIN_INT_RTN                   = 0x2a,
2417 	SQ_EXPORT_RAT_INST_MIN_UINT_RTN                  = 0x2b,
2418 	SQ_EXPORT_RAT_INST_MAX_INT_RTN                   = 0x2c,
2419 	SQ_EXPORT_RAT_INST_MAX_UINT_RTN                  = 0x2d,
2420 	SQ_EXPORT_RAT_INST_AND_RTN                       = 0x2e,
2421 	SQ_EXPORT_RAT_INST_OR_RTN                        = 0x2f,
2422 	SQ_EXPORT_RAT_INST_XOR_RTN                       = 0x30,
2423 	SQ_EXPORT_RAT_INST_MSKOR_RTN                     = 0x31,
2424 	SQ_EXPORT_RAT_INST_INC_UINT_RTN                  = 0x32,
2425 	SQ_EXPORT_RAT_INST_DEC_UINT_RTN                  = 0x33,
2426 } ENUM_SQ_EXPORT_RAT_INST;
2427 typedef enum SQ_IBUF_ST {
2428 	SQ_IBUF_IB_IDLE                                  = 0x0,
2429 	SQ_IBUF_IB_INI_WAIT_GNT                          = 0x1,
2430 	SQ_IBUF_IB_INI_WAIT_DRET                         = 0x2,
2431 	SQ_IBUF_IB_LE_4DW                                = 0x3,
2432 	SQ_IBUF_IB_WAIT_DRET                             = 0x4,
2433 	SQ_IBUF_IB_EMPTY_WAIT_DRET                       = 0x5,
2434 	SQ_IBUF_IB_DRET                                  = 0x6,
2435 	SQ_IBUF_IB_EMPTY_WAIT_GNT                        = 0x7,
2436 } SQ_IBUF_ST;
2437 typedef enum SQ_INST_STR_ST {
2438 	SQ_INST_STR_IB_WAVE_NORML                        = 0x0,
2439 	SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV            = 0x1,
2440 	SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV             = 0x2,
2441 	SQ_INST_STR_IB_WAVE_INST_SKIP_AV                 = 0x3,
2442 	SQ_INST_STR_IB_WAVE_SETVSKIP_ST0                 = 0x4,
2443 	SQ_INST_STR_IB_WAVE_SETVSKIP_ST1                 = 0x5,
2444 	SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT               = 0x6,
2445 	SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT        = 0x7,
2446 } SQ_INST_STR_ST;
2447 typedef enum SQ_WAVE_IB_ECC_ST {
2448 	SQ_WAVE_IB_ECC_CLEAN                             = 0x0,
2449 	SQ_WAVE_IB_ECC_ERR_CONTINUE                      = 0x1,
2450 	SQ_WAVE_IB_ECC_ERR_HALT                          = 0x2,
2451 	SQ_WAVE_IB_ECC_WITH_ERR_MSG                      = 0x3,
2452 } SQ_WAVE_IB_ECC_ST;
2453 typedef enum SH_MEM_ALIGNMENT_MODE {
2454 	SH_MEM_ALIGNMENT_MODE_DWORD                      = 0x0,
2455 	SH_MEM_ALIGNMENT_MODE_DWORD_STRICT               = 0x1,
2456 	SH_MEM_ALIGNMENT_MODE_STRICT                     = 0x2,
2457 	SH_MEM_ALIGNMENT_MODE_UNALIGNED                  = 0x3,
2458 } SH_MEM_ALIGNMENT_MODE;
2459 #define SQ_WAVE_TYPE_PS0                          0x0
2460 #define SQ_THREAD_TRACE_LFSR_PS                   0x8016
2461 #define SQ_THREAD_TRACE_LFSR_VS                   0x801c
2462 #define SQ_THREAD_TRACE_LFSR_GS                   0x801f
2463 #define SQ_THREAD_TRACE_LFSR_ES                   0x8029
2464 #define SQ_THREAD_TRACE_LFSR_HS                   0x805e
2465 #define SQ_THREAD_TRACE_LFSR_LS                   0x806b
2466 #define SQ_THREAD_TRACE_LFSR_CS                   0x8097
2467 #define SQIND_GLOBAL_REGS_OFFSET                  0x0
2468 #define SQIND_GLOBAL_REGS_SIZE                    0x8
2469 #define SQIND_LOCAL_REGS_OFFSET                   0x8
2470 #define SQIND_LOCAL_REGS_SIZE                     0x8
2471 #define SQIND_WAVE_HWREGS_OFFSET                  0x10
2472 #define SQIND_WAVE_HWREGS_SIZE                    0x1f0
2473 #define SQIND_WAVE_SGPRS_OFFSET                   0x200
2474 #define SQIND_WAVE_SGPRS_SIZE                     0x200
2475 #define SQ_GFXDEC_BEGIN                           0xa000
2476 #define SQ_GFXDEC_END                             0xc000
2477 #define SQ_GFXDEC_STATE_ID_SHIFT                  0xa
2478 #define SQDEC_BEGIN                               0x2300
2479 #define SQDEC_END                                 0x23ff
2480 #define SQPERFSDEC_BEGIN                          0xd9c0
2481 #define SQPERFSDEC_END                            0xda40
2482 #define SQPERFDDEC_BEGIN                          0xd1c0
2483 #define SQPERFDDEC_END                            0xd240
2484 #define SQGFXUDEC_BEGIN                           0xc340
2485 #define SQGFXUDEC_END                             0xc380
2486 #define SQPWRDEC_BEGIN                            0xf08c
2487 #define SQPWRDEC_END                              0xf094
2488 #define SQ_DISPATCHER_GFX_MIN                     0x10
2489 #define SQ_DISPATCHER_GFX_CNT_PER_RING            0x8
2490 #define SQ_MAX_PGM_SGPRS                          0x68
2491 #define SQ_MAX_PGM_VGPRS                          0x100
2492 #define SQ_THREAD_TRACE_TIME_UNIT                 0x4
2493 #define SQ_INTERRUPT_ID                           0xef
2494 #define SQ_EX_MODE_EXCP_VALU_BASE                 0x0
2495 #define SQ_EX_MODE_EXCP_VALU_SIZE                 0x7
2496 #define SQ_EX_MODE_EXCP_INVALID                   0x0
2497 #define SQ_EX_MODE_EXCP_INPUT_DENORM              0x1
2498 #define SQ_EX_MODE_EXCP_DIV0                      0x2
2499 #define SQ_EX_MODE_EXCP_OVERFLOW                  0x3
2500 #define SQ_EX_MODE_EXCP_UNDERFLOW                 0x4
2501 #define SQ_EX_MODE_EXCP_INEXACT                   0x5
2502 #define SQ_EX_MODE_EXCP_INT_DIV0                  0x6
2503 #define SQ_EX_MODE_EXCP_ADDR_WATCH                0x7
2504 #define SQ_EX_MODE_EXCP_MEM_VIOL                  0x8
2505 #define INST_ID_ECC_INTERRUPT_MSG                 0xfffffff0
2506 #define INST_ID_TTRACE_NEW_PC_MSG                 0xfffffff1
2507 #define INST_ID_HW_TRAP                           0xfffffff2
2508 #define INST_ID_KILL_SEQ                          0xfffffff3
2509 #define INST_ID_HOST_REG_TRAP_MSG                 0xfffffffe
2510 #define SQ_ENC_SOP1_BITS                          0xbe800000
2511 #define SQ_ENC_SOP1_MASK                          0xff800000
2512 #define SQ_ENC_SOP1_FIELD                         0x17d
2513 #define SQ_ENC_SOPC_BITS                          0xbf000000
2514 #define SQ_ENC_SOPC_MASK                          0xff800000
2515 #define SQ_ENC_SOPC_FIELD                         0x17e
2516 #define SQ_ENC_SOPP_BITS                          0xbf800000
2517 #define SQ_ENC_SOPP_MASK                          0xff800000
2518 #define SQ_ENC_SOPP_FIELD                         0x17f
2519 #define SQ_ENC_SOPK_BITS                          0xb0000000
2520 #define SQ_ENC_SOPK_MASK                          0xf0000000
2521 #define SQ_ENC_SOPK_FIELD                         0xb
2522 #define SQ_ENC_SOP2_BITS                          0x80000000
2523 #define SQ_ENC_SOP2_MASK                          0xc0000000
2524 #define SQ_ENC_SOP2_FIELD                         0x2
2525 #define SQ_ENC_SMRD_BITS                          0xc0000000
2526 #define SQ_ENC_SMRD_MASK                          0xf8000000
2527 #define SQ_ENC_SMRD_FIELD                         0x18
2528 #define SQ_ENC_VOP1_BITS                          0x7e000000
2529 #define SQ_ENC_VOP1_MASK                          0xfe000000
2530 #define SQ_ENC_VOP1_FIELD                         0x3f
2531 #define SQ_ENC_VOPC_BITS                          0x7c000000
2532 #define SQ_ENC_VOPC_MASK                          0xfe000000
2533 #define SQ_ENC_VOPC_FIELD                         0x3e
2534 #define SQ_ENC_VOP2_BITS                          0x0
2535 #define SQ_ENC_VOP2_MASK                          0x80000000
2536 #define SQ_ENC_VOP2_FIELD                         0x0
2537 #define SQ_ENC_VINTRP_BITS                        0xc8000000
2538 #define SQ_ENC_VINTRP_MASK                        0xfc000000
2539 #define SQ_ENC_VINTRP_FIELD                       0x32
2540 #define SQ_ENC_VOP3_BITS                          0xd0000000
2541 #define SQ_ENC_VOP3_MASK                          0xfc000000
2542 #define SQ_ENC_VOP3_FIELD                         0x34
2543 #define SQ_ENC_DS_BITS                            0xd8000000
2544 #define SQ_ENC_DS_MASK                            0xfc000000
2545 #define SQ_ENC_DS_FIELD                           0x36
2546 #define SQ_ENC_MUBUF_BITS                         0xe0000000
2547 #define SQ_ENC_MUBUF_MASK                         0xfc000000
2548 #define SQ_ENC_MUBUF_FIELD                        0x38
2549 #define SQ_ENC_MTBUF_BITS                         0xe8000000
2550 #define SQ_ENC_MTBUF_MASK                         0xfc000000
2551 #define SQ_ENC_MTBUF_FIELD                        0x3a
2552 #define SQ_ENC_MIMG_BITS                          0xf0000000
2553 #define SQ_ENC_MIMG_MASK                          0xfc000000
2554 #define SQ_ENC_MIMG_FIELD                         0x3c
2555 #define SQ_ENC_EXP_BITS                           0xf8000000
2556 #define SQ_ENC_EXP_MASK                           0xfc000000
2557 #define SQ_ENC_EXP_FIELD                          0x3e
2558 #define SQ_ENC_FLAT_BITS                          0xdc000000
2559 #define SQ_ENC_FLAT_MASK                          0xfc000000
2560 #define SQ_ENC_FLAT_FIELD                         0x37
2561 #define SQ_WAITCNT_VM_SHIFT                       0x0
2562 #define SQ_SENDMSG_STREAMID_SIZE                  0x2
2563 #define SQ_V_OPC_COUNT                            0x100
2564 #define SQ_HWREG_OFFSET_SIZE                      0x5
2565 #define SQ_HWREG_OFFSET_SHIFT                     0x6
2566 #define SQ_NUM_ATTR                               0x21
2567 #define SQ_NUM_VGPR                               0x100
2568 #define SQ_SENDMSG_MSG_SIZE                       0x4
2569 #define SQ_NUM_TTMP                               0xc
2570 #define SQ_HWREG_ID_SIZE                          0x6
2571 #define SQ_SENDMSG_GSOP_SIZE                      0x2
2572 #define SQ_NUM_SGPR                               0x68
2573 #define SQ_EXP_NUM_MRT                            0x8
2574 #define SQ_SENDMSG_SYSTEM_SIZE                    0x3
2575 #define SQ_WAITCNT_LGKM_SHIFT                     0x8
2576 #define SQ_WAITCNT_EXP_SIZE                       0x3
2577 #define SQ_SENDMSG_SYSTEM_SHIFT                   0x4
2578 #define SQ_HWREG_SIZE_SHIFT                       0xb
2579 #define SQ_EXP_NUM_GDS                            0x5
2580 #define SQ_SENDMSG_MSG_SHIFT                      0x0
2581 #define SQ_WAITCNT_EXP_SHIFT                      0x4
2582 #define SQ_WAITCNT_VM_SIZE                        0x4
2583 #define SQ_SENDMSG_GSOP_SHIFT                     0x4
2584 #define SQ_SRC_VGPR_BIT                           0x100
2585 #define SQ_V_OP2_COUNT                            0x40
2586 #define SQ_EXP_NUM_PARAM                          0x20
2587 #define SQ_SENDMSG_STREAMID_SHIFT                 0x8
2588 #define SQ_V_OP1_COUNT                            0x80
2589 #define SQ_WAITCNT_LGKM_SIZE                      0x5
2590 #define SQ_EXP_NUM_POS                            0x4
2591 #define SQ_HWREG_SIZE_SIZE                        0x5
2592 #define SQ_HWREG_ID_SHIFT                         0x0
2593 #define SQ_S_MOV_B32                              0x3
2594 #define SQ_S_MOV_B64                              0x4
2595 #define SQ_S_CMOV_B32                             0x5
2596 #define SQ_S_CMOV_B64                             0x6
2597 #define SQ_S_NOT_B32                              0x7
2598 #define SQ_S_NOT_B64                              0x8
2599 #define SQ_S_WQM_B32                              0x9
2600 #define SQ_S_WQM_B64                              0xa
2601 #define SQ_S_BREV_B32                             0xb
2602 #define SQ_S_BREV_B64                             0xc
2603 #define SQ_S_BCNT0_I32_B32                        0xd
2604 #define SQ_S_BCNT0_I32_B64                        0xe
2605 #define SQ_S_BCNT1_I32_B32                        0xf
2606 #define SQ_S_BCNT1_I32_B64                        0x10
2607 #define SQ_S_FF0_I32_B32                          0x11
2608 #define SQ_S_FF0_I32_B64                          0x12
2609 #define SQ_S_FF1_I32_B32                          0x13
2610 #define SQ_S_FF1_I32_B64                          0x14
2611 #define SQ_S_FLBIT_I32_B32                        0x15
2612 #define SQ_S_FLBIT_I32_B64                        0x16
2613 #define SQ_S_FLBIT_I32                            0x17
2614 #define SQ_S_FLBIT_I32_I64                        0x18
2615 #define SQ_S_SEXT_I32_I8                          0x19
2616 #define SQ_S_SEXT_I32_I16                         0x1a
2617 #define SQ_S_BITSET0_B32                          0x1b
2618 #define SQ_S_BITSET0_B64                          0x1c
2619 #define SQ_S_BITSET1_B32                          0x1d
2620 #define SQ_S_BITSET1_B64                          0x1e
2621 #define SQ_S_GETPC_B64                            0x1f
2622 #define SQ_S_SETPC_B64                            0x20
2623 #define SQ_S_SWAPPC_B64                           0x21
2624 #define SQ_S_RFE_B64                              0x22
2625 #define SQ_S_AND_SAVEEXEC_B64                     0x24
2626 #define SQ_S_OR_SAVEEXEC_B64                      0x25
2627 #define SQ_S_XOR_SAVEEXEC_B64                     0x26
2628 #define SQ_S_ANDN2_SAVEEXEC_B64                   0x27
2629 #define SQ_S_ORN2_SAVEEXEC_B64                    0x28
2630 #define SQ_S_NAND_SAVEEXEC_B64                    0x29
2631 #define SQ_S_NOR_SAVEEXEC_B64                     0x2a
2632 #define SQ_S_XNOR_SAVEEXEC_B64                    0x2b
2633 #define SQ_S_QUADMASK_B32                         0x2c
2634 #define SQ_S_QUADMASK_B64                         0x2d
2635 #define SQ_S_MOVRELS_B32                          0x2e
2636 #define SQ_S_MOVRELS_B64                          0x2f
2637 #define SQ_S_MOVRELD_B32                          0x30
2638 #define SQ_S_MOVRELD_B64                          0x31
2639 #define SQ_S_CBRANCH_JOIN                         0x32
2640 #define SQ_S_MOV_REGRD_B32                        0x33
2641 #define SQ_S_ABS_I32                              0x34
2642 #define SQ_S_MOV_FED_B32                          0x35
2643 #define SQ_ATTR0                                  0x0
2644 #define SQ_S_MOVK_I32                             0x0
2645 #define SQ_S_CMOVK_I32                            0x2
2646 #define SQ_S_CMPK_EQ_I32                          0x3
2647 #define SQ_S_CMPK_LG_I32                          0x4
2648 #define SQ_S_CMPK_GT_I32                          0x5
2649 #define SQ_S_CMPK_GE_I32                          0x6
2650 #define SQ_S_CMPK_LT_I32                          0x7
2651 #define SQ_S_CMPK_LE_I32                          0x8
2652 #define SQ_S_CMPK_EQ_U32                          0x9
2653 #define SQ_S_CMPK_LG_U32                          0xa
2654 #define SQ_S_CMPK_GT_U32                          0xb
2655 #define SQ_S_CMPK_GE_U32                          0xc
2656 #define SQ_S_CMPK_LT_U32                          0xd
2657 #define SQ_S_CMPK_LE_U32                          0xe
2658 #define SQ_S_ADDK_I32                             0xf
2659 #define SQ_S_MULK_I32                             0x10
2660 #define SQ_S_CBRANCH_I_FORK                       0x11
2661 #define SQ_S_GETREG_B32                           0x12
2662 #define SQ_S_SETREG_B32                           0x13
2663 #define SQ_S_GETREG_REGRD_B32                     0x14
2664 #define SQ_S_SETREG_IMM32_B32                     0x15
2665 #define SQ_TBA_LO                                 0x6c
2666 #define SQ_TBA_HI                                 0x6d
2667 #define SQ_TMA_LO                                 0x6e
2668 #define SQ_TMA_HI                                 0x6f
2669 #define SQ_TTMP0                                  0x70
2670 #define SQ_TTMP1                                  0x71
2671 #define SQ_TTMP2                                  0x72
2672 #define SQ_TTMP3                                  0x73
2673 #define SQ_TTMP4                                  0x74
2674 #define SQ_TTMP5                                  0x75
2675 #define SQ_TTMP6                                  0x76
2676 #define SQ_TTMP7                                  0x77
2677 #define SQ_TTMP8                                  0x78
2678 #define SQ_TTMP9                                  0x79
2679 #define SQ_TTMP10                                 0x7a
2680 #define SQ_TTMP11                                 0x7b
2681 #define SQ_VGPR0                                  0x0
2682 #define SQ_EXP                                    0x0
2683 #define SQ_EXP_MRT0                               0x0
2684 #define SQ_EXP_MRTZ                               0x8
2685 #define SQ_EXP_NULL                               0x9
2686 #define SQ_EXP_POS0                               0xc
2687 #define SQ_EXP_PARAM0                             0x20
2688 #define SQ_CNT1                                   0x0
2689 #define SQ_CNT2                                   0x1
2690 #define SQ_CNT3                                   0x2
2691 #define SQ_CNT4                                   0x3
2692 #define SQ_F                                      0x0
2693 #define SQ_LT                                     0x1
2694 #define SQ_EQ                                     0x2
2695 #define SQ_LE                                     0x3
2696 #define SQ_GT                                     0x4
2697 #define SQ_LG                                     0x5
2698 #define SQ_GE                                     0x6
2699 #define SQ_O                                      0x7
2700 #define SQ_U                                      0x8
2701 #define SQ_NGE                                    0x9
2702 #define SQ_NLG                                    0xa
2703 #define SQ_NGT                                    0xb
2704 #define SQ_NLE                                    0xc
2705 #define SQ_NEQ                                    0xd
2706 #define SQ_NLT                                    0xe
2707 #define SQ_TRU                                    0xf
2708 #define SQ_V_CMP_F_F32                            0x0
2709 #define SQ_V_CMP_LT_F32                           0x1
2710 #define SQ_V_CMP_EQ_F32                           0x2
2711 #define SQ_V_CMP_LE_F32                           0x3
2712 #define SQ_V_CMP_GT_F32                           0x4
2713 #define SQ_V_CMP_LG_F32                           0x5
2714 #define SQ_V_CMP_GE_F32                           0x6
2715 #define SQ_V_CMP_O_F32                            0x7
2716 #define SQ_V_CMP_U_F32                            0x8
2717 #define SQ_V_CMP_NGE_F32                          0x9
2718 #define SQ_V_CMP_NLG_F32                          0xa
2719 #define SQ_V_CMP_NGT_F32                          0xb
2720 #define SQ_V_CMP_NLE_F32                          0xc
2721 #define SQ_V_CMP_NEQ_F32                          0xd
2722 #define SQ_V_CMP_NLT_F32                          0xe
2723 #define SQ_V_CMP_TRU_F32                          0xf
2724 #define SQ_V_CMPX_F_F32                           0x10
2725 #define SQ_V_CMPX_LT_F32                          0x11
2726 #define SQ_V_CMPX_EQ_F32                          0x12
2727 #define SQ_V_CMPX_LE_F32                          0x13
2728 #define SQ_V_CMPX_GT_F32                          0x14
2729 #define SQ_V_CMPX_LG_F32                          0x15
2730 #define SQ_V_CMPX_GE_F32                          0x16
2731 #define SQ_V_CMPX_O_F32                           0x17
2732 #define SQ_V_CMPX_U_F32                           0x18
2733 #define SQ_V_CMPX_NGE_F32                         0x19
2734 #define SQ_V_CMPX_NLG_F32                         0x1a
2735 #define SQ_V_CMPX_NGT_F32                         0x1b
2736 #define SQ_V_CMPX_NLE_F32                         0x1c
2737 #define SQ_V_CMPX_NEQ_F32                         0x1d
2738 #define SQ_V_CMPX_NLT_F32                         0x1e
2739 #define SQ_V_CMPX_TRU_F32                         0x1f
2740 #define SQ_V_CMP_F_F64                            0x20
2741 #define SQ_V_CMP_LT_F64                           0x21
2742 #define SQ_V_CMP_EQ_F64                           0x22
2743 #define SQ_V_CMP_LE_F64                           0x23
2744 #define SQ_V_CMP_GT_F64                           0x24
2745 #define SQ_V_CMP_LG_F64                           0x25
2746 #define SQ_V_CMP_GE_F64                           0x26
2747 #define SQ_V_CMP_O_F64                            0x27
2748 #define SQ_V_CMP_U_F64                            0x28
2749 #define SQ_V_CMP_NGE_F64                          0x29
2750 #define SQ_V_CMP_NLG_F64                          0x2a
2751 #define SQ_V_CMP_NGT_F64                          0x2b
2752 #define SQ_V_CMP_NLE_F64                          0x2c
2753 #define SQ_V_CMP_NEQ_F64                          0x2d
2754 #define SQ_V_CMP_NLT_F64                          0x2e
2755 #define SQ_V_CMP_TRU_F64                          0x2f
2756 #define SQ_V_CMPX_F_F64                           0x30
2757 #define SQ_V_CMPX_LT_F64                          0x31
2758 #define SQ_V_CMPX_EQ_F64                          0x32
2759 #define SQ_V_CMPX_LE_F64                          0x33
2760 #define SQ_V_CMPX_GT_F64                          0x34
2761 #define SQ_V_CMPX_LG_F64                          0x35
2762 #define SQ_V_CMPX_GE_F64                          0x36
2763 #define SQ_V_CMPX_O_F64                           0x37
2764 #define SQ_V_CMPX_U_F64                           0x38
2765 #define SQ_V_CMPX_NGE_F64                         0x39
2766 #define SQ_V_CMPX_NLG_F64                         0x3a
2767 #define SQ_V_CMPX_NGT_F64                         0x3b
2768 #define SQ_V_CMPX_NLE_F64                         0x3c
2769 #define SQ_V_CMPX_NEQ_F64                         0x3d
2770 #define SQ_V_CMPX_NLT_F64                         0x3e
2771 #define SQ_V_CMPX_TRU_F64                         0x3f
2772 #define SQ_V_CMPS_F_F32                           0x40
2773 #define SQ_V_CMPS_LT_F32                          0x41
2774 #define SQ_V_CMPS_EQ_F32                          0x42
2775 #define SQ_V_CMPS_LE_F32                          0x43
2776 #define SQ_V_CMPS_GT_F32                          0x44
2777 #define SQ_V_CMPS_LG_F32                          0x45
2778 #define SQ_V_CMPS_GE_F32                          0x46
2779 #define SQ_V_CMPS_O_F32                           0x47
2780 #define SQ_V_CMPS_U_F32                           0x48
2781 #define SQ_V_CMPS_NGE_F32                         0x49
2782 #define SQ_V_CMPS_NLG_F32                         0x4a
2783 #define SQ_V_CMPS_NGT_F32                         0x4b
2784 #define SQ_V_CMPS_NLE_F32                         0x4c
2785 #define SQ_V_CMPS_NEQ_F32                         0x4d
2786 #define SQ_V_CMPS_NLT_F32                         0x4e
2787 #define SQ_V_CMPS_TRU_F32                         0x4f
2788 #define SQ_V_CMPSX_F_F32                          0x50
2789 #define SQ_V_CMPSX_LT_F32                         0x51
2790 #define SQ_V_CMPSX_EQ_F32                         0x52
2791 #define SQ_V_CMPSX_LE_F32                         0x53
2792 #define SQ_V_CMPSX_GT_F32                         0x54
2793 #define SQ_V_CMPSX_LG_F32                         0x55
2794 #define SQ_V_CMPSX_GE_F32                         0x56
2795 #define SQ_V_CMPSX_O_F32                          0x57
2796 #define SQ_V_CMPSX_U_F32                          0x58
2797 #define SQ_V_CMPSX_NGE_F32                        0x59
2798 #define SQ_V_CMPSX_NLG_F32                        0x5a
2799 #define SQ_V_CMPSX_NGT_F32                        0x5b
2800 #define SQ_V_CMPSX_NLE_F32                        0x5c
2801 #define SQ_V_CMPSX_NEQ_F32                        0x5d
2802 #define SQ_V_CMPSX_NLT_F32                        0x5e
2803 #define SQ_V_CMPSX_TRU_F32                        0x5f
2804 #define SQ_V_CMPS_F_F64                           0x60
2805 #define SQ_V_CMPS_LT_F64                          0x61
2806 #define SQ_V_CMPS_EQ_F64                          0x62
2807 #define SQ_V_CMPS_LE_F64                          0x63
2808 #define SQ_V_CMPS_GT_F64                          0x64
2809 #define SQ_V_CMPS_LG_F64                          0x65
2810 #define SQ_V_CMPS_GE_F64                          0x66
2811 #define SQ_V_CMPS_O_F64                           0x67
2812 #define SQ_V_CMPS_U_F64                           0x68
2813 #define SQ_V_CMPS_NGE_F64                         0x69
2814 #define SQ_V_CMPS_NLG_F64                         0x6a
2815 #define SQ_V_CMPS_NGT_F64                         0x6b
2816 #define SQ_V_CMPS_NLE_F64                         0x6c
2817 #define SQ_V_CMPS_NEQ_F64                         0x6d
2818 #define SQ_V_CMPS_NLT_F64                         0x6e
2819 #define SQ_V_CMPS_TRU_F64                         0x6f
2820 #define SQ_V_CMPSX_F_F64                          0x70
2821 #define SQ_V_CMPSX_LT_F64                         0x71
2822 #define SQ_V_CMPSX_EQ_F64                         0x72
2823 #define SQ_V_CMPSX_LE_F64                         0x73
2824 #define SQ_V_CMPSX_GT_F64                         0x74
2825 #define SQ_V_CMPSX_LG_F64                         0x75
2826 #define SQ_V_CMPSX_GE_F64                         0x76
2827 #define SQ_V_CMPSX_O_F64                          0x77
2828 #define SQ_V_CMPSX_U_F64                          0x78
2829 #define SQ_V_CMPSX_NGE_F64                        0x79
2830 #define SQ_V_CMPSX_NLG_F64                        0x7a
2831 #define SQ_V_CMPSX_NGT_F64                        0x7b
2832 #define SQ_V_CMPSX_NLE_F64                        0x7c
2833 #define SQ_V_CMPSX_NEQ_F64                        0x7d
2834 #define SQ_V_CMPSX_NLT_F64                        0x7e
2835 #define SQ_V_CMPSX_TRU_F64                        0x7f
2836 #define SQ_V_CMP_F_I32                            0x80
2837 #define SQ_V_CMP_LT_I32                           0x81
2838 #define SQ_V_CMP_EQ_I32                           0x82
2839 #define SQ_V_CMP_LE_I32                           0x83
2840 #define SQ_V_CMP_GT_I32                           0x84
2841 #define SQ_V_CMP_NE_I32                           0x85
2842 #define SQ_V_CMP_GE_I32                           0x86
2843 #define SQ_V_CMP_T_I32                            0x87
2844 #define SQ_V_CMPX_F_I32                           0x90
2845 #define SQ_V_CMPX_LT_I32                          0x91
2846 #define SQ_V_CMPX_EQ_I32                          0x92
2847 #define SQ_V_CMPX_LE_I32                          0x93
2848 #define SQ_V_CMPX_GT_I32                          0x94
2849 #define SQ_V_CMPX_NE_I32                          0x95
2850 #define SQ_V_CMPX_GE_I32                          0x96
2851 #define SQ_V_CMPX_T_I32                           0x97
2852 #define SQ_V_CMP_F_I64                            0xa0
2853 #define SQ_V_CMP_LT_I64                           0xa1
2854 #define SQ_V_CMP_EQ_I64                           0xa2
2855 #define SQ_V_CMP_LE_I64                           0xa3
2856 #define SQ_V_CMP_GT_I64                           0xa4
2857 #define SQ_V_CMP_NE_I64                           0xa5
2858 #define SQ_V_CMP_GE_I64                           0xa6
2859 #define SQ_V_CMP_T_I64                            0xa7
2860 #define SQ_V_CMPX_F_I64                           0xb0
2861 #define SQ_V_CMPX_LT_I64                          0xb1
2862 #define SQ_V_CMPX_EQ_I64                          0xb2
2863 #define SQ_V_CMPX_LE_I64                          0xb3
2864 #define SQ_V_CMPX_GT_I64                          0xb4
2865 #define SQ_V_CMPX_NE_I64                          0xb5
2866 #define SQ_V_CMPX_GE_I64                          0xb6
2867 #define SQ_V_CMPX_T_I64                           0xb7
2868 #define SQ_V_CMP_F_U32                            0xc0
2869 #define SQ_V_CMP_LT_U32                           0xc1
2870 #define SQ_V_CMP_EQ_U32                           0xc2
2871 #define SQ_V_CMP_LE_U32                           0xc3
2872 #define SQ_V_CMP_GT_U32                           0xc4
2873 #define SQ_V_CMP_NE_U32                           0xc5
2874 #define SQ_V_CMP_GE_U32                           0xc6
2875 #define SQ_V_CMP_T_U32                            0xc7
2876 #define SQ_V_CMPX_F_U32                           0xd0
2877 #define SQ_V_CMPX_LT_U32                          0xd1
2878 #define SQ_V_CMPX_EQ_U32                          0xd2
2879 #define SQ_V_CMPX_LE_U32                          0xd3
2880 #define SQ_V_CMPX_GT_U32                          0xd4
2881 #define SQ_V_CMPX_NE_U32                          0xd5
2882 #define SQ_V_CMPX_GE_U32                          0xd6
2883 #define SQ_V_CMPX_T_U32                           0xd7
2884 #define SQ_V_CMP_F_U64                            0xe0
2885 #define SQ_V_CMP_LT_U64                           0xe1
2886 #define SQ_V_CMP_EQ_U64                           0xe2
2887 #define SQ_V_CMP_LE_U64                           0xe3
2888 #define SQ_V_CMP_GT_U64                           0xe4
2889 #define SQ_V_CMP_NE_U64                           0xe5
2890 #define SQ_V_CMP_GE_U64                           0xe6
2891 #define SQ_V_CMP_T_U64                            0xe7
2892 #define SQ_V_CMPX_F_U64                           0xf0
2893 #define SQ_V_CMPX_LT_U64                          0xf1
2894 #define SQ_V_CMPX_EQ_U64                          0xf2
2895 #define SQ_V_CMPX_LE_U64                          0xf3
2896 #define SQ_V_CMPX_GT_U64                          0xf4
2897 #define SQ_V_CMPX_NE_U64                          0xf5
2898 #define SQ_V_CMPX_GE_U64                          0xf6
2899 #define SQ_V_CMPX_T_U64                           0xf7
2900 #define SQ_V_CMP_CLASS_F32                        0x88
2901 #define SQ_V_CMPX_CLASS_F32                       0x98
2902 #define SQ_V_CMP_CLASS_F64                        0xa8
2903 #define SQ_V_CMPX_CLASS_F64                       0xb8
2904 #define SQ_SGPR0                                  0x0
2905 #define SQ_F                                      0x0
2906 #define SQ_LT                                     0x1
2907 #define SQ_EQ                                     0x2
2908 #define SQ_LE                                     0x3
2909 #define SQ_GT                                     0x4
2910 #define SQ_NE                                     0x5
2911 #define SQ_GE                                     0x6
2912 #define SQ_T                                      0x7
2913 #define SQ_SRC_64_INT                             0xc0
2914 #define SQ_SRC_M_1_INT                            0xc1
2915 #define SQ_SRC_M_2_INT                            0xc2
2916 #define SQ_SRC_M_3_INT                            0xc3
2917 #define SQ_SRC_M_4_INT                            0xc4
2918 #define SQ_SRC_M_5_INT                            0xc5
2919 #define SQ_SRC_M_6_INT                            0xc6
2920 #define SQ_SRC_M_7_INT                            0xc7
2921 #define SQ_SRC_M_8_INT                            0xc8
2922 #define SQ_SRC_M_9_INT                            0xc9
2923 #define SQ_SRC_M_10_INT                           0xca
2924 #define SQ_SRC_M_11_INT                           0xcb
2925 #define SQ_SRC_M_12_INT                           0xcc
2926 #define SQ_SRC_M_13_INT                           0xcd
2927 #define SQ_SRC_M_14_INT                           0xce
2928 #define SQ_SRC_M_15_INT                           0xcf
2929 #define SQ_SRC_M_16_INT                           0xd0
2930 #define SQ_SRC_0_5                                0xf0
2931 #define SQ_SRC_M_0_5                              0xf1
2932 #define SQ_SRC_1                                  0xf2
2933 #define SQ_SRC_M_1                                0xf3
2934 #define SQ_SRC_2                                  0xf4
2935 #define SQ_SRC_M_2                                0xf5
2936 #define SQ_SRC_4                                  0xf6
2937 #define SQ_SRC_M_4                                0xf7
2938 #define SQ_SRC_0                                  0x80
2939 #define SQ_SRC_1_INT                              0x81
2940 #define SQ_SRC_2_INT                              0x82
2941 #define SQ_SRC_3_INT                              0x83
2942 #define SQ_SRC_4_INT                              0x84
2943 #define SQ_SRC_5_INT                              0x85
2944 #define SQ_SRC_6_INT                              0x86
2945 #define SQ_SRC_7_INT                              0x87
2946 #define SQ_SRC_8_INT                              0x88
2947 #define SQ_SRC_9_INT                              0x89
2948 #define SQ_SRC_10_INT                             0x8a
2949 #define SQ_SRC_11_INT                             0x8b
2950 #define SQ_SRC_12_INT                             0x8c
2951 #define SQ_SRC_13_INT                             0x8d
2952 #define SQ_SRC_14_INT                             0x8e
2953 #define SQ_SRC_15_INT                             0x8f
2954 #define SQ_SRC_16_INT                             0x90
2955 #define SQ_SRC_17_INT                             0x91
2956 #define SQ_SRC_18_INT                             0x92
2957 #define SQ_SRC_19_INT                             0x93
2958 #define SQ_SRC_20_INT                             0x94
2959 #define SQ_SRC_21_INT                             0x95
2960 #define SQ_SRC_22_INT                             0x96
2961 #define SQ_SRC_23_INT                             0x97
2962 #define SQ_SRC_24_INT                             0x98
2963 #define SQ_SRC_25_INT                             0x99
2964 #define SQ_SRC_26_INT                             0x9a
2965 #define SQ_SRC_27_INT                             0x9b
2966 #define SQ_SRC_28_INT                             0x9c
2967 #define SQ_SRC_29_INT                             0x9d
2968 #define SQ_SRC_30_INT                             0x9e
2969 #define SQ_SRC_31_INT                             0x9f
2970 #define SQ_SRC_32_INT                             0xa0
2971 #define SQ_SRC_33_INT                             0xa1
2972 #define SQ_SRC_34_INT                             0xa2
2973 #define SQ_SRC_35_INT                             0xa3
2974 #define SQ_SRC_36_INT                             0xa4
2975 #define SQ_SRC_37_INT                             0xa5
2976 #define SQ_SRC_38_INT                             0xa6
2977 #define SQ_SRC_39_INT                             0xa7
2978 #define SQ_SRC_40_INT                             0xa8
2979 #define SQ_SRC_41_INT                             0xa9
2980 #define SQ_SRC_42_INT                             0xaa
2981 #define SQ_SRC_43_INT                             0xab
2982 #define SQ_SRC_44_INT                             0xac
2983 #define SQ_SRC_45_INT                             0xad
2984 #define SQ_SRC_46_INT                             0xae
2985 #define SQ_SRC_47_INT                             0xaf
2986 #define SQ_SRC_48_INT                             0xb0
2987 #define SQ_SRC_49_INT                             0xb1
2988 #define SQ_SRC_50_INT                             0xb2
2989 #define SQ_SRC_51_INT                             0xb3
2990 #define SQ_SRC_52_INT                             0xb4
2991 #define SQ_SRC_53_INT                             0xb5
2992 #define SQ_SRC_54_INT                             0xb6
2993 #define SQ_SRC_55_INT                             0xb7
2994 #define SQ_SRC_56_INT                             0xb8
2995 #define SQ_SRC_57_INT                             0xb9
2996 #define SQ_SRC_58_INT                             0xba
2997 #define SQ_SRC_59_INT                             0xbb
2998 #define SQ_SRC_60_INT                             0xbc
2999 #define SQ_SRC_61_INT                             0xbd
3000 #define SQ_SRC_62_INT                             0xbe
3001 #define SQ_SRC_63_INT                             0xbf
3002 #define SQ_BUFFER_LOAD_FORMAT_X                   0x0
3003 #define SQ_BUFFER_LOAD_FORMAT_XY                  0x1
3004 #define SQ_BUFFER_LOAD_FORMAT_XYZ                 0x2
3005 #define SQ_BUFFER_LOAD_FORMAT_XYZW                0x3
3006 #define SQ_BUFFER_STORE_FORMAT_X                  0x4
3007 #define SQ_BUFFER_STORE_FORMAT_XY                 0x5
3008 #define SQ_BUFFER_STORE_FORMAT_XYZ                0x6
3009 #define SQ_BUFFER_STORE_FORMAT_XYZW               0x7
3010 #define SQ_BUFFER_LOAD_UBYTE                      0x8
3011 #define SQ_BUFFER_LOAD_SBYTE                      0x9
3012 #define SQ_BUFFER_LOAD_USHORT                     0xa
3013 #define SQ_BUFFER_LOAD_SSHORT                     0xb
3014 #define SQ_BUFFER_LOAD_DWORD                      0xc
3015 #define SQ_BUFFER_LOAD_DWORDX2                    0xd
3016 #define SQ_BUFFER_LOAD_DWORDX4                    0xe
3017 #define SQ_BUFFER_LOAD_DWORDX3                    0xf
3018 #define SQ_BUFFER_STORE_BYTE                      0x18
3019 #define SQ_BUFFER_STORE_SHORT                     0x1a
3020 #define SQ_BUFFER_STORE_DWORD                     0x1c
3021 #define SQ_BUFFER_STORE_DWORDX2                   0x1d
3022 #define SQ_BUFFER_STORE_DWORDX4                   0x1e
3023 #define SQ_BUFFER_STORE_DWORDX3                   0x1f
3024 #define SQ_BUFFER_ATOMIC_SWAP                     0x30
3025 #define SQ_BUFFER_ATOMIC_CMPSWAP                  0x31
3026 #define SQ_BUFFER_ATOMIC_ADD                      0x32
3027 #define SQ_BUFFER_ATOMIC_SUB                      0x33
3028 #define SQ_BUFFER_ATOMIC_SMIN                     0x35
3029 #define SQ_BUFFER_ATOMIC_UMIN                     0x36
3030 #define SQ_BUFFER_ATOMIC_SMAX                     0x37
3031 #define SQ_BUFFER_ATOMIC_UMAX                     0x38
3032 #define SQ_BUFFER_ATOMIC_AND                      0x39
3033 #define SQ_BUFFER_ATOMIC_OR                       0x3a
3034 #define SQ_BUFFER_ATOMIC_XOR                      0x3b
3035 #define SQ_BUFFER_ATOMIC_INC                      0x3c
3036 #define SQ_BUFFER_ATOMIC_DEC                      0x3d
3037 #define SQ_BUFFER_ATOMIC_FCMPSWAP                 0x3e
3038 #define SQ_BUFFER_ATOMIC_FMIN                     0x3f
3039 #define SQ_BUFFER_ATOMIC_FMAX                     0x40
3040 #define SQ_BUFFER_ATOMIC_SWAP_X2                  0x50
3041 #define SQ_BUFFER_ATOMIC_CMPSWAP_X2               0x51
3042 #define SQ_BUFFER_ATOMIC_ADD_X2                   0x52
3043 #define SQ_BUFFER_ATOMIC_SUB_X2                   0x53
3044 #define SQ_BUFFER_ATOMIC_SMIN_X2                  0x55
3045 #define SQ_BUFFER_ATOMIC_UMIN_X2                  0x56
3046 #define SQ_BUFFER_ATOMIC_SMAX_X2                  0x57
3047 #define SQ_BUFFER_ATOMIC_UMAX_X2                  0x58
3048 #define SQ_BUFFER_ATOMIC_AND_X2                   0x59
3049 #define SQ_BUFFER_ATOMIC_OR_X2                    0x5a
3050 #define SQ_BUFFER_ATOMIC_XOR_X2                   0x5b
3051 #define SQ_BUFFER_ATOMIC_INC_X2                   0x5c
3052 #define SQ_BUFFER_ATOMIC_DEC_X2                   0x5d
3053 #define SQ_BUFFER_ATOMIC_FCMPSWAP_X2              0x5e
3054 #define SQ_BUFFER_ATOMIC_FMIN_X2                  0x5f
3055 #define SQ_BUFFER_ATOMIC_FMAX_X2                  0x60
3056 #define SQ_BUFFER_WBINVL1_VOL                     0x70
3057 #define SQ_BUFFER_WBINVL1                         0x71
3058 #define SQ_DS_ADD_U32                             0x0
3059 #define SQ_DS_SUB_U32                             0x1
3060 #define SQ_DS_RSUB_U32                            0x2
3061 #define SQ_DS_INC_U32                             0x3
3062 #define SQ_DS_DEC_U32                             0x4
3063 #define SQ_DS_MIN_I32                             0x5
3064 #define SQ_DS_MAX_I32                             0x6
3065 #define SQ_DS_MIN_U32                             0x7
3066 #define SQ_DS_MAX_U32                             0x8
3067 #define SQ_DS_AND_B32                             0x9
3068 #define SQ_DS_OR_B32                              0xa
3069 #define SQ_DS_XOR_B32                             0xb
3070 #define SQ_DS_MSKOR_B32                           0xc
3071 #define SQ_DS_WRITE_B32                           0xd
3072 #define SQ_DS_WRITE2_B32                          0xe
3073 #define SQ_DS_WRITE2ST64_B32                      0xf
3074 #define SQ_DS_CMPST_B32                           0x10
3075 #define SQ_DS_CMPST_F32                           0x11
3076 #define SQ_DS_MIN_F32                             0x12
3077 #define SQ_DS_MAX_F32                             0x13
3078 #define SQ_DS_NOP                                 0x14
3079 #define SQ_DS_GWS_SEMA_RELEASE_ALL                0x18
3080 #define SQ_DS_GWS_INIT                            0x19
3081 #define SQ_DS_GWS_SEMA_V                          0x1a
3082 #define SQ_DS_GWS_SEMA_BR                         0x1b
3083 #define SQ_DS_GWS_SEMA_P                          0x1c
3084 #define SQ_DS_GWS_BARRIER                         0x1d
3085 #define SQ_DS_WRITE_B8                            0x1e
3086 #define SQ_DS_WRITE_B16                           0x1f
3087 #define SQ_DS_ADD_RTN_U32                         0x20
3088 #define SQ_DS_SUB_RTN_U32                         0x21
3089 #define SQ_DS_RSUB_RTN_U32                        0x22
3090 #define SQ_DS_INC_RTN_U32                         0x23
3091 #define SQ_DS_DEC_RTN_U32                         0x24
3092 #define SQ_DS_MIN_RTN_I32                         0x25
3093 #define SQ_DS_MAX_RTN_I32                         0x26
3094 #define SQ_DS_MIN_RTN_U32                         0x27
3095 #define SQ_DS_MAX_RTN_U32                         0x28
3096 #define SQ_DS_AND_RTN_B32                         0x29
3097 #define SQ_DS_OR_RTN_B32                          0x2a
3098 #define SQ_DS_XOR_RTN_B32                         0x2b
3099 #define SQ_DS_MSKOR_RTN_B32                       0x2c
3100 #define SQ_DS_WRXCHG_RTN_B32                      0x2d
3101 #define SQ_DS_WRXCHG2_RTN_B32                     0x2e
3102 #define SQ_DS_WRXCHG2ST64_RTN_B32                 0x2f
3103 #define SQ_DS_CMPST_RTN_B32                       0x30
3104 #define SQ_DS_CMPST_RTN_F32                       0x31
3105 #define SQ_DS_MIN_RTN_F32                         0x32
3106 #define SQ_DS_MAX_RTN_F32                         0x33
3107 #define SQ_DS_WRAP_RTN_B32                        0x34
3108 #define SQ_DS_SWIZZLE_B32                         0x35
3109 #define SQ_DS_READ_B32                            0x36
3110 #define SQ_DS_READ2_B32                           0x37
3111 #define SQ_DS_READ2ST64_B32                       0x38
3112 #define SQ_DS_READ_I8                             0x39
3113 #define SQ_DS_READ_U8                             0x3a
3114 #define SQ_DS_READ_I16                            0x3b
3115 #define SQ_DS_READ_U16                            0x3c
3116 #define SQ_DS_CONSUME                             0x3d
3117 #define SQ_DS_APPEND                              0x3e
3118 #define SQ_DS_ORDERED_COUNT                       0x3f
3119 #define SQ_DS_ADD_U64                             0x40
3120 #define SQ_DS_SUB_U64                             0x41
3121 #define SQ_DS_RSUB_U64                            0x42
3122 #define SQ_DS_INC_U64                             0x43
3123 #define SQ_DS_DEC_U64                             0x44
3124 #define SQ_DS_MIN_I64                             0x45
3125 #define SQ_DS_MAX_I64                             0x46
3126 #define SQ_DS_MIN_U64                             0x47
3127 #define SQ_DS_MAX_U64                             0x48
3128 #define SQ_DS_AND_B64                             0x49
3129 #define SQ_DS_OR_B64                              0x4a
3130 #define SQ_DS_XOR_B64                             0x4b
3131 #define SQ_DS_MSKOR_B64                           0x4c
3132 #define SQ_DS_WRITE_B64                           0x4d
3133 #define SQ_DS_WRITE2_B64                          0x4e
3134 #define SQ_DS_WRITE2ST64_B64                      0x4f
3135 #define SQ_DS_CMPST_B64                           0x50
3136 #define SQ_DS_CMPST_F64                           0x51
3137 #define SQ_DS_MIN_F64                             0x52
3138 #define SQ_DS_MAX_F64                             0x53
3139 #define SQ_DS_ADD_RTN_U64                         0x60
3140 #define SQ_DS_SUB_RTN_U64                         0x61
3141 #define SQ_DS_RSUB_RTN_U64                        0x62
3142 #define SQ_DS_INC_RTN_U64                         0x63
3143 #define SQ_DS_DEC_RTN_U64                         0x64
3144 #define SQ_DS_MIN_RTN_I64                         0x65
3145 #define SQ_DS_MAX_RTN_I64                         0x66
3146 #define SQ_DS_MIN_RTN_U64                         0x67
3147 #define SQ_DS_MAX_RTN_U64                         0x68
3148 #define SQ_DS_AND_RTN_B64                         0x69
3149 #define SQ_DS_OR_RTN_B64                          0x6a
3150 #define SQ_DS_XOR_RTN_B64                         0x6b
3151 #define SQ_DS_MSKOR_RTN_B64                       0x6c
3152 #define SQ_DS_WRXCHG_RTN_B64                      0x6d
3153 #define SQ_DS_WRXCHG2_RTN_B64                     0x6e
3154 #define SQ_DS_WRXCHG2ST64_RTN_B64                 0x6f
3155 #define SQ_DS_CMPST_RTN_B64                       0x70
3156 #define SQ_DS_CMPST_RTN_F64                       0x71
3157 #define SQ_DS_MIN_RTN_F64                         0x72
3158 #define SQ_DS_MAX_RTN_F64                         0x73
3159 #define SQ_DS_READ_B64                            0x76
3160 #define SQ_DS_READ2_B64                           0x77
3161 #define SQ_DS_READ2ST64_B64                       0x78
3162 #define SQ_DS_CONDXCHG32_RTN_B64                  0x7e
3163 #define SQ_DS_ADD_SRC2_U32                        0x80
3164 #define SQ_DS_SUB_SRC2_U32                        0x81
3165 #define SQ_DS_RSUB_SRC2_U32                       0x82
3166 #define SQ_DS_INC_SRC2_U32                        0x83
3167 #define SQ_DS_DEC_SRC2_U32                        0x84
3168 #define SQ_DS_MIN_SRC2_I32                        0x85
3169 #define SQ_DS_MAX_SRC2_I32                        0x86
3170 #define SQ_DS_MIN_SRC2_U32                        0x87
3171 #define SQ_DS_MAX_SRC2_U32                        0x88
3172 #define SQ_DS_AND_SRC2_B32                        0x89
3173 #define SQ_DS_OR_SRC2_B32                         0x8a
3174 #define SQ_DS_XOR_SRC2_B32                        0x8b
3175 #define SQ_DS_WRITE_SRC2_B32                      0x8d
3176 #define SQ_DS_MIN_SRC2_F32                        0x92
3177 #define SQ_DS_MAX_SRC2_F32                        0x93
3178 #define SQ_DS_ADD_SRC2_U64                        0xc0
3179 #define SQ_DS_SUB_SRC2_U64                        0xc1
3180 #define SQ_DS_RSUB_SRC2_U64                       0xc2
3181 #define SQ_DS_INC_SRC2_U64                        0xc3
3182 #define SQ_DS_DEC_SRC2_U64                        0xc4
3183 #define SQ_DS_MIN_SRC2_I64                        0xc5
3184 #define SQ_DS_MAX_SRC2_I64                        0xc6
3185 #define SQ_DS_MIN_SRC2_U64                        0xc7
3186 #define SQ_DS_MAX_SRC2_U64                        0xc8
3187 #define SQ_DS_AND_SRC2_B64                        0xc9
3188 #define SQ_DS_OR_SRC2_B64                         0xca
3189 #define SQ_DS_XOR_SRC2_B64                        0xcb
3190 #define SQ_DS_WRITE_SRC2_B64                      0xcd
3191 #define SQ_DS_MIN_SRC2_F64                        0xd2
3192 #define SQ_DS_MAX_SRC2_F64                        0xd3
3193 #define SQ_DS_WRITE_B96                           0xde
3194 #define SQ_DS_WRITE_B128                          0xdf
3195 #define SQ_DS_CONDXCHG32_RTN_B128                 0xfd
3196 #define SQ_DS_READ_B96                            0xfe
3197 #define SQ_DS_READ_B128                           0xff
3198 #define SQ_SRC_SCC                                0xfd
3199 #define SQ_OMOD_OFF                               0x0
3200 #define SQ_OMOD_M2                                0x1
3201 #define SQ_OMOD_M4                                0x2
3202 #define SQ_OMOD_D2                                0x3
3203 #define SQ_EXP_GDS0                               0x18
3204 #define SQ_GS_OP_NOP                              0x0
3205 #define SQ_GS_OP_CUT                              0x1
3206 #define SQ_GS_OP_EMIT                             0x2
3207 #define SQ_GS_OP_EMIT_CUT                         0x3
3208 #define SQ_IMAGE_LOAD                             0x0
3209 #define SQ_IMAGE_LOAD_MIP                         0x1
3210 #define SQ_IMAGE_LOAD_PCK                         0x2
3211 #define SQ_IMAGE_LOAD_PCK_SGN                     0x3
3212 #define SQ_IMAGE_LOAD_MIP_PCK                     0x4
3213 #define SQ_IMAGE_LOAD_MIP_PCK_SGN                 0x5
3214 #define SQ_IMAGE_STORE                            0x8
3215 #define SQ_IMAGE_STORE_MIP                        0x9
3216 #define SQ_IMAGE_STORE_PCK                        0xa
3217 #define SQ_IMAGE_STORE_MIP_PCK                    0xb
3218 #define SQ_IMAGE_GET_RESINFO                      0xe
3219 #define SQ_IMAGE_ATOMIC_SWAP                      0xf
3220 #define SQ_IMAGE_ATOMIC_CMPSWAP                   0x10
3221 #define SQ_IMAGE_ATOMIC_ADD                       0x11
3222 #define SQ_IMAGE_ATOMIC_SUB                       0x12
3223 #define SQ_IMAGE_ATOMIC_SMIN                      0x14
3224 #define SQ_IMAGE_ATOMIC_UMIN                      0x15
3225 #define SQ_IMAGE_ATOMIC_SMAX                      0x16
3226 #define SQ_IMAGE_ATOMIC_UMAX                      0x17
3227 #define SQ_IMAGE_ATOMIC_AND                       0x18
3228 #define SQ_IMAGE_ATOMIC_OR                        0x19
3229 #define SQ_IMAGE_ATOMIC_XOR                       0x1a
3230 #define SQ_IMAGE_ATOMIC_INC                       0x1b
3231 #define SQ_IMAGE_ATOMIC_DEC                       0x1c
3232 #define SQ_IMAGE_ATOMIC_FCMPSWAP                  0x1d
3233 #define SQ_IMAGE_ATOMIC_FMIN                      0x1e
3234 #define SQ_IMAGE_ATOMIC_FMAX                      0x1f
3235 #define SQ_IMAGE_SAMPLE                           0x20
3236 #define SQ_IMAGE_SAMPLE_CL                        0x21
3237 #define SQ_IMAGE_SAMPLE_D                         0x22
3238 #define SQ_IMAGE_SAMPLE_D_CL                      0x23
3239 #define SQ_IMAGE_SAMPLE_L                         0x24
3240 #define SQ_IMAGE_SAMPLE_B                         0x25
3241 #define SQ_IMAGE_SAMPLE_B_CL                      0x26
3242 #define SQ_IMAGE_SAMPLE_LZ                        0x27
3243 #define SQ_IMAGE_SAMPLE_C                         0x28
3244 #define SQ_IMAGE_SAMPLE_C_CL                      0x29
3245 #define SQ_IMAGE_SAMPLE_C_D                       0x2a
3246 #define SQ_IMAGE_SAMPLE_C_D_CL                    0x2b
3247 #define SQ_IMAGE_SAMPLE_C_L                       0x2c
3248 #define SQ_IMAGE_SAMPLE_C_B                       0x2d
3249 #define SQ_IMAGE_SAMPLE_C_B_CL                    0x2e
3250 #define SQ_IMAGE_SAMPLE_C_LZ                      0x2f
3251 #define SQ_IMAGE_SAMPLE_O                         0x30
3252 #define SQ_IMAGE_SAMPLE_CL_O                      0x31
3253 #define SQ_IMAGE_SAMPLE_D_O                       0x32
3254 #define SQ_IMAGE_SAMPLE_D_CL_O                    0x33
3255 #define SQ_IMAGE_SAMPLE_L_O                       0x34
3256 #define SQ_IMAGE_SAMPLE_B_O                       0x35
3257 #define SQ_IMAGE_SAMPLE_B_CL_O                    0x36
3258 #define SQ_IMAGE_SAMPLE_LZ_O                      0x37
3259 #define SQ_IMAGE_SAMPLE_C_O                       0x38
3260 #define SQ_IMAGE_SAMPLE_C_CL_O                    0x39
3261 #define SQ_IMAGE_SAMPLE_C_D_O                     0x3a
3262 #define SQ_IMAGE_SAMPLE_C_D_CL_O                  0x3b
3263 #define SQ_IMAGE_SAMPLE_C_L_O                     0x3c
3264 #define SQ_IMAGE_SAMPLE_C_B_O                     0x3d
3265 #define SQ_IMAGE_SAMPLE_C_B_CL_O                  0x3e
3266 #define SQ_IMAGE_SAMPLE_C_LZ_O                    0x3f
3267 #define SQ_IMAGE_GATHER4                          0x40
3268 #define SQ_IMAGE_GATHER4_CL                       0x41
3269 #define SQ_IMAGE_GATHER4_L                        0x44
3270 #define SQ_IMAGE_GATHER4_B                        0x45
3271 #define SQ_IMAGE_GATHER4_B_CL                     0x46
3272 #define SQ_IMAGE_GATHER4_LZ                       0x47
3273 #define SQ_IMAGE_GATHER4_C                        0x48
3274 #define SQ_IMAGE_GATHER4_C_CL                     0x49
3275 #define SQ_IMAGE_GATHER4_C_L                      0x4c
3276 #define SQ_IMAGE_GATHER4_C_B                      0x4d
3277 #define SQ_IMAGE_GATHER4_C_B_CL                   0x4e
3278 #define SQ_IMAGE_GATHER4_C_LZ                     0x4f
3279 #define SQ_IMAGE_GATHER4_O                        0x50
3280 #define SQ_IMAGE_GATHER4_CL_O                     0x51
3281 #define SQ_IMAGE_GATHER4_L_O                      0x54
3282 #define SQ_IMAGE_GATHER4_B_O                      0x55
3283 #define SQ_IMAGE_GATHER4_B_CL_O                   0x56
3284 #define SQ_IMAGE_GATHER4_LZ_O                     0x57
3285 #define SQ_IMAGE_GATHER4_C_O                      0x58
3286 #define SQ_IMAGE_GATHER4_C_CL_O                   0x59
3287 #define SQ_IMAGE_GATHER4_C_L_O                    0x5c
3288 #define SQ_IMAGE_GATHER4_C_B_O                    0x5d
3289 #define SQ_IMAGE_GATHER4_C_B_CL_O                 0x5e
3290 #define SQ_IMAGE_GATHER4_C_LZ_O                   0x5f
3291 #define SQ_IMAGE_GET_LOD                          0x60
3292 #define SQ_IMAGE_SAMPLE_CD                        0x68
3293 #define SQ_IMAGE_SAMPLE_CD_CL                     0x69
3294 #define SQ_IMAGE_SAMPLE_C_CD                      0x6a
3295 #define SQ_IMAGE_SAMPLE_C_CD_CL                   0x6b
3296 #define SQ_IMAGE_SAMPLE_CD_O                      0x6c
3297 #define SQ_IMAGE_SAMPLE_CD_CL_O                   0x6d
3298 #define SQ_IMAGE_SAMPLE_C_CD_O                    0x6e
3299 #define SQ_IMAGE_SAMPLE_C_CD_CL_O                 0x6f
3300 #define SQ_IMAGE_RSRC256                          0x7e
3301 #define SQ_IMAGE_SAMPLER                          0x7f
3302 #define SQ_SRC_VCCZ                               0xfb
3303 #define SQ_SRC_VGPR0                              0x100
3304 #define SQ_DFMT_INVALID                           0x0
3305 #define SQ_DFMT_8                                 0x1
3306 #define SQ_DFMT_16                                0x2
3307 #define SQ_DFMT_8_8                               0x3
3308 #define SQ_DFMT_32                                0x4
3309 #define SQ_DFMT_16_16                             0x5
3310 #define SQ_DFMT_10_11_11                          0x6
3311 #define SQ_DFMT_11_11_10                          0x7
3312 #define SQ_DFMT_10_10_10_2                        0x8
3313 #define SQ_DFMT_2_10_10_10                        0x9
3314 #define SQ_DFMT_8_8_8_8                           0xa
3315 #define SQ_DFMT_32_32                             0xb
3316 #define SQ_DFMT_16_16_16_16                       0xc
3317 #define SQ_DFMT_32_32_32                          0xd
3318 #define SQ_DFMT_32_32_32_32                       0xe
3319 #define SQ_TBUFFER_LOAD_FORMAT_X                  0x0
3320 #define SQ_TBUFFER_LOAD_FORMAT_XY                 0x1
3321 #define SQ_TBUFFER_LOAD_FORMAT_XYZ                0x2
3322 #define SQ_TBUFFER_LOAD_FORMAT_XYZW               0x3
3323 #define SQ_TBUFFER_STORE_FORMAT_X                 0x4
3324 #define SQ_TBUFFER_STORE_FORMAT_XY                0x5
3325 #define SQ_TBUFFER_STORE_FORMAT_XYZ               0x6
3326 #define SQ_TBUFFER_STORE_FORMAT_XYZW              0x7
3327 #define SQ_CHAN_X                                 0x0
3328 #define SQ_CHAN_Y                                 0x1
3329 #define SQ_CHAN_Z                                 0x2
3330 #define SQ_CHAN_W                                 0x3
3331 #define SQ_EXEC_LO                                0x7e
3332 #define SQ_EXEC_HI                                0x7f
3333 #define SQ_S_LOAD_DWORD                           0x0
3334 #define SQ_S_LOAD_DWORDX2                         0x1
3335 #define SQ_S_LOAD_DWORDX4                         0x2
3336 #define SQ_S_LOAD_DWORDX8                         0x3
3337 #define SQ_S_LOAD_DWORDX16                        0x4
3338 #define SQ_S_BUFFER_LOAD_DWORD                    0x8
3339 #define SQ_S_BUFFER_LOAD_DWORDX2                  0x9
3340 #define SQ_S_BUFFER_LOAD_DWORDX4                  0xa
3341 #define SQ_S_BUFFER_LOAD_DWORDX8                  0xb
3342 #define SQ_S_BUFFER_LOAD_DWORDX16                 0xc
3343 #define SQ_S_DCACHE_INV_VOL                       0x1d
3344 #define SQ_S_MEMTIME                              0x1e
3345 #define SQ_S_DCACHE_INV                           0x1f
3346 #define SQ_V_NOP                                  0x0
3347 #define SQ_V_MOV_B32                              0x1
3348 #define SQ_V_READFIRSTLANE_B32                    0x2
3349 #define SQ_V_CVT_I32_F64                          0x3
3350 #define SQ_V_CVT_F64_I32                          0x4
3351 #define SQ_V_CVT_F32_I32                          0x5
3352 #define SQ_V_CVT_F32_U32                          0x6
3353 #define SQ_V_CVT_U32_F32                          0x7
3354 #define SQ_V_CVT_I32_F32                          0x8
3355 #define SQ_V_MOV_FED_B32                          0x9
3356 #define SQ_V_CVT_F16_F32                          0xa
3357 #define SQ_V_CVT_F32_F16                          0xb
3358 #define SQ_V_CVT_RPI_I32_F32                      0xc
3359 #define SQ_V_CVT_FLR_I32_F32                      0xd
3360 #define SQ_V_CVT_OFF_F32_I4                       0xe
3361 #define SQ_V_CVT_F32_F64                          0xf
3362 #define SQ_V_CVT_F64_F32                          0x10
3363 #define SQ_V_CVT_F32_UBYTE0                       0x11
3364 #define SQ_V_CVT_F32_UBYTE1                       0x12
3365 #define SQ_V_CVT_F32_UBYTE2                       0x13
3366 #define SQ_V_CVT_F32_UBYTE3                       0x14
3367 #define SQ_V_CVT_U32_F64                          0x15
3368 #define SQ_V_CVT_F64_U32                          0x16
3369 #define SQ_V_TRUNC_F64                            0x17
3370 #define SQ_V_CEIL_F64                             0x18
3371 #define SQ_V_RNDNE_F64                            0x19
3372 #define SQ_V_FLOOR_F64                            0x1a
3373 #define SQ_V_FRACT_F32                            0x20
3374 #define SQ_V_TRUNC_F32                            0x21
3375 #define SQ_V_CEIL_F32                             0x22
3376 #define SQ_V_RNDNE_F32                            0x23
3377 #define SQ_V_FLOOR_F32                            0x24
3378 #define SQ_V_EXP_F32                              0x25
3379 #define SQ_V_LOG_CLAMP_F32                        0x26
3380 #define SQ_V_LOG_F32                              0x27
3381 #define SQ_V_RCP_CLAMP_F32                        0x28
3382 #define SQ_V_RCP_LEGACY_F32                       0x29
3383 #define SQ_V_RCP_F32                              0x2a
3384 #define SQ_V_RCP_IFLAG_F32                        0x2b
3385 #define SQ_V_RSQ_CLAMP_F32                        0x2c
3386 #define SQ_V_RSQ_LEGACY_F32                       0x2d
3387 #define SQ_V_RSQ_F32                              0x2e
3388 #define SQ_V_RCP_F64                              0x2f
3389 #define SQ_V_RCP_CLAMP_F64                        0x30
3390 #define SQ_V_RSQ_F64                              0x31
3391 #define SQ_V_RSQ_CLAMP_F64                        0x32
3392 #define SQ_V_SQRT_F32                             0x33
3393 #define SQ_V_SQRT_F64                             0x34
3394 #define SQ_V_SIN_F32                              0x35
3395 #define SQ_V_COS_F32                              0x36
3396 #define SQ_V_NOT_B32                              0x37
3397 #define SQ_V_BFREV_B32                            0x38
3398 #define SQ_V_FFBH_U32                             0x39
3399 #define SQ_V_FFBL_B32                             0x3a
3400 #define SQ_V_FFBH_I32                             0x3b
3401 #define SQ_V_FREXP_EXP_I32_F64                    0x3c
3402 #define SQ_V_FREXP_MANT_F64                       0x3d
3403 #define SQ_V_FRACT_F64                            0x3e
3404 #define SQ_V_FREXP_EXP_I32_F32                    0x3f
3405 #define SQ_V_FREXP_MANT_F32                       0x40
3406 #define SQ_V_CLREXCP                              0x41
3407 #define SQ_V_MOVRELD_B32                          0x42
3408 #define SQ_V_MOVRELS_B32                          0x43
3409 #define SQ_V_MOVRELSD_B32                         0x44
3410 #define SQ_V_LOG_LEGACY_F32                       0x45
3411 #define SQ_V_EXP_LEGACY_F32                       0x46
3412 #define SQ_NFMT_UNORM                             0x0
3413 #define SQ_NFMT_SNORM                             0x1
3414 #define SQ_NFMT_USCALED                           0x2
3415 #define SQ_NFMT_SSCALED                           0x3
3416 #define SQ_NFMT_UINT                              0x4
3417 #define SQ_NFMT_SINT                              0x5
3418 #define SQ_NFMT_SNORM_OGL                         0x6
3419 #define SQ_NFMT_FLOAT                             0x7
3420 #define SQ_V_OP1_OFFSET                           0x180
3421 #define SQ_V_OP2_OFFSET                           0x100
3422 #define SQ_V_OPC_OFFSET                           0x0
3423 #define SQ_V_INTERP_P1_F32                        0x0
3424 #define SQ_V_INTERP_P2_F32                        0x1
3425 #define SQ_V_INTERP_MOV_F32                       0x2
3426 #define SQ_S_NOP                                  0x0
3427 #define SQ_S_ENDPGM                               0x1
3428 #define SQ_S_BRANCH                               0x2
3429 #define SQ_S_CBRANCH_SCC0                         0x4
3430 #define SQ_S_CBRANCH_SCC1                         0x5
3431 #define SQ_S_CBRANCH_VCCZ                         0x6
3432 #define SQ_S_CBRANCH_VCCNZ                        0x7
3433 #define SQ_S_CBRANCH_EXECZ                        0x8
3434 #define SQ_S_CBRANCH_EXECNZ                       0x9
3435 #define SQ_S_BARRIER                              0xa
3436 #define SQ_S_SETKILL                              0xb
3437 #define SQ_S_WAITCNT                              0xc
3438 #define SQ_S_SETHALT                              0xd
3439 #define SQ_S_SLEEP                                0xe
3440 #define SQ_S_SETPRIO                              0xf
3441 #define SQ_S_SENDMSG                              0x10
3442 #define SQ_S_SENDMSGHALT                          0x11
3443 #define SQ_S_TRAP                                 0x12
3444 #define SQ_S_ICACHE_INV                           0x13
3445 #define SQ_S_INCPERFLEVEL                         0x14
3446 #define SQ_S_DECPERFLEVEL                         0x15
3447 #define SQ_S_TTRACEDATA                           0x16
3448 #define SQ_S_CBRANCH_CDBGSYS                      0x17
3449 #define SQ_S_CBRANCH_CDBGUSER                     0x18
3450 #define SQ_S_CBRANCH_CDBGSYS_OR_USER              0x19
3451 #define SQ_S_CBRANCH_CDBGSYS_AND_USER             0x1a
3452 #define SQ_SRC_LITERAL                            0xff
3453 #define SQ_VCC_LO                                 0x6a
3454 #define SQ_VCC_HI                                 0x6b
3455 #define SQ_PARAM_P10                              0x0
3456 #define SQ_PARAM_P20                              0x1
3457 #define SQ_PARAM_P0                               0x2
3458 #define SQ_SRC_LDS_DIRECT                         0xfe
3459 #define SQ_FLAT_SCRATCH_LO                        0x68
3460 #define SQ_FLAT_SCRATCH_HI                        0x69
3461 #define SQ_V_CNDMASK_B32                          0x0
3462 #define SQ_V_READLANE_B32                         0x1
3463 #define SQ_V_WRITELANE_B32                        0x2
3464 #define SQ_V_ADD_F32                              0x3
3465 #define SQ_V_SUB_F32                              0x4
3466 #define SQ_V_SUBREV_F32                           0x5
3467 #define SQ_V_MAC_LEGACY_F32                       0x6
3468 #define SQ_V_MUL_LEGACY_F32                       0x7
3469 #define SQ_V_MUL_F32                              0x8
3470 #define SQ_V_MUL_I32_I24                          0x9
3471 #define SQ_V_MUL_HI_I32_I24                       0xa
3472 #define SQ_V_MUL_U32_U24                          0xb
3473 #define SQ_V_MUL_HI_U32_U24                       0xc
3474 #define SQ_V_MIN_LEGACY_F32                       0xd
3475 #define SQ_V_MAX_LEGACY_F32                       0xe
3476 #define SQ_V_MIN_F32                              0xf
3477 #define SQ_V_MAX_F32                              0x10
3478 #define SQ_V_MIN_I32                              0x11
3479 #define SQ_V_MAX_I32                              0x12
3480 #define SQ_V_MIN_U32                              0x13
3481 #define SQ_V_MAX_U32                              0x14
3482 #define SQ_V_LSHR_B32                             0x15
3483 #define SQ_V_LSHRREV_B32                          0x16
3484 #define SQ_V_ASHR_I32                             0x17
3485 #define SQ_V_ASHRREV_I32                          0x18
3486 #define SQ_V_LSHL_B32                             0x19
3487 #define SQ_V_LSHLREV_B32                          0x1a
3488 #define SQ_V_AND_B32                              0x1b
3489 #define SQ_V_OR_B32                               0x1c
3490 #define SQ_V_XOR_B32                              0x1d
3491 #define SQ_V_BFM_B32                              0x1e
3492 #define SQ_V_MAC_F32                              0x1f
3493 #define SQ_V_MADMK_F32                            0x20
3494 #define SQ_V_MADAK_F32                            0x21
3495 #define SQ_V_BCNT_U32_B32                         0x22
3496 #define SQ_V_MBCNT_LO_U32_B32                     0x23
3497 #define SQ_V_MBCNT_HI_U32_B32                     0x24
3498 #define SQ_V_ADD_I32                              0x25
3499 #define SQ_V_SUB_I32                              0x26
3500 #define SQ_V_SUBREV_I32                           0x27
3501 #define SQ_V_ADDC_U32                             0x28
3502 #define SQ_V_SUBB_U32                             0x29
3503 #define SQ_V_SUBBREV_U32                          0x2a
3504 #define SQ_V_LDEXP_F32                            0x2b
3505 #define SQ_V_CVT_PKACCUM_U8_F32                   0x2c
3506 #define SQ_V_CVT_PKNORM_I16_F32                   0x2d
3507 #define SQ_V_CVT_PKNORM_U16_F32                   0x2e
3508 #define SQ_V_CVT_PKRTZ_F16_F32                    0x2f
3509 #define SQ_V_CVT_PK_U16_U32                       0x30
3510 #define SQ_V_CVT_PK_I16_I32                       0x31
3511 #define SQ_FLAT_LOAD_UBYTE                        0x8
3512 #define SQ_FLAT_LOAD_SBYTE                        0x9
3513 #define SQ_FLAT_LOAD_USHORT                       0xa
3514 #define SQ_FLAT_LOAD_SSHORT                       0xb
3515 #define SQ_FLAT_LOAD_DWORD                        0xc
3516 #define SQ_FLAT_LOAD_DWORDX2                      0xd
3517 #define SQ_FLAT_LOAD_DWORDX4                      0xe
3518 #define SQ_FLAT_LOAD_DWORDX3                      0xf
3519 #define SQ_FLAT_STORE_BYTE                        0x18
3520 #define SQ_FLAT_STORE_SHORT                       0x1a
3521 #define SQ_FLAT_STORE_DWORD                       0x1c
3522 #define SQ_FLAT_STORE_DWORDX2                     0x1d
3523 #define SQ_FLAT_STORE_DWORDX4                     0x1e
3524 #define SQ_FLAT_STORE_DWORDX3                     0x1f
3525 #define SQ_FLAT_ATOMIC_SWAP                       0x30
3526 #define SQ_FLAT_ATOMIC_CMPSWAP                    0x31
3527 #define SQ_FLAT_ATOMIC_ADD                        0x32
3528 #define SQ_FLAT_ATOMIC_SUB                        0x33
3529 #define SQ_FLAT_ATOMIC_SMIN                       0x35
3530 #define SQ_FLAT_ATOMIC_UMIN                       0x36
3531 #define SQ_FLAT_ATOMIC_SMAX                       0x37
3532 #define SQ_FLAT_ATOMIC_UMAX                       0x38
3533 #define SQ_FLAT_ATOMIC_AND                        0x39
3534 #define SQ_FLAT_ATOMIC_OR                         0x3a
3535 #define SQ_FLAT_ATOMIC_XOR                        0x3b
3536 #define SQ_FLAT_ATOMIC_INC                        0x3c
3537 #define SQ_FLAT_ATOMIC_DEC                        0x3d
3538 #define SQ_FLAT_ATOMIC_FCMPSWAP                   0x3e
3539 #define SQ_FLAT_ATOMIC_FMIN                       0x3f
3540 #define SQ_FLAT_ATOMIC_FMAX                       0x40
3541 #define SQ_FLAT_ATOMIC_SWAP_X2                    0x50
3542 #define SQ_FLAT_ATOMIC_CMPSWAP_X2                 0x51
3543 #define SQ_FLAT_ATOMIC_ADD_X2                     0x52
3544 #define SQ_FLAT_ATOMIC_SUB_X2                     0x53
3545 #define SQ_FLAT_ATOMIC_SMIN_X2                    0x55
3546 #define SQ_FLAT_ATOMIC_UMIN_X2                    0x56
3547 #define SQ_FLAT_ATOMIC_SMAX_X2                    0x57
3548 #define SQ_FLAT_ATOMIC_UMAX_X2                    0x58
3549 #define SQ_FLAT_ATOMIC_AND_X2                     0x59
3550 #define SQ_FLAT_ATOMIC_OR_X2                      0x5a
3551 #define SQ_FLAT_ATOMIC_XOR_X2                     0x5b
3552 #define SQ_FLAT_ATOMIC_INC_X2                     0x5c
3553 #define SQ_FLAT_ATOMIC_DEC_X2                     0x5d
3554 #define SQ_FLAT_ATOMIC_FCMPSWAP_X2                0x5e
3555 #define SQ_FLAT_ATOMIC_FMIN_X2                    0x5f
3556 #define SQ_FLAT_ATOMIC_FMAX_X2                    0x60
3557 #define SQ_S_CMP_EQ_I32                           0x0
3558 #define SQ_S_CMP_LG_I32                           0x1
3559 #define SQ_S_CMP_GT_I32                           0x2
3560 #define SQ_S_CMP_GE_I32                           0x3
3561 #define SQ_S_CMP_LT_I32                           0x4
3562 #define SQ_S_CMP_LE_I32                           0x5
3563 #define SQ_S_CMP_EQ_U32                           0x6
3564 #define SQ_S_CMP_LG_U32                           0x7
3565 #define SQ_S_CMP_GT_U32                           0x8
3566 #define SQ_S_CMP_GE_U32                           0x9
3567 #define SQ_S_CMP_LT_U32                           0xa
3568 #define SQ_S_CMP_LE_U32                           0xb
3569 #define SQ_S_BITCMP0_B32                          0xc
3570 #define SQ_S_BITCMP1_B32                          0xd
3571 #define SQ_S_BITCMP0_B64                          0xe
3572 #define SQ_S_BITCMP1_B64                          0xf
3573 #define SQ_S_SETVSKIP                             0x10
3574 #define SQ_M0                                     0x7c
3575 #define SQ_V_MAD_LEGACY_F32                       0x140
3576 #define SQ_V_MAD_F32                              0x141
3577 #define SQ_V_MAD_I32_I24                          0x142
3578 #define SQ_V_MAD_U32_U24                          0x143
3579 #define SQ_V_CUBEID_F32                           0x144
3580 #define SQ_V_CUBESC_F32                           0x145
3581 #define SQ_V_CUBETC_F32                           0x146
3582 #define SQ_V_CUBEMA_F32                           0x147
3583 #define SQ_V_BFE_U32                              0x148
3584 #define SQ_V_BFE_I32                              0x149
3585 #define SQ_V_BFI_B32                              0x14a
3586 #define SQ_V_FMA_F32                              0x14b
3587 #define SQ_V_FMA_F64                              0x14c
3588 #define SQ_V_LERP_U8                              0x14d
3589 #define SQ_V_ALIGNBIT_B32                         0x14e
3590 #define SQ_V_ALIGNBYTE_B32                        0x14f
3591 #define SQ_V_MULLIT_F32                           0x150
3592 #define SQ_V_MIN3_F32                             0x151
3593 #define SQ_V_MIN3_I32                             0x152
3594 #define SQ_V_MIN3_U32                             0x153
3595 #define SQ_V_MAX3_F32                             0x154
3596 #define SQ_V_MAX3_I32                             0x155
3597 #define SQ_V_MAX3_U32                             0x156
3598 #define SQ_V_MED3_F32                             0x157
3599 #define SQ_V_MED3_I32                             0x158
3600 #define SQ_V_MED3_U32                             0x159
3601 #define SQ_V_SAD_U8                               0x15a
3602 #define SQ_V_SAD_HI_U8                            0x15b
3603 #define SQ_V_SAD_U16                              0x15c
3604 #define SQ_V_SAD_U32                              0x15d
3605 #define SQ_V_CVT_PK_U8_F32                        0x15e
3606 #define SQ_V_DIV_FIXUP_F32                        0x15f
3607 #define SQ_V_DIV_FIXUP_F64                        0x160
3608 #define SQ_V_LSHL_B64                             0x161
3609 #define SQ_V_LSHR_B64                             0x162
3610 #define SQ_V_ASHR_I64                             0x163
3611 #define SQ_V_ADD_F64                              0x164
3612 #define SQ_V_MUL_F64                              0x165
3613 #define SQ_V_MIN_F64                              0x166
3614 #define SQ_V_MAX_F64                              0x167
3615 #define SQ_V_LDEXP_F64                            0x168
3616 #define SQ_V_MUL_LO_U32                           0x169
3617 #define SQ_V_MUL_HI_U32                           0x16a
3618 #define SQ_V_MUL_LO_I32                           0x16b
3619 #define SQ_V_MUL_HI_I32                           0x16c
3620 #define SQ_V_DIV_SCALE_F32                        0x16d
3621 #define SQ_V_DIV_SCALE_F64                        0x16e
3622 #define SQ_V_DIV_FMAS_F32                         0x16f
3623 #define SQ_V_DIV_FMAS_F64                         0x170
3624 #define SQ_V_MSAD_U8                              0x171
3625 #define SQ_V_QSAD_PK_U16_U8                       0x172
3626 #define SQ_V_MQSAD_PK_U16_U8                      0x173
3627 #define SQ_V_TRIG_PREOP_F64                       0x174
3628 #define SQ_V_MQSAD_U32_U8                         0x175
3629 #define SQ_V_MAD_U64_U32                          0x176
3630 #define SQ_V_MAD_I64_I32                          0x177
3631 #define SQ_VCC_ALL                                0x0
3632 #define SQ_SRC_EXECZ                              0xfc
3633 #define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT            0x1
3634 #define SQ_SYSMSG_OP_REG_RD                       0x2
3635 #define SQ_SYSMSG_OP_HOST_TRAP_ACK                0x3
3636 #define SQ_SYSMSG_OP_TTRACE_PC                    0x4
3637 #define SQ_HW_REG_MODE                            0x1
3638 #define SQ_HW_REG_STATUS                          0x2
3639 #define SQ_HW_REG_TRAPSTS                         0x3
3640 #define SQ_HW_REG_HW_ID                           0x4
3641 #define SQ_HW_REG_GPR_ALLOC                       0x5
3642 #define SQ_HW_REG_LDS_ALLOC                       0x6
3643 #define SQ_HW_REG_IB_STS                          0x7
3644 #define SQ_HW_REG_PC_LO                           0x8
3645 #define SQ_HW_REG_PC_HI                           0x9
3646 #define SQ_HW_REG_INST_DW0                        0xa
3647 #define SQ_HW_REG_INST_DW1                        0xb
3648 #define SQ_HW_REG_IB_DBG0                         0xc
3649 #define SQ_S_ADD_U32                              0x0
3650 #define SQ_S_SUB_U32                              0x1
3651 #define SQ_S_ADD_I32                              0x2
3652 #define SQ_S_SUB_I32                              0x3
3653 #define SQ_S_ADDC_U32                             0x4
3654 #define SQ_S_SUBB_U32                             0x5
3655 #define SQ_S_MIN_I32                              0x6
3656 #define SQ_S_MIN_U32                              0x7
3657 #define SQ_S_MAX_I32                              0x8
3658 #define SQ_S_MAX_U32                              0x9
3659 #define SQ_S_CSELECT_B32                          0xa
3660 #define SQ_S_CSELECT_B64                          0xb
3661 #define SQ_S_AND_B32                              0xe
3662 #define SQ_S_AND_B64                              0xf
3663 #define SQ_S_OR_B32                               0x10
3664 #define SQ_S_OR_B64                               0x11
3665 #define SQ_S_XOR_B32                              0x12
3666 #define SQ_S_XOR_B64                              0x13
3667 #define SQ_S_ANDN2_B32                            0x14
3668 #define SQ_S_ANDN2_B64                            0x15
3669 #define SQ_S_ORN2_B32                             0x16
3670 #define SQ_S_ORN2_B64                             0x17
3671 #define SQ_S_NAND_B32                             0x18
3672 #define SQ_S_NAND_B64                             0x19
3673 #define SQ_S_NOR_B32                              0x1a
3674 #define SQ_S_NOR_B64                              0x1b
3675 #define SQ_S_XNOR_B32                             0x1c
3676 #define SQ_S_XNOR_B64                             0x1d
3677 #define SQ_S_LSHL_B32                             0x1e
3678 #define SQ_S_LSHL_B64                             0x1f
3679 #define SQ_S_LSHR_B32                             0x20
3680 #define SQ_S_LSHR_B64                             0x21
3681 #define SQ_S_ASHR_I32                             0x22
3682 #define SQ_S_ASHR_I64                             0x23
3683 #define SQ_S_BFM_B32                              0x24
3684 #define SQ_S_BFM_B64                              0x25
3685 #define SQ_S_MUL_I32                              0x26
3686 #define SQ_S_BFE_U32                              0x27
3687 #define SQ_S_BFE_I32                              0x28
3688 #define SQ_S_BFE_U64                              0x29
3689 #define SQ_S_BFE_I64                              0x2a
3690 #define SQ_S_CBRANCH_G_FORK                       0x2b
3691 #define SQ_S_ABSDIFF_I32                          0x2c
3692 #define SQ_MSG_INTERRUPT                          0x1
3693 #define SQ_MSG_GS                                 0x2
3694 #define SQ_MSG_GS_DONE                            0x3
3695 #define SQ_MSG_SYSMSG                             0xf
3696 typedef enum TEX_BORDER_COLOR_TYPE {
3697 	TEX_BorderColor_TransparentBlack                 = 0x0,
3698 	TEX_BorderColor_OpaqueBlack                      = 0x1,
3699 	TEX_BorderColor_OpaqueWhite                      = 0x2,
3700 	TEX_BorderColor_Register                         = 0x3,
3701 } TEX_BORDER_COLOR_TYPE;
3702 typedef enum TEX_CHROMA_KEY {
3703 	TEX_ChromaKey_Disabled                           = 0x0,
3704 	TEX_ChromaKey_Kill                               = 0x1,
3705 	TEX_ChromaKey_Blend                              = 0x2,
3706 	TEX_ChromaKey_RESERVED_3                         = 0x3,
3707 } TEX_CHROMA_KEY;
3708 typedef enum TEX_CLAMP {
3709 	TEX_Clamp_Repeat                                 = 0x0,
3710 	TEX_Clamp_Mirror                                 = 0x1,
3711 	TEX_Clamp_ClampToLast                            = 0x2,
3712 	TEX_Clamp_MirrorOnceToLast                       = 0x3,
3713 	TEX_Clamp_ClampHalfToBorder                      = 0x4,
3714 	TEX_Clamp_MirrorOnceHalfToBorder                 = 0x5,
3715 	TEX_Clamp_ClampToBorder                          = 0x6,
3716 	TEX_Clamp_MirrorOnceToBorder                     = 0x7,
3717 } TEX_CLAMP;
3718 typedef enum TEX_COORD_TYPE {
3719 	TEX_CoordType_Unnormalized                       = 0x0,
3720 	TEX_CoordType_Normalized                         = 0x1,
3721 } TEX_COORD_TYPE;
3722 typedef enum TEX_DEPTH_COMPARE_FUNCTION {
3723 	TEX_DepthCompareFunction_Never                   = 0x0,
3724 	TEX_DepthCompareFunction_Less                    = 0x1,
3725 	TEX_DepthCompareFunction_Equal                   = 0x2,
3726 	TEX_DepthCompareFunction_LessEqual               = 0x3,
3727 	TEX_DepthCompareFunction_Greater                 = 0x4,
3728 	TEX_DepthCompareFunction_NotEqual                = 0x5,
3729 	TEX_DepthCompareFunction_GreaterEqual            = 0x6,
3730 	TEX_DepthCompareFunction_Always                  = 0x7,
3731 } TEX_DEPTH_COMPARE_FUNCTION;
3732 typedef enum TEX_DIM {
3733 	TEX_Dim_1D                                       = 0x0,
3734 	TEX_Dim_2D                                       = 0x1,
3735 	TEX_Dim_3D                                       = 0x2,
3736 	TEX_Dim_CubeMap                                  = 0x3,
3737 	TEX_Dim_1DArray                                  = 0x4,
3738 	TEX_Dim_2DArray                                  = 0x5,
3739 	TEX_Dim_2D_MSAA                                  = 0x6,
3740 	TEX_Dim_2DArray_MSAA                             = 0x7,
3741 } TEX_DIM;
3742 typedef enum TEX_FORMAT_COMP {
3743 	TEX_FormatComp_Unsigned                          = 0x0,
3744 	TEX_FormatComp_Signed                            = 0x1,
3745 	TEX_FormatComp_UnsignedBiased                    = 0x2,
3746 	TEX_FormatComp_RESERVED_3                        = 0x3,
3747 } TEX_FORMAT_COMP;
3748 typedef enum TEX_MAX_ANISO_RATIO {
3749 	TEX_MaxAnisoRatio_1to1                           = 0x0,
3750 	TEX_MaxAnisoRatio_2to1                           = 0x1,
3751 	TEX_MaxAnisoRatio_4to1                           = 0x2,
3752 	TEX_MaxAnisoRatio_8to1                           = 0x3,
3753 	TEX_MaxAnisoRatio_16to1                          = 0x4,
3754 	TEX_MaxAnisoRatio_RESERVED_5                     = 0x5,
3755 	TEX_MaxAnisoRatio_RESERVED_6                     = 0x6,
3756 	TEX_MaxAnisoRatio_RESERVED_7                     = 0x7,
3757 } TEX_MAX_ANISO_RATIO;
3758 typedef enum TEX_MIP_FILTER {
3759 	TEX_MipFilter_None                               = 0x0,
3760 	TEX_MipFilter_Point                              = 0x1,
3761 	TEX_MipFilter_Linear                             = 0x2,
3762 	TEX_MipFilter_RESERVED_3                         = 0x3,
3763 } TEX_MIP_FILTER;
3764 typedef enum TEX_REQUEST_SIZE {
3765 	TEX_RequestSize_32B                              = 0x0,
3766 	TEX_RequestSize_64B                              = 0x1,
3767 	TEX_RequestSize_128B                             = 0x2,
3768 	TEX_RequestSize_2X64B                            = 0x3,
3769 } TEX_REQUEST_SIZE;
3770 typedef enum TEX_SAMPLER_TYPE {
3771 	TEX_SamplerType_Invalid                          = 0x0,
3772 	TEX_SamplerType_Valid                            = 0x1,
3773 } TEX_SAMPLER_TYPE;
3774 typedef enum TEX_XY_FILTER {
3775 	TEX_XYFilter_Point                               = 0x0,
3776 	TEX_XYFilter_Linear                              = 0x1,
3777 	TEX_XYFilter_AnisoPoint                          = 0x2,
3778 	TEX_XYFilter_AnisoLinear                         = 0x3,
3779 } TEX_XY_FILTER;
3780 typedef enum TEX_Z_FILTER {
3781 	TEX_ZFilter_None                                 = 0x0,
3782 	TEX_ZFilter_Point                                = 0x1,
3783 	TEX_ZFilter_Linear                               = 0x2,
3784 	TEX_ZFilter_RESERVED_3                           = 0x3,
3785 } TEX_Z_FILTER;
3786 typedef enum VTX_CLAMP {
3787 	VTX_Clamp_ClampToZero                            = 0x0,
3788 	VTX_Clamp_ClampToNAN                             = 0x1,
3789 } VTX_CLAMP;
3790 typedef enum VTX_FETCH_TYPE {
3791 	VTX_FetchType_VertexData                         = 0x0,
3792 	VTX_FetchType_InstanceData                       = 0x1,
3793 	VTX_FetchType_NoIndexOffset                      = 0x2,
3794 	VTX_FetchType_RESERVED_3                         = 0x3,
3795 } VTX_FETCH_TYPE;
3796 typedef enum VTX_FORMAT_COMP_ALL {
3797 	VTX_FormatCompAll_Unsigned                       = 0x0,
3798 	VTX_FormatCompAll_Signed                         = 0x1,
3799 } VTX_FORMAT_COMP_ALL;
3800 typedef enum VTX_MEM_REQUEST_SIZE {
3801 	VTX_MemRequestSize_32B                           = 0x0,
3802 	VTX_MemRequestSize_64B                           = 0x1,
3803 } VTX_MEM_REQUEST_SIZE;
3804 typedef enum TVX_DATA_FORMAT {
3805 	TVX_FMT_INVALID                                  = 0x0,
3806 	TVX_FMT_8                                        = 0x1,
3807 	TVX_FMT_4_4                                      = 0x2,
3808 	TVX_FMT_3_3_2                                    = 0x3,
3809 	TVX_FMT_RESERVED_4                               = 0x4,
3810 	TVX_FMT_16                                       = 0x5,
3811 	TVX_FMT_16_FLOAT                                 = 0x6,
3812 	TVX_FMT_8_8                                      = 0x7,
3813 	TVX_FMT_5_6_5                                    = 0x8,
3814 	TVX_FMT_6_5_5                                    = 0x9,
3815 	TVX_FMT_1_5_5_5                                  = 0xa,
3816 	TVX_FMT_4_4_4_4                                  = 0xb,
3817 	TVX_FMT_5_5_5_1                                  = 0xc,
3818 	TVX_FMT_32                                       = 0xd,
3819 	TVX_FMT_32_FLOAT                                 = 0xe,
3820 	TVX_FMT_16_16                                    = 0xf,
3821 	TVX_FMT_16_16_FLOAT                              = 0x10,
3822 	TVX_FMT_8_24                                     = 0x11,
3823 	TVX_FMT_8_24_FLOAT                               = 0x12,
3824 	TVX_FMT_24_8                                     = 0x13,
3825 	TVX_FMT_24_8_FLOAT                               = 0x14,
3826 	TVX_FMT_10_11_11                                 = 0x15,
3827 	TVX_FMT_10_11_11_FLOAT                           = 0x16,
3828 	TVX_FMT_11_11_10                                 = 0x17,
3829 	TVX_FMT_11_11_10_FLOAT                           = 0x18,
3830 	TVX_FMT_2_10_10_10                               = 0x19,
3831 	TVX_FMT_8_8_8_8                                  = 0x1a,
3832 	TVX_FMT_10_10_10_2                               = 0x1b,
3833 	TVX_FMT_X24_8_32_FLOAT                           = 0x1c,
3834 	TVX_FMT_32_32                                    = 0x1d,
3835 	TVX_FMT_32_32_FLOAT                              = 0x1e,
3836 	TVX_FMT_16_16_16_16                              = 0x1f,
3837 	TVX_FMT_16_16_16_16_FLOAT                        = 0x20,
3838 	TVX_FMT_RESERVED_33                              = 0x21,
3839 	TVX_FMT_32_32_32_32                              = 0x22,
3840 	TVX_FMT_32_32_32_32_FLOAT                        = 0x23,
3841 	TVX_FMT_RESERVED_36                              = 0x24,
3842 	TVX_FMT_1                                        = 0x25,
3843 	TVX_FMT_1_REVERSED                               = 0x26,
3844 	TVX_FMT_GB_GR                                    = 0x27,
3845 	TVX_FMT_BG_RG                                    = 0x28,
3846 	TVX_FMT_32_AS_8                                  = 0x29,
3847 	TVX_FMT_32_AS_8_8                                = 0x2a,
3848 	TVX_FMT_5_9_9_9_SHAREDEXP                        = 0x2b,
3849 	TVX_FMT_8_8_8                                    = 0x2c,
3850 	TVX_FMT_16_16_16                                 = 0x2d,
3851 	TVX_FMT_16_16_16_FLOAT                           = 0x2e,
3852 	TVX_FMT_32_32_32                                 = 0x2f,
3853 	TVX_FMT_32_32_32_FLOAT                           = 0x30,
3854 	TVX_FMT_BC1                                      = 0x31,
3855 	TVX_FMT_BC2                                      = 0x32,
3856 	TVX_FMT_BC3                                      = 0x33,
3857 	TVX_FMT_BC4                                      = 0x34,
3858 	TVX_FMT_BC5                                      = 0x35,
3859 	TVX_FMT_APC0                                     = 0x36,
3860 	TVX_FMT_APC1                                     = 0x37,
3861 	TVX_FMT_APC2                                     = 0x38,
3862 	TVX_FMT_APC3                                     = 0x39,
3863 	TVX_FMT_APC4                                     = 0x3a,
3864 	TVX_FMT_APC5                                     = 0x3b,
3865 	TVX_FMT_APC6                                     = 0x3c,
3866 	TVX_FMT_APC7                                     = 0x3d,
3867 	TVX_FMT_CTX1                                     = 0x3e,
3868 	TVX_FMT_RESERVED_63                              = 0x3f,
3869 } TVX_DATA_FORMAT;
3870 typedef enum TVX_DST_SEL {
3871 	TVX_DstSel_X                                     = 0x0,
3872 	TVX_DstSel_Y                                     = 0x1,
3873 	TVX_DstSel_Z                                     = 0x2,
3874 	TVX_DstSel_W                                     = 0x3,
3875 	TVX_DstSel_0f                                    = 0x4,
3876 	TVX_DstSel_1f                                    = 0x5,
3877 	TVX_DstSel_RESERVED_6                            = 0x6,
3878 	TVX_DstSel_Mask                                  = 0x7,
3879 } TVX_DST_SEL;
3880 typedef enum TVX_ENDIAN_SWAP {
3881 	TVX_EndianSwap_None                              = 0x0,
3882 	TVX_EndianSwap_8in16                             = 0x1,
3883 	TVX_EndianSwap_8in32                             = 0x2,
3884 	TVX_EndianSwap_8in64                             = 0x3,
3885 } TVX_ENDIAN_SWAP;
3886 typedef enum TVX_INST {
3887 	TVX_Inst_NormalVertexFetch                       = 0x0,
3888 	TVX_Inst_SemanticVertexFetch                     = 0x1,
3889 	TVX_Inst_RESERVED_2                              = 0x2,
3890 	TVX_Inst_LD                                      = 0x3,
3891 	TVX_Inst_GetTextureResInfo                       = 0x4,
3892 	TVX_Inst_GetNumberOfSamples                      = 0x5,
3893 	TVX_Inst_GetLOD                                  = 0x6,
3894 	TVX_Inst_GetGradientsH                           = 0x7,
3895 	TVX_Inst_GetGradientsV                           = 0x8,
3896 	TVX_Inst_SetTextureOffsets                       = 0x9,
3897 	TVX_Inst_KeepGradients                           = 0xa,
3898 	TVX_Inst_SetGradientsH                           = 0xb,
3899 	TVX_Inst_SetGradientsV                           = 0xc,
3900 	TVX_Inst_Pass                                    = 0xd,
3901 	TVX_Inst_GetBufferResInfo                        = 0xe,
3902 	TVX_Inst_RESERVED_15                             = 0xf,
3903 	TVX_Inst_Sample                                  = 0x10,
3904 	TVX_Inst_Sample_L                                = 0x11,
3905 	TVX_Inst_Sample_LB                               = 0x12,
3906 	TVX_Inst_Sample_LZ                               = 0x13,
3907 	TVX_Inst_Sample_G                                = 0x14,
3908 	TVX_Inst_Gather4                                 = 0x15,
3909 	TVX_Inst_Sample_G_LB                             = 0x16,
3910 	TVX_Inst_Gather4_O                               = 0x17,
3911 	TVX_Inst_Sample_C                                = 0x18,
3912 	TVX_Inst_Sample_C_L                              = 0x19,
3913 	TVX_Inst_Sample_C_LB                             = 0x1a,
3914 	TVX_Inst_Sample_C_LZ                             = 0x1b,
3915 	TVX_Inst_Sample_C_G                              = 0x1c,
3916 	TVX_Inst_Gather4_C                               = 0x1d,
3917 	TVX_Inst_Sample_C_G_LB                           = 0x1e,
3918 	TVX_Inst_Gather4_C_O                             = 0x1f,
3919 } TVX_INST;
3920 typedef enum TVX_NUM_FORMAT_ALL {
3921 	TVX_NumFormatAll_Norm                            = 0x0,
3922 	TVX_NumFormatAll_Int                             = 0x1,
3923 	TVX_NumFormatAll_Scaled                          = 0x2,
3924 	TVX_NumFormatAll_RESERVED_3                      = 0x3,
3925 } TVX_NUM_FORMAT_ALL;
3926 typedef enum TVX_SRC_SEL {
3927 	TVX_SrcSel_X                                     = 0x0,
3928 	TVX_SrcSel_Y                                     = 0x1,
3929 	TVX_SrcSel_Z                                     = 0x2,
3930 	TVX_SrcSel_W                                     = 0x3,
3931 	TVX_SrcSel_0f                                    = 0x4,
3932 	TVX_SrcSel_1f                                    = 0x5,
3933 } TVX_SRC_SEL;
3934 typedef enum TVX_SRF_MODE_ALL {
3935 	TVX_SRFModeAll_ZCMO                              = 0x0,
3936 	TVX_SRFModeAll_NZ                                = 0x1,
3937 } TVX_SRF_MODE_ALL;
3938 typedef enum TVX_TYPE {
3939 	TVX_Type_InvalidTextureResource                  = 0x0,
3940 	TVX_Type_InvalidVertexBuffer                     = 0x1,
3941 	TVX_Type_ValidTextureResource                    = 0x2,
3942 	TVX_Type_ValidVertexBuffer                       = 0x3,
3943 } TVX_TYPE;
3944 typedef enum TC_OP_MASKS {
3945 	TC_OP_MASK_FLUSH_DENROM                          = 0x8,
3946 	TC_OP_MASK_64                                    = 0x20,
3947 	TC_OP_MASK_NO_RTN                                = 0x40,
3948 } TC_OP_MASKS;
3949 typedef enum TC_OP {
3950 	TC_OP_READ                                       = 0x0,
3951 	TC_OP_ATOMIC_FCMPSWAP_RTN_32                     = 0x1,
3952 	TC_OP_ATOMIC_FMIN_RTN_32                         = 0x2,
3953 	TC_OP_ATOMIC_FMAX_RTN_32                         = 0x3,
3954 	TC_OP_RESERVED_FOP_RTN_32_0                      = 0x4,
3955 	TC_OP_RESERVED_FOP_RTN_32_1                      = 0x5,
3956 	TC_OP_RESERVED_FOP_RTN_32_2                      = 0x6,
3957 	TC_OP_ATOMIC_SWAP_RTN_32                         = 0x7,
3958 	TC_OP_ATOMIC_CMPSWAP_RTN_32                      = 0x8,
3959 	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32        = 0x9,
3960 	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32            = 0xa,
3961 	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32            = 0xb,
3962 	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0         = 0xc,
3963 	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1         = 0xd,
3964 	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2         = 0xe,
3965 	TC_OP_ATOMIC_ADD_RTN_32                          = 0xf,
3966 	TC_OP_ATOMIC_SUB_RTN_32                          = 0x10,
3967 	TC_OP_ATOMIC_SMIN_RTN_32                         = 0x11,
3968 	TC_OP_ATOMIC_UMIN_RTN_32                         = 0x12,
3969 	TC_OP_ATOMIC_SMAX_RTN_32                         = 0x13,
3970 	TC_OP_ATOMIC_UMAX_RTN_32                         = 0x14,
3971 	TC_OP_ATOMIC_AND_RTN_32                          = 0x15,
3972 	TC_OP_ATOMIC_OR_RTN_32                           = 0x16,
3973 	TC_OP_ATOMIC_XOR_RTN_32                          = 0x17,
3974 	TC_OP_ATOMIC_INC_RTN_32                          = 0x18,
3975 	TC_OP_ATOMIC_DEC_RTN_32                          = 0x19,
3976 	TC_OP_WBINVL1_VOL                                = 0x1a,
3977 	TC_OP_RESERVED_NON_FLOAT_RTN_32_0                = 0x1b,
3978 	TC_OP_RESERVED_NON_FLOAT_RTN_32_1                = 0x1c,
3979 	TC_OP_RESERVED_NON_FLOAT_RTN_32_2                = 0x1d,
3980 	TC_OP_RESERVED_NON_FLOAT_RTN_32_3                = 0x1e,
3981 	TC_OP_RESERVED_NON_FLOAT_RTN_32_4                = 0x1f,
3982 	TC_OP_WRITE                                      = 0x20,
3983 	TC_OP_ATOMIC_FCMPSWAP_RTN_64                     = 0x21,
3984 	TC_OP_ATOMIC_FMIN_RTN_64                         = 0x22,
3985 	TC_OP_ATOMIC_FMAX_RTN_64                         = 0x23,
3986 	TC_OP_RESERVED_FOP_RTN_64_0                      = 0x24,
3987 	TC_OP_RESERVED_FOP_RTN_64_1                      = 0x25,
3988 	TC_OP_RESERVED_FOP_RTN_64_2                      = 0x26,
3989 	TC_OP_ATOMIC_SWAP_RTN_64                         = 0x27,
3990 	TC_OP_ATOMIC_CMPSWAP_RTN_64                      = 0x28,
3991 	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64        = 0x29,
3992 	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64            = 0x2a,
3993 	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64            = 0x2b,
3994 	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0         = 0x2c,
3995 	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1         = 0x2d,
3996 	TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2         = 0x2e,
3997 	TC_OP_ATOMIC_ADD_RTN_64                          = 0x2f,
3998 	TC_OP_ATOMIC_SUB_RTN_64                          = 0x30,
3999 	TC_OP_ATOMIC_SMIN_RTN_64                         = 0x31,
4000 	TC_OP_ATOMIC_UMIN_RTN_64                         = 0x32,
4001 	TC_OP_ATOMIC_SMAX_RTN_64                         = 0x33,
4002 	TC_OP_ATOMIC_UMAX_RTN_64                         = 0x34,
4003 	TC_OP_ATOMIC_AND_RTN_64                          = 0x35,
4004 	TC_OP_ATOMIC_OR_RTN_64                           = 0x36,
4005 	TC_OP_ATOMIC_XOR_RTN_64                          = 0x37,
4006 	TC_OP_ATOMIC_INC_RTN_64                          = 0x38,
4007 	TC_OP_ATOMIC_DEC_RTN_64                          = 0x39,
4008 	TC_OP_WBL2_VOL                                   = 0x3a,
4009 	TC_OP_RESERVED_NON_FLOAT_RTN_64_0                = 0x3b,
4010 	TC_OP_RESERVED_NON_FLOAT_RTN_64_1                = 0x3c,
4011 	TC_OP_RESERVED_NON_FLOAT_RTN_64_2                = 0x3d,
4012 	TC_OP_RESERVED_NON_FLOAT_RTN_64_3                = 0x3e,
4013 	TC_OP_RESERVED_NON_FLOAT_RTN_64_4                = 0x3f,
4014 	TC_OP_WBINVL1                                    = 0x40,
4015 	TC_OP_ATOMIC_FCMPSWAP_32                         = 0x41,
4016 	TC_OP_ATOMIC_FMIN_32                             = 0x42,
4017 	TC_OP_ATOMIC_FMAX_32                             = 0x43,
4018 	TC_OP_RESERVED_FOP_32_0                          = 0x44,
4019 	TC_OP_RESERVED_FOP_32_1                          = 0x45,
4020 	TC_OP_RESERVED_FOP_32_2                          = 0x46,
4021 	TC_OP_ATOMIC_SWAP_32                             = 0x47,
4022 	TC_OP_ATOMIC_CMPSWAP_32                          = 0x48,
4023 	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32            = 0x49,
4024 	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32                = 0x4a,
4025 	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32                = 0x4b,
4026 	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0             = 0x4c,
4027 	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1             = 0x4d,
4028 	TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2             = 0x4e,
4029 	TC_OP_ATOMIC_ADD_32                              = 0x4f,
4030 	TC_OP_ATOMIC_SUB_32                              = 0x50,
4031 	TC_OP_ATOMIC_SMIN_32                             = 0x51,
4032 	TC_OP_ATOMIC_UMIN_32                             = 0x52,
4033 	TC_OP_ATOMIC_SMAX_32                             = 0x53,
4034 	TC_OP_ATOMIC_UMAX_32                             = 0x54,
4035 	TC_OP_ATOMIC_AND_32                              = 0x55,
4036 	TC_OP_ATOMIC_OR_32                               = 0x56,
4037 	TC_OP_ATOMIC_XOR_32                              = 0x57,
4038 	TC_OP_ATOMIC_INC_32                              = 0x58,
4039 	TC_OP_ATOMIC_DEC_32                              = 0x59,
4040 	TC_OP_INVL2_VOL                                  = 0x5a,
4041 	TC_OP_RESERVED_NON_FLOAT_32_0                    = 0x5b,
4042 	TC_OP_RESERVED_NON_FLOAT_32_1                    = 0x5c,
4043 	TC_OP_RESERVED_NON_FLOAT_32_2                    = 0x5d,
4044 	TC_OP_RESERVED_NON_FLOAT_32_3                    = 0x5e,
4045 	TC_OP_RESERVED_NON_FLOAT_32_4                    = 0x5f,
4046 	TC_OP_WBINVL2                                    = 0x60,
4047 	TC_OP_ATOMIC_FCMPSWAP_64                         = 0x61,
4048 	TC_OP_ATOMIC_FMIN_64                             = 0x62,
4049 	TC_OP_ATOMIC_FMAX_64                             = 0x63,
4050 	TC_OP_RESERVED_FOP_64_0                          = 0x64,
4051 	TC_OP_RESERVED_FOP_64_1                          = 0x65,
4052 	TC_OP_RESERVED_FOP_64_2                          = 0x66,
4053 	TC_OP_ATOMIC_SWAP_64                             = 0x67,
4054 	TC_OP_ATOMIC_CMPSWAP_64                          = 0x68,
4055 	TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64            = 0x69,
4056 	TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64                = 0x6a,
4057 	TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64                = 0x6b,
4058 	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0             = 0x6c,
4059 	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1             = 0x6d,
4060 	TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2             = 0x6e,
4061 	TC_OP_ATOMIC_ADD_64                              = 0x6f,
4062 	TC_OP_ATOMIC_SUB_64                              = 0x70,
4063 	TC_OP_ATOMIC_SMIN_64                             = 0x71,
4064 	TC_OP_ATOMIC_UMIN_64                             = 0x72,
4065 	TC_OP_ATOMIC_SMAX_64                             = 0x73,
4066 	TC_OP_ATOMIC_UMAX_64                             = 0x74,
4067 	TC_OP_ATOMIC_AND_64                              = 0x75,
4068 	TC_OP_ATOMIC_OR_64                               = 0x76,
4069 	TC_OP_ATOMIC_XOR_64                              = 0x77,
4070 	TC_OP_ATOMIC_INC_64                              = 0x78,
4071 	TC_OP_ATOMIC_DEC_64                              = 0x79,
4072 	TC_OP_INVL1L2_VOL                                = 0x7a,
4073 	TC_OP_RESERVED_NON_FLOAT_64_0                    = 0x7b,
4074 	TC_OP_RESERVED_NON_FLOAT_64_1                    = 0x7c,
4075 	TC_OP_RESERVED_NON_FLOAT_64_2                    = 0x7d,
4076 	TC_OP_RESERVED_NON_FLOAT_64_3                    = 0x7e,
4077 	TC_OP_RESERVED_NON_FLOAT_64_4                    = 0x7f,
4078 } TC_OP;
4079 typedef enum TC_CHUB_REQ_CREDITS_ENUM {
4080 	TC_CHUB_REQ_CREDITS                              = 0x10,
4081 } TC_CHUB_REQ_CREDITS_ENUM;
4082 typedef enum CHUB_TC_RET_CREDITS_ENUM {
4083 	CHUB_TC_RET_CREDITS                              = 0x20,
4084 } CHUB_TC_RET_CREDITS_ENUM;
4085 typedef enum TC_NACKS {
4086 	TC_NACK_NO_FAULT                                 = 0x0,
4087 	TC_NACK_PAGE_FAULT                               = 0x1,
4088 	TC_NACK_PROTECTION_FAULT                         = 0x2,
4089 	TC_NACK_DATA_ERROR                               = 0x3,
4090 } TC_NACKS;
4091 typedef enum TCC_PERF_SEL {
4092 	TCC_PERF_SEL_NONE                                = 0x0,
4093 	TCC_PERF_SEL_CYCLE                               = 0x1,
4094 	TCC_PERF_SEL_BUSY                                = 0x2,
4095 	TCC_PERF_SEL_REQ                                 = 0x3,
4096 	TCC_PERF_SEL_STREAMING_REQ                       = 0x4,
4097 	TCC_PERF_SEL_READ                                = 0x5,
4098 	TCC_PERF_SEL_WRITE                               = 0x6,
4099 	TCC_PERF_SEL_ATOMIC                              = 0x7,
4100 	TCC_PERF_SEL_WBINVL2                             = 0x8,
4101 	TCC_PERF_SEL_WBINVL2_CYCLE                       = 0x9,
4102 	TCC_PERF_SEL_HIT                                 = 0xa,
4103 	TCC_PERF_SEL_MISS                                = 0xb,
4104 	TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT                = 0xc,
4105 	TCC_PERF_SEL_FULLY_WRITTEN_HIT                   = 0xd,
4106 	TCC_PERF_SEL_WRITEBACK                           = 0xe,
4107 	TCC_PERF_SEL_LATENCY_FIFO_FULL                   = 0xf,
4108 	TCC_PERF_SEL_SRC_FIFO_FULL                       = 0x10,
4109 	TCC_PERF_SEL_HOLE_FIFO_FULL                      = 0x11,
4110 	TCC_PERF_SEL_MC_WRREQ                            = 0x12,
4111 	TCC_PERF_SEL_MC_WRREQ_STALL                      = 0x13,
4112 	TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL               = 0x14,
4113 	TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL              = 0x15,
4114 	TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL            = 0x16,
4115 	TCC_PERF_SEL_MC_WRREQ_LEVEL                      = 0x17,
4116 	TCC_PERF_SEL_MC_RDREQ                            = 0x18,
4117 	TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL               = 0x19,
4118 	TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL              = 0x1a,
4119 	TCC_PERF_SEL_MC_RDREQ_LEVEL                      = 0x1b,
4120 	TCC_PERF_SEL_TAG_STALL                           = 0x1c,
4121 	TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL             = 0x1d,
4122 	TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL  = 0x1e,
4123 	TCC_PERF_SEL_READ_RETURN_TIMEOUT                 = 0x1f,
4124 	TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT              = 0x20,
4125 	TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE             = 0x21,
4126 	TCC_PERF_SEL_BUBBLE                              = 0x22,
4127 	TCC_PERF_SEL_RETURN_ACK                          = 0x23,
4128 	TCC_PERF_SEL_RETURN_DATA                         = 0x24,
4129 	TCC_PERF_SEL_RETURN_HOLE                         = 0x25,
4130 	TCC_PERF_SEL_RETURN_ACK_HOLE                     = 0x26,
4131 	TCC_PERF_SEL_IB_STALL                            = 0x27,
4132 	TCC_PERF_SEL_TCA_LEVEL                           = 0x28,
4133 	TCC_PERF_SEL_HOLE_LEVEL                          = 0x29,
4134 	TCC_PERF_SEL_MC_RDRET_NACK                       = 0x2a,
4135 	TCC_PERF_SEL_MC_WRRET_NACK                       = 0x2b,
4136 	TCC_PERF_SEL_EXE_REQ                             = 0x2c,
4137 	TCC_PERF_SEL_CLIENT0_REQ                         = 0x40,
4138 	TCC_PERF_SEL_CLIENT1_REQ                         = 0x41,
4139 	TCC_PERF_SEL_CLIENT2_REQ                         = 0x42,
4140 	TCC_PERF_SEL_CLIENT3_REQ                         = 0x43,
4141 	TCC_PERF_SEL_CLIENT4_REQ                         = 0x44,
4142 	TCC_PERF_SEL_CLIENT5_REQ                         = 0x45,
4143 	TCC_PERF_SEL_CLIENT6_REQ                         = 0x46,
4144 	TCC_PERF_SEL_CLIENT7_REQ                         = 0x47,
4145 	TCC_PERF_SEL_CLIENT8_REQ                         = 0x48,
4146 	TCC_PERF_SEL_CLIENT9_REQ                         = 0x49,
4147 	TCC_PERF_SEL_CLIENT10_REQ                        = 0x4a,
4148 	TCC_PERF_SEL_CLIENT11_REQ                        = 0x4b,
4149 	TCC_PERF_SEL_CLIENT12_REQ                        = 0x4c,
4150 	TCC_PERF_SEL_CLIENT13_REQ                        = 0x4d,
4151 	TCC_PERF_SEL_CLIENT14_REQ                        = 0x4e,
4152 	TCC_PERF_SEL_CLIENT15_REQ                        = 0x4f,
4153 	TCC_PERF_SEL_CLIENT16_REQ                        = 0x50,
4154 	TCC_PERF_SEL_CLIENT17_REQ                        = 0x51,
4155 	TCC_PERF_SEL_CLIENT18_REQ                        = 0x52,
4156 	TCC_PERF_SEL_CLIENT19_REQ                        = 0x53,
4157 	TCC_PERF_SEL_CLIENT20_REQ                        = 0x54,
4158 	TCC_PERF_SEL_CLIENT21_REQ                        = 0x55,
4159 	TCC_PERF_SEL_CLIENT22_REQ                        = 0x56,
4160 	TCC_PERF_SEL_CLIENT23_REQ                        = 0x57,
4161 	TCC_PERF_SEL_CLIENT24_REQ                        = 0x58,
4162 	TCC_PERF_SEL_CLIENT25_REQ                        = 0x59,
4163 	TCC_PERF_SEL_CLIENT26_REQ                        = 0x5a,
4164 	TCC_PERF_SEL_CLIENT27_REQ                        = 0x5b,
4165 	TCC_PERF_SEL_CLIENT28_REQ                        = 0x5c,
4166 	TCC_PERF_SEL_CLIENT29_REQ                        = 0x5d,
4167 	TCC_PERF_SEL_CLIENT30_REQ                        = 0x5e,
4168 	TCC_PERF_SEL_CLIENT31_REQ                        = 0x5f,
4169 	TCC_PERF_SEL_CLIENT32_REQ                        = 0x60,
4170 	TCC_PERF_SEL_CLIENT33_REQ                        = 0x61,
4171 	TCC_PERF_SEL_CLIENT34_REQ                        = 0x62,
4172 	TCC_PERF_SEL_CLIENT35_REQ                        = 0x63,
4173 	TCC_PERF_SEL_CLIENT36_REQ                        = 0x64,
4174 	TCC_PERF_SEL_CLIENT37_REQ                        = 0x65,
4175 	TCC_PERF_SEL_CLIENT38_REQ                        = 0x66,
4176 	TCC_PERF_SEL_CLIENT39_REQ                        = 0x67,
4177 	TCC_PERF_SEL_CLIENT40_REQ                        = 0x68,
4178 	TCC_PERF_SEL_CLIENT41_REQ                        = 0x69,
4179 	TCC_PERF_SEL_CLIENT42_REQ                        = 0x6a,
4180 	TCC_PERF_SEL_CLIENT43_REQ                        = 0x6b,
4181 	TCC_PERF_SEL_CLIENT44_REQ                        = 0x6c,
4182 	TCC_PERF_SEL_CLIENT45_REQ                        = 0x6d,
4183 	TCC_PERF_SEL_CLIENT46_REQ                        = 0x6e,
4184 	TCC_PERF_SEL_CLIENT47_REQ                        = 0x6f,
4185 	TCC_PERF_SEL_CLIENT48_REQ                        = 0x70,
4186 	TCC_PERF_SEL_CLIENT49_REQ                        = 0x71,
4187 	TCC_PERF_SEL_CLIENT50_REQ                        = 0x72,
4188 	TCC_PERF_SEL_CLIENT51_REQ                        = 0x73,
4189 	TCC_PERF_SEL_CLIENT52_REQ                        = 0x74,
4190 	TCC_PERF_SEL_CLIENT53_REQ                        = 0x75,
4191 	TCC_PERF_SEL_CLIENT54_REQ                        = 0x76,
4192 	TCC_PERF_SEL_CLIENT55_REQ                        = 0x77,
4193 	TCC_PERF_SEL_CLIENT56_REQ                        = 0x78,
4194 	TCC_PERF_SEL_CLIENT57_REQ                        = 0x79,
4195 	TCC_PERF_SEL_CLIENT58_REQ                        = 0x7a,
4196 	TCC_PERF_SEL_CLIENT59_REQ                        = 0x7b,
4197 	TCC_PERF_SEL_CLIENT60_REQ                        = 0x7c,
4198 	TCC_PERF_SEL_CLIENT61_REQ                        = 0x7d,
4199 	TCC_PERF_SEL_CLIENT62_REQ                        = 0x7e,
4200 	TCC_PERF_SEL_CLIENT63_REQ                        = 0x7f,
4201 	TCC_PERF_SEL_NORMAL_WRITEBACK                    = 0x80,
4202 	TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK            = 0x81,
4203 	TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK             = 0x82,
4204 	TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK              = 0x83,
4205 	TCC_PERF_SEL_NORMAL_EVICT                        = 0x84,
4206 	TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT               = 0x85,
4207 	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT             = 0x86,
4208 	TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT                = 0x87,
4209 	TCC_PERF_SEL_TC_OP_WBINVL2_EVICT                 = 0x88,
4210 	TCC_PERF_SEL_ALL_TC_OP_INV_EVICT                 = 0x89,
4211 	TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT             = 0x8a,
4212 	TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE                = 0x8b,
4213 	TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE               = 0x8c,
4214 	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE             = 0x8d,
4215 	TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE                 = 0x8e,
4216 	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE           = 0x8f,
4217 	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE       = 0x90,
4218 	TCC_PERF_SEL_TC_OP_WBL2_VOL_START                = 0x91,
4219 	TCC_PERF_SEL_TC_OP_INVL2_VOL_START               = 0x92,
4220 	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START             = 0x93,
4221 	TCC_PERF_SEL_TC_OP_WBINVL2_START                 = 0x94,
4222 	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START           = 0x95,
4223 	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START       = 0x96,
4224 	TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH               = 0x97,
4225 	TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH              = 0x98,
4226 	TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH            = 0x99,
4227 	TCC_PERF_SEL_TC_OP_WBINVL2_FINISH                = 0x9a,
4228 	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH          = 0x9b,
4229 	TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH      = 0x9c,
4230 	TCC_PERF_SEL_VOL_MC_WRREQ                        = 0x9d,
4231 	TCC_PERF_SEL_VOL_MC_RDREQ                        = 0x9e,
4232 	TCC_PERF_SEL_VOL_REQ                             = 0x9f,
4233 } TCC_PERF_SEL;
4234 typedef enum TCA_PERF_SEL {
4235 	TCA_PERF_SEL_NONE                                = 0x0,
4236 	TCA_PERF_SEL_CYCLE                               = 0x1,
4237 	TCA_PERF_SEL_BUSY                                = 0x2,
4238 	TCA_PERF_SEL_FORCED_HOLE_TCC0                    = 0x3,
4239 	TCA_PERF_SEL_FORCED_HOLE_TCC1                    = 0x4,
4240 	TCA_PERF_SEL_FORCED_HOLE_TCC2                    = 0x5,
4241 	TCA_PERF_SEL_FORCED_HOLE_TCC3                    = 0x6,
4242 	TCA_PERF_SEL_FORCED_HOLE_TCC4                    = 0x7,
4243 	TCA_PERF_SEL_FORCED_HOLE_TCC5                    = 0x8,
4244 	TCA_PERF_SEL_FORCED_HOLE_TCC6                    = 0x9,
4245 	TCA_PERF_SEL_FORCED_HOLE_TCC7                    = 0xa,
4246 	TCA_PERF_SEL_REQ_TCC0                            = 0xb,
4247 	TCA_PERF_SEL_REQ_TCC1                            = 0xc,
4248 	TCA_PERF_SEL_REQ_TCC2                            = 0xd,
4249 	TCA_PERF_SEL_REQ_TCC3                            = 0xe,
4250 	TCA_PERF_SEL_REQ_TCC4                            = 0xf,
4251 	TCA_PERF_SEL_REQ_TCC5                            = 0x10,
4252 	TCA_PERF_SEL_REQ_TCC6                            = 0x11,
4253 	TCA_PERF_SEL_REQ_TCC7                            = 0x12,
4254 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0            = 0x13,
4255 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1            = 0x14,
4256 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2            = 0x15,
4257 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3            = 0x16,
4258 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4            = 0x17,
4259 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5            = 0x18,
4260 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6            = 0x19,
4261 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7            = 0x1a,
4262 	TCA_PERF_SEL_CROSSBAR_STALL_TCC0                 = 0x1b,
4263 	TCA_PERF_SEL_CROSSBAR_STALL_TCC1                 = 0x1c,
4264 	TCA_PERF_SEL_CROSSBAR_STALL_TCC2                 = 0x1d,
4265 	TCA_PERF_SEL_CROSSBAR_STALL_TCC3                 = 0x1e,
4266 	TCA_PERF_SEL_CROSSBAR_STALL_TCC4                 = 0x1f,
4267 	TCA_PERF_SEL_CROSSBAR_STALL_TCC5                 = 0x20,
4268 	TCA_PERF_SEL_CROSSBAR_STALL_TCC6                 = 0x21,
4269 	TCA_PERF_SEL_CROSSBAR_STALL_TCC7                 = 0x22,
4270 	TCA_PERF_SEL_FORCED_HOLE_TCS                     = 0x23,
4271 	TCA_PERF_SEL_REQ_TCS                             = 0x24,
4272 	TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS             = 0x25,
4273 	TCA_PERF_SEL_CROSSBAR_STALL_TCS                  = 0x26,
4274 } TCA_PERF_SEL;
4275 typedef enum TCS_PERF_SEL {
4276 	TCS_PERF_SEL_NONE                                = 0x0,
4277 	TCS_PERF_SEL_CYCLE                               = 0x1,
4278 	TCS_PERF_SEL_BUSY                                = 0x2,
4279 	TCS_PERF_SEL_REQ                                 = 0x3,
4280 	TCS_PERF_SEL_READ                                = 0x4,
4281 	TCS_PERF_SEL_WRITE                               = 0x5,
4282 	TCS_PERF_SEL_ATOMIC                              = 0x6,
4283 	TCS_PERF_SEL_HOLE_FIFO_FULL                      = 0x7,
4284 	TCS_PERF_SEL_REQ_FIFO_FULL                       = 0x8,
4285 	TCS_PERF_SEL_REQ_CREDIT_STALL                    = 0x9,
4286 	TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL               = 0xa,
4287 	TCS_PERF_SEL_REQ_STALL                           = 0xb,
4288 	TCS_PERF_SEL_TCS_CHUB_REQ_SEND                   = 0xc,
4289 	TCS_PERF_SEL_CHUB_TCS_RET_SEND                   = 0xd,
4290 	TCS_PERF_SEL_RETURN_ACK                          = 0xe,
4291 	TCS_PERF_SEL_RETURN_DATA                         = 0xf,
4292 	TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL             = 0x10,
4293 	TCS_PERF_SEL_IB_STALL                            = 0x11,
4294 	TCS_PERF_SEL_TCA_LEVEL                           = 0x12,
4295 	TCS_PERF_SEL_HOLE_LEVEL                          = 0x13,
4296 	TCS_PERF_SEL_CHUB_LEVEL                          = 0x14,
4297 	TCS_PERF_SEL_CLIENT0_REQ                         = 0x40,
4298 	TCS_PERF_SEL_CLIENT1_REQ                         = 0x41,
4299 	TCS_PERF_SEL_CLIENT2_REQ                         = 0x42,
4300 	TCS_PERF_SEL_CLIENT3_REQ                         = 0x43,
4301 	TCS_PERF_SEL_CLIENT4_REQ                         = 0x44,
4302 	TCS_PERF_SEL_CLIENT5_REQ                         = 0x45,
4303 	TCS_PERF_SEL_CLIENT6_REQ                         = 0x46,
4304 	TCS_PERF_SEL_CLIENT7_REQ                         = 0x47,
4305 	TCS_PERF_SEL_CLIENT8_REQ                         = 0x48,
4306 	TCS_PERF_SEL_CLIENT9_REQ                         = 0x49,
4307 	TCS_PERF_SEL_CLIENT10_REQ                        = 0x4a,
4308 	TCS_PERF_SEL_CLIENT11_REQ                        = 0x4b,
4309 	TCS_PERF_SEL_CLIENT12_REQ                        = 0x4c,
4310 	TCS_PERF_SEL_CLIENT13_REQ                        = 0x4d,
4311 	TCS_PERF_SEL_CLIENT14_REQ                        = 0x4e,
4312 	TCS_PERF_SEL_CLIENT15_REQ                        = 0x4f,
4313 	TCS_PERF_SEL_CLIENT16_REQ                        = 0x50,
4314 	TCS_PERF_SEL_CLIENT17_REQ                        = 0x51,
4315 	TCS_PERF_SEL_CLIENT18_REQ                        = 0x52,
4316 	TCS_PERF_SEL_CLIENT19_REQ                        = 0x53,
4317 	TCS_PERF_SEL_CLIENT20_REQ                        = 0x54,
4318 	TCS_PERF_SEL_CLIENT21_REQ                        = 0x55,
4319 	TCS_PERF_SEL_CLIENT22_REQ                        = 0x56,
4320 	TCS_PERF_SEL_CLIENT23_REQ                        = 0x57,
4321 	TCS_PERF_SEL_CLIENT24_REQ                        = 0x58,
4322 	TCS_PERF_SEL_CLIENT25_REQ                        = 0x59,
4323 	TCS_PERF_SEL_CLIENT26_REQ                        = 0x5a,
4324 	TCS_PERF_SEL_CLIENT27_REQ                        = 0x5b,
4325 	TCS_PERF_SEL_CLIENT28_REQ                        = 0x5c,
4326 	TCS_PERF_SEL_CLIENT29_REQ                        = 0x5d,
4327 	TCS_PERF_SEL_CLIENT30_REQ                        = 0x5e,
4328 	TCS_PERF_SEL_CLIENT31_REQ                        = 0x5f,
4329 	TCS_PERF_SEL_CLIENT32_REQ                        = 0x60,
4330 	TCS_PERF_SEL_CLIENT33_REQ                        = 0x61,
4331 	TCS_PERF_SEL_CLIENT34_REQ                        = 0x62,
4332 	TCS_PERF_SEL_CLIENT35_REQ                        = 0x63,
4333 	TCS_PERF_SEL_CLIENT36_REQ                        = 0x64,
4334 	TCS_PERF_SEL_CLIENT37_REQ                        = 0x65,
4335 	TCS_PERF_SEL_CLIENT38_REQ                        = 0x66,
4336 	TCS_PERF_SEL_CLIENT39_REQ                        = 0x67,
4337 	TCS_PERF_SEL_CLIENT40_REQ                        = 0x68,
4338 	TCS_PERF_SEL_CLIENT41_REQ                        = 0x69,
4339 	TCS_PERF_SEL_CLIENT42_REQ                        = 0x6a,
4340 	TCS_PERF_SEL_CLIENT43_REQ                        = 0x6b,
4341 	TCS_PERF_SEL_CLIENT44_REQ                        = 0x6c,
4342 	TCS_PERF_SEL_CLIENT45_REQ                        = 0x6d,
4343 	TCS_PERF_SEL_CLIENT46_REQ                        = 0x6e,
4344 	TCS_PERF_SEL_CLIENT47_REQ                        = 0x6f,
4345 	TCS_PERF_SEL_CLIENT48_REQ                        = 0x70,
4346 	TCS_PERF_SEL_CLIENT49_REQ                        = 0x71,
4347 	TCS_PERF_SEL_CLIENT50_REQ                        = 0x72,
4348 	TCS_PERF_SEL_CLIENT51_REQ                        = 0x73,
4349 	TCS_PERF_SEL_CLIENT52_REQ                        = 0x74,
4350 	TCS_PERF_SEL_CLIENT53_REQ                        = 0x75,
4351 	TCS_PERF_SEL_CLIENT54_REQ                        = 0x76,
4352 	TCS_PERF_SEL_CLIENT55_REQ                        = 0x77,
4353 	TCS_PERF_SEL_CLIENT56_REQ                        = 0x78,
4354 	TCS_PERF_SEL_CLIENT57_REQ                        = 0x79,
4355 	TCS_PERF_SEL_CLIENT58_REQ                        = 0x7a,
4356 	TCS_PERF_SEL_CLIENT59_REQ                        = 0x7b,
4357 	TCS_PERF_SEL_CLIENT60_REQ                        = 0x7c,
4358 	TCS_PERF_SEL_CLIENT61_REQ                        = 0x7d,
4359 	TCS_PERF_SEL_CLIENT62_REQ                        = 0x7e,
4360 	TCS_PERF_SEL_CLIENT63_REQ                        = 0x7f,
4361 } TCS_PERF_SEL;
4362 typedef enum TA_TC_ADDR_MODES {
4363 	TA_TC_ADDR_MODE_DEFAULT                          = 0x0,
4364 	TA_TC_ADDR_MODE_COMP0                            = 0x1,
4365 	TA_TC_ADDR_MODE_COMP1                            = 0x2,
4366 	TA_TC_ADDR_MODE_COMP2                            = 0x3,
4367 	TA_TC_ADDR_MODE_COMP3                            = 0x4,
4368 	TA_TC_ADDR_MODE_UNALIGNED                        = 0x5,
4369 	TA_TC_ADDR_MODE_BORDER_COLOR                     = 0x6,
4370 } TA_TC_ADDR_MODES;
4371 typedef enum TA_PERFCOUNT_SEL {
4372 	TA_PERF_SEL_ta_busy                              = 0x0,
4373 	TA_PERF_SEL_sh_fifo_busy                         = 0x1,
4374 	TA_PERF_SEL_sh_fifo_cmd_busy                     = 0x2,
4375 	TA_PERF_SEL_sh_fifo_addr_busy                    = 0x3,
4376 	TA_PERF_SEL_sh_fifo_data_busy                    = 0x4,
4377 	TA_PERF_SEL_sh_fifo_data_sfifo_busy              = 0x5,
4378 	TA_PERF_SEL_sh_fifo_data_tfifo_busy              = 0x6,
4379 	TA_PERF_SEL_gradient_busy                        = 0x7,
4380 	TA_PERF_SEL_gradient_fifo_busy                   = 0x8,
4381 	TA_PERF_SEL_lod_busy                             = 0x9,
4382 	TA_PERF_SEL_lod_fifo_busy                        = 0xa,
4383 	TA_PERF_SEL_addresser_busy                       = 0xb,
4384 	TA_PERF_SEL_addresser_fifo_busy                  = 0xc,
4385 	TA_PERF_SEL_aligner_busy                         = 0xd,
4386 	TA_PERF_SEL_write_path_busy                      = 0xe,
4387 	TA_PERF_SEL_RESERVED_15                          = 0xf,
4388 	TA_PERF_SEL_sq_ta_cmd_cycles                     = 0x10,
4389 	TA_PERF_SEL_sp_ta_addr_cycles                    = 0x11,
4390 	TA_PERF_SEL_sp_ta_data_cycles                    = 0x12,
4391 	TA_PERF_SEL_ta_fa_data_state_cycles              = 0x13,
4392 	TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles   = 0x14,
4393 	TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles   = 0x15,
4394 	TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16,
4395 	TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17,
4396 	TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18,
4397 	TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19,
4398 	TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a,
4399 	TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b,
4400 	TA_PERF_SEL_RESERVED_28                          = 0x1c,
4401 	TA_PERF_SEL_RESERVED_29                          = 0x1d,
4402 	TA_PERF_SEL_sh_fifo_addr_cycles                  = 0x1e,
4403 	TA_PERF_SEL_sh_fifo_data_cycles                  = 0x1f,
4404 	TA_PERF_SEL_total_wavefronts                     = 0x20,
4405 	TA_PERF_SEL_gradient_cycles                      = 0x21,
4406 	TA_PERF_SEL_walker_cycles                        = 0x22,
4407 	TA_PERF_SEL_aligner_cycles                       = 0x23,
4408 	TA_PERF_SEL_image_wavefronts                     = 0x24,
4409 	TA_PERF_SEL_image_read_wavefronts                = 0x25,
4410 	TA_PERF_SEL_image_write_wavefronts               = 0x26,
4411 	TA_PERF_SEL_image_atomic_wavefronts              = 0x27,
4412 	TA_PERF_SEL_image_total_cycles                   = 0x28,
4413 	TA_PERF_SEL_RESERVED_41                          = 0x29,
4414 	TA_PERF_SEL_RESERVED_42                          = 0x2a,
4415 	TA_PERF_SEL_RESERVED_43                          = 0x2b,
4416 	TA_PERF_SEL_buffer_wavefronts                    = 0x2c,
4417 	TA_PERF_SEL_buffer_read_wavefronts               = 0x2d,
4418 	TA_PERF_SEL_buffer_write_wavefronts              = 0x2e,
4419 	TA_PERF_SEL_buffer_atomic_wavefronts             = 0x2f,
4420 	TA_PERF_SEL_buffer_coalescable_wavefronts        = 0x30,
4421 	TA_PERF_SEL_buffer_total_cycles                  = 0x31,
4422 	TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32,
4423 	TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33,
4424 	TA_PERF_SEL_buffer_coalesced_read_cycles         = 0x34,
4425 	TA_PERF_SEL_buffer_coalesced_write_cycles        = 0x35,
4426 	TA_PERF_SEL_addr_stalled_by_tc_cycles            = 0x36,
4427 	TA_PERF_SEL_addr_stalled_by_td_cycles            = 0x37,
4428 	TA_PERF_SEL_data_stalled_by_tc_cycles            = 0x38,
4429 	TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39,
4430 	TA_PERF_SEL_addresser_stalled_cycles             = 0x3a,
4431 	TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b,
4432 	TA_PERF_SEL_aniso_stalled_cycles                 = 0x3c,
4433 	TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles   = 0x3d,
4434 	TA_PERF_SEL_deriv_stalled_cycles                 = 0x3e,
4435 	TA_PERF_SEL_aniso_gt1_cycle_quads                = 0x3f,
4436 	TA_PERF_SEL_color_1_cycle_pixels                 = 0x40,
4437 	TA_PERF_SEL_color_2_cycle_pixels                 = 0x41,
4438 	TA_PERF_SEL_color_3_cycle_pixels                 = 0x42,
4439 	TA_PERF_SEL_color_4_cycle_pixels                 = 0x43,
4440 	TA_PERF_SEL_mip_1_cycle_pixels                   = 0x44,
4441 	TA_PERF_SEL_mip_2_cycle_pixels                   = 0x45,
4442 	TA_PERF_SEL_vol_1_cycle_pixels                   = 0x46,
4443 	TA_PERF_SEL_vol_2_cycle_pixels                   = 0x47,
4444 	TA_PERF_SEL_bilin_point_1_cycle_pixels           = 0x48,
4445 	TA_PERF_SEL_mipmap_lod_0_samples                 = 0x49,
4446 	TA_PERF_SEL_mipmap_lod_1_samples                 = 0x4a,
4447 	TA_PERF_SEL_mipmap_lod_2_samples                 = 0x4b,
4448 	TA_PERF_SEL_mipmap_lod_3_samples                 = 0x4c,
4449 	TA_PERF_SEL_mipmap_lod_4_samples                 = 0x4d,
4450 	TA_PERF_SEL_mipmap_lod_5_samples                 = 0x4e,
4451 	TA_PERF_SEL_mipmap_lod_6_samples                 = 0x4f,
4452 	TA_PERF_SEL_mipmap_lod_7_samples                 = 0x50,
4453 	TA_PERF_SEL_mipmap_lod_8_samples                 = 0x51,
4454 	TA_PERF_SEL_mipmap_lod_9_samples                 = 0x52,
4455 	TA_PERF_SEL_mipmap_lod_10_samples                = 0x53,
4456 	TA_PERF_SEL_mipmap_lod_11_samples                = 0x54,
4457 	TA_PERF_SEL_mipmap_lod_12_samples                = 0x55,
4458 	TA_PERF_SEL_mipmap_lod_13_samples                = 0x56,
4459 	TA_PERF_SEL_mipmap_lod_14_samples                = 0x57,
4460 	TA_PERF_SEL_mipmap_invalid_samples               = 0x58,
4461 	TA_PERF_SEL_aniso_1_cycle_quads                  = 0x59,
4462 	TA_PERF_SEL_aniso_2_cycle_quads                  = 0x5a,
4463 	TA_PERF_SEL_aniso_4_cycle_quads                  = 0x5b,
4464 	TA_PERF_SEL_aniso_6_cycle_quads                  = 0x5c,
4465 	TA_PERF_SEL_aniso_8_cycle_quads                  = 0x5d,
4466 	TA_PERF_SEL_aniso_10_cycle_quads                 = 0x5e,
4467 	TA_PERF_SEL_aniso_12_cycle_quads                 = 0x5f,
4468 	TA_PERF_SEL_aniso_14_cycle_quads                 = 0x60,
4469 	TA_PERF_SEL_aniso_16_cycle_quads                 = 0x61,
4470 	TA_PERF_SEL_write_path_input_cycles              = 0x62,
4471 	TA_PERF_SEL_write_path_output_cycles             = 0x63,
4472 	TA_PERF_SEL_flat_wavefronts                      = 0x64,
4473 	TA_PERF_SEL_flat_read_wavefronts                 = 0x65,
4474 	TA_PERF_SEL_flat_write_wavefronts                = 0x66,
4475 	TA_PERF_SEL_flat_atomic_wavefronts               = 0x67,
4476 	TA_PERF_SEL_flat_coalesceable_wavefronts         = 0x68,
4477 	TA_PERF_SEL_reg_sclk_vld                         = 0x69,
4478 	TA_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6a,
4479 	TA_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x6b,
4480 	TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en       = 0x6c,
4481 	TA_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x6d,
4482 	TA_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x6e,
4483 } TA_PERFCOUNT_SEL;
4484 typedef enum TD_PERFCOUNT_SEL {
4485 	TD_PERF_SEL_td_busy                              = 0x0,
4486 	TD_PERF_SEL_input_busy                           = 0x1,
4487 	TD_PERF_SEL_output_busy                          = 0x2,
4488 	TD_PERF_SEL_lerp_busy                            = 0x3,
4489 	TD_PERF_SEL_RESERVED_4                           = 0x4,
4490 	TD_PERF_SEL_reg_sclk_vld                         = 0x5,
4491 	TD_PERF_SEL_local_cg_dyn_sclk_grp0_en            = 0x6,
4492 	TD_PERF_SEL_local_cg_dyn_sclk_grp1_en            = 0x7,
4493 	TD_PERF_SEL_local_cg_dyn_sclk_grp4_en            = 0x8,
4494 	TD_PERF_SEL_local_cg_dyn_sclk_grp5_en            = 0x9,
4495 	TD_PERF_SEL_tc_td_fifo_full                      = 0xa,
4496 	TD_PERF_SEL_constant_state_full                  = 0xb,
4497 	TD_PERF_SEL_sample_state_full                    = 0xc,
4498 	TD_PERF_SEL_output_fifo_full                     = 0xd,
4499 	TD_PERF_SEL_RESERVED_14                          = 0xe,
4500 	TD_PERF_SEL_tc_stall                             = 0xf,
4501 	TD_PERF_SEL_pc_stall                             = 0x10,
4502 	TD_PERF_SEL_gds_stall                            = 0x11,
4503 	TD_PERF_SEL_RESERVED_18                          = 0x12,
4504 	TD_PERF_SEL_RESERVED_19                          = 0x13,
4505 	TD_PERF_SEL_gather4_wavefront                    = 0x14,
4506 	TD_PERF_SEL_sample_c_wavefront                   = 0x15,
4507 	TD_PERF_SEL_load_wavefront                       = 0x16,
4508 	TD_PERF_SEL_atomic_wavefront                     = 0x17,
4509 	TD_PERF_SEL_store_wavefront                      = 0x18,
4510 	TD_PERF_SEL_ldfptr_wavefront                     = 0x19,
4511 	TD_PERF_SEL_RESERVED_26                          = 0x1a,
4512 	TD_PERF_SEL_RESERVED_27                          = 0x1b,
4513 	TD_PERF_SEL_RESERVED_28                          = 0x1c,
4514 	TD_PERF_SEL_RESERVED_29                          = 0x1d,
4515 	TD_PERF_SEL_bypass_filter_wavefront              = 0x1e,
4516 	TD_PERF_SEL_min_max_filter_wavefront             = 0x1f,
4517 	TD_PERF_SEL_coalescable_wavefront                = 0x20,
4518 	TD_PERF_SEL_coalesced_phase                      = 0x21,
4519 	TD_PERF_SEL_four_phase_wavefront                 = 0x22,
4520 	TD_PERF_SEL_eight_phase_wavefront                = 0x23,
4521 	TD_PERF_SEL_sixteen_phase_wavefront              = 0x24,
4522 	TD_PERF_SEL_four_phase_forward_wavefront         = 0x25,
4523 	TD_PERF_SEL_write_ack_wavefront                  = 0x26,
4524 	TD_PERF_SEL_RESERVED_39                          = 0x27,
4525 	TD_PERF_SEL_user_defined_border                  = 0x28,
4526 	TD_PERF_SEL_white_border                         = 0x29,
4527 	TD_PERF_SEL_opaque_black_border                  = 0x2a,
4528 	TD_PERF_SEL_RESERVED_43                          = 0x2b,
4529 	TD_PERF_SEL_RESERVED_44                          = 0x2c,
4530 	TD_PERF_SEL_nack                                 = 0x2d,
4531 	TD_PERF_SEL_td_sp_traffic                        = 0x2e,
4532 	TD_PERF_SEL_consume_gds_traffic                  = 0x2f,
4533 	TD_PERF_SEL_addresscmd_poison                    = 0x30,
4534 	TD_PERF_SEL_data_poison                          = 0x31,
4535 	TD_PERF_SEL_start_cycle_0                        = 0x32,
4536 	TD_PERF_SEL_start_cycle_1                        = 0x33,
4537 	TD_PERF_SEL_start_cycle_2                        = 0x34,
4538 	TD_PERF_SEL_start_cycle_3                        = 0x35,
4539 	TD_PERF_SEL_null_cycle_output                    = 0x36,
4540 } TD_PERFCOUNT_SEL;
4541 typedef enum TCP_PERFCOUNT_SELECT {
4542 	TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES           = 0x0,
4543 	TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES           = 0x1,
4544 	TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES            = 0x2,
4545 	TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES            = 0x3,
4546 	TCP_PERF_SEL_TD_TCP_STALL_CYCLES                 = 0x4,
4547 	TCP_PERF_SEL_TCR_TCP_STALL_CYCLES                = 0x5,
4548 	TCP_PERF_SEL_LOD_STALL_CYCLES                    = 0x6,
4549 	TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES       = 0x7,
4550 	TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES      = 0x8,
4551 	TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES     = 0x9,
4552 	TCP_PERF_SEL_ALLOC_STALL_CYCLES                  = 0xa,
4553 	TCP_PERF_SEL_LFIFO_STALL_CYCLES                  = 0xb,
4554 	TCP_PERF_SEL_RFIFO_STALL_CYCLES                  = 0xc,
4555 	TCP_PERF_SEL_TCR_RDRET_STALL                     = 0xd,
4556 	TCP_PERF_SEL_WRITE_CONFLICT_STALL                = 0xe,
4557 	TCP_PERF_SEL_HOLE_READ_STALL                     = 0xf,
4558 	TCP_PERF_SEL_READCONFLICT_STALL_CYCLES           = 0x10,
4559 	TCP_PERF_SEL_PENDING_STALL_CYCLES                = 0x11,
4560 	TCP_PERF_SEL_READFIFO_STALL_CYCLES               = 0x12,
4561 	TCP_PERF_SEL_TCP_LATENCY                         = 0x13,
4562 	TCP_PERF_SEL_TCC_READ_REQ_LATENCY                = 0x14,
4563 	TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY               = 0x15,
4564 	TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY          = 0x16,
4565 	TCP_PERF_SEL_TCC_READ_REQ                        = 0x17,
4566 	TCP_PERF_SEL_TCC_WRITE_REQ                       = 0x18,
4567 	TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ             = 0x19,
4568 	TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ          = 0x1a,
4569 	TCP_PERF_SEL_TOTAL_LOCAL_READ                    = 0x1b,
4570 	TCP_PERF_SEL_TOTAL_GLOBAL_READ                   = 0x1c,
4571 	TCP_PERF_SEL_TOTAL_LOCAL_WRITE                   = 0x1d,
4572 	TCP_PERF_SEL_TOTAL_GLOBAL_WRITE                  = 0x1e,
4573 	TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET               = 0x1f,
4574 	TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET            = 0x20,
4575 	TCP_PERF_SEL_TOTAL_WBINVL1                       = 0x21,
4576 	TCP_PERF_SEL_IMG_READ_FMT_1                      = 0x22,
4577 	TCP_PERF_SEL_IMG_READ_FMT_8                      = 0x23,
4578 	TCP_PERF_SEL_IMG_READ_FMT_16                     = 0x24,
4579 	TCP_PERF_SEL_IMG_READ_FMT_32                     = 0x25,
4580 	TCP_PERF_SEL_IMG_READ_FMT_32_AS_8                = 0x26,
4581 	TCP_PERF_SEL_IMG_READ_FMT_32_AS_16               = 0x27,
4582 	TCP_PERF_SEL_IMG_READ_FMT_32_AS_128              = 0x28,
4583 	TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE             = 0x29,
4584 	TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE             = 0x2a,
4585 	TCP_PERF_SEL_IMG_READ_FMT_96                     = 0x2b,
4586 	TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE            = 0x2c,
4587 	TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE            = 0x2d,
4588 	TCP_PERF_SEL_IMG_READ_FMT_BC1                    = 0x2e,
4589 	TCP_PERF_SEL_IMG_READ_FMT_BC2                    = 0x2f,
4590 	TCP_PERF_SEL_IMG_READ_FMT_BC3                    = 0x30,
4591 	TCP_PERF_SEL_IMG_READ_FMT_BC4                    = 0x31,
4592 	TCP_PERF_SEL_IMG_READ_FMT_BC5                    = 0x32,
4593 	TCP_PERF_SEL_IMG_READ_FMT_BC6                    = 0x33,
4594 	TCP_PERF_SEL_IMG_READ_FMT_BC7                    = 0x34,
4595 	TCP_PERF_SEL_IMG_READ_FMT_I8                     = 0x35,
4596 	TCP_PERF_SEL_IMG_READ_FMT_I16                    = 0x36,
4597 	TCP_PERF_SEL_IMG_READ_FMT_I32                    = 0x37,
4598 	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8               = 0x38,
4599 	TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16              = 0x39,
4600 	TCP_PERF_SEL_IMG_READ_FMT_D8                     = 0x3a,
4601 	TCP_PERF_SEL_IMG_READ_FMT_D16                    = 0x3b,
4602 	TCP_PERF_SEL_IMG_READ_FMT_D32                    = 0x3c,
4603 	TCP_PERF_SEL_IMG_WRITE_FMT_8                     = 0x3d,
4604 	TCP_PERF_SEL_IMG_WRITE_FMT_16                    = 0x3e,
4605 	TCP_PERF_SEL_IMG_WRITE_FMT_32                    = 0x3f,
4606 	TCP_PERF_SEL_IMG_WRITE_FMT_64                    = 0x40,
4607 	TCP_PERF_SEL_IMG_WRITE_FMT_128                   = 0x41,
4608 	TCP_PERF_SEL_IMG_WRITE_FMT_D8                    = 0x42,
4609 	TCP_PERF_SEL_IMG_WRITE_FMT_D16                   = 0x43,
4610 	TCP_PERF_SEL_IMG_WRITE_FMT_D32                   = 0x44,
4611 	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32          = 0x45,
4612 	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32       = 0x46,
4613 	TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64          = 0x47,
4614 	TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64       = 0x48,
4615 	TCP_PERF_SEL_BUF_READ_FMT_8                      = 0x49,
4616 	TCP_PERF_SEL_BUF_READ_FMT_16                     = 0x4a,
4617 	TCP_PERF_SEL_BUF_READ_FMT_32                     = 0x4b,
4618 	TCP_PERF_SEL_BUF_WRITE_FMT_8                     = 0x4c,
4619 	TCP_PERF_SEL_BUF_WRITE_FMT_16                    = 0x4d,
4620 	TCP_PERF_SEL_BUF_WRITE_FMT_32                    = 0x4e,
4621 	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32          = 0x4f,
4622 	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32       = 0x50,
4623 	TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64          = 0x51,
4624 	TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64       = 0x52,
4625 	TCP_PERF_SEL_ARR_LINEAR_GENERAL                  = 0x53,
4626 	TCP_PERF_SEL_ARR_LINEAR_ALIGNED                  = 0x54,
4627 	TCP_PERF_SEL_ARR_1D_THIN1                        = 0x55,
4628 	TCP_PERF_SEL_ARR_1D_THICK                        = 0x56,
4629 	TCP_PERF_SEL_ARR_2D_THIN1                        = 0x57,
4630 	TCP_PERF_SEL_ARR_2D_THICK                        = 0x58,
4631 	TCP_PERF_SEL_ARR_2D_XTHICK                       = 0x59,
4632 	TCP_PERF_SEL_ARR_3D_THIN1                        = 0x5a,
4633 	TCP_PERF_SEL_ARR_3D_THICK                        = 0x5b,
4634 	TCP_PERF_SEL_ARR_3D_XTHICK                       = 0x5c,
4635 	TCP_PERF_SEL_DIM_1D                              = 0x5d,
4636 	TCP_PERF_SEL_DIM_2D                              = 0x5e,
4637 	TCP_PERF_SEL_DIM_3D                              = 0x5f,
4638 	TCP_PERF_SEL_DIM_1D_ARRAY                        = 0x60,
4639 	TCP_PERF_SEL_DIM_2D_ARRAY                        = 0x61,
4640 	TCP_PERF_SEL_DIM_2D_MSAA                         = 0x62,
4641 	TCP_PERF_SEL_DIM_2D_ARRAY_MSAA                   = 0x63,
4642 	TCP_PERF_SEL_DIM_CUBE_ARRAY                      = 0x64,
4643 	TCP_PERF_SEL_CP_TCP_INVALIDATE                   = 0x65,
4644 	TCP_PERF_SEL_TA_TCP_STATE_READ                   = 0x66,
4645 	TCP_PERF_SEL_TAGRAM0_REQ                         = 0x67,
4646 	TCP_PERF_SEL_TAGRAM1_REQ                         = 0x68,
4647 	TCP_PERF_SEL_TAGRAM2_REQ                         = 0x69,
4648 	TCP_PERF_SEL_TAGRAM3_REQ                         = 0x6a,
4649 	TCP_PERF_SEL_GATE_EN1                            = 0x6b,
4650 	TCP_PERF_SEL_GATE_EN2                            = 0x6c,
4651 	TCP_PERF_SEL_CORE_REG_SCLK_VLD                   = 0x6d,
4652 	TCP_PERF_SEL_TCC_REQ                             = 0x6e,
4653 	TCP_PERF_SEL_TCC_NON_READ_REQ                    = 0x6f,
4654 	TCP_PERF_SEL_TCC_BYPASS_READ_REQ                 = 0x70,
4655 	TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ             = 0x71,
4656 	TCP_PERF_SEL_TCC_VOLATILE_READ_REQ               = 0x72,
4657 	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ        = 0x73,
4658 	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ    = 0x74,
4659 	TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ                = 0x75,
4660 	TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ            = 0x76,
4661 	TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ       = 0x77,
4662 	TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ              = 0x78,
4663 	TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ   = 0x79,
4664 	TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ               = 0x7a,
4665 	TCP_PERF_SEL_TCC_ATOMIC_REQ                      = 0x7b,
4666 	TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ             = 0x7c,
4667 	TCP_PERF_SEL_TCC_DATA_BUS_BUSY                   = 0x7d,
4668 	TCP_PERF_SEL_TOTAL_ACCESSES                      = 0x7e,
4669 	TCP_PERF_SEL_TOTAL_READ                          = 0x7f,
4670 	TCP_PERF_SEL_TOTAL_HIT_LRU_READ                  = 0x80,
4671 	TCP_PERF_SEL_TOTAL_HIT_EVICT_READ                = 0x81,
4672 	TCP_PERF_SEL_TOTAL_MISS_LRU_READ                 = 0x82,
4673 	TCP_PERF_SEL_TOTAL_MISS_EVICT_READ               = 0x83,
4674 	TCP_PERF_SEL_TOTAL_NON_READ                      = 0x84,
4675 	TCP_PERF_SEL_TOTAL_WRITE                         = 0x85,
4676 	TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE                = 0x86,
4677 	TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE              = 0x87,
4678 	TCP_PERF_SEL_TOTAL_WBINVL1_VOL                   = 0x88,
4679 	TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES         = 0x89,
4680 	TCP_PERF_SEL_DISPLAY_MICROTILING                 = 0x8a,
4681 	TCP_PERF_SEL_THIN_MICROTILING                    = 0x8b,
4682 	TCP_PERF_SEL_DEPTH_MICROTILING                   = 0x8c,
4683 	TCP_PERF_SEL_ARR_PRT_THIN1                       = 0x8d,
4684 	TCP_PERF_SEL_ARR_PRT_2D_THIN1                    = 0x8e,
4685 	TCP_PERF_SEL_ARR_PRT_3D_THIN1                    = 0x8f,
4686 	TCP_PERF_SEL_ARR_PRT_THICK                       = 0x90,
4687 	TCP_PERF_SEL_ARR_PRT_2D_THICK                    = 0x91,
4688 	TCP_PERF_SEL_ARR_PRT_3D_THICK                    = 0x92,
4689 	TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL               = 0x93,
4690 	TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL               = 0x94,
4691 	TCP_PERF_SEL_UNALIGNED                           = 0x95,
4692 	TCP_PERF_SEL_ROTATED_MICROTILING                 = 0x96,
4693 	TCP_PERF_SEL_THICK_MICROTILING                   = 0x97,
4694 	TCP_PERF_SEL_ATC                                 = 0x98,
4695 	TCP_PERF_SEL_POWER_STALL                         = 0x99,
4696 } TCP_PERFCOUNT_SELECT;
4697 typedef enum TCP_CACHE_POLICIES {
4698 	TCP_CACHE_POLICY_MISS_LRU                        = 0x0,
4699 	TCP_CACHE_POLICY_MISS_EVICT                      = 0x1,
4700 	TCP_CACHE_POLICY_HIT_LRU                         = 0x2,
4701 	TCP_CACHE_POLICY_HIT_EVICT                       = 0x3,
4702 } TCP_CACHE_POLICIES;
4703 typedef enum TCP_CACHE_STORE_POLICIES {
4704 	TCP_CACHE_STORE_POLICY_MISS_LRU                  = 0x0,
4705 	TCP_CACHE_STORE_POLICY_MISS_EVICT                = 0x1,
4706 } TCP_CACHE_STORE_POLICIES;
4707 typedef enum TCP_WATCH_MODES {
4708 	TCP_WATCH_MODE_READ                              = 0x0,
4709 	TCP_WATCH_MODE_NONREAD                           = 0x1,
4710 	TCP_WATCH_MODE_ATOMIC                            = 0x2,
4711 	TCP_WATCH_MODE_ALL                               = 0x3,
4712 } TCP_WATCH_MODES;
4713 typedef enum VGT_OUT_PRIM_TYPE {
4714 	VGT_OUT_POINT                                    = 0x0,
4715 	VGT_OUT_LINE                                     = 0x1,
4716 	VGT_OUT_TRI                                      = 0x2,
4717 	VGT_OUT_RECT_V0                                  = 0x3,
4718 	VGT_OUT_RECT_V1                                  = 0x4,
4719 	VGT_OUT_RECT_V2                                  = 0x5,
4720 	VGT_OUT_RECT_V3                                  = 0x6,
4721 	VGT_OUT_RESERVED                                 = 0x7,
4722 	VGT_TE_QUAD                                      = 0x8,
4723 	VGT_TE_PRIM_INDEX_LINE                           = 0x9,
4724 	VGT_TE_PRIM_INDEX_TRI                            = 0xa,
4725 	VGT_TE_PRIM_INDEX_QUAD                           = 0xb,
4726 	VGT_OUT_LINE_ADJ                                 = 0xc,
4727 	VGT_OUT_TRI_ADJ                                  = 0xd,
4728 	VGT_OUT_PATCH                                    = 0xe,
4729 } VGT_OUT_PRIM_TYPE;
4730 typedef enum VGT_DI_PRIM_TYPE {
4731 	DI_PT_NONE                                       = 0x0,
4732 	DI_PT_POINTLIST                                  = 0x1,
4733 	DI_PT_LINELIST                                   = 0x2,
4734 	DI_PT_LINESTRIP                                  = 0x3,
4735 	DI_PT_TRILIST                                    = 0x4,
4736 	DI_PT_TRIFAN                                     = 0x5,
4737 	DI_PT_TRISTRIP                                   = 0x6,
4738 	DI_PT_UNUSED_0                                   = 0x7,
4739 	DI_PT_UNUSED_1                                   = 0x8,
4740 	DI_PT_PATCH                                      = 0x9,
4741 	DI_PT_LINELIST_ADJ                               = 0xa,
4742 	DI_PT_LINESTRIP_ADJ                              = 0xb,
4743 	DI_PT_TRILIST_ADJ                                = 0xc,
4744 	DI_PT_TRISTRIP_ADJ                               = 0xd,
4745 	DI_PT_UNUSED_3                                   = 0xe,
4746 	DI_PT_UNUSED_4                                   = 0xf,
4747 	DI_PT_TRI_WITH_WFLAGS                            = 0x10,
4748 	DI_PT_RECTLIST                                   = 0x11,
4749 	DI_PT_LINELOOP                                   = 0x12,
4750 	DI_PT_QUADLIST                                   = 0x13,
4751 	DI_PT_QUADSTRIP                                  = 0x14,
4752 	DI_PT_POLYGON                                    = 0x15,
4753 	DI_PT_2D_COPY_RECT_LIST_V0                       = 0x16,
4754 	DI_PT_2D_COPY_RECT_LIST_V1                       = 0x17,
4755 	DI_PT_2D_COPY_RECT_LIST_V2                       = 0x18,
4756 	DI_PT_2D_COPY_RECT_LIST_V3                       = 0x19,
4757 	DI_PT_2D_FILL_RECT_LIST                          = 0x1a,
4758 	DI_PT_2D_LINE_STRIP                              = 0x1b,
4759 	DI_PT_2D_TRI_STRIP                               = 0x1c,
4760 } VGT_DI_PRIM_TYPE;
4761 typedef enum VGT_DI_SOURCE_SELECT {
4762 	DI_SRC_SEL_DMA                                   = 0x0,
4763 	DI_SRC_SEL_IMMEDIATE                             = 0x1,
4764 	DI_SRC_SEL_AUTO_INDEX                            = 0x2,
4765 	DI_SRC_SEL_RESERVED                              = 0x3,
4766 } VGT_DI_SOURCE_SELECT;
4767 typedef enum VGT_DI_MAJOR_MODE_SELECT {
4768 	DI_MAJOR_MODE_0                                  = 0x0,
4769 	DI_MAJOR_MODE_1                                  = 0x1,
4770 } VGT_DI_MAJOR_MODE_SELECT;
4771 typedef enum VGT_DI_INDEX_SIZE {
4772 	DI_INDEX_SIZE_16_BIT                             = 0x0,
4773 	DI_INDEX_SIZE_32_BIT                             = 0x1,
4774 } VGT_DI_INDEX_SIZE;
4775 typedef enum VGT_EVENT_TYPE {
4776 	Reserved_0x00                                    = 0x0,
4777 	SAMPLE_STREAMOUTSTATS1                           = 0x1,
4778 	SAMPLE_STREAMOUTSTATS2                           = 0x2,
4779 	SAMPLE_STREAMOUTSTATS3                           = 0x3,
4780 	CACHE_FLUSH_TS                                   = 0x4,
4781 	CONTEXT_DONE                                     = 0x5,
4782 	CACHE_FLUSH                                      = 0x6,
4783 	CS_PARTIAL_FLUSH                                 = 0x7,
4784 	VGT_STREAMOUT_SYNC                               = 0x8,
4785 	Reserved_0x09                                    = 0x9,
4786 	VGT_STREAMOUT_RESET                              = 0xa,
4787 	END_OF_PIPE_INCR_DE                              = 0xb,
4788 	END_OF_PIPE_IB_END                               = 0xc,
4789 	RST_PIX_CNT                                      = 0xd,
4790 	Reserved_0x0E                                    = 0xe,
4791 	VS_PARTIAL_FLUSH                                 = 0xf,
4792 	PS_PARTIAL_FLUSH                                 = 0x10,
4793 	FLUSH_HS_OUTPUT                                  = 0x11,
4794 	FLUSH_LS_OUTPUT                                  = 0x12,
4795 	Reserved_0x13                                    = 0x13,
4796 	CACHE_FLUSH_AND_INV_TS_EVENT                     = 0x14,
4797 	ZPASS_DONE                                       = 0x15,
4798 	CACHE_FLUSH_AND_INV_EVENT                        = 0x16,
4799 	PERFCOUNTER_START                                = 0x17,
4800 	PERFCOUNTER_STOP                                 = 0x18,
4801 	PIPELINESTAT_START                               = 0x19,
4802 	PIPELINESTAT_STOP                                = 0x1a,
4803 	PERFCOUNTER_SAMPLE                               = 0x1b,
4804 	FLUSH_ES_OUTPUT                                  = 0x1c,
4805 	FLUSH_GS_OUTPUT                                  = 0x1d,
4806 	SAMPLE_PIPELINESTAT                              = 0x1e,
4807 	SO_VGTSTREAMOUT_FLUSH                            = 0x1f,
4808 	SAMPLE_STREAMOUTSTATS                            = 0x20,
4809 	RESET_VTX_CNT                                    = 0x21,
4810 	BLOCK_CONTEXT_DONE                               = 0x22,
4811 	CS_CONTEXT_DONE                                  = 0x23,
4812 	VGT_FLUSH                                        = 0x24,
4813 	Reserved_0x25                                    = 0x25,
4814 	SQ_NON_EVENT                                     = 0x26,
4815 	SC_SEND_DB_VPZ                                   = 0x27,
4816 	BOTTOM_OF_PIPE_TS                                = 0x28,
4817 	FLUSH_SX_TS                                      = 0x29,
4818 	DB_CACHE_FLUSH_AND_INV                           = 0x2a,
4819 	FLUSH_AND_INV_DB_DATA_TS                         = 0x2b,
4820 	FLUSH_AND_INV_DB_META                            = 0x2c,
4821 	FLUSH_AND_INV_CB_DATA_TS                         = 0x2d,
4822 	FLUSH_AND_INV_CB_META                            = 0x2e,
4823 	CS_DONE                                          = 0x2f,
4824 	PS_DONE                                          = 0x30,
4825 	FLUSH_AND_INV_CB_PIXEL_DATA                      = 0x31,
4826 	SX_CB_RAT_ACK_REQUEST                            = 0x32,
4827 	THREAD_TRACE_START                               = 0x33,
4828 	THREAD_TRACE_STOP                                = 0x34,
4829 	THREAD_TRACE_MARKER                              = 0x35,
4830 	THREAD_TRACE_FLUSH                               = 0x36,
4831 	THREAD_TRACE_FINISH                              = 0x37,
4832 	PIXEL_PIPE_STAT_CONTROL                          = 0x38,
4833 	PIXEL_PIPE_STAT_DUMP                             = 0x39,
4834 	PIXEL_PIPE_STAT_RESET                            = 0x3a,
4835 	CONTEXT_SUSPEND                                  = 0x3b,
4836 } VGT_EVENT_TYPE;
4837 typedef enum VGT_DMA_SWAP_MODE {
4838 	VGT_DMA_SWAP_NONE                                = 0x0,
4839 	VGT_DMA_SWAP_16_BIT                              = 0x1,
4840 	VGT_DMA_SWAP_32_BIT                              = 0x2,
4841 	VGT_DMA_SWAP_WORD                                = 0x3,
4842 } VGT_DMA_SWAP_MODE;
4843 typedef enum VGT_INDEX_TYPE_MODE {
4844 	VGT_INDEX_16                                     = 0x0,
4845 	VGT_INDEX_32                                     = 0x1,
4846 } VGT_INDEX_TYPE_MODE;
4847 typedef enum VGT_DMA_BUF_TYPE {
4848 	VGT_DMA_BUF_MEM                                  = 0x0,
4849 	VGT_DMA_BUF_RING                                 = 0x1,
4850 	VGT_DMA_BUF_SETUP                                = 0x2,
4851 } VGT_DMA_BUF_TYPE;
4852 typedef enum VGT_OUTPATH_SELECT {
4853 	VGT_OUTPATH_VTX_REUSE                            = 0x0,
4854 	VGT_OUTPATH_TESS_EN                              = 0x1,
4855 	VGT_OUTPATH_PASSTHRU                             = 0x2,
4856 	VGT_OUTPATH_GS_BLOCK                             = 0x3,
4857 	VGT_OUTPATH_HS_BLOCK                             = 0x4,
4858 } VGT_OUTPATH_SELECT;
4859 typedef enum VGT_GRP_PRIM_TYPE {
4860 	VGT_GRP_3D_POINT                                 = 0x0,
4861 	VGT_GRP_3D_LINE                                  = 0x1,
4862 	VGT_GRP_3D_TRI                                   = 0x2,
4863 	VGT_GRP_3D_RECT                                  = 0x3,
4864 	VGT_GRP_3D_QUAD                                  = 0x4,
4865 	VGT_GRP_2D_COPY_RECT_V0                          = 0x5,
4866 	VGT_GRP_2D_COPY_RECT_V1                          = 0x6,
4867 	VGT_GRP_2D_COPY_RECT_V2                          = 0x7,
4868 	VGT_GRP_2D_COPY_RECT_V3                          = 0x8,
4869 	VGT_GRP_2D_FILL_RECT                             = 0x9,
4870 	VGT_GRP_2D_LINE                                  = 0xa,
4871 	VGT_GRP_2D_TRI                                   = 0xb,
4872 	VGT_GRP_PRIM_INDEX_LINE                          = 0xc,
4873 	VGT_GRP_PRIM_INDEX_TRI                           = 0xd,
4874 	VGT_GRP_PRIM_INDEX_QUAD                          = 0xe,
4875 	VGT_GRP_3D_LINE_ADJ                              = 0xf,
4876 	VGT_GRP_3D_TRI_ADJ                               = 0x10,
4877 	VGT_GRP_3D_PATCH                                 = 0x11,
4878 } VGT_GRP_PRIM_TYPE;
4879 typedef enum VGT_GRP_PRIM_ORDER {
4880 	VGT_GRP_LIST                                     = 0x0,
4881 	VGT_GRP_STRIP                                    = 0x1,
4882 	VGT_GRP_FAN                                      = 0x2,
4883 	VGT_GRP_LOOP                                     = 0x3,
4884 	VGT_GRP_POLYGON                                  = 0x4,
4885 } VGT_GRP_PRIM_ORDER;
4886 typedef enum VGT_GROUP_CONV_SEL {
4887 	VGT_GRP_INDEX_16                                 = 0x0,
4888 	VGT_GRP_INDEX_32                                 = 0x1,
4889 	VGT_GRP_UINT_16                                  = 0x2,
4890 	VGT_GRP_UINT_32                                  = 0x3,
4891 	VGT_GRP_SINT_16                                  = 0x4,
4892 	VGT_GRP_SINT_32                                  = 0x5,
4893 	VGT_GRP_FLOAT_32                                 = 0x6,
4894 	VGT_GRP_AUTO_PRIM                                = 0x7,
4895 	VGT_GRP_FIX_1_23_TO_FLOAT                        = 0x8,
4896 } VGT_GROUP_CONV_SEL;
4897 typedef enum VGT_GS_MODE_TYPE {
4898 	GS_OFF                                           = 0x0,
4899 	GS_SCENARIO_A                                    = 0x1,
4900 	GS_SCENARIO_B                                    = 0x2,
4901 	GS_SCENARIO_G                                    = 0x3,
4902 	GS_SCENARIO_C                                    = 0x4,
4903 	SPRITE_EN                                        = 0x5,
4904 } VGT_GS_MODE_TYPE;
4905 typedef enum VGT_GS_CUT_MODE {
4906 	GS_CUT_1024                                      = 0x0,
4907 	GS_CUT_512                                       = 0x1,
4908 	GS_CUT_256                                       = 0x2,
4909 	GS_CUT_128                                       = 0x3,
4910 } VGT_GS_CUT_MODE;
4911 typedef enum VGT_GS_OUTPRIM_TYPE {
4912 	POINTLIST                                        = 0x0,
4913 	LINESTRIP                                        = 0x1,
4914 	TRISTRIP                                         = 0x2,
4915 } VGT_GS_OUTPRIM_TYPE;
4916 typedef enum VGT_CACHE_INVALID_MODE {
4917 	VC_ONLY                                          = 0x0,
4918 	TC_ONLY                                          = 0x1,
4919 	VC_AND_TC                                        = 0x2,
4920 } VGT_CACHE_INVALID_MODE;
4921 typedef enum VGT_TESS_TYPE {
4922 	TESS_ISOLINE                                     = 0x0,
4923 	TESS_TRIANGLE                                    = 0x1,
4924 	TESS_QUAD                                        = 0x2,
4925 } VGT_TESS_TYPE;
4926 typedef enum VGT_TESS_PARTITION {
4927 	PART_INTEGER                                     = 0x0,
4928 	PART_POW2                                        = 0x1,
4929 	PART_FRAC_ODD                                    = 0x2,
4930 	PART_FRAC_EVEN                                   = 0x3,
4931 } VGT_TESS_PARTITION;
4932 typedef enum VGT_TESS_TOPOLOGY {
4933 	OUTPUT_POINT                                     = 0x0,
4934 	OUTPUT_LINE                                      = 0x1,
4935 	OUTPUT_TRIANGLE_CW                               = 0x2,
4936 	OUTPUT_TRIANGLE_CCW                              = 0x3,
4937 } VGT_TESS_TOPOLOGY;
4938 typedef enum VGT_RDREQ_POLICY {
4939 	VGT_POLICY_LRU                                   = 0x0,
4940 	VGT_POLICY_STREAM                                = 0x1,
4941 	VGT_POLICY_BYPASS                                = 0x2,
4942 	VGT_POLICY_RESERVED                              = 0x3,
4943 } VGT_RDREQ_POLICY;
4944 typedef enum VGT_STAGES_LS_EN {
4945 	LS_STAGE_OFF                                     = 0x0,
4946 	LS_STAGE_ON                                      = 0x1,
4947 	CS_STAGE_ON                                      = 0x2,
4948 	RESERVED_LS                                      = 0x3,
4949 } VGT_STAGES_LS_EN;
4950 typedef enum VGT_STAGES_HS_EN {
4951 	HS_STAGE_OFF                                     = 0x0,
4952 	HS_STAGE_ON                                      = 0x1,
4953 } VGT_STAGES_HS_EN;
4954 typedef enum VGT_STAGES_ES_EN {
4955 	ES_STAGE_OFF                                     = 0x0,
4956 	ES_STAGE_DS                                      = 0x1,
4957 	ES_STAGE_REAL                                    = 0x2,
4958 	RESERVED_ES                                      = 0x3,
4959 } VGT_STAGES_ES_EN;
4960 typedef enum VGT_STAGES_GS_EN {
4961 	GS_STAGE_OFF                                     = 0x0,
4962 	GS_STAGE_ON                                      = 0x1,
4963 } VGT_STAGES_GS_EN;
4964 typedef enum VGT_STAGES_VS_EN {
4965 	VS_STAGE_REAL                                    = 0x0,
4966 	VS_STAGE_DS                                      = 0x1,
4967 	VS_STAGE_COPY_SHADER                             = 0x2,
4968 	RESERVED_VS                                      = 0x3,
4969 } VGT_STAGES_VS_EN;
4970 typedef enum VGT_PERFCOUNT_SELECT {
4971 	vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE    = 0x0,
4972 	vgt_perf_VGT_SPI_ESVERT_VALID                    = 0x1,
4973 	vgt_perf_VGT_SPI_ESVERT_EOV                      = 0x2,
4974 	vgt_perf_VGT_SPI_ESVERT_STALLED                  = 0x3,
4975 	vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY             = 0x4,
4976 	vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE             = 0x5,
4977 	vgt_perf_VGT_SPI_ESVERT_STATIC                   = 0x6,
4978 	vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT               = 0x7,
4979 	vgt_perf_VGT_SPI_ESTHREAD_SEND                   = 0x8,
4980 	vgt_perf_VGT_SPI_GSPRIM_VALID                    = 0x9,
4981 	vgt_perf_VGT_SPI_GSPRIM_EOV                      = 0xa,
4982 	vgt_perf_VGT_SPI_GSPRIM_CONT                     = 0xb,
4983 	vgt_perf_VGT_SPI_GSPRIM_STALLED                  = 0xc,
4984 	vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY             = 0xd,
4985 	vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE             = 0xe,
4986 	vgt_perf_VGT_SPI_GSPRIM_STATIC                   = 0xf,
4987 	vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE    = 0x10,
4988 	vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT               = 0x11,
4989 	vgt_perf_VGT_SPI_GSTHREAD_SEND                   = 0x12,
4990 	vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE    = 0x13,
4991 	vgt_perf_VGT_SPI_VSVERT_SEND                     = 0x14,
4992 	vgt_perf_VGT_SPI_VSVERT_EOV                      = 0x15,
4993 	vgt_perf_VGT_SPI_VSVERT_STALLED                  = 0x16,
4994 	vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY             = 0x17,
4995 	vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE             = 0x18,
4996 	vgt_perf_VGT_SPI_VSVERT_STATIC                   = 0x19,
4997 	vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT               = 0x1a,
4998 	vgt_perf_VGT_SPI_VSTHREAD_SEND                   = 0x1b,
4999 	vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE              = 0x1c,
5000 	vgt_perf_VGT_PA_CLIPV_SEND                       = 0x1d,
5001 	vgt_perf_VGT_PA_CLIPV_FIRSTVERT                  = 0x1e,
5002 	vgt_perf_VGT_PA_CLIPV_STALLED                    = 0x1f,
5003 	vgt_perf_VGT_PA_CLIPV_STARVED_BUSY               = 0x20,
5004 	vgt_perf_VGT_PA_CLIPV_STARVED_IDLE               = 0x21,
5005 	vgt_perf_VGT_PA_CLIPV_STATIC                     = 0x22,
5006 	vgt_perf_VGT_PA_CLIPP_SEND                       = 0x23,
5007 	vgt_perf_VGT_PA_CLIPP_EOP                        = 0x24,
5008 	vgt_perf_VGT_PA_CLIPP_IS_EVENT                   = 0x25,
5009 	vgt_perf_VGT_PA_CLIPP_NULL_PRIM                  = 0x26,
5010 	vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT               = 0x27,
5011 	vgt_perf_VGT_PA_CLIPP_STALLED                    = 0x28,
5012 	vgt_perf_VGT_PA_CLIPP_STARVED_BUSY               = 0x29,
5013 	vgt_perf_VGT_PA_CLIPP_STARVED_IDLE               = 0x2a,
5014 	vgt_perf_VGT_PA_CLIPP_STATIC                     = 0x2b,
5015 	vgt_perf_VGT_PA_CLIPS_SEND                       = 0x2c,
5016 	vgt_perf_VGT_PA_CLIPS_STALLED                    = 0x2d,
5017 	vgt_perf_VGT_PA_CLIPS_STARVED_BUSY               = 0x2e,
5018 	vgt_perf_VGT_PA_CLIPS_STARVED_IDLE               = 0x2f,
5019 	vgt_perf_VGT_PA_CLIPS_STATIC                     = 0x30,
5020 	vgt_perf_vsvert_ds_send                          = 0x31,
5021 	vgt_perf_vsvert_api_send                         = 0x32,
5022 	vgt_perf_hs_tif_stall                            = 0x33,
5023 	vgt_perf_hs_input_stall                          = 0x34,
5024 	vgt_perf_hs_interface_stall                      = 0x35,
5025 	vgt_perf_hs_tfm_stall                            = 0x36,
5026 	vgt_perf_te11_starved                            = 0x37,
5027 	vgt_perf_gs_event_stall                          = 0x38,
5028 	vgt_perf_vgt_pa_clipp_send_not_event             = 0x39,
5029 	vgt_perf_vgt_pa_clipp_valid_prim                 = 0x3a,
5030 	vgt_perf_reused_es_indices                       = 0x3b,
5031 	vgt_perf_vs_cache_hits                           = 0x3c,
5032 	vgt_perf_gs_cache_hits                           = 0x3d,
5033 	vgt_perf_ds_cache_hits                           = 0x3e,
5034 	vgt_perf_total_cache_hits                        = 0x3f,
5035 	vgt_perf_vgt_busy                                = 0x40,
5036 	vgt_perf_vgt_gs_busy                             = 0x41,
5037 	vgt_perf_esvert_stalled_es_tbl                   = 0x42,
5038 	vgt_perf_esvert_stalled_gs_tbl                   = 0x43,
5039 	vgt_perf_esvert_stalled_gs_event                 = 0x44,
5040 	vgt_perf_esvert_stalled_gsprim                   = 0x45,
5041 	vgt_perf_gsprim_stalled_es_tbl                   = 0x46,
5042 	vgt_perf_gsprim_stalled_gs_tbl                   = 0x47,
5043 	vgt_perf_gsprim_stalled_gs_event                 = 0x48,
5044 	vgt_perf_gsprim_stalled_esvert                   = 0x49,
5045 	vgt_perf_esthread_stalled_es_rb_full             = 0x4a,
5046 	vgt_perf_esthread_stalled_spi_bp                 = 0x4b,
5047 	vgt_perf_counters_avail_stalled                  = 0x4c,
5048 	vgt_perf_gs_rb_space_avail_stalled               = 0x4d,
5049 	vgt_perf_gs_issue_rtr_stalled                    = 0x4e,
5050 	vgt_perf_gsthread_stalled                        = 0x4f,
5051 	vgt_perf_strmout_stalled                         = 0x50,
5052 	vgt_perf_wait_for_es_done_stalled                = 0x51,
5053 	vgt_perf_cm_stalled_by_gog                       = 0x52,
5054 	vgt_perf_cm_reading_stalled                      = 0x53,
5055 	vgt_perf_cm_stalled_by_gsfetch_done              = 0x54,
5056 	vgt_perf_gog_vs_tbl_stalled                      = 0x55,
5057 	vgt_perf_gog_out_indx_stalled                    = 0x56,
5058 	vgt_perf_gog_out_prim_stalled                    = 0x57,
5059 	vgt_perf_waveid_stalled                          = 0x58,
5060 	vgt_perf_gog_busy                                = 0x59,
5061 	vgt_perf_reused_vs_indices                       = 0x5a,
5062 	vgt_perf_sclk_reg_vld_event                      = 0x5b,
5063 	vgt_perf_RESERVED0                               = 0x5c,
5064 	vgt_perf_sclk_core_vld_event                     = 0x5d,
5065 	vgt_perf_RESERVED1                               = 0x5e,
5066 	vgt_perf_sclk_gs_vld_event                       = 0x5f,
5067 	vgt_perf_VGT_SPI_LSVERT_VALID                    = 0x60,
5068 	vgt_perf_VGT_SPI_LSVERT_EOV                      = 0x61,
5069 	vgt_perf_VGT_SPI_LSVERT_STALLED                  = 0x62,
5070 	vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY             = 0x63,
5071 	vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE             = 0x64,
5072 	vgt_perf_VGT_SPI_LSVERT_STATIC                   = 0x65,
5073 	vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE      = 0x66,
5074 	vgt_perf_VGT_SPI_LSWAVE_IS_EVENT                 = 0x67,
5075 	vgt_perf_VGT_SPI_LSWAVE_SEND                     = 0x68,
5076 	vgt_perf_VGT_SPI_HSVERT_VALID                    = 0x69,
5077 	vgt_perf_VGT_SPI_HSVERT_EOV                      = 0x6a,
5078 	vgt_perf_VGT_SPI_HSVERT_STALLED                  = 0x6b,
5079 	vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY             = 0x6c,
5080 	vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE             = 0x6d,
5081 	vgt_perf_VGT_SPI_HSVERT_STATIC                   = 0x6e,
5082 	vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE      = 0x6f,
5083 	vgt_perf_VGT_SPI_HSWAVE_IS_EVENT                 = 0x70,
5084 	vgt_perf_VGT_SPI_HSWAVE_SEND                     = 0x71,
5085 	vgt_perf_ds_prims                                = 0x72,
5086 	vgt_perf_null_tess_patches                       = 0x73,
5087 	vgt_perf_ls_thread_groups                        = 0x74,
5088 	vgt_perf_hs_thread_groups                        = 0x75,
5089 	vgt_perf_es_thread_groups                        = 0x76,
5090 	vgt_perf_vs_thread_groups                        = 0x77,
5091 	vgt_perf_ls_done_latency                         = 0x78,
5092 	vgt_perf_hs_done_latency                         = 0x79,
5093 	vgt_perf_es_done_latency                         = 0x7a,
5094 	vgt_perf_gs_done_latency                         = 0x7b,
5095 	vgt_perf_vgt_hs_busy                             = 0x7c,
5096 	vgt_perf_vgt_te11_busy                           = 0x7d,
5097 	vgt_perf_ls_flush                                = 0x7e,
5098 	vgt_perf_hs_flush                                = 0x7f,
5099 	vgt_perf_es_flush                                = 0x80,
5100 	vgt_perf_gs_flush                                = 0x81,
5101 	vgt_perf_ls_done                                 = 0x82,
5102 	vgt_perf_hs_done                                 = 0x83,
5103 	vgt_perf_es_done                                 = 0x84,
5104 	vgt_perf_gs_done                                 = 0x85,
5105 	vgt_perf_vsfetch_done                            = 0x86,
5106 	vgt_perf_RESERVED2                               = 0x87,
5107 	vgt_perf_es_ring_high_water_mark                 = 0x88,
5108 	vgt_perf_gs_ring_high_water_mark                 = 0x89,
5109 	vgt_perf_vs_table_high_water_mark                = 0x8a,
5110 	vgt_perf_hs_tgs_active_high_water_mark           = 0x8b,
5111 } VGT_PERFCOUNT_SELECT;
5112 typedef enum IA_PERFCOUNT_SELECT {
5113 	ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE            = 0x0,
5114 	ia_perf_MC_LAT_BIN_0                             = 0x1,
5115 	ia_perf_MC_LAT_BIN_1                             = 0x2,
5116 	ia_perf_MC_LAT_BIN_2                             = 0x3,
5117 	ia_perf_MC_LAT_BIN_3                             = 0x4,
5118 	ia_perf_MC_LAT_BIN_4                             = 0x5,
5119 	ia_perf_MC_LAT_BIN_5                             = 0x6,
5120 	ia_perf_MC_LAT_BIN_6                             = 0x7,
5121 	ia_perf_MC_LAT_BIN_7                             = 0x8,
5122 	ia_perf_ia_busy                                  = 0x9,
5123 	ia_perf_ia_sclk_reg_vld_event                    = 0xa,
5124 	ia_perf_RESERVED0                                = 0xb,
5125 	ia_perf_ia_sclk_core_vld_event                   = 0xc,
5126 	ia_perf_RESERVED1                                = 0xd,
5127 	ia_perf_ia_dma_return                            = 0xe,
5128 	ia_perf_shift_starved_pipe1_event                = 0xf,
5129 	ia_perf_shift_starved_pipe0_event                = 0x10,
5130 	ia_perf_ia_stalled                               = 0x11,
5131 } IA_PERFCOUNT_SELECT;
5132 typedef enum WD_PERFCOUNT_SELECT {
5133 	wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE           = 0x0,
5134 	wd_perf_RBIU_DR_FIFO_STARVED                     = 0x1,
5135 	wd_perf_RBIU_DR_FIFO_STALLED                     = 0x2,
5136 	wd_perf_RBIU_DI_FIFO_STARVED                     = 0x3,
5137 	wd_perf_RBIU_DI_FIFO_STALLED                     = 0x4,
5138 	wd_perf_wd_busy                                  = 0x5,
5139 	wd_perf_wd_sclk_reg_vld_event                    = 0x6,
5140 	wd_perf_wd_sclk_input_vld_event                  = 0x7,
5141 	wd_perf_wd_sclk_core_vld_event                   = 0x8,
5142 	wd_perf_wd_stalled                               = 0x9,
5143 } WD_PERFCOUNT_SELECT;
5144 typedef enum WD_IA_DRAW_TYPE {
5145 	WD_IA_DRAW_TYPE_DI_MM0                           = 0x0,
5146 	WD_IA_DRAW_TYPE_DI_MM1                           = 0x1,
5147 	WD_IA_DRAW_TYPE_EVENT_INIT                       = 0x2,
5148 	WD_IA_DRAW_TYPE_EVENT_ADDR                       = 0x3,
5149 	WD_IA_DRAW_TYPE_MIN_INDX                         = 0x4,
5150 	WD_IA_DRAW_TYPE_MAX_INDX                         = 0x5,
5151 	WD_IA_DRAW_TYPE_INDX_OFF                         = 0x6,
5152 	WD_IA_DRAW_TYPE_IMM_DATA                         = 0x7,
5153 } WD_IA_DRAW_TYPE;
5154 #define GSTHREADID_SIZE                           0x2
5155 typedef enum SurfaceEndian {
5156 	ENDIAN_NONE                                      = 0x0,
5157 	ENDIAN_8IN16                                     = 0x1,
5158 	ENDIAN_8IN32                                     = 0x2,
5159 	ENDIAN_8IN64                                     = 0x3,
5160 } SurfaceEndian;
5161 typedef enum ArrayMode {
5162 	ARRAY_LINEAR_GENERAL                             = 0x0,
5163 	ARRAY_LINEAR_ALIGNED                             = 0x1,
5164 	ARRAY_1D_TILED_THIN1                             = 0x2,
5165 	ARRAY_1D_TILED_THICK                             = 0x3,
5166 	ARRAY_2D_TILED_THIN1                             = 0x4,
5167 	ARRAY_PRT_TILED_THIN1                            = 0x5,
5168 	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
5169 	ARRAY_2D_TILED_THICK                             = 0x7,
5170 	ARRAY_2D_TILED_XTHICK                            = 0x8,
5171 	ARRAY_PRT_TILED_THICK                            = 0x9,
5172 	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
5173 	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
5174 	ARRAY_3D_TILED_THIN1                             = 0xc,
5175 	ARRAY_3D_TILED_THICK                             = 0xd,
5176 	ARRAY_3D_TILED_XTHICK                            = 0xe,
5177 	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
5178 } ArrayMode;
5179 typedef enum PipeTiling {
5180 	CONFIG_1_PIPE                                    = 0x0,
5181 	CONFIG_2_PIPE                                    = 0x1,
5182 	CONFIG_4_PIPE                                    = 0x2,
5183 	CONFIG_8_PIPE                                    = 0x3,
5184 } PipeTiling;
5185 typedef enum BankTiling {
5186 	CONFIG_4_BANK                                    = 0x0,
5187 	CONFIG_8_BANK                                    = 0x1,
5188 } BankTiling;
5189 typedef enum GroupInterleave {
5190 	CONFIG_256B_GROUP                                = 0x0,
5191 	CONFIG_512B_GROUP                                = 0x1,
5192 } GroupInterleave;
5193 typedef enum RowTiling {
5194 	CONFIG_1KB_ROW                                   = 0x0,
5195 	CONFIG_2KB_ROW                                   = 0x1,
5196 	CONFIG_4KB_ROW                                   = 0x2,
5197 	CONFIG_8KB_ROW                                   = 0x3,
5198 	CONFIG_1KB_ROW_OPT                               = 0x4,
5199 	CONFIG_2KB_ROW_OPT                               = 0x5,
5200 	CONFIG_4KB_ROW_OPT                               = 0x6,
5201 	CONFIG_8KB_ROW_OPT                               = 0x7,
5202 } RowTiling;
5203 typedef enum BankSwapBytes {
5204 	CONFIG_128B_SWAPS                                = 0x0,
5205 	CONFIG_256B_SWAPS                                = 0x1,
5206 	CONFIG_512B_SWAPS                                = 0x2,
5207 	CONFIG_1KB_SWAPS                                 = 0x3,
5208 } BankSwapBytes;
5209 typedef enum SampleSplitBytes {
5210 	CONFIG_1KB_SPLIT                                 = 0x0,
5211 	CONFIG_2KB_SPLIT                                 = 0x1,
5212 	CONFIG_4KB_SPLIT                                 = 0x2,
5213 	CONFIG_8KB_SPLIT                                 = 0x3,
5214 } SampleSplitBytes;
5215 typedef enum NumPipes {
5216 	ADDR_CONFIG_1_PIPE                               = 0x0,
5217 	ADDR_CONFIG_2_PIPE                               = 0x1,
5218 	ADDR_CONFIG_4_PIPE                               = 0x2,
5219 	ADDR_CONFIG_8_PIPE                               = 0x3,
5220 	ADDR_CONFIG_16_PIPE                              = 0x4,
5221 } NumPipes;
5222 typedef enum PipeInterleaveSize {
5223 	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
5224 	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
5225 } PipeInterleaveSize;
5226 typedef enum BankInterleaveSize {
5227 	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
5228 	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
5229 	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
5230 	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
5231 } BankInterleaveSize;
5232 typedef enum NumShaderEngines {
5233 	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
5234 	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
5235 } NumShaderEngines;
5236 typedef enum ShaderEngineTileSize {
5237 	ADDR_CONFIG_SE_TILE_16                           = 0x0,
5238 	ADDR_CONFIG_SE_TILE_32                           = 0x1,
5239 } ShaderEngineTileSize;
5240 typedef enum NumGPUs {
5241 	ADDR_CONFIG_1_GPU                                = 0x0,
5242 	ADDR_CONFIG_2_GPU                                = 0x1,
5243 	ADDR_CONFIG_4_GPU                                = 0x2,
5244 } NumGPUs;
5245 typedef enum MultiGPUTileSize {
5246 	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
5247 	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
5248 	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
5249 	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
5250 } MultiGPUTileSize;
5251 typedef enum RowSize {
5252 	ADDR_CONFIG_1KB_ROW                              = 0x0,
5253 	ADDR_CONFIG_2KB_ROW                              = 0x1,
5254 	ADDR_CONFIG_4KB_ROW                              = 0x2,
5255 } RowSize;
5256 typedef enum NumLowerPipes {
5257 	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
5258 	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
5259 } NumLowerPipes;
5260 typedef enum DebugBlockId {
5261 	DBG_CLIENT_BLKID_RESERVED                        = 0x0,
5262 	DBG_CLIENT_BLKID_dbg                             = 0x1,
5263 	DBG_CLIENT_BLKID_dco0                            = 0x2,
5264 	DBG_CLIENT_BLKID_wd                              = 0x3,
5265 	DBG_CLIENT_BLKID_vmc                             = 0x4,
5266 	DBG_CLIENT_BLKID_scf2                            = 0x5,
5267 	DBG_CLIENT_BLKID_spim3                           = 0x6,
5268 	DBG_CLIENT_BLKID_cb3                             = 0x7,
5269 	DBG_CLIENT_BLKID_sx0                             = 0x8,
5270 	DBG_CLIENT_BLKID_cb2                             = 0x9,
5271 	DBG_CLIENT_BLKID_bci1                            = 0xa,
5272 	DBG_CLIENT_BLKID_xdma                            = 0xb,
5273 	DBG_CLIENT_BLKID_bci0                            = 0xc,
5274 	DBG_CLIENT_BLKID_spim0                           = 0xd,
5275 	DBG_CLIENT_BLKID_mcd0                            = 0xe,
5276 	DBG_CLIENT_BLKID_mcc0                            = 0xf,
5277 	DBG_CLIENT_BLKID_cb0                             = 0x10,
5278 	DBG_CLIENT_BLKID_cb1                             = 0x11,
5279 	DBG_CLIENT_BLKID_cpc_0                           = 0x12,
5280 	DBG_CLIENT_BLKID_cpc_1                           = 0x13,
5281 	DBG_CLIENT_BLKID_cpf                             = 0x14,
5282 	DBG_CLIENT_BLKID_rlc                             = 0x15,
5283 	DBG_CLIENT_BLKID_grbm                            = 0x16,
5284 	DBG_CLIENT_BLKID_bif                             = 0x17,
5285 	DBG_CLIENT_BLKID_scf1                            = 0x18,
5286 	DBG_CLIENT_BLKID_sam                             = 0x19,
5287 	DBG_CLIENT_BLKID_mcd4                            = 0x1a,
5288 	DBG_CLIENT_BLKID_mcc4                            = 0x1b,
5289 	DBG_CLIENT_BLKID_gmcon                           = 0x1c,
5290 	DBG_CLIENT_BLKID_mcb                             = 0x1d,
5291 	DBG_CLIENT_BLKID_vgt0                            = 0x1e,
5292 	DBG_CLIENT_BLKID_pc0                             = 0x1f,
5293 	DBG_CLIENT_BLKID_spim1                           = 0x20,
5294 	DBG_CLIENT_BLKID_bci2                            = 0x21,
5295 	DBG_CLIENT_BLKID_mcd6                            = 0x22,
5296 	DBG_CLIENT_BLKID_mcc6                            = 0x23,
5297 	DBG_CLIENT_BLKID_mcd3                            = 0x24,
5298 	DBG_CLIENT_BLKID_mcc3                            = 0x25,
5299 	DBG_CLIENT_BLKID_uvdm_0                          = 0x26,
5300 	DBG_CLIENT_BLKID_uvdm_1                          = 0x27,
5301 	DBG_CLIENT_BLKID_uvdm_2                          = 0x28,
5302 	DBG_CLIENT_BLKID_uvdm_3                          = 0x29,
5303 	DBG_CLIENT_BLKID_spim2                           = 0x2a,
5304 	DBG_CLIENT_BLKID_ds                              = 0x2b,
5305 	DBG_CLIENT_BLKID_srbm                            = 0x2c,
5306 	DBG_CLIENT_BLKID_ih                              = 0x2d,
5307 	DBG_CLIENT_BLKID_sem                             = 0x2e,
5308 	DBG_CLIENT_BLKID_sdma_0                          = 0x2f,
5309 	DBG_CLIENT_BLKID_sdma_1                          = 0x30,
5310 	DBG_CLIENT_BLKID_hdp                             = 0x31,
5311 	DBG_CLIENT_BLKID_acp_0                           = 0x32,
5312 	DBG_CLIENT_BLKID_acp_1                           = 0x33,
5313 	DBG_CLIENT_BLKID_vceb_0                          = 0x34,
5314 	DBG_CLIENT_BLKID_vceb_1                          = 0x35,
5315 	DBG_CLIENT_BLKID_vceb_2                          = 0x36,
5316 	DBG_CLIENT_BLKID_mcd2                            = 0x37,
5317 	DBG_CLIENT_BLKID_mcc2                            = 0x38,
5318 	DBG_CLIENT_BLKID_scf3                            = 0x39,
5319 	DBG_CLIENT_BLKID_bci3                            = 0x3a,
5320 	DBG_CLIENT_BLKID_mcd5                            = 0x3b,
5321 	DBG_CLIENT_BLKID_mcc5                            = 0x3c,
5322 	DBG_CLIENT_BLKID_vgt2                            = 0x3d,
5323 	DBG_CLIENT_BLKID_pc2                             = 0x3e,
5324 	DBG_CLIENT_BLKID_smu_0                           = 0x3f,
5325 	DBG_CLIENT_BLKID_smu_1                           = 0x40,
5326 	DBG_CLIENT_BLKID_smu_2                           = 0x41,
5327 	DBG_CLIENT_BLKID_vcea_0                          = 0x42,
5328 	DBG_CLIENT_BLKID_vcea_1                          = 0x43,
5329 	DBG_CLIENT_BLKID_vcea_2                          = 0x44,
5330 	DBG_CLIENT_BLKID_vcea_3                          = 0x45,
5331 	DBG_CLIENT_BLKID_vcea_4                          = 0x46,
5332 	DBG_CLIENT_BLKID_vcea_5                          = 0x47,
5333 	DBG_CLIENT_BLKID_vcea_6                          = 0x48,
5334 	DBG_CLIENT_BLKID_scf0                            = 0x49,
5335 	DBG_CLIENT_BLKID_vgt1                            = 0x4a,
5336 	DBG_CLIENT_BLKID_pc1                             = 0x4b,
5337 	DBG_CLIENT_BLKID_gdc_0                           = 0x4c,
5338 	DBG_CLIENT_BLKID_gdc_1                           = 0x4d,
5339 	DBG_CLIENT_BLKID_gdc_2                           = 0x4e,
5340 	DBG_CLIENT_BLKID_gdc_3                           = 0x4f,
5341 	DBG_CLIENT_BLKID_gdc_4                           = 0x50,
5342 	DBG_CLIENT_BLKID_gdc_5                           = 0x51,
5343 	DBG_CLIENT_BLKID_gdc_6                           = 0x52,
5344 	DBG_CLIENT_BLKID_gdc_7                           = 0x53,
5345 	DBG_CLIENT_BLKID_gdc_8                           = 0x54,
5346 	DBG_CLIENT_BLKID_gdc_9                           = 0x55,
5347 	DBG_CLIENT_BLKID_gdc_10                          = 0x56,
5348 	DBG_CLIENT_BLKID_gdc_11                          = 0x57,
5349 	DBG_CLIENT_BLKID_gdc_12                          = 0x58,
5350 	DBG_CLIENT_BLKID_gdc_13                          = 0x59,
5351 	DBG_CLIENT_BLKID_gdc_14                          = 0x5a,
5352 	DBG_CLIENT_BLKID_gdc_15                          = 0x5b,
5353 	DBG_CLIENT_BLKID_gdc_16                          = 0x5c,
5354 	DBG_CLIENT_BLKID_gdc_17                          = 0x5d,
5355 	DBG_CLIENT_BLKID_gdc_18                          = 0x5e,
5356 	DBG_CLIENT_BLKID_gdc_19                          = 0x5f,
5357 	DBG_CLIENT_BLKID_gdc_20                          = 0x60,
5358 	DBG_CLIENT_BLKID_gdc_21                          = 0x61,
5359 	DBG_CLIENT_BLKID_gdc_22                          = 0x62,
5360 	DBG_CLIENT_BLKID_vgt3                            = 0x63,
5361 	DBG_CLIENT_BLKID_pc3                             = 0x64,
5362 	DBG_CLIENT_BLKID_uvdu_0                          = 0x65,
5363 	DBG_CLIENT_BLKID_uvdu_1                          = 0x66,
5364 	DBG_CLIENT_BLKID_uvdu_2                          = 0x67,
5365 	DBG_CLIENT_BLKID_uvdu_3                          = 0x68,
5366 	DBG_CLIENT_BLKID_uvdu_4                          = 0x69,
5367 	DBG_CLIENT_BLKID_uvdu_5                          = 0x6a,
5368 	DBG_CLIENT_BLKID_uvdu_6                          = 0x6b,
5369 	DBG_CLIENT_BLKID_mcd7                            = 0x6c,
5370 	DBG_CLIENT_BLKID_mcc7                            = 0x6d,
5371 	DBG_CLIENT_BLKID_cpg_0                           = 0x6e,
5372 	DBG_CLIENT_BLKID_cpg_1                           = 0x6f,
5373 	DBG_CLIENT_BLKID_gck                             = 0x70,
5374 	DBG_CLIENT_BLKID_mcd1                            = 0x71,
5375 	DBG_CLIENT_BLKID_mcc1                            = 0x72,
5376 	DBG_CLIENT_BLKID_cb101                           = 0x73,
5377 	DBG_CLIENT_BLKID_cb103                           = 0x74,
5378 	DBG_CLIENT_BLKID_sx10                            = 0x75,
5379 	DBG_CLIENT_BLKID_cb102                           = 0x76,
5380 	DBG_CLIENT_BLKID_cb002                           = 0x77,
5381 	DBG_CLIENT_BLKID_cb100                           = 0x78,
5382 	DBG_CLIENT_BLKID_cb000                           = 0x79,
5383 	DBG_CLIENT_BLKID_pa00                            = 0x7a,
5384 	DBG_CLIENT_BLKID_pa10                            = 0x7b,
5385 	DBG_CLIENT_BLKID_ia0                             = 0x7c,
5386 	DBG_CLIENT_BLKID_ia1                             = 0x7d,
5387 	DBG_CLIENT_BLKID_tmonw00                         = 0x7e,
5388 	DBG_CLIENT_BLKID_cb001                           = 0x7f,
5389 	DBG_CLIENT_BLKID_cb003                           = 0x80,
5390 	DBG_CLIENT_BLKID_sx00                            = 0x81,
5391 	DBG_CLIENT_BLKID_sx20                            = 0x82,
5392 	DBG_CLIENT_BLKID_cb203                           = 0x83,
5393 	DBG_CLIENT_BLKID_cb201                           = 0x84,
5394 	DBG_CLIENT_BLKID_cb302                           = 0x85,
5395 	DBG_CLIENT_BLKID_cb202                           = 0x86,
5396 	DBG_CLIENT_BLKID_cb300                           = 0x87,
5397 	DBG_CLIENT_BLKID_cb200                           = 0x88,
5398 	DBG_CLIENT_BLKID_pa01                            = 0x89,
5399 	DBG_CLIENT_BLKID_pa11                            = 0x8a,
5400 	DBG_CLIENT_BLKID_sx30                            = 0x8b,
5401 	DBG_CLIENT_BLKID_cb303                           = 0x8c,
5402 	DBG_CLIENT_BLKID_cb301                           = 0x8d,
5403 	DBG_CLIENT_BLKID_dco                             = 0x8e,
5404 	DBG_CLIENT_BLKID_scb0                            = 0x8f,
5405 	DBG_CLIENT_BLKID_scb1                            = 0x90,
5406 	DBG_CLIENT_BLKID_scb2                            = 0x91,
5407 	DBG_CLIENT_BLKID_scb3                            = 0x92,
5408 	DBG_CLIENT_BLKID_tmonw01                         = 0x93,
5409 	DBG_CLIENT_BLKID_RESERVED_LAST                   = 0x94,
5410 } DebugBlockId;
5411 typedef enum DebugBlockId_OLD {
5412 	DBG_BLOCK_ID_RESERVED                            = 0x0,
5413 	DBG_BLOCK_ID_DBG                                 = 0x1,
5414 	DBG_BLOCK_ID_VMC                                 = 0x2,
5415 	DBG_BLOCK_ID_PDMA                                = 0x3,
5416 	DBG_BLOCK_ID_CG                                  = 0x4,
5417 	DBG_BLOCK_ID_SRBM                                = 0x5,
5418 	DBG_BLOCK_ID_GRBM                                = 0x6,
5419 	DBG_BLOCK_ID_RLC                                 = 0x7,
5420 	DBG_BLOCK_ID_CSC                                 = 0x8,
5421 	DBG_BLOCK_ID_SEM                                 = 0x9,
5422 	DBG_BLOCK_ID_IH                                  = 0xa,
5423 	DBG_BLOCK_ID_SC                                  = 0xb,
5424 	DBG_BLOCK_ID_SQ                                  = 0xc,
5425 	DBG_BLOCK_ID_AVP                                 = 0xd,
5426 	DBG_BLOCK_ID_GMCON                               = 0xe,
5427 	DBG_BLOCK_ID_SMU                                 = 0xf,
5428 	DBG_BLOCK_ID_DMA0                                = 0x10,
5429 	DBG_BLOCK_ID_DMA1                                = 0x11,
5430 	DBG_BLOCK_ID_SPIM                                = 0x12,
5431 	DBG_BLOCK_ID_GDS                                 = 0x13,
5432 	DBG_BLOCK_ID_SPIS                                = 0x14,
5433 	DBG_BLOCK_ID_UNUSED0                             = 0x15,
5434 	DBG_BLOCK_ID_PA0                                 = 0x16,
5435 	DBG_BLOCK_ID_PA1                                 = 0x17,
5436 	DBG_BLOCK_ID_CP0                                 = 0x18,
5437 	DBG_BLOCK_ID_CP1                                 = 0x19,
5438 	DBG_BLOCK_ID_CP2                                 = 0x1a,
5439 	DBG_BLOCK_ID_UNUSED1                             = 0x1b,
5440 	DBG_BLOCK_ID_UVDU                                = 0x1c,
5441 	DBG_BLOCK_ID_UVDM                                = 0x1d,
5442 	DBG_BLOCK_ID_VCE                                 = 0x1e,
5443 	DBG_BLOCK_ID_UNUSED2                             = 0x1f,
5444 	DBG_BLOCK_ID_VGT0                                = 0x20,
5445 	DBG_BLOCK_ID_VGT1                                = 0x21,
5446 	DBG_BLOCK_ID_IA                                  = 0x22,
5447 	DBG_BLOCK_ID_UNUSED3                             = 0x23,
5448 	DBG_BLOCK_ID_SCT0                                = 0x24,
5449 	DBG_BLOCK_ID_SCT1                                = 0x25,
5450 	DBG_BLOCK_ID_SPM0                                = 0x26,
5451 	DBG_BLOCK_ID_SPM1                                = 0x27,
5452 	DBG_BLOCK_ID_TCAA                                = 0x28,
5453 	DBG_BLOCK_ID_TCAB                                = 0x29,
5454 	DBG_BLOCK_ID_TCCA                                = 0x2a,
5455 	DBG_BLOCK_ID_TCCB                                = 0x2b,
5456 	DBG_BLOCK_ID_MCC0                                = 0x2c,
5457 	DBG_BLOCK_ID_MCC1                                = 0x2d,
5458 	DBG_BLOCK_ID_MCC2                                = 0x2e,
5459 	DBG_BLOCK_ID_MCC3                                = 0x2f,
5460 	DBG_BLOCK_ID_SX0                                 = 0x30,
5461 	DBG_BLOCK_ID_SX1                                 = 0x31,
5462 	DBG_BLOCK_ID_SX2                                 = 0x32,
5463 	DBG_BLOCK_ID_SX3                                 = 0x33,
5464 	DBG_BLOCK_ID_UNUSED4                             = 0x34,
5465 	DBG_BLOCK_ID_UNUSED5                             = 0x35,
5466 	DBG_BLOCK_ID_UNUSED6                             = 0x36,
5467 	DBG_BLOCK_ID_UNUSED7                             = 0x37,
5468 	DBG_BLOCK_ID_PC0                                 = 0x38,
5469 	DBG_BLOCK_ID_PC1                                 = 0x39,
5470 	DBG_BLOCK_ID_UNUSED8                             = 0x3a,
5471 	DBG_BLOCK_ID_UNUSED9                             = 0x3b,
5472 	DBG_BLOCK_ID_UNUSED10                            = 0x3c,
5473 	DBG_BLOCK_ID_UNUSED11                            = 0x3d,
5474 	DBG_BLOCK_ID_MCB                                 = 0x3e,
5475 	DBG_BLOCK_ID_UNUSED12                            = 0x3f,
5476 	DBG_BLOCK_ID_SCB0                                = 0x40,
5477 	DBG_BLOCK_ID_SCB1                                = 0x41,
5478 	DBG_BLOCK_ID_UNUSED13                            = 0x42,
5479 	DBG_BLOCK_ID_UNUSED14                            = 0x43,
5480 	DBG_BLOCK_ID_SCF0                                = 0x44,
5481 	DBG_BLOCK_ID_SCF1                                = 0x45,
5482 	DBG_BLOCK_ID_UNUSED15                            = 0x46,
5483 	DBG_BLOCK_ID_UNUSED16                            = 0x47,
5484 	DBG_BLOCK_ID_BCI0                                = 0x48,
5485 	DBG_BLOCK_ID_BCI1                                = 0x49,
5486 	DBG_BLOCK_ID_BCI2                                = 0x4a,
5487 	DBG_BLOCK_ID_BCI3                                = 0x4b,
5488 	DBG_BLOCK_ID_UNUSED17                            = 0x4c,
5489 	DBG_BLOCK_ID_UNUSED18                            = 0x4d,
5490 	DBG_BLOCK_ID_UNUSED19                            = 0x4e,
5491 	DBG_BLOCK_ID_UNUSED20                            = 0x4f,
5492 	DBG_BLOCK_ID_CB00                                = 0x50,
5493 	DBG_BLOCK_ID_CB01                                = 0x51,
5494 	DBG_BLOCK_ID_CB02                                = 0x52,
5495 	DBG_BLOCK_ID_CB03                                = 0x53,
5496 	DBG_BLOCK_ID_CB04                                = 0x54,
5497 	DBG_BLOCK_ID_UNUSED21                            = 0x55,
5498 	DBG_BLOCK_ID_UNUSED22                            = 0x56,
5499 	DBG_BLOCK_ID_UNUSED23                            = 0x57,
5500 	DBG_BLOCK_ID_CB10                                = 0x58,
5501 	DBG_BLOCK_ID_CB11                                = 0x59,
5502 	DBG_BLOCK_ID_CB12                                = 0x5a,
5503 	DBG_BLOCK_ID_CB13                                = 0x5b,
5504 	DBG_BLOCK_ID_CB14                                = 0x5c,
5505 	DBG_BLOCK_ID_UNUSED24                            = 0x5d,
5506 	DBG_BLOCK_ID_UNUSED25                            = 0x5e,
5507 	DBG_BLOCK_ID_UNUSED26                            = 0x5f,
5508 	DBG_BLOCK_ID_TCP0                                = 0x60,
5509 	DBG_BLOCK_ID_TCP1                                = 0x61,
5510 	DBG_BLOCK_ID_TCP2                                = 0x62,
5511 	DBG_BLOCK_ID_TCP3                                = 0x63,
5512 	DBG_BLOCK_ID_TCP4                                = 0x64,
5513 	DBG_BLOCK_ID_TCP5                                = 0x65,
5514 	DBG_BLOCK_ID_TCP6                                = 0x66,
5515 	DBG_BLOCK_ID_TCP7                                = 0x67,
5516 	DBG_BLOCK_ID_TCP8                                = 0x68,
5517 	DBG_BLOCK_ID_TCP9                                = 0x69,
5518 	DBG_BLOCK_ID_TCP10                               = 0x6a,
5519 	DBG_BLOCK_ID_TCP11                               = 0x6b,
5520 	DBG_BLOCK_ID_TCP12                               = 0x6c,
5521 	DBG_BLOCK_ID_TCP13                               = 0x6d,
5522 	DBG_BLOCK_ID_TCP14                               = 0x6e,
5523 	DBG_BLOCK_ID_TCP15                               = 0x6f,
5524 	DBG_BLOCK_ID_TCP16                               = 0x70,
5525 	DBG_BLOCK_ID_TCP17                               = 0x71,
5526 	DBG_BLOCK_ID_TCP18                               = 0x72,
5527 	DBG_BLOCK_ID_TCP19                               = 0x73,
5528 	DBG_BLOCK_ID_TCP20                               = 0x74,
5529 	DBG_BLOCK_ID_TCP21                               = 0x75,
5530 	DBG_BLOCK_ID_TCP22                               = 0x76,
5531 	DBG_BLOCK_ID_TCP23                               = 0x77,
5532 	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
5533 	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
5534 	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
5535 	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
5536 	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
5537 	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
5538 	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
5539 	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
5540 	DBG_BLOCK_ID_DB00                                = 0x80,
5541 	DBG_BLOCK_ID_DB01                                = 0x81,
5542 	DBG_BLOCK_ID_DB02                                = 0x82,
5543 	DBG_BLOCK_ID_DB03                                = 0x83,
5544 	DBG_BLOCK_ID_DB04                                = 0x84,
5545 	DBG_BLOCK_ID_UNUSED27                            = 0x85,
5546 	DBG_BLOCK_ID_UNUSED28                            = 0x86,
5547 	DBG_BLOCK_ID_UNUSED29                            = 0x87,
5548 	DBG_BLOCK_ID_DB10                                = 0x88,
5549 	DBG_BLOCK_ID_DB11                                = 0x89,
5550 	DBG_BLOCK_ID_DB12                                = 0x8a,
5551 	DBG_BLOCK_ID_DB13                                = 0x8b,
5552 	DBG_BLOCK_ID_DB14                                = 0x8c,
5553 	DBG_BLOCK_ID_UNUSED30                            = 0x8d,
5554 	DBG_BLOCK_ID_UNUSED31                            = 0x8e,
5555 	DBG_BLOCK_ID_UNUSED32                            = 0x8f,
5556 	DBG_BLOCK_ID_TCC0                                = 0x90,
5557 	DBG_BLOCK_ID_TCC1                                = 0x91,
5558 	DBG_BLOCK_ID_TCC2                                = 0x92,
5559 	DBG_BLOCK_ID_TCC3                                = 0x93,
5560 	DBG_BLOCK_ID_TCC4                                = 0x94,
5561 	DBG_BLOCK_ID_TCC5                                = 0x95,
5562 	DBG_BLOCK_ID_TCC6                                = 0x96,
5563 	DBG_BLOCK_ID_TCC7                                = 0x97,
5564 	DBG_BLOCK_ID_SPS00                               = 0x98,
5565 	DBG_BLOCK_ID_SPS01                               = 0x99,
5566 	DBG_BLOCK_ID_SPS02                               = 0x9a,
5567 	DBG_BLOCK_ID_SPS10                               = 0x9b,
5568 	DBG_BLOCK_ID_SPS11                               = 0x9c,
5569 	DBG_BLOCK_ID_SPS12                               = 0x9d,
5570 	DBG_BLOCK_ID_UNUSED33                            = 0x9e,
5571 	DBG_BLOCK_ID_UNUSED34                            = 0x9f,
5572 	DBG_BLOCK_ID_TA00                                = 0xa0,
5573 	DBG_BLOCK_ID_TA01                                = 0xa1,
5574 	DBG_BLOCK_ID_TA02                                = 0xa2,
5575 	DBG_BLOCK_ID_TA03                                = 0xa3,
5576 	DBG_BLOCK_ID_TA04                                = 0xa4,
5577 	DBG_BLOCK_ID_TA05                                = 0xa5,
5578 	DBG_BLOCK_ID_TA06                                = 0xa6,
5579 	DBG_BLOCK_ID_TA07                                = 0xa7,
5580 	DBG_BLOCK_ID_TA08                                = 0xa8,
5581 	DBG_BLOCK_ID_TA09                                = 0xa9,
5582 	DBG_BLOCK_ID_TA0A                                = 0xaa,
5583 	DBG_BLOCK_ID_TA0B                                = 0xab,
5584 	DBG_BLOCK_ID_UNUSED35                            = 0xac,
5585 	DBG_BLOCK_ID_UNUSED36                            = 0xad,
5586 	DBG_BLOCK_ID_UNUSED37                            = 0xae,
5587 	DBG_BLOCK_ID_UNUSED38                            = 0xaf,
5588 	DBG_BLOCK_ID_TA10                                = 0xb0,
5589 	DBG_BLOCK_ID_TA11                                = 0xb1,
5590 	DBG_BLOCK_ID_TA12                                = 0xb2,
5591 	DBG_BLOCK_ID_TA13                                = 0xb3,
5592 	DBG_BLOCK_ID_TA14                                = 0xb4,
5593 	DBG_BLOCK_ID_TA15                                = 0xb5,
5594 	DBG_BLOCK_ID_TA16                                = 0xb6,
5595 	DBG_BLOCK_ID_TA17                                = 0xb7,
5596 	DBG_BLOCK_ID_TA18                                = 0xb8,
5597 	DBG_BLOCK_ID_TA19                                = 0xb9,
5598 	DBG_BLOCK_ID_TA1A                                = 0xba,
5599 	DBG_BLOCK_ID_TA1B                                = 0xbb,
5600 	DBG_BLOCK_ID_UNUSED39                            = 0xbc,
5601 	DBG_BLOCK_ID_UNUSED40                            = 0xbd,
5602 	DBG_BLOCK_ID_UNUSED41                            = 0xbe,
5603 	DBG_BLOCK_ID_UNUSED42                            = 0xbf,
5604 	DBG_BLOCK_ID_TD00                                = 0xc0,
5605 	DBG_BLOCK_ID_TD01                                = 0xc1,
5606 	DBG_BLOCK_ID_TD02                                = 0xc2,
5607 	DBG_BLOCK_ID_TD03                                = 0xc3,
5608 	DBG_BLOCK_ID_TD04                                = 0xc4,
5609 	DBG_BLOCK_ID_TD05                                = 0xc5,
5610 	DBG_BLOCK_ID_TD06                                = 0xc6,
5611 	DBG_BLOCK_ID_TD07                                = 0xc7,
5612 	DBG_BLOCK_ID_TD08                                = 0xc8,
5613 	DBG_BLOCK_ID_TD09                                = 0xc9,
5614 	DBG_BLOCK_ID_TD0A                                = 0xca,
5615 	DBG_BLOCK_ID_TD0B                                = 0xcb,
5616 	DBG_BLOCK_ID_UNUSED43                            = 0xcc,
5617 	DBG_BLOCK_ID_UNUSED44                            = 0xcd,
5618 	DBG_BLOCK_ID_UNUSED45                            = 0xce,
5619 	DBG_BLOCK_ID_UNUSED46                            = 0xcf,
5620 	DBG_BLOCK_ID_TD10                                = 0xd0,
5621 	DBG_BLOCK_ID_TD11                                = 0xd1,
5622 	DBG_BLOCK_ID_TD12                                = 0xd2,
5623 	DBG_BLOCK_ID_TD13                                = 0xd3,
5624 	DBG_BLOCK_ID_TD14                                = 0xd4,
5625 	DBG_BLOCK_ID_TD15                                = 0xd5,
5626 	DBG_BLOCK_ID_TD16                                = 0xd6,
5627 	DBG_BLOCK_ID_TD17                                = 0xd7,
5628 	DBG_BLOCK_ID_TD18                                = 0xd8,
5629 	DBG_BLOCK_ID_TD19                                = 0xd9,
5630 	DBG_BLOCK_ID_TD1A                                = 0xda,
5631 	DBG_BLOCK_ID_TD1B                                = 0xdb,
5632 	DBG_BLOCK_ID_UNUSED47                            = 0xdc,
5633 	DBG_BLOCK_ID_UNUSED48                            = 0xdd,
5634 	DBG_BLOCK_ID_UNUSED49                            = 0xde,
5635 	DBG_BLOCK_ID_UNUSED50                            = 0xdf,
5636 	DBG_BLOCK_ID_MCD0                                = 0xe0,
5637 	DBG_BLOCK_ID_MCD1                                = 0xe1,
5638 	DBG_BLOCK_ID_MCD2                                = 0xe2,
5639 	DBG_BLOCK_ID_MCD3                                = 0xe3,
5640 	DBG_BLOCK_ID_MCD4                                = 0xe4,
5641 	DBG_BLOCK_ID_MCD5                                = 0xe5,
5642 	DBG_BLOCK_ID_UNUSED51                            = 0xe6,
5643 	DBG_BLOCK_ID_UNUSED52                            = 0xe7,
5644 } DebugBlockId_OLD;
5645 typedef enum DebugBlockId_BY2 {
5646 	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
5647 	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
5648 	DBG_BLOCK_ID_CG_BY2                              = 0x2,
5649 	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
5650 	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
5651 	DBG_BLOCK_ID_IH_BY2                              = 0x5,
5652 	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
5653 	DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
5654 	DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
5655 	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
5656 	DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
5657 	DBG_BLOCK_ID_PA0_BY2                             = 0xb,
5658 	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
5659 	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
5660 	DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
5661 	DBG_BLOCK_ID_VCE_BY2                             = 0xf,
5662 	DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
5663 	DBG_BLOCK_ID_IA_BY2                              = 0x11,
5664 	DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
5665 	DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
5666 	DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
5667 	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
5668 	DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
5669 	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
5670 	DBG_BLOCK_ID_SX0_BY2                             = 0x18,
5671 	DBG_BLOCK_ID_SX2_BY2                             = 0x19,
5672 	DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
5673 	DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
5674 	DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
5675 	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
5676 	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
5677 	DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
5678 	DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
5679 	DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
5680 	DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
5681 	DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
5682 	DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
5683 	DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
5684 	DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
5685 	DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
5686 	DBG_BLOCK_ID_CB00_BY2                            = 0x28,
5687 	DBG_BLOCK_ID_CB02_BY2                            = 0x29,
5688 	DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
5689 	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
5690 	DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
5691 	DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
5692 	DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
5693 	DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
5694 	DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
5695 	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
5696 	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
5697 	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
5698 	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
5699 	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
5700 	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
5701 	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
5702 	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
5703 	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
5704 	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
5705 	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
5706 	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
5707 	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
5708 	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
5709 	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
5710 	DBG_BLOCK_ID_DB00_BY2                            = 0x40,
5711 	DBG_BLOCK_ID_DB02_BY2                            = 0x41,
5712 	DBG_BLOCK_ID_DB04_BY2                            = 0x42,
5713 	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
5714 	DBG_BLOCK_ID_DB10_BY2                            = 0x44,
5715 	DBG_BLOCK_ID_DB12_BY2                            = 0x45,
5716 	DBG_BLOCK_ID_DB14_BY2                            = 0x46,
5717 	DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
5718 	DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
5719 	DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
5720 	DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
5721 	DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
5722 	DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
5723 	DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
5724 	DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
5725 	DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
5726 	DBG_BLOCK_ID_TA00_BY2                            = 0x50,
5727 	DBG_BLOCK_ID_TA02_BY2                            = 0x51,
5728 	DBG_BLOCK_ID_TA04_BY2                            = 0x52,
5729 	DBG_BLOCK_ID_TA06_BY2                            = 0x53,
5730 	DBG_BLOCK_ID_TA08_BY2                            = 0x54,
5731 	DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
5732 	DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
5733 	DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
5734 	DBG_BLOCK_ID_TA10_BY2                            = 0x58,
5735 	DBG_BLOCK_ID_TA12_BY2                            = 0x59,
5736 	DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
5737 	DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
5738 	DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
5739 	DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
5740 	DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
5741 	DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
5742 	DBG_BLOCK_ID_TD00_BY2                            = 0x60,
5743 	DBG_BLOCK_ID_TD02_BY2                            = 0x61,
5744 	DBG_BLOCK_ID_TD04_BY2                            = 0x62,
5745 	DBG_BLOCK_ID_TD06_BY2                            = 0x63,
5746 	DBG_BLOCK_ID_TD08_BY2                            = 0x64,
5747 	DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
5748 	DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
5749 	DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
5750 	DBG_BLOCK_ID_TD10_BY2                            = 0x68,
5751 	DBG_BLOCK_ID_TD12_BY2                            = 0x69,
5752 	DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
5753 	DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
5754 	DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
5755 	DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
5756 	DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
5757 	DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
5758 	DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
5759 	DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
5760 	DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
5761 	DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
5762 } DebugBlockId_BY2;
5763 typedef enum DebugBlockId_BY4 {
5764 	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
5765 	DBG_BLOCK_ID_CG_BY4                              = 0x1,
5766 	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
5767 	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
5768 	DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
5769 	DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
5770 	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
5771 	DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
5772 	DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
5773 	DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
5774 	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
5775 	DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
5776 	DBG_BLOCK_ID_SX0_BY4                             = 0xc,
5777 	DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
5778 	DBG_BLOCK_ID_PC0_BY4                             = 0xe,
5779 	DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
5780 	DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
5781 	DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
5782 	DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
5783 	DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
5784 	DBG_BLOCK_ID_CB00_BY4                            = 0x14,
5785 	DBG_BLOCK_ID_CB04_BY4                            = 0x15,
5786 	DBG_BLOCK_ID_CB10_BY4                            = 0x16,
5787 	DBG_BLOCK_ID_CB14_BY4                            = 0x17,
5788 	DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
5789 	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
5790 	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
5791 	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
5792 	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
5793 	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
5794 	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
5795 	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
5796 	DBG_BLOCK_ID_DB_BY4                              = 0x20,
5797 	DBG_BLOCK_ID_DB04_BY4                            = 0x21,
5798 	DBG_BLOCK_ID_DB10_BY4                            = 0x22,
5799 	DBG_BLOCK_ID_DB14_BY4                            = 0x23,
5800 	DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
5801 	DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
5802 	DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
5803 	DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
5804 	DBG_BLOCK_ID_TA00_BY4                            = 0x28,
5805 	DBG_BLOCK_ID_TA04_BY4                            = 0x29,
5806 	DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
5807 	DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
5808 	DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
5809 	DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
5810 	DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
5811 	DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
5812 	DBG_BLOCK_ID_TD00_BY4                            = 0x30,
5813 	DBG_BLOCK_ID_TD04_BY4                            = 0x31,
5814 	DBG_BLOCK_ID_TD08_BY4                            = 0x32,
5815 	DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
5816 	DBG_BLOCK_ID_TD10_BY4                            = 0x34,
5817 	DBG_BLOCK_ID_TD14_BY4                            = 0x35,
5818 	DBG_BLOCK_ID_TD18_BY4                            = 0x36,
5819 	DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
5820 	DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
5821 	DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
5822 } DebugBlockId_BY4;
5823 typedef enum DebugBlockId_BY8 {
5824 	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
5825 	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
5826 	DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
5827 	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
5828 	DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
5829 	DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
5830 	DBG_BLOCK_ID_SX0_BY8                             = 0x6,
5831 	DBG_BLOCK_ID_PC0_BY8                             = 0x7,
5832 	DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
5833 	DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
5834 	DBG_BLOCK_ID_CB00_BY8                            = 0xa,
5835 	DBG_BLOCK_ID_CB10_BY8                            = 0xb,
5836 	DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
5837 	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
5838 	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
5839 	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
5840 	DBG_BLOCK_ID_DB00_BY8                            = 0x10,
5841 	DBG_BLOCK_ID_DB10_BY8                            = 0x11,
5842 	DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
5843 	DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
5844 	DBG_BLOCK_ID_TA00_BY8                            = 0x14,
5845 	DBG_BLOCK_ID_TA08_BY8                            = 0x15,
5846 	DBG_BLOCK_ID_TA10_BY8                            = 0x16,
5847 	DBG_BLOCK_ID_TA18_BY8                            = 0x17,
5848 	DBG_BLOCK_ID_TD00_BY8                            = 0x18,
5849 	DBG_BLOCK_ID_TD08_BY8                            = 0x19,
5850 	DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
5851 	DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
5852 	DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
5853 } DebugBlockId_BY8;
5854 typedef enum DebugBlockId_BY16 {
5855 	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
5856 	DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
5857 	DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
5858 	DBG_BLOCK_ID_SX0_BY16                            = 0x3,
5859 	DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
5860 	DBG_BLOCK_ID_CB00_BY16                           = 0x5,
5861 	DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
5862 	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
5863 	DBG_BLOCK_ID_DB00_BY16                           = 0x8,
5864 	DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
5865 	DBG_BLOCK_ID_TA00_BY16                           = 0xa,
5866 	DBG_BLOCK_ID_TA10_BY16                           = 0xb,
5867 	DBG_BLOCK_ID_TD00_BY16                           = 0xc,
5868 	DBG_BLOCK_ID_TD10_BY16                           = 0xd,
5869 	DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
5870 } DebugBlockId_BY16;
5871 typedef enum CompareRef {
5872 	REF_NEVER                                        = 0x0,
5873 	REF_LESS                                         = 0x1,
5874 	REF_EQUAL                                        = 0x2,
5875 	REF_LEQUAL                                       = 0x3,
5876 	REF_GREATER                                      = 0x4,
5877 	REF_NOTEQUAL                                     = 0x5,
5878 	REF_GEQUAL                                       = 0x6,
5879 	REF_ALWAYS                                       = 0x7,
5880 } CompareRef;
5881 typedef enum ReadSize {
5882 	READ_256_BITS                                    = 0x0,
5883 	READ_512_BITS                                    = 0x1,
5884 } ReadSize;
5885 typedef enum DepthFormat {
5886 	DEPTH_INVALID                                    = 0x0,
5887 	DEPTH_16                                         = 0x1,
5888 	DEPTH_X8_24                                      = 0x2,
5889 	DEPTH_8_24                                       = 0x3,
5890 	DEPTH_X8_24_FLOAT                                = 0x4,
5891 	DEPTH_8_24_FLOAT                                 = 0x5,
5892 	DEPTH_32_FLOAT                                   = 0x6,
5893 	DEPTH_X24_8_32_FLOAT                             = 0x7,
5894 } DepthFormat;
5895 typedef enum ZFormat {
5896 	Z_INVALID                                        = 0x0,
5897 	Z_16                                             = 0x1,
5898 	Z_24                                             = 0x2,
5899 	Z_32_FLOAT                                       = 0x3,
5900 } ZFormat;
5901 typedef enum StencilFormat {
5902 	STENCIL_INVALID                                  = 0x0,
5903 	STENCIL_8                                        = 0x1,
5904 } StencilFormat;
5905 typedef enum CmaskMode {
5906 	CMASK_CLEAR_NONE                                 = 0x0,
5907 	CMASK_CLEAR_ONE                                  = 0x1,
5908 	CMASK_CLEAR_ALL                                  = 0x2,
5909 	CMASK_ANY_EXPANDED                               = 0x3,
5910 	CMASK_ALPHA0_FRAG1                               = 0x4,
5911 	CMASK_ALPHA0_FRAG2                               = 0x5,
5912 	CMASK_ALPHA0_FRAG4                               = 0x6,
5913 	CMASK_ALPHA0_FRAGS                               = 0x7,
5914 	CMASK_ALPHA1_FRAG1                               = 0x8,
5915 	CMASK_ALPHA1_FRAG2                               = 0x9,
5916 	CMASK_ALPHA1_FRAG4                               = 0xa,
5917 	CMASK_ALPHA1_FRAGS                               = 0xb,
5918 	CMASK_ALPHAX_FRAG1                               = 0xc,
5919 	CMASK_ALPHAX_FRAG2                               = 0xd,
5920 	CMASK_ALPHAX_FRAG4                               = 0xe,
5921 	CMASK_ALPHAX_FRAGS                               = 0xf,
5922 } CmaskMode;
5923 typedef enum QuadExportFormat {
5924 	EXPORT_UNUSED                                    = 0x0,
5925 	EXPORT_32_R                                      = 0x1,
5926 	EXPORT_32_GR                                     = 0x2,
5927 	EXPORT_32_AR                                     = 0x3,
5928 	EXPORT_FP16_ABGR                                 = 0x4,
5929 	EXPORT_UNSIGNED16_ABGR                           = 0x5,
5930 	EXPORT_SIGNED16_ABGR                             = 0x6,
5931 	EXPORT_32_ABGR                                   = 0x7,
5932 } QuadExportFormat;
5933 typedef enum QuadExportFormatOld {
5934 	EXPORT_4P_32BPC_ABGR                             = 0x0,
5935 	EXPORT_4P_16BPC_ABGR                             = 0x1,
5936 	EXPORT_4P_32BPC_GR                               = 0x2,
5937 	EXPORT_4P_32BPC_AR                               = 0x3,
5938 	EXPORT_2P_32BPC_ABGR                             = 0x4,
5939 	EXPORT_8P_32BPC_R                                = 0x5,
5940 } QuadExportFormatOld;
5941 typedef enum ColorFormat {
5942 	COLOR_INVALID                                    = 0x0,
5943 	COLOR_8                                          = 0x1,
5944 	COLOR_16                                         = 0x2,
5945 	COLOR_8_8                                        = 0x3,
5946 	COLOR_32                                         = 0x4,
5947 	COLOR_16_16                                      = 0x5,
5948 	COLOR_10_11_11                                   = 0x6,
5949 	COLOR_11_11_10                                   = 0x7,
5950 	COLOR_10_10_10_2                                 = 0x8,
5951 	COLOR_2_10_10_10                                 = 0x9,
5952 	COLOR_8_8_8_8                                    = 0xa,
5953 	COLOR_32_32                                      = 0xb,
5954 	COLOR_16_16_16_16                                = 0xc,
5955 	COLOR_RESERVED_13                                = 0xd,
5956 	COLOR_32_32_32_32                                = 0xe,
5957 	COLOR_RESERVED_15                                = 0xf,
5958 	COLOR_5_6_5                                      = 0x10,
5959 	COLOR_1_5_5_5                                    = 0x11,
5960 	COLOR_5_5_5_1                                    = 0x12,
5961 	COLOR_4_4_4_4                                    = 0x13,
5962 	COLOR_8_24                                       = 0x14,
5963 	COLOR_24_8                                       = 0x15,
5964 	COLOR_X24_8_32_FLOAT                             = 0x16,
5965 	COLOR_RESERVED_23                                = 0x17,
5966 } ColorFormat;
5967 typedef enum SurfaceFormat {
5968 	FMT_INVALID                                      = 0x0,
5969 	FMT_8                                            = 0x1,
5970 	FMT_16                                           = 0x2,
5971 	FMT_8_8                                          = 0x3,
5972 	FMT_32                                           = 0x4,
5973 	FMT_16_16                                        = 0x5,
5974 	FMT_10_11_11                                     = 0x6,
5975 	FMT_11_11_10                                     = 0x7,
5976 	FMT_10_10_10_2                                   = 0x8,
5977 	FMT_2_10_10_10                                   = 0x9,
5978 	FMT_8_8_8_8                                      = 0xa,
5979 	FMT_32_32                                        = 0xb,
5980 	FMT_16_16_16_16                                  = 0xc,
5981 	FMT_32_32_32                                     = 0xd,
5982 	FMT_32_32_32_32                                  = 0xe,
5983 	FMT_RESERVED_4                                   = 0xf,
5984 	FMT_5_6_5                                        = 0x10,
5985 	FMT_1_5_5_5                                      = 0x11,
5986 	FMT_5_5_5_1                                      = 0x12,
5987 	FMT_4_4_4_4                                      = 0x13,
5988 	FMT_8_24                                         = 0x14,
5989 	FMT_24_8                                         = 0x15,
5990 	FMT_X24_8_32_FLOAT                               = 0x16,
5991 	FMT_RESERVED_33                                  = 0x17,
5992 	FMT_11_11_10_FLOAT                               = 0x18,
5993 	FMT_16_FLOAT                                     = 0x19,
5994 	FMT_32_FLOAT                                     = 0x1a,
5995 	FMT_16_16_FLOAT                                  = 0x1b,
5996 	FMT_8_24_FLOAT                                   = 0x1c,
5997 	FMT_24_8_FLOAT                                   = 0x1d,
5998 	FMT_32_32_FLOAT                                  = 0x1e,
5999 	FMT_10_11_11_FLOAT                               = 0x1f,
6000 	FMT_16_16_16_16_FLOAT                            = 0x20,
6001 	FMT_3_3_2                                        = 0x21,
6002 	FMT_6_5_5                                        = 0x22,
6003 	FMT_32_32_32_32_FLOAT                            = 0x23,
6004 	FMT_RESERVED_36                                  = 0x24,
6005 	FMT_1                                            = 0x25,
6006 	FMT_1_REVERSED                                   = 0x26,
6007 	FMT_GB_GR                                        = 0x27,
6008 	FMT_BG_RG                                        = 0x28,
6009 	FMT_32_AS_8                                      = 0x29,
6010 	FMT_32_AS_8_8                                    = 0x2a,
6011 	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
6012 	FMT_8_8_8                                        = 0x2c,
6013 	FMT_16_16_16                                     = 0x2d,
6014 	FMT_16_16_16_FLOAT                               = 0x2e,
6015 	FMT_4_4                                          = 0x2f,
6016 	FMT_32_32_32_FLOAT                               = 0x30,
6017 	FMT_BC1                                          = 0x31,
6018 	FMT_BC2                                          = 0x32,
6019 	FMT_BC3                                          = 0x33,
6020 	FMT_BC4                                          = 0x34,
6021 	FMT_BC5                                          = 0x35,
6022 	FMT_BC6                                          = 0x36,
6023 	FMT_BC7                                          = 0x37,
6024 	FMT_32_AS_32_32_32_32                            = 0x38,
6025 	FMT_APC3                                         = 0x39,
6026 	FMT_APC4                                         = 0x3a,
6027 	FMT_APC5                                         = 0x3b,
6028 	FMT_APC6                                         = 0x3c,
6029 	FMT_APC7                                         = 0x3d,
6030 	FMT_CTX1                                         = 0x3e,
6031 	FMT_RESERVED_63                                  = 0x3f,
6032 } SurfaceFormat;
6033 typedef enum BUF_DATA_FORMAT {
6034 	BUF_DATA_FORMAT_INVALID                          = 0x0,
6035 	BUF_DATA_FORMAT_8                                = 0x1,
6036 	BUF_DATA_FORMAT_16                               = 0x2,
6037 	BUF_DATA_FORMAT_8_8                              = 0x3,
6038 	BUF_DATA_FORMAT_32                               = 0x4,
6039 	BUF_DATA_FORMAT_16_16                            = 0x5,
6040 	BUF_DATA_FORMAT_10_11_11                         = 0x6,
6041 	BUF_DATA_FORMAT_11_11_10                         = 0x7,
6042 	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
6043 	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
6044 	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
6045 	BUF_DATA_FORMAT_32_32                            = 0xb,
6046 	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
6047 	BUF_DATA_FORMAT_32_32_32                         = 0xd,
6048 	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
6049 	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
6050 } BUF_DATA_FORMAT;
6051 typedef enum IMG_DATA_FORMAT {
6052 	IMG_DATA_FORMAT_INVALID                          = 0x0,
6053 	IMG_DATA_FORMAT_8                                = 0x1,
6054 	IMG_DATA_FORMAT_16                               = 0x2,
6055 	IMG_DATA_FORMAT_8_8                              = 0x3,
6056 	IMG_DATA_FORMAT_32                               = 0x4,
6057 	IMG_DATA_FORMAT_16_16                            = 0x5,
6058 	IMG_DATA_FORMAT_10_11_11                         = 0x6,
6059 	IMG_DATA_FORMAT_11_11_10                         = 0x7,
6060 	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
6061 	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
6062 	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
6063 	IMG_DATA_FORMAT_32_32                            = 0xb,
6064 	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
6065 	IMG_DATA_FORMAT_32_32_32                         = 0xd,
6066 	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
6067 	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
6068 	IMG_DATA_FORMAT_5_6_5                            = 0x10,
6069 	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
6070 	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
6071 	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
6072 	IMG_DATA_FORMAT_8_24                             = 0x14,
6073 	IMG_DATA_FORMAT_24_8                             = 0x15,
6074 	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
6075 	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
6076 	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
6077 	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
6078 	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
6079 	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
6080 	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
6081 	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
6082 	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
6083 	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
6084 	IMG_DATA_FORMAT_GB_GR                            = 0x20,
6085 	IMG_DATA_FORMAT_BG_RG                            = 0x21,
6086 	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
6087 	IMG_DATA_FORMAT_BC1                              = 0x23,
6088 	IMG_DATA_FORMAT_BC2                              = 0x24,
6089 	IMG_DATA_FORMAT_BC3                              = 0x25,
6090 	IMG_DATA_FORMAT_BC4                              = 0x26,
6091 	IMG_DATA_FORMAT_BC5                              = 0x27,
6092 	IMG_DATA_FORMAT_BC6                              = 0x28,
6093 	IMG_DATA_FORMAT_BC7                              = 0x29,
6094 	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
6095 	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
6096 	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
6097 	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
6098 	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
6099 	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
6100 	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
6101 	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
6102 	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
6103 	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
6104 	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
6105 	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
6106 	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
6107 	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
6108 	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
6109 	IMG_DATA_FORMAT_4_4                              = 0x39,
6110 	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
6111 	IMG_DATA_FORMAT_1                                = 0x3b,
6112 	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
6113 	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
6114 	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
6115 	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
6116 } IMG_DATA_FORMAT;
6117 typedef enum BUF_NUM_FORMAT {
6118 	BUF_NUM_FORMAT_UNORM                             = 0x0,
6119 	BUF_NUM_FORMAT_SNORM                             = 0x1,
6120 	BUF_NUM_FORMAT_USCALED                           = 0x2,
6121 	BUF_NUM_FORMAT_SSCALED                           = 0x3,
6122 	BUF_NUM_FORMAT_UINT                              = 0x4,
6123 	BUF_NUM_FORMAT_SINT                              = 0x5,
6124 	BUF_NUM_FORMAT_SNORM_OGL                         = 0x6,
6125 	BUF_NUM_FORMAT_FLOAT                             = 0x7,
6126 } BUF_NUM_FORMAT;
6127 typedef enum IMG_NUM_FORMAT {
6128 	IMG_NUM_FORMAT_UNORM                             = 0x0,
6129 	IMG_NUM_FORMAT_SNORM                             = 0x1,
6130 	IMG_NUM_FORMAT_USCALED                           = 0x2,
6131 	IMG_NUM_FORMAT_SSCALED                           = 0x3,
6132 	IMG_NUM_FORMAT_UINT                              = 0x4,
6133 	IMG_NUM_FORMAT_SINT                              = 0x5,
6134 	IMG_NUM_FORMAT_SNORM_OGL                         = 0x6,
6135 	IMG_NUM_FORMAT_FLOAT                             = 0x7,
6136 	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
6137 	IMG_NUM_FORMAT_SRGB                              = 0x9,
6138 	IMG_NUM_FORMAT_UBNORM                            = 0xa,
6139 	IMG_NUM_FORMAT_UBNORM_OGL                        = 0xb,
6140 	IMG_NUM_FORMAT_UBINT                             = 0xc,
6141 	IMG_NUM_FORMAT_UBSCALED                          = 0xd,
6142 	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
6143 	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
6144 } IMG_NUM_FORMAT;
6145 typedef enum TileType {
6146 	ARRAY_COLOR_TILE                                 = 0x0,
6147 	ARRAY_DEPTH_TILE                                 = 0x1,
6148 } TileType;
6149 typedef enum NonDispTilingOrder {
6150 	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
6151 	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
6152 } NonDispTilingOrder;
6153 typedef enum MicroTileMode {
6154 	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
6155 	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
6156 	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
6157 	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
6158 	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
6159 } MicroTileMode;
6160 typedef enum TileSplit {
6161 	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
6162 	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
6163 	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
6164 	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
6165 	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
6166 	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
6167 	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
6168 } TileSplit;
6169 typedef enum SampleSplit {
6170 	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
6171 	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
6172 	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
6173 	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
6174 } SampleSplit;
6175 typedef enum PipeConfig {
6176 	ADDR_SURF_P2                                     = 0x0,
6177 	ADDR_SURF_P2_RESERVED0                           = 0x1,
6178 	ADDR_SURF_P2_RESERVED1                           = 0x2,
6179 	ADDR_SURF_P2_RESERVED2                           = 0x3,
6180 	ADDR_SURF_P4_8x16                                = 0x4,
6181 	ADDR_SURF_P4_16x16                               = 0x5,
6182 	ADDR_SURF_P4_16x32                               = 0x6,
6183 	ADDR_SURF_P4_32x32                               = 0x7,
6184 	ADDR_SURF_P8_16x16_8x16                          = 0x8,
6185 	ADDR_SURF_P8_16x32_8x16                          = 0x9,
6186 	ADDR_SURF_P8_32x32_8x16                          = 0xa,
6187 	ADDR_SURF_P8_16x32_16x16                         = 0xb,
6188 	ADDR_SURF_P8_32x32_16x16                         = 0xc,
6189 	ADDR_SURF_P8_32x32_16x32                         = 0xd,
6190 	ADDR_SURF_P8_32x64_32x32                         = 0xe,
6191 	ADDR_SURF_P8_RESERVED0                           = 0xf,
6192 	ADDR_SURF_P16_32x32_8x16                         = 0x10,
6193 	ADDR_SURF_P16_32x32_16x16                        = 0x11,
6194 } PipeConfig;
6195 typedef enum NumBanks {
6196 	ADDR_SURF_2_BANK                                 = 0x0,
6197 	ADDR_SURF_4_BANK                                 = 0x1,
6198 	ADDR_SURF_8_BANK                                 = 0x2,
6199 	ADDR_SURF_16_BANK                                = 0x3,
6200 } NumBanks;
6201 typedef enum BankWidth {
6202 	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
6203 	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
6204 	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
6205 	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
6206 } BankWidth;
6207 typedef enum BankHeight {
6208 	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
6209 	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
6210 	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
6211 	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
6212 } BankHeight;
6213 typedef enum BankWidthHeight {
6214 	ADDR_SURF_BANK_WH_1                              = 0x0,
6215 	ADDR_SURF_BANK_WH_2                              = 0x1,
6216 	ADDR_SURF_BANK_WH_4                              = 0x2,
6217 	ADDR_SURF_BANK_WH_8                              = 0x3,
6218 } BankWidthHeight;
6219 typedef enum MacroTileAspect {
6220 	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
6221 	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
6222 	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
6223 	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
6224 } MacroTileAspect;
6225 typedef enum TCC_CACHE_POLICIES {
6226 	TCC_CACHE_POLICY_LRU                             = 0x0,
6227 	TCC_CACHE_POLICY_STREAM                          = 0x1,
6228 	TCC_CACHE_POLICY_BYPASS                          = 0x2,
6229 } TCC_CACHE_POLICIES;
6230 typedef enum MTYPE {
6231 	MTYPE_NC_NV                                      = 0x0,
6232 	MTYPE_NC                                         = 0x1,
6233 	MTYPE_CC                                         = 0x2,
6234 	MTYPE_UC                                         = 0x3,
6235 } MTYPE;
6236 typedef enum PERFMON_COUNTER_MODE {
6237 	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
6238 	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
6239 	PERFMON_COUNTER_MODE_MAX                         = 0x2,
6240 	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
6241 	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
6242 	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
6243 	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
6244 	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
6245 	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
6246 	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
6247 	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
6248 } PERFMON_COUNTER_MODE;
6249 typedef enum PERFMON_SPM_MODE {
6250 	PERFMON_SPM_MODE_OFF                             = 0x0,
6251 	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
6252 	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
6253 	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
6254 	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
6255 	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
6256 	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
6257 	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
6258 	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
6259 	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
6260 	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
6261 } PERFMON_SPM_MODE;
6262 typedef enum SurfaceTiling {
6263 	ARRAY_LINEAR                                     = 0x0,
6264 	ARRAY_TILED                                      = 0x1,
6265 } SurfaceTiling;
6266 typedef enum SurfaceArray {
6267 	ARRAY_1D                                         = 0x0,
6268 	ARRAY_2D                                         = 0x1,
6269 	ARRAY_3D                                         = 0x2,
6270 	ARRAY_3D_SLICE                                   = 0x3,
6271 } SurfaceArray;
6272 typedef enum ColorArray {
6273 	ARRAY_2D_ALT_COLOR                               = 0x0,
6274 	ARRAY_2D_COLOR                                   = 0x1,
6275 	ARRAY_3D_SLICE_COLOR                             = 0x3,
6276 } ColorArray;
6277 typedef enum DepthArray {
6278 	ARRAY_2D_ALT_DEPTH                               = 0x0,
6279 	ARRAY_2D_DEPTH                                   = 0x1,
6280 } DepthArray;
6281 
6282 #endif /* GFX_7_2_ENUM_H */
6283