1 /* $NetBSD: gc_9_4_1_sh_mask.h,v 1.2 2021/12/18 23:45:14 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2020 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _gc_9_4_1_SH_MASK_HEADER 24 #define _gc_9_4_1_SH_MASK_HEADER 25 26 // addressBlock: gc_cppdec2 27 //CPF_EDC_TAG_CNT 28 #define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 29 #define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 30 #define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L 31 #define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL 32 //CPF_EDC_ROQ_CNT 33 #define CPF_EDC_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0 34 #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2 35 #define CPF_EDC_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4 36 #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6 37 #define CPF_EDC_ROQ_CNT__DED_COUNT_ME1_MASK 0x00000003L 38 #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 39 #define CPF_EDC_ROQ_CNT__DED_COUNT_ME2_MASK 0x00000030L 40 #define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2_MASK 0x000000C0L 41 //CPG_EDC_TAG_CNT 42 #define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0 43 #define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2 44 #define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L 45 #define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL 46 //CPG_EDC_DMA_CNT 47 #define CPG_EDC_DMA_CNT__ROQ_DED_COUNT__SHIFT 0x0 48 #define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT__SHIFT 0x2 49 #define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x4 50 #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x6 51 #define CPG_EDC_DMA_CNT__ROQ_DED_COUNT_MASK 0x00000003L 52 #define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT_MASK 0x0000000CL 53 #define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x00000030L 54 #define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x000000C0L 55 //CPC_EDC_SCRATCH_CNT 56 #define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0 57 #define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2 58 #define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L 59 #define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL 60 //CPC_EDC_UCODE_CNT 61 #define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0 62 #define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2 63 #define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L 64 #define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL 65 //DC_EDC_STATE_CNT 66 #define DC_EDC_STATE_CNT__DED_COUNT_ME1__SHIFT 0x0 67 #define DC_EDC_STATE_CNT__SEC_COUNT_ME1__SHIFT 0x2 68 #define DC_EDC_STATE_CNT__DED_COUNT_ME1_MASK 0x00000003L 69 #define DC_EDC_STATE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 70 //DC_EDC_CSINVOC_CNT 71 #define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1__SHIFT 0x0 72 #define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1__SHIFT 0x2 73 #define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1__SHIFT 0x4 74 #define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1__SHIFT 0x6 75 #define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1_MASK 0x00000003L 76 #define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 77 #define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1_MASK 0x00000030L 78 #define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L 79 //DC_EDC_RESTORE_CNT 80 #define DC_EDC_RESTORE_CNT__DED_COUNT_ME1__SHIFT 0x0 81 #define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1__SHIFT 0x2 82 #define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1__SHIFT 0x4 83 #define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1__SHIFT 0x6 84 #define DC_EDC_RESTORE_CNT__DED_COUNT_ME1_MASK 0x00000003L 85 #define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL 86 #define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1_MASK 0x00000030L 87 #define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L 88 89 // addressBlock: gc_gdsdec 90 //GDS_EDC_CNT 91 #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 92 #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 93 #define GDS_EDC_CNT__UNUSED__SHIFT 0x6 94 #define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L 95 #define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L 96 #define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L 97 //GDS_EDC_GRBM_CNT 98 #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 99 #define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 100 #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 101 #define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L 102 #define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL 103 #define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L 104 //GDS_EDC_OA_DED 105 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 106 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 107 #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 108 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 109 #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 110 #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 111 #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 112 #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 113 #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 114 #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 115 #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa 116 #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb 117 #define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc 118 #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L 119 #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L 120 #define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L 121 #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L 122 #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L 123 #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L 124 #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L 125 #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L 126 #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L 127 #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L 128 #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L 129 #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L 130 #define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L 131 //GDS_EDC_OA_PHY_CNT 132 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 133 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 134 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 135 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 136 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC__SHIFT 0x8 137 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED__SHIFT 0xa 138 #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xc 139 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L 140 #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL 141 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L 142 #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L 143 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SEC_MASK 0x00000300L 144 #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_DED_MASK 0x00000C00L 145 #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFF000L 146 //GDS_EDC_OA_PIPE_CNT 147 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 148 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 149 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 150 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 151 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 152 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa 153 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc 154 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe 155 #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 156 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L 157 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL 158 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L 159 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L 160 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L 161 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L 162 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L 163 #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L 164 #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L 165 166 // addressBlock: gc_shsdec 167 //SPI_EDC_CNT 168 #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT__SHIFT 0x0 169 #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT__SHIFT 0x2 170 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT__SHIFT 0x4 171 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT__SHIFT 0x6 172 #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT__SHIFT 0x8 173 #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT__SHIFT 0xa 174 #define SPI_EDC_CNT__SPI_WB_GRANT_61_SEC_COUNT__SHIFT 0xc 175 #define SPI_EDC_CNT__SPI_WB_GRANT_61_DED_COUNT__SHIFT 0xe 176 #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT__SHIFT 0x10 177 #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT__SHIFT 0x12 178 #define SPI_EDC_CNT__SPI_SR_MEM_SEC_COUNT_MASK 0x00000003L 179 #define SPI_EDC_CNT__SPI_SR_MEM_DED_COUNT_MASK 0x0000000CL 180 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_SEC_COUNT_MASK 0x00000030L 181 #define SPI_EDC_CNT__SPI_GDS_EXPREQ_DED_COUNT_MASK 0x000000C0L 182 #define SPI_EDC_CNT__SPI_WB_GRANT_30_SEC_COUNT_MASK 0x00000300L 183 #define SPI_EDC_CNT__SPI_WB_GRANT_30_DED_COUNT_MASK 0x00000C00L 184 #define SPI_EDC_CNT__SPI_WB_GRANT_61_SEC_COUNT_MASK 0x00003000L 185 #define SPI_EDC_CNT__SPI_WB_GRANT_61_DED_COUNT_MASK 0x0000C000L 186 #define SPI_EDC_CNT__SPI_LIFE_CNT_SEC_COUNT_MASK 0x00030000L 187 #define SPI_EDC_CNT__SPI_LIFE_CNT_DED_COUNT_MASK 0x000C0000L 188 189 // addressBlock: gc_sqdec 190 //SQC_EDC_CNT2 191 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 192 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 193 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 194 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 195 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 196 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa 197 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc 198 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe 199 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x10 200 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x12 201 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L 202 #define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL 203 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L 204 #define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L 205 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L 206 #define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L 207 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L 208 #define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L 209 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x00030000L 210 #define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x000C0000L 211 //SQC_EDC_CNT3 212 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 213 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 214 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 215 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 216 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 217 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa 218 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc 219 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe 220 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L 221 #define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL 222 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L 223 #define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L 224 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L 225 #define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L 226 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L 227 #define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L 228 //SQC_EDC_PARITY_CNT3 229 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x0 230 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x2 231 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0x4 232 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0x6 233 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT__SHIFT 0x8 234 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT__SHIFT 0xa 235 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT__SHIFT 0xc 236 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT__SHIFT 0xe 237 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT__SHIFT 0x10 238 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT__SHIFT 0x12 239 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x14 240 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x16 241 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT__SHIFT 0x18 242 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT__SHIFT 0x1a 243 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT__SHIFT 0x1c 244 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT__SHIFT 0x1e 245 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00000003L 246 #define SQC_EDC_PARITY_CNT3__INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x0000000CL 247 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00000030L 248 #define SQC_EDC_PARITY_CNT3__INST_BANKA_MISS_FIFO_DED_COUNT_MASK 0x000000C0L 249 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_SEC_COUNT_MASK 0x00000300L 250 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_HIT_FIFO_DED_COUNT_MASK 0x00000C00L 251 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_SEC_COUNT_MASK 0x00003000L 252 #define SQC_EDC_PARITY_CNT3__DATA_BANKA_MISS_FIFO_DED_COUNT_MASK 0x0000C000L 253 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT_MASK 0x00030000L 254 #define SQC_EDC_PARITY_CNT3__INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT_MASK 0x000C0000L 255 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x00300000L 256 #define SQC_EDC_PARITY_CNT3__INST_BANKB_MISS_FIFO_DED_COUNT_MASK 0x00C00000L 257 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_SEC_COUNT_MASK 0x03000000L 258 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_HIT_FIFO_DED_COUNT_MASK 0x0C000000L 259 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_SEC_COUNT_MASK 0x30000000L 260 #define SQC_EDC_PARITY_CNT3__DATA_BANKB_MISS_FIFO_DED_COUNT_MASK 0xC0000000L 261 //SQC_EDC_CNT 262 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 263 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 264 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 265 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 266 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 267 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa 268 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc 269 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe 270 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 271 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 272 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 273 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 274 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 275 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a 276 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c 277 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e 278 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L 279 #define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL 280 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L 281 #define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L 282 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L 283 #define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L 284 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L 285 #define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L 286 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L 287 #define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L 288 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L 289 #define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L 290 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L 291 #define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L 292 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L 293 #define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L 294 //SQ_EDC_SEC_CNT 295 #define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 296 #define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 297 #define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 298 #define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL 299 #define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L 300 #define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L 301 //SQ_EDC_DED_CNT 302 #define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 303 #define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 304 #define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 305 #define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL 306 #define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L 307 #define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L 308 //SQ_EDC_INFO 309 #define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 310 #define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 311 #define SQ_EDC_INFO__SOURCE__SHIFT 0x6 312 #define SQ_EDC_INFO__VM_ID__SHIFT 0x9 313 #define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL 314 #define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L 315 #define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L 316 #define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L 317 //SQ_EDC_CNT 318 #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 319 #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 320 #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 321 #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 322 #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 323 #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa 324 #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc 325 #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe 326 #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 327 #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 328 #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 329 #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 330 #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 331 #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a 332 #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L 333 #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL 334 #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L 335 #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L 336 #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L 337 #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L 338 #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L 339 #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L 340 #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L 341 #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L 342 #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L 343 #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L 344 #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L 345 #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L 346 347 // addressBlock: gc_tpdec 348 //TA_EDC_CNT 349 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0 350 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2 351 #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT__SHIFT 0x4 352 #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT__SHIFT 0x6 353 #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT 0x8 354 #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT 0xa 355 #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT 0xc 356 #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT 0xe 357 #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT 0x10 358 #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT 0x12 359 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L 360 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL 361 #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT_MASK 0x00000030L 362 #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT_MASK 0x000000C0L 363 #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK 0x00000300L 364 #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK 0x00000C00L 365 #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK 0x00003000L 366 #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK 0x0000C000L 367 #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK 0x00030000L 368 #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK 0x000C0000L 369 370 // addressBlock: gc_tcdec 371 //TCP_EDC_CNT 372 #define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 373 #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 374 #define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 375 #define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL 376 #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L 377 #define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L 378 //TCP_EDC_CNT_NEW 379 #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT 0x0 380 #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT 0x2 381 #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT 0x4 382 #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT 0x6 383 #define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT__SHIFT 0x8 384 #define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT__SHIFT 0xa 385 #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT 0xc 386 #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT 0xe 387 #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT 0x10 388 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT 0x12 389 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT 0x14 390 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT 0x16 391 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT 0x18 392 #define TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK 0x00000003L 393 #define TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK 0x0000000CL 394 #define TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK 0x00000030L 395 #define TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK 0x000000C0L 396 #define TCP_EDC_CNT_NEW__CMD_FIFO_SEC_COUNT_MASK 0x00000300L 397 #define TCP_EDC_CNT_NEW__CMD_FIFO_DED_COUNT_MASK 0x00000C00L 398 #define TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK 0x00003000L 399 #define TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK 0x0000C000L 400 #define TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK 0x00030000L 401 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK 0x000C0000L 402 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK 0x00300000L 403 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK 0x00C00000L 404 #define TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK 0x03000000L 405 //TCP_ATC_EDC_GATCL1_CNT 406 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 407 #define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL 408 //TCI_EDC_CNT 409 #define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT__SHIFT 0x0 410 #define TCI_EDC_CNT__WRITE_RAM_DED_COUNT__SHIFT 0x2 411 #define TCI_EDC_CNT__WRITE_RAM_SEC_COUNT_MASK 0x00000003L 412 #define TCI_EDC_CNT__WRITE_RAM_DED_COUNT_MASK 0x0000000CL 413 //TCA_EDC_CNT 414 #define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT__SHIFT 0x0 415 #define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT__SHIFT 0x2 416 #define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT__SHIFT 0x4 417 #define TCA_EDC_CNT__REQ_FIFO_DED_COUNT__SHIFT 0x6 418 #define TCA_EDC_CNT__HOLE_FIFO_SEC_COUNT_MASK 0x00000003L 419 #define TCA_EDC_CNT__HOLE_FIFO_DED_COUNT_MASK 0x0000000CL 420 #define TCA_EDC_CNT__REQ_FIFO_SEC_COUNT_MASK 0x00000030L 421 #define TCA_EDC_CNT__REQ_FIFO_DED_COUNT_MASK 0x000000C0L 422 //TCC_EDC_CNT 423 #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 424 #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 425 #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 426 #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 427 #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 428 #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa 429 #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc 430 #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe 431 #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 432 #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 433 #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT__SHIFT 0x14 434 #define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT__SHIFT 0x16 435 #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT__SHIFT 0x18 436 #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT__SHIFT 0x1a 437 #define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L 438 #define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL 439 #define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L 440 #define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L 441 #define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L 442 #define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L 443 #define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L 444 #define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L 445 #define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L 446 #define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L 447 #define TCC_EDC_CNT__LATENCY_FIFO_SEC_COUNT_MASK 0x00300000L 448 #define TCC_EDC_CNT__LATENCY_FIFO_DED_COUNT_MASK 0x00C00000L 449 #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_SEC_COUNT_MASK 0x03000000L 450 #define TCC_EDC_CNT__LATENCY_FIFO_NEXT_RAM_DED_COUNT_MASK 0x0C000000L 451 //TCC_EDC_CNT2 452 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT__SHIFT 0x0 453 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT__SHIFT 0x2 454 #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT__SHIFT 0x4 455 #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT__SHIFT 0x6 456 #define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT__SHIFT 0x8 457 #define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT__SHIFT 0xa 458 #define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT__SHIFT 0xc 459 #define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT__SHIFT 0xe 460 #define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT__SHIFT 0x10 461 #define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT__SHIFT 0x12 462 #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT__SHIFT 0x14 463 #define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT__SHIFT 0x16 464 #define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT__SHIFT 0x18 465 #define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT__SHIFT 0x1a 466 #define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT__SHIFT 0x1c 467 #define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT__SHIFT 0x1e 468 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SEC_COUNT_MASK 0x00000003L 469 #define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_DED_COUNT_MASK 0x0000000CL 470 #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_SEC_COUNT_MASK 0x00000030L 471 #define TCC_EDC_CNT2__UC_ATOMIC_FIFO_DED_COUNT_MASK 0x000000C0L 472 #define TCC_EDC_CNT2__WRITE_CACHE_READ_SEC_COUNT_MASK 0x00000300L 473 #define TCC_EDC_CNT2__WRITE_CACHE_READ_DED_COUNT_MASK 0x00000C00L 474 #define TCC_EDC_CNT2__RETURN_CONTROL_SEC_COUNT_MASK 0x00003000L 475 #define TCC_EDC_CNT2__RETURN_CONTROL_DED_COUNT_MASK 0x0000C000L 476 #define TCC_EDC_CNT2__IN_USE_TRANSFER_SEC_COUNT_MASK 0x00030000L 477 #define TCC_EDC_CNT2__IN_USE_TRANSFER_DED_COUNT_MASK 0x000C0000L 478 #define TCC_EDC_CNT2__IN_USE_DEC_SEC_COUNT_MASK 0x00300000L 479 #define TCC_EDC_CNT2__IN_USE_DEC_DED_COUNT_MASK 0x00C00000L 480 #define TCC_EDC_CNT2__WRITE_RETURN_SEC_COUNT_MASK 0x03000000L 481 #define TCC_EDC_CNT2__WRITE_RETURN_DED_COUNT_MASK 0x0C000000L 482 #define TCC_EDC_CNT2__RETURN_DATA_SEC_COUNT_MASK 0x30000000L 483 #define TCC_EDC_CNT2__RETURN_DATA_DED_COUNT_MASK 0xC0000000L 484 485 // addressBlock: gc_tpdec 486 //TD_EDC_CNT 487 #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT 0x0 488 #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT 0x2 489 #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT 0x4 490 #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT 0x6 491 #define TD_EDC_CNT__CS_FIFO_SEC_COUNT__SHIFT 0x8 492 #define TD_EDC_CNT__CS_FIFO_DED_COUNT__SHIFT 0xa 493 #define TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK 0x00000003L 494 #define TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK 0x0000000CL 495 #define TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK 0x00000030L 496 #define TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK 0x000000C0L 497 #define TD_EDC_CNT__CS_FIFO_SEC_COUNT_MASK 0x00000300L 498 #define TD_EDC_CNT__CS_FIFO_DED_COUNT_MASK 0x00000C00L 499 //TA_EDC_CNT 500 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT 0x0 501 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT 0x2 502 #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT__SHIFT 0x4 503 #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT__SHIFT 0x6 504 #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT__SHIFT 0x8 505 #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT__SHIFT 0xa 506 #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT__SHIFT 0xc 507 #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT__SHIFT 0xe 508 #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT__SHIFT 0x10 509 #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT__SHIFT 0x12 510 #define TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK 0x00000003L 511 #define TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK 0x0000000CL 512 #define TA_EDC_CNT__TA_FS_AFIFO_SEC_COUNT_MASK 0x00000030L 513 #define TA_EDC_CNT__TA_FS_AFIFO_DED_COUNT_MASK 0x000000C0L 514 #define TA_EDC_CNT__TA_FL_LFIFO_SEC_COUNT_MASK 0x00000300L 515 #define TA_EDC_CNT__TA_FL_LFIFO_DED_COUNT_MASK 0x00000C00L 516 #define TA_EDC_CNT__TA_FX_LFIFO_SEC_COUNT_MASK 0x00003000L 517 #define TA_EDC_CNT__TA_FX_LFIFO_DED_COUNT_MASK 0x0000C000L 518 #define TA_EDC_CNT__TA_FS_CFIFO_SEC_COUNT_MASK 0x00030000L 519 #define TA_EDC_CNT__TA_FS_CFIFO_DED_COUNT_MASK 0x000C0000L 520 521 // addressBlock: gc_ea_gceadec2 522 //GCEA_EDC_CNT 523 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 524 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 525 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 526 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 527 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 528 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 529 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 530 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 531 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 532 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 533 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 534 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 535 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 536 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 537 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 538 #define GCEA_EDC_CNT__MAM_AFMEM_SEC_COUNT__SHIFT 0x1e 539 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 540 #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 541 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 542 #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 543 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 544 #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 545 #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 546 #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 547 #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 548 #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 549 #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 550 #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 551 #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 552 #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 553 #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 554 #define GCEA_EDC_CNT__MAM_AFMEM_SEC_COUNT_MASK 0xC0000000L 555 //GCEA_EDC_CNT2 556 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 557 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 558 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 559 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 560 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 561 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 562 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 563 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 564 #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 565 #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 566 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 567 #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 568 #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 569 #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 570 #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 571 #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 572 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 573 #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 574 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 575 #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 576 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 577 #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 578 #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 579 #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 580 #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 581 #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 582 #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 583 #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 584 #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 585 #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 586 #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 587 #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 588 //GCEA_EDC_CNT3 589 #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 590 #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 591 #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 592 #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 593 #define GCEA_EDC_CNT3__IOWR_DATAMEM_DED_COUNT__SHIFT 0x8 594 #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0xa 595 #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xc 596 #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT 0xe 597 #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT 0x10 598 #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT 0x12 599 #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x14 600 #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT 0x16 601 #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT 0x18 602 #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT 0x1a 603 #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT 0x1c 604 #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT 0x1e 605 #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 606 #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 607 #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 608 #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 609 #define GCEA_EDC_CNT3__IOWR_DATAMEM_DED_COUNT_MASK 0x00000300L 610 #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000C00L 611 #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00003000L 612 #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK 0x0000C000L 613 #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK 0x00030000L 614 #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK 0x000C0000L 615 #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK 0x00300000L 616 #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK 0x00C00000L 617 #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK 0x03000000L 618 #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK 0x0C000000L 619 #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x30000000L 620 #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0xC0000000L 621 622 // addressBlock: gc_gfxudec 623 //GRBM_GFX_INDEX 624 #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 625 #define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 626 #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 627 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 628 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 629 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f 630 #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL 631 #define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L 632 #define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L 633 #define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L 634 #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L 635 #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L 636 637 // addressBlock: gc_utcl2_atcl2dec 638 //ATC_L2_CNTL 639 //ATC_L2_CACHE_4K_DSM_INDEX 640 #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 641 #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL 642 //ATC_L2_CACHE_2M_DSM_INDEX 643 #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 644 #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL 645 //ATC_L2_CACHE_4K_DSM_CNTL 646 #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd 647 #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf 648 #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 649 #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L 650 //ATC_L2_CACHE_2M_DSM_CNTL 651 #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd 652 #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf 653 #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 654 #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L 655 656 // addressBlock: gc_utcl2_vml2pfdec 657 //VML2_MEM_ECC_INDEX 658 #define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 659 #define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 660 //VML2_WALKER_MEM_ECC_INDEX 661 #define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 662 #define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 663 //UTCL2_MEM_ECC_INDEX 664 #define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 665 #define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 666 //VML2_MEM_ECC_CNTL 667 #define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 668 #define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 669 #define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 670 #define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 671 //VML2_WALKER_MEM_ECC_CNTL 672 #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 673 #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 674 #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 675 #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 676 //UTCL2_MEM_ECC_CNTL 677 #define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 678 #define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 679 #define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 680 #define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 681 682 // addressBlock: gc_rlcpdec 683 //RLC_EDC_CNT 684 #define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT__SHIFT 0x0 685 #define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT__SHIFT 0x2 686 #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 687 #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 688 #define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT__SHIFT 0x8 689 #define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT__SHIFT 0xa 690 #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc 691 #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT__SHIFT 0xe 692 #define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT__SHIFT 0x10 693 #define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT__SHIFT 0x12 694 #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 695 #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 696 #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT__SHIFT 0x18 697 #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT__SHIFT 0x1a 698 #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT__SHIFT 0x1c 699 #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT__SHIFT 0x1e 700 #define RLC_EDC_CNT__RLCG_INSTR_RAM_SEC_COUNT_MASK 0x00000003L 701 #define RLC_EDC_CNT__RLCG_INSTR_RAM_DED_COUNT_MASK 0x0000000CL 702 #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L 703 #define RLC_EDC_CNT__RLCG_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L 704 #define RLC_EDC_CNT__RLCV_INSTR_RAM_SEC_COUNT_MASK 0x00000300L 705 #define RLC_EDC_CNT__RLCV_INSTR_RAM_DED_COUNT_MASK 0x00000C00L 706 #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L 707 #define RLC_EDC_CNT__RLCV_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L 708 #define RLC_EDC_CNT__RLC_TCTAG_RAM_SEC_COUNT_MASK 0x00030000L 709 #define RLC_EDC_CNT__RLC_TCTAG_RAM_DED_COUNT_MASK 0x000C0000L 710 #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L 711 #define RLC_EDC_CNT__RLC_SPM_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L 712 #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_SEC_COUNT_MASK 0x03000000L 713 #define RLC_EDC_CNT__RLC_SRM_DATA_RAM_DED_COUNT_MASK 0x0C000000L 714 #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_SEC_COUNT_MASK 0x30000000L 715 #define RLC_EDC_CNT__RLC_SRM_ADDR_RAM_DED_COUNT_MASK 0xC0000000L 716 //RLC_EDC_CNT2 717 #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT__SHIFT 0x0 718 #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT__SHIFT 0x2 719 #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT__SHIFT 0x4 720 #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT__SHIFT 0x6 721 #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT__SHIFT 0x8 722 #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT__SHIFT 0xa 723 #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT__SHIFT 0xc 724 #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT__SHIFT 0xe 725 #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT__SHIFT 0x10 726 #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT__SHIFT 0x12 727 #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT__SHIFT 0x14 728 #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT__SHIFT 0x16 729 #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT__SHIFT 0x18 730 #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT__SHIFT 0x1a 731 #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT__SHIFT 0x1c 732 #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT__SHIFT 0x1e 733 #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT_MASK 0x00000003L 734 #define RLC_EDC_CNT2__RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT_MASK 0x0000000CL 735 #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT_MASK 0x00000030L 736 #define RLC_EDC_CNT2__RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT_MASK 0x000000C0L 737 #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT_MASK 0x00000300L 738 #define RLC_EDC_CNT2__RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT_MASK 0x00000C00L 739 #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT_MASK 0x00003000L 740 #define RLC_EDC_CNT2__RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT_MASK 0x0000C000L 741 #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT_MASK 0x00030000L 742 #define RLC_EDC_CNT2__RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT_MASK 0x000C0000L 743 #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT_MASK 0x00300000L 744 #define RLC_EDC_CNT2__RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT_MASK 0x00C00000L 745 #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT_MASK 0x03000000L 746 #define RLC_EDC_CNT2__RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT_MASK 0x0C000000L 747 #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT_MASK 0x30000000L 748 #define RLC_EDC_CNT2__RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT_MASK 0xC0000000L 749 750 #endif