xref: /dpdk/drivers/net/dpaa2/mc/fsl_dprtc_cmd.h (revision 2cb2abf304fcecc0e2804b8da61760d4f2cb9a7e)
1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2  * Copyright 2019-2021 NXP
3  */
4 #include <fsl_mc_sys.h>
5 #ifndef _FSL_DPRTC_CMD_H
6 #define _FSL_DPRTC_CMD_H
7 
8 /* DPRTC Version */
9 #define DPRTC_VER_MAJOR			2
10 #define DPRTC_VER_MINOR			3
11 
12 /* Command versioning */
13 #define DPRTC_CMD_BASE_VERSION		1
14 #define DPRTC_CMD_VERSION_2		2
15 #define DPRTC_CMD_ID_OFFSET		4
16 
17 #define DPRTC_CMD(id)	(((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_BASE_VERSION)
18 #define DPRTC_CMD_V2(id) (((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_VERSION_2)
19 
20 /* Command IDs */
21 #define DPRTC_CMDID_CLOSE			DPRTC_CMD(0x800)
22 #define DPRTC_CMDID_OPEN			DPRTC_CMD(0x810)
23 #define DPRTC_CMDID_CREATE			DPRTC_CMD(0x910)
24 #define DPRTC_CMDID_DESTROY			DPRTC_CMD(0x990)
25 #define DPRTC_CMDID_GET_API_VERSION		DPRTC_CMD(0xa10)
26 
27 #define DPRTC_CMDID_ENABLE			DPRTC_CMD(0x002)
28 #define DPRTC_CMDID_DISABLE			DPRTC_CMD(0x003)
29 #define DPRTC_CMDID_GET_ATTR			DPRTC_CMD(0x004)
30 #define DPRTC_CMDID_RESET			DPRTC_CMD(0x005)
31 #define DPRTC_CMDID_IS_ENABLED			DPRTC_CMD(0x006)
32 
33 #define DPRTC_CMDID_SET_CLOCK_OFFSET		DPRTC_CMD(0x1d0)
34 #define DPRTC_CMDID_SET_FREQ_COMPENSATION	DPRTC_CMD(0x1d1)
35 #define DPRTC_CMDID_GET_FREQ_COMPENSATION	DPRTC_CMD(0x1d2)
36 #define DPRTC_CMDID_GET_TIME			DPRTC_CMD(0x1d3)
37 #define DPRTC_CMDID_SET_TIME			DPRTC_CMD(0x1d4)
38 #define DPRTC_CMDID_SET_ALARM			DPRTC_CMD(0x1d5)
39 #define DPRTC_CMDID_SET_PERIODIC_PULSE		DPRTC_CMD(0x1d6)
40 #define DPRTC_CMDID_CLEAR_PERIODIC_PULSE	DPRTC_CMD(0x1d7)
41 #define DPRTC_CMDID_SET_EXT_TRIGGER		DPRTC_CMD(0x1d8)
42 #define DPRTC_CMDID_CLEAR_EXT_TRIGGER		DPRTC_CMD(0x1d9)
43 #define DPRTC_CMDID_GET_EXT_TRIGGER_TIMESTAMP	DPRTC_CMD(0x1dA)
44 #define DPRTC_CMDID_SET_FIPER_LOOPBACK	DPRTC_CMD(0x1dB)
45 
46 /* Macros for accessing command fields smaller than 1byte */
47 #define DPRTC_MASK(field)        \
48 	GENMASK(DPRTC_##field##_SHIFT + DPRTC_##field##_SIZE - 1, \
49 		DPRTC_##field##_SHIFT)
50 #define dprtc_get_field(var, field)      \
51 	(((var) & DPRTC_MASK(field)) >> DPRTC_##field##_SHIFT)
52 
53 #pragma pack(push, 1)
54 struct dprtc_cmd_open {
55 	uint32_t dprtc_id;
56 };
57 
58 struct dprtc_cmd_destroy {
59 	uint32_t object_id;
60 };
61 
62 #define DPRTC_ENABLE_SHIFT	0
63 #define DPRTC_ENABLE_SIZE	1
64 #define DPRTC_ENDIANNESS_SHIFT 0
65 #define DPRTC_ENDIANNESS_SIZE  1
66 
67 struct dprtc_rsp_is_enabled {
68 	uint8_t en;
69 };
70 
71 struct dprtc_rsp_get_attributes {
72 	uint32_t paddr;
73 	uint32_t id;
74 	uint8_t little_endian;
75 };
76 
77 struct dprtc_cmd_set_clock_offset {
78 	uint64_t offset;
79 };
80 
81 struct dprtc_get_freq_compensation {
82 	uint32_t freq_compensation;
83 };
84 
85 struct dprtc_time {
86 	uint64_t time;
87 };
88 
89 struct dprtc_rsp_get_api_version {
90 	uint16_t major;
91 	uint16_t minor;
92 };
93 
94 struct dprtc_cmd_ext_trigger_timestamp {
95 	uint32_t pad;
96 	uint8_t id;
97 };
98 
99 struct dprtc_rsp_ext_trigger_timestamp {
100 	uint8_t unread_valid_timestamp;
101 	uint8_t pad1;
102 	uint16_t pad2;
103 	uint32_t pad3;
104 	uint64_t timestamp;
105 };
106 
107 struct dprtc_ext_trigger_cfg {
108 	uint8_t id;
109 	uint8_t fiper_as_input;
110 };
111 #pragma pack(pop)
112 #endif /* _FSL_DPRTC_CMD_H */
113