1 /* $NetBSD: exynos5422_clock.c,v 1.16 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "locators.h"
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: exynos5422_clock.c,v 1.16 2021/01/27 03:10:19 thorpej Exp $");
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/intr.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/atomic.h>
41
42 #include <dev/clk/clk_backend.h>
43
44 #include <arm/samsung/exynos_reg.h>
45 #include <arm/samsung/exynos_var.h>
46 #include <arm/samsung/exynos_clock.h>
47
48 #include <dev/fdt/fdtvar.h>
49
50 static struct clk *exynos5422_clock_decode(device_t, int, const void *, size_t);
51
52 static const struct fdtbus_clock_controller_func exynos5422_car_fdtclock_funcs = {
53 .decode = exynos5422_clock_decode
54 };
55
56 /* DT clock ID to clock name mappings */
57 static struct exynos5422_clock_id {
58 u_int id;
59 const char *name;
60 } exynos5422_clock_ids[] = {
61 { 1, "fin_pll" },
62 { 2, "fout_apll" },
63 { 3, "fout_cpll" },
64 { 4, "fout_dpll" },
65 { 5, "fout_epll" },
66 { 6, "fout_rpll" },
67 { 7, "fout_ipll" },
68 { 8, "fout_spll" },
69 { 9, "fout_vpll" },
70 { 10, "fout_mpll" },
71 { 11, "fout_bpll" },
72 { 12, "fout_kpll" },
73 { 128, "sclk_uart0" },
74 { 129, "sclk_uart1" },
75 { 130, "sclk_uart2" },
76 { 131, "sclk_uart3" },
77 { 132, "sclk_mmc0" },
78 { 133, "sclk_mmc1" },
79 { 134, "sclk_mmc2" },
80 { 135, "sclk_spi0" },
81 { 136, "sclk_spi1" },
82 { 137, "sclk_spi2" },
83 { 138, "sclk_i2s1" },
84 { 139, "sclk_i2s2" },
85 { 140, "sclk_pcm1" },
86 { 141, "sclk_pcm2" },
87 { 142, "sclk_spdif" },
88 { 143, "sclk_hdmi" },
89 { 144, "sclk_pixel" },
90 { 145, "sclk_dp1" },
91 { 146, "sclk_mipi1" },
92 { 147, "sclk_fimd1" },
93 { 148, "sclk_maudio0" },
94 { 149, "sclk_maupcm0" },
95 { 150, "sclk_usbd300" },
96 { 151, "sclk_usbd301" },
97 { 152, "sclk_usbphy300" },
98 { 153, "sclk_usbphy301" },
99 { 154, "sclk_unipro" },
100 { 155, "sclk_pwm" },
101 { 156, "sclk_gscl_wa" },
102 { 157, "sclk_gscl_wb" },
103 { 158, "sclk_hdmiphy" },
104 { 159, "mau_epll" },
105 { 160, "sclk_hsic_12m" },
106 { 161, "sclk_mphy_ixtal24" },
107 { 257, "uart0" },
108 { 258, "uart1" },
109 { 259, "uart2" },
110 { 260, "uart3" },
111 { 261, "i2c0" },
112 { 262, "i2c1" },
113 { 263, "i2c2" },
114 { 264, "i2c3" },
115 { 265, "usi0" },
116 { 266, "usi1" },
117 { 267, "usi2" },
118 { 268, "usi3" },
119 { 269, "i2c_hdmi" },
120 { 270, "tsadc" },
121 { 271, "spi0" },
122 { 272, "spi1" },
123 { 273, "spi2" },
124 { 274, "keyif" },
125 { 275, "i2s1" },
126 { 276, "i2s2" },
127 { 277, "pcm1" },
128 { 278, "pcm2" },
129 { 279, "pwm" },
130 { 280, "spdif" },
131 { 281, "usi4" },
132 { 282, "usi5" },
133 { 283, "usi6" },
134 { 300, "aclk66_psgen" },
135 { 301, "chipid" },
136 { 302, "sysreg" },
137 { 303, "tzpc0" },
138 { 304, "tzpc1" },
139 { 305, "tzpc2" },
140 { 306, "tzpc3" },
141 { 307, "tzpc4" },
142 { 308, "tzpc5" },
143 { 309, "tzpc6" },
144 { 310, "tzpc7" },
145 { 311, "tzpc8" },
146 { 312, "tzpc9" },
147 { 313, "hdmi_cec" },
148 { 314, "seckey" },
149 { 315, "mct" },
150 { 316, "wdt" },
151 { 317, "rtc" },
152 { 318, "tmu" },
153 { 319, "tmu_gpu" },
154 { 330, "pclk66_gpio" },
155 { 350, "aclk200_fsys2" },
156 { 351, "mout_mmc0" },
157 { 352, "mout_mmc1" },
158 { 353, "mout_mmc2" },
159 { 354, "sromc" },
160 { 355, "ufs" },
161 { 360, "aclk200_fsys" },
162 { 361, "tsi" },
163 { 362, "pdma0" },
164 { 363, "pdma1" },
165 { 364, "rtic" },
166 { 365, "usbh20" },
167 { 366, "usbd300" },
168 { 367, "usbd301" },
169 { 380, "aclk400_mscl" },
170 { 381, "mscl0" },
171 { 382, "mscl1" },
172 { 383, "mscl2" },
173 { 384, "smmu_mscl0" },
174 { 385, "smmu_mscl1" },
175 { 386, "smmu_mscl2" },
176 { 400, "aclk333" },
177 { 401, "mfc" },
178 { 402, "smmu_mfcl" },
179 { 403, "smmu_mfcr" },
180 { 410, "aclk200_disp1" },
181 { 411, "dsim1" },
182 { 412, "dp1" },
183 { 413, "hdmi" },
184 { 420, "aclk300_disp1" },
185 { 421, "fimd1" },
186 { 422, "smmu_fimd1m0" },
187 { 423, "smmu_fimd1m1" },
188 { 430, "aclk166" },
189 { 431, "mixer" },
190 { 440, "aclk266" },
191 { 441, "rotator" },
192 { 442, "mdma1" },
193 { 443, "smmu_rotator" },
194 { 444, "smmu_mdma1" },
195 { 450, "aclk300_jpeg" },
196 { 451, "jpeg" },
197 { 452, "jpeg2" },
198 { 453, "smmu_jpeg" },
199 { 454, "smmu_jpeg2" },
200 { 460, "aclk300_gscl" },
201 { 461, "smmu_gscl0" },
202 { 462, "smmu_gscl1" },
203 { 463, "gscl_wa" },
204 { 464, "gscl_wb" },
205 { 465, "gscl0" },
206 { 466, "gscl1" },
207 { 467, "fimc_3aa" },
208 { 470, "aclk266_g2d" },
209 { 471, "sss" },
210 { 472, "slim_sss" },
211 { 473, "mdma0" },
212 { 480, "aclk333_g2d" },
213 { 481, "g2d" },
214 { 490, "aclk333_432_gscl" },
215 { 491, "smmu_3aa" },
216 { 492, "smmu_fimcl0" },
217 { 493, "smmu_fimcl1" },
218 { 494, "smmu_fimcl3" },
219 { 495, "fimc_lite3" },
220 { 496, "fimc_lite0" },
221 { 497, "fimc_lite1" },
222 { 500, "aclk_g3d" },
223 { 501, "g3d" },
224 { 502, "smmu_mixer" },
225 { 503, "smmu_g2d" },
226 { 504, "smmu_mdma0" },
227 { 505, "mc" },
228 { 506, "top_rtc" },
229 { 510, "sclk_uart_isp" },
230 { 511, "sclk_spi0_isp" },
231 { 512, "sclk_spi1_isp" },
232 { 513, "sclk_pwm_isp" },
233 { 514, "sclk_isp_sensor0" },
234 { 515, "sclk_isp_sensor1" },
235 { 516, "sclk_isp_sensor2" },
236 { 517, "aclk432_scaler" },
237 { 518, "aclk432_cam" },
238 { 519, "aclk_fl1550_cam" },
239 { 520, "aclk550_cam" },
240 { 640, "mout_hdmi" },
241 { 641, "mout_g3d" },
242 { 642, "mout_vpll" },
243 { 643, "mout_maudio0" },
244 { 644, "mout_user_aclk333" },
245 { 645, "mout_sw_aclk333" },
246 { 646, "mout_user_aclk200_disp1" },
247 { 647, "mout_sw_aclk200" },
248 { 648, "mout_user_aclk300_disp1" },
249 { 649, "mout_sw_aclk300" },
250 { 650, "mout_user_aclk400_disp1" },
251 { 651, "mout_sw_aclk400" },
252 { 768, "dout_pixel" },
253 };
254
255 static struct clk *exynos5422_clock_get(void *, const char *);
256 static void exynos5422_clock_put(void *, struct clk *);
257 static u_int exynos5422_clock_get_rate(void *, struct clk *);
258 static int exynos5422_clock_set_rate(void *, struct clk *, u_int);
259 static int exynos5422_clock_enable(void *, struct clk *);
260 static int exynos5422_clock_disable(void *, struct clk *);
261 static int exynos5422_clock_set_parent(void *, struct clk *, struct clk *);
262 static struct clk *exynos5422_clock_get_parent(void *, struct clk *);
263
264 static const struct clk_funcs exynos5422_clock_funcs = {
265 .get = exynos5422_clock_get,
266 .put = exynos5422_clock_put,
267 .get_rate = exynos5422_clock_get_rate,
268 .set_rate = exynos5422_clock_set_rate,
269 .enable = exynos5422_clock_enable,
270 .disable = exynos5422_clock_disable,
271 .set_parent = exynos5422_clock_set_parent,
272 .get_parent = exynos5422_clock_get_parent,
273 };
274
275 #define CLK_FIXED(_name, _rate) { \
276 .base = { .name = (_name) }, .type = EXYNOS_CLK_FIXED, \
277 .u = { .fixed = { .rate = (_rate) } } \
278 }
279
280 #define CLK_PLL(_name, _parent, _lock, _con0) { \
281 .base = { .name = (_name) }, .type = EXYNOS_CLK_PLL, \
282 .parent = (_parent), \
283 .u = { \
284 .pll = { \
285 .lock_reg = (_lock), \
286 .con0_reg = (_con0), \
287 } \
288 } \
289 }
290
291 #define CLK_MUXF(_name, _alias, _reg, _bits, _f, _p) { \
292 .base = { .name = (_name), .flags = (_f) }, \
293 .type = EXYNOS_CLK_MUX, \
294 .alias = (_alias), \
295 .u = { \
296 .mux = { \
297 .nparents = __arraycount(_p), \
298 .parents = (_p), \
299 .reg = (_reg), \
300 .bits = (_bits) \
301 } \
302 } \
303 }
304
305 #define CLK_MUXA(_name, _alias, _reg, _bits, _p) \
306 CLK_MUXF(_name, _alias, _reg, _bits, 0, _p)
307
308 #define CLK_MUX(_name, _reg, _bits, _p) \
309 CLK_MUXF(_name, NULL, _reg, _bits, 0, _p)
310
311 #define CLK_DIV(_name, _parent, _reg, _bits) { \
312 .base = { .name = (_name) }, .type = EXYNOS_CLK_DIV, \
313 .parent = (_parent), \
314 .u = { \
315 .div = { \
316 .reg = (_reg), \
317 .bits = (_bits) \
318 } \
319 } \
320 }
321
322 #define CLK_GATE(_name, _parent, _reg, _bits, _f) { \
323 .base = { .name = (_name), .flags = (_f) }, \
324 .type = EXYNOS_CLK_GATE, \
325 .parent = (_parent), \
326 .u = { \
327 .gate = { \
328 .reg = (_reg), \
329 .bits = (_bits) \
330 } \
331 } \
332 }
333
334 #define EXYNOS5422_APLL_LOCK 0x00000
335 #define EXYNOS5422_APLL_CON0 0x00100
336 #define EXYNOS5422_CPLL_LOCK 0x10020
337 #define EXYNOS5422_DPLL_LOCK 0x10030
338 #define EXYNOS5422_EPLL_LOCK 0x10040
339 #define EXYNOS5422_RPLL_LOCK 0x10050
340 #define EXYNOS5422_IPLL_LOCK 0x10060
341 #define EXYNOS5422_SPLL_LOCK 0x10070
342 #define EXYNOS5422_VPLL_LOCK 0x10080
343 #define EXYNOS5422_MPLL_LOCK 0x10090
344 #define EXYNOS5422_CPLL_CON0 0x10120
345 #define EXYNOS5422_DPLL_CON0 0x10128
346 #define EXYNOS5422_EPLL_CON0 0x10130
347 #define EXYNOS5422_EPLL_CON1 0x10134
348 #define EXYNOS5422_EPLL_CON2 0x10138
349 #define EXYNOS5422_RPLL_CON0 0x10140
350 #define EXYNOS5422_RPLL_CON1 0x10144
351 #define EXYNOS5422_RPLL_CON2 0x10148
352 #define EXYNOS5422_IPLL_CON0 0x10150
353 #define EXYNOS5422_SPLL_CON0 0x10160
354 #define EXYNOS5422_VPLL_CON0 0x10170
355 #define EXYNOS5422_MPLL_CON0 0x10180
356 #define EXYNOS5422_BPLL_LOCK 0x20010
357 #define EXYNOS5422_BPLL_CON0 0x20110
358 #define EXYNOS5422_KPLL_LOCK 0x28000
359 #define EXYNOS5422_KPLL_CON0 0x28100
360
361 #define EXYNOS5422_SRC_CPU 0x00200
362 #define EXYNOS5422_SRC_TOP0 0x10200
363 #define EXYNOS5422_SRC_TOP1 0x10204
364 #define EXYNOS5422_SRC_TOP2 0x10208
365 #define EXYNOS5422_SRC_TOP3 0x1020c
366 #define EXYNOS5422_SRC_TOP4 0x10210
367 #define EXYNOS5422_SRC_TOP5 0x10214
368 #define EXYNOS5422_SRC_TOP6 0x10218
369 #define EXYNOS5422_SRC_TOP7 0x1021c
370 #define EXYNOS5422_SRC_DISP10 0x1022c
371 #define EXYNOS5422_SRC_MAU 0x10240
372 #define EXYNOS5422_SRC_FSYS 0x10244
373 #define EXYNOS5422_SRC_PERIC0 0x10250
374 #define EXYNOS5422_SRC_PERIC1 0x10254
375 #define EXYNOS5422_SRC_ISP 0x10270
376 #define EXYNOS5422_SRC_TOP10 0x10280
377 #define EXYNOS5422_SRC_TOP11 0x10284
378 #define EXYNOS5422_SRC_TOP12 0x10288
379
380 #define EXYNOS5422_DIV_TOP0 0x10500
381 #define EXYNOS5422_DIV_TOP1 0x10504
382 #define EXYNOS5422_DIV_FSYS0 0x10548
383 #define EXYNOS5422_DIV_FSYS1 0x1054c
384 #define EXYNOS5422_DIV_PERIC0 0x10558
385
386 #define EXYNOS5422_GATE_BUS_FSYS0 0x10740
387 #define EXYNOS5422_GATE_TOP_SCLK_FSYS 0x10840
388 #define EXYNOS5422_GATE_TOP_SCLK_PERIC 0x10850
389 #define EXYNOS5422_GATE_IP_FSYS 0x10944
390 #define EXYNOS5422_GATE_IP_PERIC 0x10950
391
392 static const char *mout_cpll_p[] = { "fin_pll", "fout_cpll" };
393 static const char *mout_dpll_p[] = { "fin_pll", "fout_dpll" };
394 static const char *mout_mpll_p[] = { "fin_pll", "fout_mpll" };
395 static const char *mout_spll_p[] = { "fin_pll", "fout_spll" };
396 static const char *mout_ipll_p[] = { "fin_pll", "fout_ipll" };
397 static const char *mout_epll_p[] = { "fin_pll", "fout_epll" };
398 static const char *mout_rpll_p[] = { "fin_pll", "fout_rpll" };
399 static const char *mout_group1_p[] =
400 { "sclk_cpll", "sclk_dpll", "sclk_mpp" };
401 static const char *mout_group2_p[] =
402 { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll",
403 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
404 static const char *mout_user_aclk200_fsys_p[] =
405 { "fin_pll", "mout_sw_aclk200_fsys" };
406 static const char *mout_user_aclk200_fsys2_p[] =
407 { "fin_pll", "mout_sw_aclk200_fsys2" };
408 static const char *mout_user_aclk66_peric_p[] =
409 { "fin_pll", "mout_sw_aclk66" };
410 static const char *mout_sw_aclk66_p[] =
411 { "dout_aclk66", "sclk_spll" };
412 static const char *mout_sw_aclk200_fsys_p[] =
413 { "dout_aclk200_fsys", "sclk_spll" };
414 static const char *mout_sw_aclk200_fsys2_p[] =
415 { "dout_aclk200_fsys2", "sclk_spll" };
416
417 static struct exynos_clk exynos5422_clocks[] = {
418 CLK_FIXED("fin_pll", EXYNOS_F_IN_FREQ),
419
420 CLK_PLL("fout_apll", "fin_pll", EXYNOS5422_APLL_LOCK,
421 EXYNOS5422_APLL_CON0),
422 CLK_PLL("fout_cpll", "fin_pll", EXYNOS5422_CPLL_LOCK,
423 EXYNOS5422_CPLL_CON0),
424 CLK_PLL("fout_dpll", "fin_pll", EXYNOS5422_DPLL_LOCK,
425 EXYNOS5422_DPLL_CON0),
426 CLK_PLL("fout_epll", "fin_pll", EXYNOS5422_EPLL_LOCK,
427 EXYNOS5422_EPLL_CON0),
428 CLK_PLL("fout_rpll", "fin_pll", EXYNOS5422_RPLL_LOCK,
429 EXYNOS5422_RPLL_CON0),
430 CLK_PLL("fout_ipll", "fin_pll", EXYNOS5422_IPLL_LOCK,
431 EXYNOS5422_IPLL_CON0),
432 CLK_PLL("fout_spll", "fin_pll", EXYNOS5422_SPLL_LOCK,
433 EXYNOS5422_SPLL_CON0),
434 CLK_PLL("fout_vpll", "fin_pll", EXYNOS5422_VPLL_LOCK,
435 EXYNOS5422_VPLL_CON0),
436 CLK_PLL("fout_mpll", "fin_pll", EXYNOS5422_MPLL_LOCK,
437 EXYNOS5422_MPLL_CON0),
438 CLK_PLL("fout_bpll", "fin_pll", EXYNOS5422_BPLL_LOCK,
439 EXYNOS5422_BPLL_CON0),
440 CLK_PLL("fout_kpll", "fin_pll", EXYNOS5422_KPLL_LOCK,
441 EXYNOS5422_KPLL_CON0),
442
443 CLK_MUXA("sclk_cpll", "mout_cpll", EXYNOS5422_SRC_TOP6, __BIT(28),
444 mout_cpll_p),
445 CLK_MUXA("sclk_dpll", "mout_dpll", EXYNOS5422_SRC_TOP6, __BIT(24),
446 mout_dpll_p),
447 CLK_MUXA("sclk_mpll", "mout_mpll", EXYNOS5422_SRC_TOP6, __BIT(0),
448 mout_mpll_p),
449 CLK_MUXA("sclk_spll", "mout_spll", EXYNOS5422_SRC_TOP6, __BIT(8),
450 mout_spll_p),
451 CLK_MUXA("sclk_ipll", "mout_ipll", EXYNOS5422_SRC_TOP6, __BIT(12),
452 mout_ipll_p),
453 CLK_MUXF("sclk_epll", "mout_epll", EXYNOS5422_SRC_TOP6, __BIT(20),
454 CLK_SET_RATE_PARENT, mout_epll_p),
455 CLK_MUXF("sclk_rpll", "mout_rpll", EXYNOS5422_SRC_TOP6, __BIT(16),
456 CLK_SET_RATE_PARENT, mout_rpll_p),
457
458 CLK_MUX("mout_sw_aclk200_fsys", EXYNOS5422_SRC_TOP10, __BIT(24),
459 mout_sw_aclk200_fsys_p),
460 CLK_MUX("mout_sw_aclk200_fsys2", EXYNOS5422_SRC_TOP10, __BIT(12),
461 mout_sw_aclk200_fsys2_p),
462 CLK_MUX("mout_user_aclk200_fsys", EXYNOS5422_SRC_TOP3, __BIT(28),
463 mout_user_aclk200_fsys_p),
464 CLK_MUX("mout_user_aclk200_fsys2", EXYNOS5422_SRC_TOP3, __BIT(12),
465 mout_user_aclk200_fsys2_p),
466 CLK_MUX("mout_aclk66", EXYNOS5422_SRC_TOP1, __BITS(9,8),
467 mout_group1_p),
468 CLK_MUX("mout_aclk200_fsys", EXYNOS5422_SRC_TOP0, __BITS(25,24),
469 mout_group1_p),
470 CLK_MUX("mout_aclk200_fsys2", EXYNOS5422_SRC_TOP0, __BITS(13,12),
471 mout_group1_p),
472
473 CLK_MUX("mout_sw_aclk66", EXYNOS5422_SRC_TOP11, __BIT(8),
474 mout_sw_aclk66_p),
475 CLK_MUX("mout_user_aclk66_peric", EXYNOS5422_SRC_TOP4, __BIT(8),
476 mout_user_aclk66_peric_p),
477
478 CLK_MUX("mout_usbd301", EXYNOS5422_SRC_FSYS, __BITS(6,4),
479 mout_group2_p),
480 CLK_MUX("mout_usbd300", EXYNOS5422_SRC_FSYS, __BITS(22,20),
481 mout_group2_p),
482 CLK_MUX("mout_mmc0", EXYNOS5422_SRC_FSYS, __BITS(10,8),
483 mout_group2_p),
484 CLK_MUX("mout_mmc1", EXYNOS5422_SRC_FSYS, __BITS(14,12),
485 mout_group2_p),
486 CLK_MUX("mout_mmc2", EXYNOS5422_SRC_FSYS, __BITS(18,16),
487 mout_group2_p),
488 CLK_MUX("mout_uart0", EXYNOS5422_SRC_PERIC0, __BITS(6,4),
489 mout_group2_p),
490 CLK_MUX("mout_uart1", EXYNOS5422_SRC_PERIC0, __BITS(10,8),
491 mout_group2_p),
492 CLK_MUX("mout_uart2", EXYNOS5422_SRC_PERIC0, __BITS(14,12),
493 mout_group2_p),
494 CLK_MUX("mout_uart3", EXYNOS5422_SRC_PERIC0, __BITS(18,16),
495 mout_group2_p),
496
497 CLK_DIV("dout_aclk66", "mout_aclk66", EXYNOS5422_DIV_TOP1, __BITS(13,8)),
498 CLK_DIV("dout_aclk200_fsys", "mout_aclk200_fsys", EXYNOS5422_DIV_TOP0, __BITS(30,28)),
499 CLK_DIV("dout_aclk200_fsys2", "mout_aclk200_fsys2", EXYNOS5422_DIV_TOP0, __BITS(14,12)),
500
501 CLK_DIV("dout_usbphy301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(15,12)),
502 CLK_DIV("dout_usbphy300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(19,16)),
503 CLK_DIV("dout_usbd301", "mout_usbd301", EXYNOS5422_DIV_FSYS0, __BITS(23,20)),
504 CLK_DIV("dout_usbd300", "mout_usbd300", EXYNOS5422_DIV_FSYS0, __BITS(27,24)),
505 CLK_DIV("dout_mmc0", "mout_mmc0", EXYNOS5422_DIV_FSYS1, __BITS(9,0)),
506 CLK_DIV("dout_mmc1", "mout_mmc1", EXYNOS5422_DIV_FSYS1, __BITS(19,10)),
507 CLK_DIV("dout_mmc2", "mout_mmc2", EXYNOS5422_DIV_FSYS1, __BITS(29,20)),
508 CLK_DIV("dout_uart0", "mout_uart0", EXYNOS5422_DIV_PERIC0,
509 __BITS(11,8)),
510 CLK_DIV("dout_uart1", "mout_uart1", EXYNOS5422_DIV_PERIC0,
511 __BITS(15,12)),
512 CLK_DIV("dout_uart2", "mout_uart2", EXYNOS5422_DIV_PERIC0,
513 __BITS(19,16)),
514 CLK_DIV("dout_uart3", "mout_uart3", EXYNOS5422_DIV_PERIC0,
515 __BITS(23,20)),
516
517 CLK_GATE("aclk200_fsys", "mout_user_aclk200_fsys", EXYNOS5422_GATE_BUS_FSYS0,
518 __BIT(9), CLK_SET_RATE_PARENT),
519 CLK_GATE("aclk200_fsys2", "mout_user_aclk200_fsys2", EXYNOS5422_GATE_BUS_FSYS0,
520 __BIT(10), CLK_SET_RATE_PARENT),
521
522 CLK_GATE("sclk_mmc0", "dout_mmc0", EXYNOS5422_GATE_TOP_SCLK_FSYS,
523 __BIT(0), CLK_SET_RATE_PARENT),
524 CLK_GATE("sclk_mmc1", "dout_mmc1", EXYNOS5422_GATE_TOP_SCLK_FSYS,
525 __BIT(1), CLK_SET_RATE_PARENT),
526 CLK_GATE("sclk_mmc2", "dout_mmc2", EXYNOS5422_GATE_TOP_SCLK_FSYS,
527 __BIT(2), CLK_SET_RATE_PARENT),
528 CLK_GATE("sclk_usbphy301", "dout_usbphy301", EXYNOS5422_GATE_TOP_SCLK_FSYS,
529 __BIT(7), CLK_SET_RATE_PARENT),
530 CLK_GATE("sclk_usbphy300", "dout_usbphy300", EXYNOS5422_GATE_TOP_SCLK_FSYS,
531 __BIT(8), CLK_SET_RATE_PARENT),
532 CLK_GATE("sclk_usbd300", "dout_usbd300", EXYNOS5422_GATE_TOP_SCLK_FSYS,
533 __BIT(9), CLK_SET_RATE_PARENT),
534 CLK_GATE("sclk_usbd301", "dout_usbd301", EXYNOS5422_GATE_TOP_SCLK_FSYS,
535 __BIT(10), CLK_SET_RATE_PARENT),
536 CLK_GATE("sclk_uart0", "dout_uart0", EXYNOS5422_GATE_TOP_SCLK_PERIC,
537 __BIT(0), CLK_SET_RATE_PARENT),
538 CLK_GATE("sclk_uart1", "dout_uart1", EXYNOS5422_GATE_TOP_SCLK_PERIC,
539 __BIT(1), CLK_SET_RATE_PARENT),
540 CLK_GATE("sclk_uart2", "dout_uart2", EXYNOS5422_GATE_TOP_SCLK_PERIC,
541 __BIT(2), CLK_SET_RATE_PARENT),
542 CLK_GATE("sclk_uart3", "dout_uart3", EXYNOS5422_GATE_TOP_SCLK_PERIC,
543 __BIT(3), CLK_SET_RATE_PARENT),
544
545 CLK_GATE("mmc0", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS,
546 __BIT(12), CLK_SET_RATE_PARENT),
547 CLK_GATE("mmc1", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS,
548 __BIT(13), CLK_SET_RATE_PARENT),
549 CLK_GATE("mmc2", "aclk200_fsys2", EXYNOS5422_GATE_IP_FSYS,
550 __BIT(14), CLK_SET_RATE_PARENT),
551 CLK_GATE("usbh20", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS,
552 __BIT(18), CLK_SET_RATE_PARENT),
553 CLK_GATE("usbd300", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS,
554 __BIT(19), CLK_SET_RATE_PARENT),
555 CLK_GATE("usbd301", "aclk200_fsys", EXYNOS5422_GATE_IP_FSYS,
556 __BIT(20), CLK_SET_RATE_PARENT),
557
558 CLK_GATE("uart0", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
559 __BIT(0), CLK_SET_RATE_PARENT),
560 CLK_GATE("uart1", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
561 __BIT(1), CLK_SET_RATE_PARENT),
562 CLK_GATE("uart2", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
563 __BIT(2), CLK_SET_RATE_PARENT),
564 CLK_GATE("uart3", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
565 __BIT(3), CLK_SET_RATE_PARENT),
566 CLK_GATE("i2c0", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
567 __BIT(6), CLK_SET_RATE_PARENT),
568 CLK_GATE("i2c1", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
569 __BIT(7), CLK_SET_RATE_PARENT),
570 CLK_GATE("i2c2", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
571 __BIT(8), CLK_SET_RATE_PARENT),
572 CLK_GATE("i2c3", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
573 __BIT(9), CLK_SET_RATE_PARENT),
574 CLK_GATE("i2c_hdmi", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
575 __BIT(14), CLK_SET_RATE_PARENT),
576 CLK_GATE("pwm", "mout_user_aclk66_peric", EXYNOS5422_GATE_IP_PERIC,
577 __BIT(24), CLK_SET_RATE_PARENT),
578 };
579
580 static int exynos5422_clock_match(device_t, cfdata_t, void *);
581 static void exynos5422_clock_attach(device_t, device_t, void *);
582
583 struct exynos5422_clock_softc {
584 device_t sc_dev;
585 bus_space_tag_t sc_bst;
586 bus_space_handle_t sc_bsh;
587
588 struct clk_domain sc_clkdom;
589 };
590
591 static void exynos5422_clock_print_header(void);
592 static void exynos5422_clock_print(struct exynos5422_clock_softc *,
593 struct exynos_clk *);
594
595 CFATTACH_DECL_NEW(exynos5422_clock, sizeof(struct exynos5422_clock_softc),
596 exynos5422_clock_match, exynos5422_clock_attach, NULL, NULL);
597
598 #define CLOCK_READ(sc, reg) \
599 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
600 #define CLOCK_WRITE(sc, reg, val) \
601 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
602
603 static const struct device_compatible_entry compat_data[] = {
604 { .compat = "samsung,exynos5800-clock" },
605 DEVICE_COMPAT_EOL
606 };
607
608 static int
exynos5422_clock_match(device_t parent,cfdata_t cf,void * aux)609 exynos5422_clock_match(device_t parent, cfdata_t cf, void *aux)
610 {
611 struct fdt_attach_args * const faa = aux;
612
613 return of_compatible_match(faa->faa_phandle, compat_data);
614 }
615
616 static void
exynos5422_clock_attach(device_t parent,device_t self,void * aux)617 exynos5422_clock_attach(device_t parent, device_t self, void *aux)
618 {
619 struct exynos5422_clock_softc * const sc = device_private(self);
620 struct fdt_attach_args * const faa = aux;
621 bus_addr_t addr;
622 bus_size_t size;
623 int error;
624
625 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
626 aprint_error(": couldn't get registers\n");
627 return;
628 }
629
630 sc->sc_dev = self;
631 sc->sc_bst = faa->faa_bst;
632
633 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
634 if (error) {
635 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d",
636 addr, error);
637 return;
638 }
639
640 aprint_naive("\n");
641 aprint_normal(": Exynos5422 Clock Controller\n");
642
643 sc->sc_clkdom.funcs = &exynos5422_clock_funcs;
644 sc->sc_clkdom.priv = sc;
645 for (u_int n = 0; n < __arraycount(exynos5422_clocks); n++) {
646 exynos5422_clocks[n].base.domain = &sc->sc_clkdom;
647 }
648
649 fdtbus_register_clock_controller(self, faa->faa_phandle,
650 &exynos5422_car_fdtclock_funcs);
651
652 exynos5422_clock_print_header();
653 for (u_int n = 0; n < __arraycount(exynos5422_clocks); n++) {
654 exynos5422_clock_print(sc, &exynos5422_clocks[n]);
655 }
656 }
657
658 static struct exynos_clk *
exynos5422_clock_find(const char * name)659 exynos5422_clock_find(const char *name)
660 {
661 u_int n;
662
663 for (n = 0; n < __arraycount(exynos5422_clocks); n++) {
664 if (strcmp(exynos5422_clocks[n].base.name, name) == 0) {
665 return &exynos5422_clocks[n];
666 }
667 }
668
669 return NULL;
670 }
671
672 static struct exynos_clk *
exynos5422_clock_find_by_id(u_int clock_id)673 exynos5422_clock_find_by_id(u_int clock_id)
674 {
675 u_int n;
676
677 for (n = 0; n < __arraycount(exynos5422_clock_ids); n++) {
678 if (exynos5422_clock_ids[n].id == clock_id) {
679 const char *name = exynos5422_clock_ids[n].name;
680 return exynos5422_clock_find(name);
681 }
682 }
683
684 return NULL;
685 }
686
687 static void
exynos5422_clock_print_header(void)688 exynos5422_clock_print_header(void)
689 {
690 aprint_debug(" %-10s %2s %-10s %-5s %10s\n",
691 "clock", "", "parent", "type", "rate");
692 aprint_debug(" %-10s %2s %-10s %-5s %10s\n",
693 "=====", "", "======", "====", "====");
694 }
695
696 static void
exynos5422_clock_print(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk)697 exynos5422_clock_print(struct exynos5422_clock_softc *sc,
698 struct exynos_clk *eclk)
699 {
700 struct exynos_clk *eclk_parent;
701 struct clk *clk_parent;
702 const char *type = "?";
703
704 switch (eclk->type) {
705 case EXYNOS_CLK_FIXED:
706 type = "fixed";
707 break;
708 case EXYNOS_CLK_PLL:
709 type = "pll";
710 break;
711 case EXYNOS_CLK_MUX:
712 type = "mux";
713 break;
714 case EXYNOS_CLK_DIV:
715 type = "div";
716 break;
717 case EXYNOS_CLK_GATE:
718 type = "gate";
719 break;
720 }
721
722 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base);
723 eclk_parent = (struct exynos_clk *)clk_parent;
724
725 aprint_debug(" %-10s %2s %-10s %-5s %10d Hz\n",
726 eclk->base.name,
727 eclk_parent ? "<-" : "",
728 eclk_parent ? eclk_parent->base.name : "",
729 type, clk_get_rate(&eclk->base));
730 }
731
732 static struct clk *
exynos5422_clock_decode(device_t dev,int cc_phandle,const void * data,size_t len)733 exynos5422_clock_decode(device_t dev, int cc_phandle, const void *data,
734 size_t len)
735 {
736 struct exynos_clk *eclk;
737
738 /* #clock-cells should be 1 */
739 if (len != 4) {
740 return NULL;
741 }
742
743 const u_int clock_id = be32dec(data);
744
745 eclk = exynos5422_clock_find_by_id(clock_id);
746 if (eclk)
747 return &eclk->base;
748
749 return NULL;
750 }
751
752 static u_int
exynos5422_clock_get_rate_pll(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk)753 exynos5422_clock_get_rate_pll(struct exynos5422_clock_softc *sc,
754 struct exynos_clk *eclk)
755 {
756 struct exynos_pll_clk *epll = &eclk->u.pll;
757 struct exynos_clk *clk_parent;
758
759 KASSERT(eclk->type == EXYNOS_CLK_PLL);
760
761 clk_parent = exynos5422_clock_find(eclk->parent);
762 KASSERT(clk_parent != NULL);
763 const u_int rate_parent = exynos5422_clock_get_rate(sc,
764 &clk_parent->base);
765
766 const uint32_t v = CLOCK_READ(sc, epll->con0_reg);
767
768 return PLL_FREQ(rate_parent, v);
769 }
770
771 static int
exynos5422_clock_set_rate_pll(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk,u_int rate)772 exynos5422_clock_set_rate_pll(struct exynos5422_clock_softc *sc,
773 struct exynos_clk *eclk, u_int rate)
774 {
775 /* TODO */
776 return EOPNOTSUPP;
777 }
778
779 static int
exynos5422_clock_set_parent_mux(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk,struct exynos_clk * eclk_parent)780 exynos5422_clock_set_parent_mux(struct exynos5422_clock_softc *sc,
781 struct exynos_clk *eclk, struct exynos_clk *eclk_parent)
782 {
783 struct exynos_mux_clk *emux = &eclk->u.mux;
784 const char *pname = eclk_parent->base.name;
785 u_int sel;
786
787 KASSERT(eclk->type == EXYNOS_CLK_MUX);
788
789 for (sel = 0; sel < emux->nparents; sel++) {
790 if (strcmp(pname, emux->parents[sel]) == 0) {
791 break;
792 }
793 }
794 if (sel == emux->nparents) {
795 return EINVAL;
796 }
797
798 uint32_t v = CLOCK_READ(sc, emux->reg);
799 v &= ~emux->bits;
800 v |= __SHIFTIN(sel, emux->bits);
801 CLOCK_WRITE(sc, emux->reg, v);
802
803 return 0;
804 }
805
806 static struct exynos_clk *
exynos5422_clock_get_parent_mux(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk)807 exynos5422_clock_get_parent_mux(struct exynos5422_clock_softc *sc,
808 struct exynos_clk *eclk)
809 {
810 struct exynos_mux_clk *emux = &eclk->u.mux;
811
812 KASSERT(eclk->type == EXYNOS_CLK_MUX);
813
814 const uint32_t v = CLOCK_READ(sc, emux->reg);
815 const u_int sel = __SHIFTOUT(v, emux->bits);
816
817 KASSERT(sel < emux->nparents);
818
819 return exynos5422_clock_find(emux->parents[sel]);
820 }
821
822 static u_int
exynos5422_clock_get_rate_div(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk)823 exynos5422_clock_get_rate_div(struct exynos5422_clock_softc *sc,
824 struct exynos_clk *eclk)
825 {
826 struct exynos_div_clk *ediv = &eclk->u.div;
827 struct clk *clk_parent;
828
829 KASSERT(eclk->type == EXYNOS_CLK_DIV);
830
831 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base);
832 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent);
833
834 const uint32_t v = CLOCK_READ(sc, ediv->reg);
835 const u_int div = __SHIFTOUT(v, ediv->bits);
836
837 return parent_rate / (div + 1);
838 }
839
840 static int
exynos5422_clock_set_rate_div(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk,u_int rate)841 exynos5422_clock_set_rate_div(struct exynos5422_clock_softc *sc,
842 struct exynos_clk *eclk, u_int rate)
843 {
844 struct exynos_div_clk *ediv = &eclk->u.div;
845 struct clk *clk_parent;
846 int tmp_div, new_div = -1;
847 u_int tmp_rate;
848
849 KASSERT(eclk->type == EXYNOS_CLK_DIV);
850
851 clk_parent = exynos5422_clock_get_parent(sc, &eclk->base);
852 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent);
853
854 for (tmp_div = 0; tmp_div < __SHIFTOUT_MASK(ediv->bits); tmp_div++) {
855 tmp_rate = parent_rate / (tmp_div + 1);
856 if (tmp_rate <= rate) {
857 new_div = tmp_div;
858 break;
859 }
860 }
861 if (new_div == -1)
862 return EINVAL;
863
864 uint32_t v = CLOCK_READ(sc, ediv->reg);
865 v &= ~ediv->bits;
866 v |= __SHIFTIN(new_div, ediv->bits);
867 CLOCK_WRITE(sc, ediv->reg, v);
868
869 return 0;
870 }
871
872 static int
exynos5422_clock_enable_gate(struct exynos5422_clock_softc * sc,struct exynos_clk * eclk,bool enable)873 exynos5422_clock_enable_gate(struct exynos5422_clock_softc *sc,
874 struct exynos_clk *eclk, bool enable)
875 {
876 struct exynos_gate_clk *egate = &eclk->u.gate;
877
878 KASSERT(eclk->type == EXYNOS_CLK_GATE);
879
880 uint32_t v = CLOCK_READ(sc, egate->reg);
881 if (enable) {
882 v |= egate->bits;
883 } else {
884 v &= ~egate->bits;
885 }
886 CLOCK_WRITE(sc, egate->reg, v);
887
888 return 0;
889 }
890
891 /*
892 * clk api
893 */
894
895 static struct clk *
exynos5422_clock_get(void * priv,const char * name)896 exynos5422_clock_get(void *priv, const char *name)
897 {
898 struct exynos_clk *eclk;
899
900 eclk = exynos5422_clock_find(name);
901 if (eclk == NULL)
902 return NULL;
903
904 atomic_inc_uint(&eclk->refcnt);
905
906 return &eclk->base;
907 }
908
909 static void
exynos5422_clock_put(void * priv,struct clk * clk)910 exynos5422_clock_put(void *priv, struct clk *clk)
911 {
912 struct exynos_clk *eclk = (struct exynos_clk *)clk;
913
914 KASSERT(eclk->refcnt > 0);
915
916 atomic_dec_uint(&eclk->refcnt);
917 }
918
919 static u_int
exynos5422_clock_get_rate(void * priv,struct clk * clk)920 exynos5422_clock_get_rate(void *priv, struct clk *clk)
921 {
922 struct exynos_clk *eclk = (struct exynos_clk *)clk;
923 struct clk *clk_parent;
924
925 switch (eclk->type) {
926 case EXYNOS_CLK_FIXED:
927 return eclk->u.fixed.rate;
928 case EXYNOS_CLK_PLL:
929 return exynos5422_clock_get_rate_pll(priv, eclk);
930 case EXYNOS_CLK_MUX:
931 case EXYNOS_CLK_GATE:
932 clk_parent = exynos5422_clock_get_parent(priv, clk);
933 return exynos5422_clock_get_rate(priv, clk_parent);
934 case EXYNOS_CLK_DIV:
935 return exynos5422_clock_get_rate_div(priv, eclk);
936 default:
937 panic("exynos5422: unknown eclk type %d", eclk->type);
938 }
939 }
940
941 static int
exynos5422_clock_set_rate(void * priv,struct clk * clk,u_int rate)942 exynos5422_clock_set_rate(void *priv, struct clk *clk, u_int rate)
943 {
944 struct exynos_clk *eclk = (struct exynos_clk *)clk;
945
946 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
947
948 switch (eclk->type) {
949 case EXYNOS_CLK_FIXED:
950 return EIO;
951 case EXYNOS_CLK_PLL:
952 return exynos5422_clock_set_rate_pll(priv, eclk, rate);
953 case EXYNOS_CLK_MUX:
954 return EIO;
955 case EXYNOS_CLK_DIV:
956 return exynos5422_clock_set_rate_div(priv, eclk, rate);
957 case EXYNOS_CLK_GATE:
958 return EINVAL;
959 default:
960 panic("exynos5422: unknown eclk type %d", eclk->type);
961 }
962 }
963
964 static int
exynos5422_clock_enable(void * priv,struct clk * clk)965 exynos5422_clock_enable(void *priv, struct clk *clk)
966 {
967 struct exynos_clk *eclk = (struct exynos_clk *)clk;
968
969 switch (eclk->type) {
970 case EXYNOS_CLK_FIXED:
971 return 0; /* always on */
972 case EXYNOS_CLK_PLL:
973 return 0; /* XXX */
974 case EXYNOS_CLK_MUX:
975 case EXYNOS_CLK_DIV:
976 return 0;
977 case EXYNOS_CLK_GATE:
978 return exynos5422_clock_enable_gate(priv, eclk, true);
979 default:
980 panic("exynos5422: unknown eclk type %d", eclk->type);
981 }
982 }
983
984 static int
exynos5422_clock_disable(void * priv,struct clk * clk)985 exynos5422_clock_disable(void *priv, struct clk *clk)
986 {
987 struct exynos_clk *eclk = (struct exynos_clk *)clk;
988
989 switch (eclk->type) {
990 case EXYNOS_CLK_FIXED:
991 return EINVAL; /* always on */
992 case EXYNOS_CLK_PLL:
993 return EINVAL; /* XXX */
994 case EXYNOS_CLK_MUX:
995 case EXYNOS_CLK_DIV:
996 return EINVAL;
997 case EXYNOS_CLK_GATE:
998 return exynos5422_clock_enable_gate(priv, eclk, false);
999 default:
1000 panic("exynos5422: unknown eclk type %d", eclk->type);
1001 }
1002 }
1003
1004 static int
exynos5422_clock_set_parent(void * priv,struct clk * clk,struct clk * clk_parent)1005 exynos5422_clock_set_parent(void *priv, struct clk *clk, struct clk *clk_parent)
1006 {
1007 struct exynos_clk *eclk = (struct exynos_clk *)clk;
1008 struct exynos_clk *eclk_parent = (struct exynos_clk *)clk_parent;
1009
1010 switch (eclk->type) {
1011 case EXYNOS_CLK_FIXED:
1012 case EXYNOS_CLK_PLL:
1013 case EXYNOS_CLK_DIV:
1014 case EXYNOS_CLK_GATE:
1015 return EINVAL;
1016 case EXYNOS_CLK_MUX:
1017 return exynos5422_clock_set_parent_mux(priv, eclk, eclk_parent);
1018 default:
1019 panic("exynos5422: unknown eclk type %d", eclk->type);
1020 }
1021 }
1022
1023 static struct clk *
exynos5422_clock_get_parent(void * priv,struct clk * clk)1024 exynos5422_clock_get_parent(void *priv, struct clk *clk)
1025 {
1026 struct exynos_clk *eclk = (struct exynos_clk *)clk;
1027 struct exynos_clk *eclk_parent = NULL;
1028
1029 switch (eclk->type) {
1030 case EXYNOS_CLK_FIXED:
1031 case EXYNOS_CLK_PLL:
1032 case EXYNOS_CLK_DIV:
1033 case EXYNOS_CLK_GATE:
1034 if (eclk->parent != NULL) {
1035 eclk_parent = exynos5422_clock_find(eclk->parent);
1036 }
1037 break;
1038 case EXYNOS_CLK_MUX:
1039 eclk_parent = exynos5422_clock_get_parent_mux(priv, eclk);
1040 break;
1041 default:
1042 panic("exynos5422: unknown eclk type %d", eclk->type);
1043 }
1044
1045 return (struct clk *)eclk_parent;
1046 }
1047