1 /* $NetBSD: radeon_uvd_v4_2.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2013 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König <christian.koenig@amd.com>
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: radeon_uvd_v4_2.c,v 1.3 2021/12/18 23:45:43 riastradh Exp $");
29
30 #include <linux/firmware.h>
31
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "cikd.h"
35
36 /**
37 * uvd_v4_2_resume - memory controller programming
38 *
39 * @rdev: radeon_device pointer
40 *
41 * Let the UVD memory controller know it's offsets
42 */
uvd_v4_2_resume(struct radeon_device * rdev)43 int uvd_v4_2_resume(struct radeon_device *rdev)
44 {
45 uint64_t addr;
46 uint32_t size;
47
48 /* programm the VCPU memory controller bits 0-27 */
49
50 /* skip over the header of the new firmware format */
51 if (rdev->uvd.fw_header_present)
52 addr = (rdev->uvd.gpu_addr + 0x200) >> 3;
53 else
54 addr = rdev->uvd.gpu_addr >> 3;
55
56 size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;
57 WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
58 WREG32(UVD_VCPU_CACHE_SIZE0, size);
59
60 addr += size;
61 size = RADEON_UVD_HEAP_SIZE >> 3;
62 WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
63 WREG32(UVD_VCPU_CACHE_SIZE1, size);
64
65 addr += size;
66 size = (RADEON_UVD_STACK_SIZE +
67 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;
68 WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
69 WREG32(UVD_VCPU_CACHE_SIZE2, size);
70
71 /* bits 28-31 */
72 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
73 WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
74
75 /* bits 32-39 */
76 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
77 WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1U << 31));
78
79 if (rdev->uvd.fw_header_present)
80 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);
81
82 return 0;
83 }
84