1 /* $NetBSD: radeon_cik_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Alex Deucher <alexander.deucher@amd.com> 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_cik_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 31 32 #include <linux/types.h> 33 #include <linux/bug.h> 34 #include <linux/kernel.h> 35 36 const u32 cik_default_state[] = 37 { 38 0xc0066900, 39 0x00000000, 40 0x00000060, /* DB_RENDER_CONTROL */ 41 0x00000000, /* DB_COUNT_CONTROL */ 42 0x00000000, /* DB_DEPTH_VIEW */ 43 0x0000002a, /* DB_RENDER_OVERRIDE */ 44 0x00000000, /* DB_RENDER_OVERRIDE2 */ 45 0x00000000, /* DB_HTILE_DATA_BASE */ 46 47 0xc0046900, 48 0x00000008, 49 0x00000000, /* DB_DEPTH_BOUNDS_MIN */ 50 0x00000000, /* DB_DEPTH_BOUNDS_MAX */ 51 0x00000000, /* DB_STENCIL_CLEAR */ 52 0x00000000, /* DB_DEPTH_CLEAR */ 53 54 0xc0036900, 55 0x0000000f, 56 0x00000000, /* DB_DEPTH_INFO */ 57 0x00000000, /* DB_Z_INFO */ 58 0x00000000, /* DB_STENCIL_INFO */ 59 60 0xc0016900, 61 0x00000080, 62 0x00000000, /* PA_SC_WINDOW_OFFSET */ 63 64 0xc00d6900, 65 0x00000083, 66 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ 67 0x00000000, /* PA_SC_CLIPRECT_0_TL */ 68 0x20002000, /* PA_SC_CLIPRECT_0_BR */ 69 0x00000000, 70 0x20002000, 71 0x00000000, 72 0x20002000, 73 0x00000000, 74 0x20002000, 75 0xaaaaaaaa, /* PA_SC_EDGERULE */ 76 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ 77 0x0000000f, /* CB_TARGET_MASK */ 78 0x0000000f, /* CB_SHADER_MASK */ 79 80 0xc0226900, 81 0x00000094, 82 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ 83 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ 84 0x80000000, 85 0x20002000, 86 0x80000000, 87 0x20002000, 88 0x80000000, 89 0x20002000, 90 0x80000000, 91 0x20002000, 92 0x80000000, 93 0x20002000, 94 0x80000000, 95 0x20002000, 96 0x80000000, 97 0x20002000, 98 0x80000000, 99 0x20002000, 100 0x80000000, 101 0x20002000, 102 0x80000000, 103 0x20002000, 104 0x80000000, 105 0x20002000, 106 0x80000000, 107 0x20002000, 108 0x80000000, 109 0x20002000, 110 0x80000000, 111 0x20002000, 112 0x80000000, 113 0x20002000, 114 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ 115 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ 116 117 0xc0046900, 118 0x00000100, 119 0xffffffff, /* VGT_MAX_VTX_INDX */ 120 0x00000000, /* VGT_MIN_VTX_INDX */ 121 0x00000000, /* VGT_INDX_OFFSET */ 122 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 123 124 0xc0046900, 125 0x00000105, 126 0x00000000, /* CB_BLEND_RED */ 127 0x00000000, /* CB_BLEND_GREEN */ 128 0x00000000, /* CB_BLEND_BLUE */ 129 0x00000000, /* CB_BLEND_ALPHA */ 130 131 0xc0016900, 132 0x000001e0, 133 0x00000000, /* CB_BLEND0_CONTROL */ 134 135 0xc00c6900, 136 0x00000200, 137 0x00000000, /* DB_DEPTH_CONTROL */ 138 0x00000000, /* DB_EQAA */ 139 0x00cc0010, /* CB_COLOR_CONTROL */ 140 0x00000210, /* DB_SHADER_CONTROL */ 141 0x00010000, /* PA_CL_CLIP_CNTL */ 142 0x00000004, /* PA_SU_SC_MODE_CNTL */ 143 0x00000100, /* PA_CL_VTE_CNTL */ 144 0x00000000, /* PA_CL_VS_OUT_CNTL */ 145 0x00000000, /* PA_CL_NANINF_CNTL */ 146 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ 147 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ 148 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ 149 150 0xc0116900, 151 0x00000280, 152 0x00000000, /* PA_SU_POINT_SIZE */ 153 0x00000000, /* PA_SU_POINT_MINMAX */ 154 0x00000008, /* PA_SU_LINE_CNTL */ 155 0x00000000, /* PA_SC_LINE_STIPPLE */ 156 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 157 0x00000000, /* VGT_HOS_CNTL */ 158 0x00000000, 159 0x00000000, 160 0x00000000, 161 0x00000000, 162 0x00000000, 163 0x00000000, 164 0x00000000, 165 0x00000000, 166 0x00000000, 167 0x00000000, 168 0x00000000, /* VGT_GS_MODE */ 169 170 0xc0026900, 171 0x00000292, 172 0x00000000, /* PA_SC_MODE_CNTL_0 */ 173 0x00000000, /* PA_SC_MODE_CNTL_1 */ 174 175 0xc0016900, 176 0x000002a1, 177 0x00000000, /* VGT_PRIMITIVEID_EN */ 178 179 0xc0016900, 180 0x000002a5, 181 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ 182 183 0xc0026900, 184 0x000002a8, 185 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 186 0x00000000, 187 188 0xc0026900, 189 0x000002ad, 190 0x00000000, /* VGT_REUSE_OFF */ 191 0x00000000, 192 193 0xc0016900, 194 0x000002d5, 195 0x00000000, /* VGT_SHADER_STAGES_EN */ 196 197 0xc0016900, 198 0x000002dc, 199 0x0000aa00, /* DB_ALPHA_TO_MASK */ 200 201 0xc0066900, 202 0x000002de, 203 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 204 0x00000000, 205 0x00000000, 206 0x00000000, 207 0x00000000, 208 0x00000000, 209 210 0xc0026900, 211 0x000002e5, 212 0x00000000, /* VGT_STRMOUT_CONFIG */ 213 0x00000000, 214 215 0xc01b6900, 216 0x000002f5, 217 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ 218 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ 219 0x00000000, /* PA_SC_LINE_CNTL */ 220 0x00000000, /* PA_SC_AA_CONFIG */ 221 0x00000005, /* PA_SU_VTX_CNTL */ 222 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ 223 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ 224 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ 225 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ 226 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ 227 0x00000000, 228 0x00000000, 229 0x00000000, 230 0x00000000, 231 0x00000000, 232 0x00000000, 233 0x00000000, 234 0x00000000, 235 0x00000000, 236 0x00000000, 237 0x00000000, 238 0x00000000, 239 0x00000000, 240 0x00000000, 241 0x00000000, 242 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ 243 0xffffffff, 244 245 0xc0026900, 246 0x00000316, 247 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 248 0x00000010, /* */ 249 }; 250 251 const u32 cik_default_size = ARRAY_SIZE(cik_default_state); 252