1 /* $NetBSD: nouveau_nvkm_subdev_pmu_gp10b.c,v 1.2 2021/12/18 23:45:41 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24 #include <sys/cdefs.h>
25 __KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_subdev_pmu_gp10b.c,v 1.2 2021/12/18 23:45:41 riastradh Exp $");
26
27 #include "priv.h"
28
29 #include <subdev/acr.h>
30
31 #include <nvfw/flcn.h>
32 #include <nvfw/pmu.h>
33
34 static int
gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void * priv,struct nv_falcon_msg * hdr)35 gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void *priv,
36 struct nv_falcon_msg *hdr)
37 {
38 struct nv_pmu_acr_bootstrap_multiple_falcons_msg *msg =
39 container_of(hdr, typeof(*msg), msg.hdr);
40 return msg->falcon_mask;
41 }
42 static int
gp10b_pmu_acr_bootstrap_multiple_falcons(struct nvkm_falcon * falcon,u32 mask)43 gp10b_pmu_acr_bootstrap_multiple_falcons(struct nvkm_falcon *falcon, u32 mask)
44 {
45 struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
46 struct nv_pmu_acr_bootstrap_multiple_falcons_cmd cmd = {
47 .cmd.hdr.unit_id = NV_PMU_UNIT_ACR,
48 .cmd.hdr.size = sizeof(cmd),
49 .cmd.cmd_type = NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS,
50 .flags = NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES,
51 .falcon_mask = mask,
52 .wpr_lo = 0, /*XXX*/
53 .wpr_hi = 0, /*XXX*/
54 };
55 int ret;
56
57 ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
58 gp10b_pmu_acr_bootstrap_multiple_falcons_cb,
59 &pmu->subdev, msecs_to_jiffies(1000));
60 if (ret >= 0) {
61 if (ret != cmd.falcon_mask)
62 ret = -EIO;
63 else
64 ret = 0;
65 }
66
67 return ret;
68 }
69
70 static const struct nvkm_acr_lsf_func
71 gp10b_pmu_acr = {
72 .flags = NVKM_ACR_LSF_DMACTL_REQ_CTX,
73 .bld_size = sizeof(struct loader_config),
74 .bld_write = gm20b_pmu_acr_bld_write,
75 .bld_patch = gm20b_pmu_acr_bld_patch,
76 .boot = gm20b_pmu_acr_boot,
77 .bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon,
78 .bootstrap_multiple_falcons = gp10b_pmu_acr_bootstrap_multiple_falcons,
79 };
80
81 static const struct nvkm_pmu_func
82 gp10b_pmu = {
83 .flcn = >215_pmu_flcn,
84 .enabled = gf100_pmu_enabled,
85 .intr = gt215_pmu_intr,
86 .recv = gm20b_pmu_recv,
87 .initmsg = gm20b_pmu_initmsg,
88 };
89
90 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
91 MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
92 MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
93 MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
94 #endif
95
96 static const struct nvkm_pmu_fwif
97 gp10b_pmu_fwif[] = {
98 { 0, gm20b_pmu_load, &gp10b_pmu, &gp10b_pmu_acr },
99 {}
100 };
101
102 int
gp10b_pmu_new(struct nvkm_device * device,int index,struct nvkm_pmu ** ppmu)103 gp10b_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
104 {
105 return nvkm_pmu_new_(gp10b_pmu_fwif, device, index, ppmu);
106 }
107