1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_IMPL_H 8 #define _SYS_EFX_IMPL_H 9 10 #include "efx.h" 11 #include "efx_regs.h" 12 #include "efx_regs_ef10.h" 13 #include "efx_regs_ef100.h" 14 #if EFSYS_OPT_MCDI 15 #include "efx_mcdi.h" 16 #endif /* EFSYS_OPT_MCDI */ 17 18 /* FIXME: Add definition for driver generated software events */ 19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 21 #endif 22 23 24 #if EFSYS_OPT_SIENA 25 #include "siena_impl.h" 26 #endif /* EFSYS_OPT_SIENA */ 27 28 #if EFSYS_OPT_HUNTINGTON 29 #include "hunt_impl.h" 30 #endif /* EFSYS_OPT_HUNTINGTON */ 31 32 #if EFSYS_OPT_MEDFORD 33 #include "medford_impl.h" 34 #endif /* EFSYS_OPT_MEDFORD */ 35 36 #if EFSYS_OPT_MEDFORD2 37 #include "medford2_impl.h" 38 #endif /* EFSYS_OPT_MEDFORD2 */ 39 40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 41 #include "ef10_impl.h" 42 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 43 44 #if EFSYS_OPT_RIVERHEAD 45 #include "rhead_impl.h" 46 #endif /* EFSYS_OPT_RIVERHEAD */ 47 48 #ifdef __cplusplus 49 extern "C" { 50 #endif 51 52 #define EFX_MOD_MCDI 0x00000001 53 #define EFX_MOD_PROBE 0x00000002 54 #define EFX_MOD_NVRAM 0x00000004 55 #define EFX_MOD_VPD 0x00000008 56 #define EFX_MOD_NIC 0x00000010 57 #define EFX_MOD_INTR 0x00000020 58 #define EFX_MOD_EV 0x00000040 59 #define EFX_MOD_RX 0x00000080 60 #define EFX_MOD_TX 0x00000100 61 #define EFX_MOD_PORT 0x00000200 62 #define EFX_MOD_MON 0x00000400 63 #define EFX_MOD_FILTER 0x00001000 64 #define EFX_MOD_LIC 0x00002000 65 #define EFX_MOD_TUNNEL 0x00004000 66 #define EFX_MOD_EVB 0x00008000 67 #define EFX_MOD_PROXY 0x00010000 68 #define EFX_MOD_VIRTIO 0x00020000 69 70 #define EFX_RESET_PHY 0x00000001 71 #define EFX_RESET_RXQ_ERR 0x00000002 72 #define EFX_RESET_TXQ_ERR 0x00000004 73 #define EFX_RESET_HW_UNAVAIL 0x00000008 74 75 typedef enum efx_mac_type_e { 76 EFX_MAC_INVALID = 0, 77 EFX_MAC_SIENA, 78 EFX_MAC_HUNTINGTON, 79 EFX_MAC_MEDFORD, 80 EFX_MAC_MEDFORD2, 81 EFX_MAC_RIVERHEAD, 82 EFX_MAC_NTYPES 83 } efx_mac_type_t; 84 85 typedef struct efx_ev_ops_s { 86 efx_rc_t (*eevo_init)(efx_nic_t *); 87 void (*eevo_fini)(efx_nic_t *); 88 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 89 efsys_mem_t *, size_t, uint32_t, 90 uint32_t, uint32_t, uint32_t, 91 efx_evq_t *); 92 void (*eevo_qdestroy)(efx_evq_t *); 93 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 94 void (*eevo_qpost)(efx_evq_t *, uint16_t); 95 void (*eevo_qpoll)(efx_evq_t *, unsigned int *, 96 const efx_ev_callbacks_t *, void *); 97 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 98 #if EFSYS_OPT_QSTATS 99 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 100 #endif 101 } efx_ev_ops_t; 102 103 typedef struct efx_tx_ops_s { 104 efx_rc_t (*etxo_init)(efx_nic_t *); 105 void (*etxo_fini)(efx_nic_t *); 106 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 107 unsigned int, unsigned int, 108 efsys_mem_t *, size_t, 109 uint32_t, uint16_t, 110 efx_evq_t *, efx_txq_t *, 111 unsigned int *); 112 void (*etxo_qdestroy)(efx_txq_t *); 113 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 114 unsigned int, unsigned int, 115 unsigned int *); 116 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 117 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 118 efx_rc_t (*etxo_qflush)(efx_txq_t *); 119 void (*etxo_qenable)(efx_txq_t *); 120 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 121 void (*etxo_qpio_disable)(efx_txq_t *); 122 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 123 size_t); 124 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 125 unsigned int *); 126 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 127 unsigned int, unsigned int, 128 unsigned int *); 129 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 130 size_t, boolean_t, 131 efx_desc_t *); 132 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 133 uint32_t, uint8_t, 134 efx_desc_t *); 135 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 136 uint16_t, uint32_t, uint16_t, 137 efx_desc_t *, int); 138 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 139 efx_desc_t *); 140 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 141 efx_desc_t *); 142 #if EFSYS_OPT_QSTATS 143 void (*etxo_qstats_update)(efx_txq_t *, 144 efsys_stat_t *); 145 #endif 146 } efx_tx_ops_t; 147 148 typedef union efx_rxq_type_data_u { 149 struct { 150 size_t ed_buf_size; 151 } ertd_default; 152 #if EFSYS_OPT_RX_PACKED_STREAM 153 struct { 154 uint32_t eps_buf_size; 155 } ertd_packed_stream; 156 #endif 157 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 158 struct { 159 uint32_t eessb_bufs_per_desc; 160 uint32_t eessb_max_dma_len; 161 uint32_t eessb_buf_stride; 162 uint32_t eessb_hol_block_timeout; 163 } ertd_es_super_buffer; 164 #endif 165 } efx_rxq_type_data_t; 166 167 typedef struct efx_rx_ops_s { 168 efx_rc_t (*erxo_init)(efx_nic_t *); 169 void (*erxo_fini)(efx_nic_t *); 170 #if EFSYS_OPT_RX_SCATTER 171 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 172 #endif 173 #if EFSYS_OPT_RX_SCALE 174 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 175 efx_rx_scale_context_type_t, 176 uint32_t, uint32_t, 177 uint32_t *); 178 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 179 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 180 efx_rx_hash_alg_t, 181 efx_rx_hash_type_t, boolean_t); 182 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 183 uint8_t *, size_t); 184 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 185 unsigned int *, size_t); 186 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 187 uint8_t *); 188 #endif /* EFSYS_OPT_RX_SCALE */ 189 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 190 uint16_t *); 191 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 192 unsigned int, unsigned int, 193 unsigned int); 194 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 195 #if EFSYS_OPT_RX_PACKED_STREAM 196 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 197 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 198 uint32_t, uint32_t, 199 uint16_t *, uint32_t *, uint32_t *); 200 #endif 201 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 202 void (*erxo_qenable)(efx_rxq_t *); 203 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 204 unsigned int, efx_rxq_type_t, 205 const efx_rxq_type_data_t *, 206 efsys_mem_t *, size_t, uint32_t, 207 unsigned int, 208 efx_evq_t *, efx_rxq_t *); 209 void (*erxo_qdestroy)(efx_rxq_t *); 210 } efx_rx_ops_t; 211 212 typedef struct efx_mac_ops_s { 213 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 214 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 215 efx_rc_t (*emo_addr_set)(efx_nic_t *); 216 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 217 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 218 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 219 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 220 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 221 efx_rxq_t *, boolean_t); 222 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 223 #if EFSYS_OPT_LOOPBACK 224 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 225 efx_loopback_type_t); 226 #endif /* EFSYS_OPT_LOOPBACK */ 227 #if EFSYS_OPT_MAC_STATS 228 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 229 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 230 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 231 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 232 uint16_t, boolean_t); 233 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 234 efsys_stat_t *, uint32_t *); 235 #endif /* EFSYS_OPT_MAC_STATS */ 236 } efx_mac_ops_t; 237 238 typedef struct efx_phy_ops_s { 239 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 240 efx_rc_t (*epo_reset)(efx_nic_t *); 241 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 242 efx_rc_t (*epo_verify)(efx_nic_t *); 243 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 244 efx_rc_t (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *); 245 #if EFSYS_OPT_PHY_STATS 246 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 247 uint32_t *); 248 #endif /* EFSYS_OPT_PHY_STATS */ 249 #if EFSYS_OPT_BIST 250 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 251 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 252 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 253 efx_bist_result_t *, uint32_t *, 254 unsigned long *, size_t); 255 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 256 #endif /* EFSYS_OPT_BIST */ 257 } efx_phy_ops_t; 258 259 #if EFSYS_OPT_FILTER 260 261 /* 262 * Policy for replacing existing filter when inserting a new one. 263 * Note that all policies allow for storing the new lower priority 264 * filters as overridden by existing higher priority ones. It is needed 265 * to restore the lower priority filters on higher priority ones removal. 266 */ 267 typedef enum efx_filter_replacement_policy_e { 268 /* Cannot replace existing filter */ 269 EFX_FILTER_REPLACEMENT_NEVER, 270 /* Higher priority filters can replace lower priotiry ones */ 271 EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY, 272 /* 273 * Higher priority filters can replace lower priority ones and 274 * equal priority filters can replace each other. 275 */ 276 EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY, 277 } efx_filter_replacement_policy_t; 278 279 typedef struct efx_filter_ops_s { 280 efx_rc_t (*efo_init)(efx_nic_t *); 281 void (*efo_fini)(efx_nic_t *); 282 efx_rc_t (*efo_restore)(efx_nic_t *); 283 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 284 efx_filter_replacement_policy_t policy); 285 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 286 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 287 size_t, size_t *); 288 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 289 boolean_t, boolean_t, boolean_t, 290 uint8_t const *, uint32_t); 291 efx_rc_t (*efo_get_count)(efx_nic_t *, uint32_t *); 292 } efx_filter_ops_t; 293 294 LIBEFX_INTERNAL 295 extern __checkReturn efx_rc_t 296 efx_filter_reconfigure( 297 __in efx_nic_t *enp, 298 __in_ecount(6) uint8_t const *mac_addr, 299 __in boolean_t all_unicst, 300 __in boolean_t mulcst, 301 __in boolean_t all_mulcst, 302 __in boolean_t brdcst, 303 __in_ecount(6*count) uint8_t const *addrs, 304 __in uint32_t count); 305 306 LIBEFX_INTERNAL 307 extern __checkReturn efx_rc_t 308 efx_filter_get_count( 309 __in efx_nic_t *enp, 310 __out uint32_t *countp); 311 312 #endif /* EFSYS_OPT_FILTER */ 313 314 #if EFSYS_OPT_TUNNEL 315 typedef struct efx_tunnel_ops_s { 316 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 317 void (*eto_fini)(efx_nic_t *); 318 } efx_tunnel_ops_t; 319 #endif /* EFSYS_OPT_TUNNEL */ 320 321 #if EFSYS_OPT_VIRTIO 322 typedef struct efx_virtio_ops_s { 323 efx_rc_t (*evo_virtio_qstart)(efx_virtio_vq_t *, 324 efx_virtio_vq_cfg_t *, 325 efx_virtio_vq_dyncfg_t *); 326 efx_rc_t (*evo_virtio_qstop)(efx_virtio_vq_t *, 327 efx_virtio_vq_dyncfg_t *); 328 efx_rc_t (*evo_get_doorbell_offset)(efx_virtio_vq_t *, 329 uint32_t *); 330 efx_rc_t (*evo_get_features)(efx_nic_t *, 331 efx_virtio_device_type_t, uint64_t *); 332 efx_rc_t (*evo_verify_features)(efx_nic_t *, 333 efx_virtio_device_type_t, uint64_t); 334 } efx_virtio_ops_t; 335 #endif /* EFSYS_OPT_VIRTIO */ 336 337 typedef struct efx_port_s { 338 efx_mac_type_t ep_mac_type; 339 uint32_t ep_phy_type; 340 uint8_t ep_port; 341 uint32_t ep_mac_pdu; 342 uint8_t ep_mac_addr[6]; 343 efx_link_mode_t ep_link_mode; 344 boolean_t ep_all_unicst; 345 boolean_t ep_all_unicst_inserted; 346 boolean_t ep_mulcst; 347 boolean_t ep_all_mulcst; 348 boolean_t ep_all_mulcst_inserted; 349 boolean_t ep_brdcst; 350 unsigned int ep_fcntl; 351 boolean_t ep_fcntl_autoneg; 352 efx_oword_t ep_multicst_hash[2]; 353 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 354 EFX_MAC_MULTICAST_LIST_MAX]; 355 uint32_t ep_mulcst_addr_count; 356 #if EFSYS_OPT_LOOPBACK 357 efx_loopback_type_t ep_loopback_type; 358 efx_link_mode_t ep_loopback_link_mode; 359 #endif /* EFSYS_OPT_LOOPBACK */ 360 #if EFSYS_OPT_PHY_FLAGS 361 uint32_t ep_phy_flags; 362 #endif /* EFSYS_OPT_PHY_FLAGS */ 363 #if EFSYS_OPT_PHY_LED_CONTROL 364 efx_phy_led_mode_t ep_phy_led_mode; 365 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 366 efx_phy_media_type_t ep_fixed_port_type; 367 efx_phy_media_type_t ep_module_type; 368 uint32_t ep_adv_cap_mask; 369 uint32_t ep_lp_cap_mask; 370 uint32_t ep_default_adv_cap_mask; 371 uint32_t ep_phy_cap_mask; 372 boolean_t ep_mac_drain; 373 boolean_t ep_include_fcs; 374 boolean_t ep_vlan_strip; 375 #if EFSYS_OPT_BIST 376 efx_bist_type_t ep_current_bist; 377 #endif 378 const efx_mac_ops_t *ep_emop; 379 const efx_phy_ops_t *ep_epop; 380 } efx_port_t; 381 382 typedef struct efx_mon_ops_s { 383 #if EFSYS_OPT_MON_STATS 384 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 385 efx_mon_stat_value_t *); 386 efx_rc_t (*emo_limits_update)(efx_nic_t *, 387 efx_mon_stat_limits_t *); 388 #endif /* EFSYS_OPT_MON_STATS */ 389 } efx_mon_ops_t; 390 391 typedef struct efx_mon_s { 392 efx_mon_type_t em_type; 393 const efx_mon_ops_t *em_emop; 394 } efx_mon_t; 395 396 typedef struct efx_intr_ops_s { 397 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 398 void (*eio_enable)(efx_nic_t *); 399 void (*eio_disable)(efx_nic_t *); 400 void (*eio_disable_unlocked)(efx_nic_t *); 401 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 402 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 403 void (*eio_status_message)(efx_nic_t *, unsigned int, 404 boolean_t *); 405 void (*eio_fatal)(efx_nic_t *); 406 void (*eio_fini)(efx_nic_t *); 407 } efx_intr_ops_t; 408 409 typedef struct efx_intr_s { 410 const efx_intr_ops_t *ei_eiop; 411 efsys_mem_t *ei_esmp; 412 efx_intr_type_t ei_type; 413 unsigned int ei_level; 414 } efx_intr_t; 415 416 typedef struct efx_nic_ops_s { 417 efx_rc_t (*eno_probe)(efx_nic_t *); 418 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 419 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 420 efx_rc_t (*eno_reset)(efx_nic_t *); 421 efx_rc_t (*eno_init)(efx_nic_t *); 422 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 423 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 424 uint32_t *, size_t *); 425 boolean_t (*eno_hw_unavailable)(efx_nic_t *); 426 void (*eno_set_hw_unavailable)(efx_nic_t *); 427 #if EFSYS_OPT_DIAG 428 efx_rc_t (*eno_register_test)(efx_nic_t *); 429 #endif /* EFSYS_OPT_DIAG */ 430 void (*eno_fini)(efx_nic_t *); 431 void (*eno_unprobe)(efx_nic_t *); 432 } efx_nic_ops_t; 433 434 #ifndef EFX_TXQ_LIMIT_TARGET 435 #define EFX_TXQ_LIMIT_TARGET 259 436 #endif 437 #ifndef EFX_RXQ_LIMIT_TARGET 438 #define EFX_RXQ_LIMIT_TARGET 512 439 #endif 440 441 typedef struct efx_nic_dma_region_s { 442 efsys_dma_addr_t endr_nic_base; 443 efsys_dma_addr_t endr_trgt_base; 444 unsigned int endr_window_log2; 445 unsigned int endr_align_log2; 446 boolean_t endr_inuse; 447 } efx_nic_dma_region_t; 448 449 typedef struct efx_nic_dma_region_info_s { 450 unsigned int endri_count; 451 efx_nic_dma_region_t *endri_regions; 452 } efx_nic_dma_region_info_t; 453 454 typedef struct efx_nic_dma_s { 455 union { 456 /* No configuration in the case flat mapping type */ 457 efx_nic_dma_region_info_t endu_region_info; 458 } end_u; 459 } efx_nic_dma_t; 460 461 #if EFSYS_OPT_FILTER 462 463 #if EFSYS_OPT_SIENA 464 465 typedef struct siena_filter_spec_s { 466 uint8_t sfs_type; 467 uint32_t sfs_flags; 468 uint32_t sfs_dmaq_id; 469 uint32_t sfs_dword[3]; 470 } siena_filter_spec_t; 471 472 typedef enum siena_filter_type_e { 473 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 474 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 475 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 476 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 477 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 478 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 479 480 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 481 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 482 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 483 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 484 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 485 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 486 487 EFX_SIENA_FILTER_NTYPES 488 } siena_filter_type_t; 489 490 typedef enum siena_filter_tbl_id_e { 491 EFX_SIENA_FILTER_TBL_RX_IP = 0, 492 EFX_SIENA_FILTER_TBL_RX_MAC, 493 EFX_SIENA_FILTER_TBL_TX_IP, 494 EFX_SIENA_FILTER_TBL_TX_MAC, 495 EFX_SIENA_FILTER_NTBLS 496 } siena_filter_tbl_id_t; 497 498 typedef struct siena_filter_tbl_s { 499 int sft_size; /* number of entries */ 500 int sft_used; /* active count */ 501 uint32_t *sft_bitmap; /* active bitmap */ 502 siena_filter_spec_t *sft_spec; /* array of saved specs */ 503 } siena_filter_tbl_t; 504 505 typedef struct siena_filter_s { 506 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 507 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 508 } siena_filter_t; 509 510 #endif /* EFSYS_OPT_SIENA */ 511 512 typedef struct efx_filter_s { 513 #if EFSYS_OPT_SIENA 514 siena_filter_t *ef_siena_filter; 515 #endif /* EFSYS_OPT_SIENA */ 516 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 517 ef10_filter_table_t *ef_ef10_filter_table; 518 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 519 } efx_filter_t; 520 521 #if EFSYS_OPT_SIENA 522 523 LIBEFX_INTERNAL 524 extern void 525 siena_filter_tbl_clear( 526 __in efx_nic_t *enp, 527 __in siena_filter_tbl_id_t tbl); 528 529 #endif /* EFSYS_OPT_SIENA */ 530 531 #endif /* EFSYS_OPT_FILTER */ 532 533 #if EFSYS_OPT_MCDI 534 535 #define EFX_TUNNEL_MAXNENTRIES (16) 536 537 #if EFSYS_OPT_TUNNEL 538 539 /* State of a UDP tunnel table entry */ 540 typedef enum efx_tunnel_udp_entry_state_e { 541 EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */ 542 EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */ 543 EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */ 544 } efx_tunnel_udp_entry_state_t; 545 546 #if EFSYS_OPT_RIVERHEAD 547 typedef uint32_t efx_vnic_encap_rule_handle_t; 548 #endif /* EFSYS_OPT_RIVERHEAD */ 549 550 typedef struct efx_tunnel_udp_entry_s { 551 uint16_t etue_port; /* host/cpu-endian */ 552 uint16_t etue_protocol; 553 boolean_t etue_busy; 554 efx_tunnel_udp_entry_state_t etue_state; 555 #if EFSYS_OPT_RIVERHEAD 556 efx_vnic_encap_rule_handle_t etue_handle; 557 #endif /* EFSYS_OPT_RIVERHEAD */ 558 } efx_tunnel_udp_entry_t; 559 560 typedef struct efx_tunnel_cfg_s { 561 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 562 unsigned int etc_udp_entries_num; 563 } efx_tunnel_cfg_t; 564 565 #endif /* EFSYS_OPT_TUNNEL */ 566 567 typedef struct efx_mcdi_ops_s { 568 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 569 void (*emco_send_request)(efx_nic_t *, void *, size_t, 570 void *, size_t); 571 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 572 boolean_t (*emco_poll_response)(efx_nic_t *); 573 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 574 void (*emco_fini)(efx_nic_t *); 575 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 576 efx_mcdi_feature_id_t, boolean_t *); 577 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 578 uint32_t *); 579 } efx_mcdi_ops_t; 580 581 typedef struct efx_mcdi_s { 582 const efx_mcdi_ops_t *em_emcop; 583 const efx_mcdi_transport_t *em_emtp; 584 efx_mcdi_iface_t em_emip; 585 } efx_mcdi_t; 586 587 #endif /* EFSYS_OPT_MCDI */ 588 589 #if EFSYS_OPT_NVRAM 590 591 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 592 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 593 594 typedef struct efx_nvram_ops_s { 595 #if EFSYS_OPT_DIAG 596 efx_rc_t (*envo_test)(efx_nic_t *); 597 #endif /* EFSYS_OPT_DIAG */ 598 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 599 uint32_t *); 600 efx_rc_t (*envo_partn_info)(efx_nic_t *, uint32_t, 601 efx_nvram_info_t *); 602 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 603 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 604 unsigned int, caddr_t, size_t); 605 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 606 unsigned int, caddr_t, size_t); 607 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 608 unsigned int, size_t); 609 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 610 unsigned int, caddr_t, size_t); 611 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 612 uint32_t *); 613 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 614 uint32_t *, uint16_t *); 615 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 616 uint16_t *); 617 efx_rc_t (*envo_buffer_validate)(uint32_t, 618 caddr_t, size_t); 619 } efx_nvram_ops_t; 620 #endif /* EFSYS_OPT_NVRAM */ 621 622 #if EFSYS_OPT_VPD 623 typedef struct efx_vpd_ops_s { 624 efx_rc_t (*evpdo_init)(efx_nic_t *); 625 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 626 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 627 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 628 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 629 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 630 efx_vpd_value_t *); 631 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 632 efx_vpd_value_t *); 633 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 634 efx_vpd_value_t *, unsigned int *); 635 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 636 void (*evpdo_fini)(efx_nic_t *); 637 } efx_vpd_ops_t; 638 #endif /* EFSYS_OPT_VPD */ 639 640 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 641 642 LIBEFX_INTERNAL 643 extern __checkReturn efx_rc_t 644 efx_mcdi_nvram_partitions( 645 __in efx_nic_t *enp, 646 __out_bcount(size) caddr_t data, 647 __in size_t size, 648 __out unsigned int *npartnp); 649 650 LIBEFX_INTERNAL 651 extern __checkReturn efx_rc_t 652 efx_mcdi_nvram_metadata( 653 __in efx_nic_t *enp, 654 __in uint32_t partn, 655 __out uint32_t *subtypep, 656 __out_ecount(4) uint16_t version[4], 657 __out_bcount_opt(size) char *descp, 658 __in size_t size); 659 660 LIBEFX_INTERNAL 661 extern __checkReturn efx_rc_t 662 efx_mcdi_nvram_info( 663 __in efx_nic_t *enp, 664 __in uint32_t partn, 665 __out efx_nvram_info_t *eni); 666 667 LIBEFX_INTERNAL 668 extern __checkReturn efx_rc_t 669 efx_mcdi_nvram_update_start( 670 __in efx_nic_t *enp, 671 __in uint32_t partn); 672 673 LIBEFX_INTERNAL 674 extern __checkReturn efx_rc_t 675 efx_mcdi_nvram_read( 676 __in efx_nic_t *enp, 677 __in uint32_t partn, 678 __in uint32_t offset, 679 __out_bcount(size) caddr_t data, 680 __in size_t size, 681 __in uint32_t mode); 682 683 LIBEFX_INTERNAL 684 extern __checkReturn efx_rc_t 685 efx_mcdi_nvram_erase( 686 __in efx_nic_t *enp, 687 __in uint32_t partn, 688 __in uint32_t offset, 689 __in size_t size); 690 691 LIBEFX_INTERNAL 692 extern __checkReturn efx_rc_t 693 efx_mcdi_nvram_write( 694 __in efx_nic_t *enp, 695 __in uint32_t partn, 696 __in uint32_t offset, 697 __in_bcount(size) caddr_t data, 698 __in size_t size); 699 700 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND 0x00000001 701 #define EFX_NVRAM_UPDATE_FLAGS_POLL 0x00000002 702 703 LIBEFX_INTERNAL 704 extern __checkReturn efx_rc_t 705 efx_mcdi_nvram_update_finish( 706 __in efx_nic_t *enp, 707 __in uint32_t partn, 708 __in boolean_t reboot, 709 __in uint32_t flags, 710 __out_opt uint32_t *verify_resultp); 711 712 #if EFSYS_OPT_DIAG 713 714 LIBEFX_INTERNAL 715 extern __checkReturn efx_rc_t 716 efx_mcdi_nvram_test( 717 __in efx_nic_t *enp, 718 __in uint32_t partn); 719 720 #endif /* EFSYS_OPT_DIAG */ 721 722 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 723 724 #if EFSYS_OPT_LICENSING 725 726 typedef struct efx_lic_ops_s { 727 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 728 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 729 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 730 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 731 size_t *, uint8_t *); 732 efx_rc_t (*elo_find_start) 733 (efx_nic_t *, caddr_t, size_t, uint32_t *); 734 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 735 uint32_t, uint32_t *); 736 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 737 uint32_t, uint32_t *, uint32_t *); 738 boolean_t (*elo_validate_key)(efx_nic_t *, 739 caddr_t, uint32_t); 740 efx_rc_t (*elo_read_key)(efx_nic_t *, 741 caddr_t, size_t, uint32_t, uint32_t, 742 caddr_t, size_t, uint32_t *); 743 efx_rc_t (*elo_write_key)(efx_nic_t *, 744 caddr_t, size_t, uint32_t, 745 caddr_t, uint32_t, uint32_t *); 746 efx_rc_t (*elo_delete_key)(efx_nic_t *, 747 caddr_t, size_t, uint32_t, 748 uint32_t, uint32_t, uint32_t *); 749 efx_rc_t (*elo_create_partition)(efx_nic_t *, 750 caddr_t, size_t); 751 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 752 caddr_t, size_t); 753 } efx_lic_ops_t; 754 755 #endif 756 757 #if EFSYS_OPT_EVB 758 759 struct efx_vswitch_s { 760 efx_nic_t *ev_enp; 761 efx_vswitch_id_t ev_vswitch_id; 762 uint32_t ev_num_vports; 763 /* 764 * Vport configuration array: index 0 to store PF configuration 765 * and next ev_num_vports-1 entries hold VFs configuration. 766 */ 767 efx_vport_config_t *ev_evcp; 768 }; 769 770 typedef struct efx_evb_ops_s { 771 efx_rc_t (*eeo_init)(efx_nic_t *); 772 void (*eeo_fini)(efx_nic_t *); 773 efx_rc_t (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *); 774 efx_rc_t (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t); 775 efx_rc_t (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t, 776 efx_vport_type_t, uint16_t, 777 boolean_t, efx_vport_id_t *); 778 efx_rc_t (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t, 779 efx_vport_id_t); 780 efx_rc_t (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t, 781 efx_vport_id_t, uint8_t *); 782 efx_rc_t (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t, 783 efx_vport_id_t, uint8_t *); 784 efx_rc_t (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t, 785 efx_vport_id_t); 786 efx_rc_t (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t, 787 efx_vport_id_t); 788 efx_rc_t (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t, 789 efx_vport_id_t, uint32_t); 790 efx_rc_t (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t, 791 efx_vport_id_t, 792 uint16_t *, uint8_t *, 793 boolean_t *); 794 efx_rc_t (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t, 795 efx_vport_id_t, efsys_mem_t *); 796 } efx_evb_ops_t; 797 798 LIBEFX_INTERNAL 799 extern __checkReturn boolean_t 800 efx_is_zero_eth_addr( 801 __in_bcount(EFX_MAC_ADDR_LEN) const uint8_t *addrp); 802 803 #endif /* EFSYS_OPT_EVB */ 804 805 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 806 807 #define EFX_PROXY_CONFIGURE_MAGIC 0xAB2015EF 808 809 810 typedef struct efx_proxy_ops_s { 811 efx_rc_t (*epo_init)(efx_nic_t *); 812 void (*epo_fini)(efx_nic_t *); 813 efx_rc_t (*epo_mc_config)(efx_nic_t *, efsys_mem_t *, 814 efsys_mem_t *, efsys_mem_t *, 815 uint32_t, uint32_t *, size_t); 816 efx_rc_t (*epo_disable)(efx_nic_t *); 817 efx_rc_t (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t, 818 uint32_t, uint32_t, uint32_t); 819 efx_rc_t (*epo_set_privilege_mask)(efx_nic_t *, uint32_t, 820 uint32_t, uint32_t); 821 efx_rc_t (*epo_complete_request)(efx_nic_t *, uint32_t, 822 uint32_t, uint32_t); 823 efx_rc_t (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *); 824 efx_rc_t (*epo_get_privilege_mask)(efx_nic_t *, uint32_t, 825 uint32_t, uint32_t *); 826 } efx_proxy_ops_t; 827 828 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 829 830 #if EFSYS_OPT_MAE 831 832 typedef struct efx_mae_field_cap_s { 833 uint32_t emfc_support; 834 boolean_t emfc_mask_affects_class; 835 boolean_t emfc_match_affects_class; 836 } efx_mae_field_cap_t; 837 838 typedef struct efx_mae_s { 839 uint32_t em_max_n_action_prios; 840 /* 841 * The number of MAE field IDs recognised by the FW implementation. 842 * Any field ID greater than or equal to this value is unsupported. 843 */ 844 uint32_t em_max_nfields; 845 /** Action rule match field capabilities. */ 846 efx_mae_field_cap_t *em_action_rule_field_caps; 847 size_t em_action_rule_field_caps_size; 848 uint32_t em_max_n_outer_prios; 849 uint32_t em_encap_types_supported; 850 /** Outer rule match field capabilities. */ 851 efx_mae_field_cap_t *em_outer_rule_field_caps; 852 size_t em_outer_rule_field_caps_size; 853 uint32_t em_max_n_action_counters; 854 uint32_t em_max_n_conntrack_counters; 855 } efx_mae_t; 856 857 #endif /* EFSYS_OPT_MAE */ 858 859 #define EFX_DRV_VER_MAX 20 860 861 typedef struct efx_drv_cfg_s { 862 uint32_t edc_min_vi_count; 863 uint32_t edc_max_vi_count; 864 865 uint32_t edc_max_piobuf_count; 866 uint32_t edc_pio_alloc_size; 867 } efx_drv_cfg_t; 868 869 struct efx_nic_s { 870 uint32_t en_magic; 871 efx_family_t en_family; 872 uint32_t en_features; 873 efsys_identifier_t *en_esip; 874 efsys_lock_t *en_eslp; 875 efsys_bar_t *en_esbp; 876 unsigned int en_mod_flags; 877 unsigned int en_reset_flags; 878 efx_nic_cfg_t en_nic_cfg; 879 efx_drv_cfg_t en_drv_cfg; 880 efx_port_t en_port; 881 efx_mon_t en_mon; 882 efx_intr_t en_intr; 883 uint32_t en_ev_qcount; 884 uint32_t en_rx_qcount; 885 uint32_t en_tx_qcount; 886 const efx_nic_ops_t *en_enop; 887 const efx_ev_ops_t *en_eevop; 888 const efx_tx_ops_t *en_etxop; 889 const efx_rx_ops_t *en_erxop; 890 efx_fw_variant_t efv; 891 char en_drv_version[EFX_DRV_VER_MAX]; 892 efx_nic_dma_t en_dma; 893 #if EFSYS_OPT_FILTER 894 efx_filter_t en_filter; 895 const efx_filter_ops_t *en_efop; 896 #endif /* EFSYS_OPT_FILTER */ 897 #if EFSYS_OPT_TUNNEL 898 efx_tunnel_cfg_t en_tunnel_cfg; 899 const efx_tunnel_ops_t *en_etop; 900 #endif /* EFSYS_OPT_TUNNEL */ 901 #if EFSYS_OPT_MCDI 902 efx_mcdi_t en_mcdi; 903 #endif /* EFSYS_OPT_MCDI */ 904 #if EFSYS_OPT_NVRAM 905 uint32_t en_nvram_partn_locked; 906 const efx_nvram_ops_t *en_envop; 907 #endif /* EFSYS_OPT_NVRAM */ 908 #if EFSYS_OPT_VPD 909 const efx_vpd_ops_t *en_evpdop; 910 #endif /* EFSYS_OPT_VPD */ 911 #if EFSYS_OPT_VIRTIO 912 const efx_virtio_ops_t *en_evop; 913 #endif /* EFSYS_OPT_VPD */ 914 #if EFSYS_OPT_RX_SCALE 915 efx_rx_hash_support_t en_hash_support; 916 efx_rx_scale_context_type_t en_rss_context_type; 917 uint32_t en_rss_context; 918 #endif /* EFSYS_OPT_RX_SCALE */ 919 uint32_t en_vport_id; 920 #if EFSYS_OPT_LICENSING 921 const efx_lic_ops_t *en_elop; 922 boolean_t en_licensing_supported; 923 #endif 924 union { 925 #if EFSYS_OPT_SIENA 926 struct { 927 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 928 unsigned int enu_partn_mask; 929 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 930 #if EFSYS_OPT_VPD 931 caddr_t enu_svpd; 932 size_t enu_svpd_length; 933 #endif /* EFSYS_OPT_VPD */ 934 int enu_unused; 935 } siena; 936 #endif /* EFSYS_OPT_SIENA */ 937 int enu_unused; 938 } en_u; 939 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 940 union en_arch { 941 struct { 942 int ena_vi_base; 943 int ena_vi_count; 944 int ena_vi_shift; 945 uint32_t ena_fcw_base; 946 #if EFSYS_OPT_VPD 947 caddr_t ena_svpd; 948 size_t ena_svpd_length; 949 #endif /* EFSYS_OPT_VPD */ 950 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 951 uint32_t ena_piobuf_count; 952 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 953 uint32_t ena_pio_write_vi_base; 954 /* Memory BAR mapping regions */ 955 uint32_t ena_uc_mem_map_offset; 956 size_t ena_uc_mem_map_size; 957 uint32_t ena_wc_mem_map_offset; 958 size_t ena_wc_mem_map_size; 959 } ef10; 960 } en_arch; 961 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 962 #if EFSYS_OPT_EVB 963 const efx_evb_ops_t *en_eeop; 964 struct efx_vswitch_s *en_vswitchp; 965 #endif /* EFSYS_OPT_EVB */ 966 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 967 const efx_proxy_ops_t *en_epop; 968 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 969 #if EFSYS_OPT_MAE 970 efx_mae_t *en_maep; 971 #endif /* EFSYS_OPT_MAE */ 972 }; 973 974 #define EFX_FAMILY_IS_EF10(_enp) \ 975 ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \ 976 (_enp)->en_family == EFX_FAMILY_MEDFORD || \ 977 (_enp)->en_family == EFX_FAMILY_HUNTINGTON) 978 979 #define EFX_FAMILY_IS_EF100(_enp) \ 980 ((_enp)->en_family == EFX_FAMILY_RIVERHEAD) 981 982 983 #define EFX_NIC_MAGIC 0x02121996 984 985 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 986 const efx_ev_callbacks_t *, void *); 987 988 #if EFSYS_OPT_EV_EXTENDED_WIDTH 989 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *, 990 const efx_ev_callbacks_t *, void *); 991 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */ 992 993 typedef struct efx_evq_rxq_state_s { 994 unsigned int eers_rx_read_ptr; 995 unsigned int eers_rx_mask; 996 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 997 unsigned int eers_rx_stream_npackets; 998 boolean_t eers_rx_packed_stream; 999 #endif 1000 #if EFSYS_OPT_RX_PACKED_STREAM 1001 unsigned int eers_rx_packed_stream_credits; 1002 #endif 1003 } efx_evq_rxq_state_t; 1004 1005 struct efx_evq_s { 1006 uint32_t ee_magic; 1007 uint32_t ee_flags; 1008 efx_nic_t *ee_enp; 1009 unsigned int ee_index; 1010 unsigned int ee_mask; 1011 efsys_mem_t *ee_esmp; 1012 #if EFSYS_OPT_QSTATS 1013 uint32_t ee_stat[EV_NQSTATS]; 1014 #endif /* EFSYS_OPT_QSTATS */ 1015 1016 efx_ev_handler_t ee_rx; 1017 efx_ev_handler_t ee_tx; 1018 efx_ev_handler_t ee_driver; 1019 efx_ev_handler_t ee_global; 1020 efx_ev_handler_t ee_drv_gen; 1021 #if EFSYS_OPT_MCDI 1022 efx_ev_handler_t ee_mcdi; 1023 #endif /* EFSYS_OPT_MCDI */ 1024 1025 #if EFSYS_OPT_DESC_PROXY 1026 efx_ev_ew_handler_t ee_ew_txq_desc; 1027 efx_ev_ew_handler_t ee_ew_virtq_desc; 1028 #endif /* EFSYS_OPT_DESC_PROXY */ 1029 1030 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 1031 }; 1032 1033 #define EFX_EVQ_MAGIC 0x08081997 1034 1035 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 1036 1037 #if EFSYS_OPT_QSTATS 1038 #define EFX_EV_QSTAT_INCR(_eep, _stat) \ 1039 do { \ 1040 (_eep)->ee_stat[_stat]++; \ 1041 _NOTE(CONSTANTCONDITION) \ 1042 } while (B_FALSE) 1043 #else 1044 #define EFX_EV_QSTAT_INCR(_eep, _stat) 1045 #endif 1046 1047 struct efx_rxq_s { 1048 uint32_t er_magic; 1049 efx_nic_t *er_enp; 1050 efx_evq_t *er_eep; 1051 unsigned int er_index; 1052 unsigned int er_label; 1053 unsigned int er_mask; 1054 size_t er_buf_size; 1055 efsys_mem_t *er_esmp; 1056 efx_evq_rxq_state_t *er_ev_qstate; 1057 efx_rx_prefix_layout_t er_prefix_layout; 1058 }; 1059 1060 #define EFX_RXQ_MAGIC 0x15022005 1061 1062 struct efx_txq_s { 1063 uint32_t et_magic; 1064 efx_nic_t *et_enp; 1065 unsigned int et_index; 1066 unsigned int et_mask; 1067 efsys_mem_t *et_esmp; 1068 #if EFSYS_OPT_HUNTINGTON 1069 uint32_t et_pio_bufnum; 1070 uint32_t et_pio_blknum; 1071 uint32_t et_pio_write_offset; 1072 uint32_t et_pio_offset; 1073 size_t et_pio_size; 1074 #endif 1075 #if EFSYS_OPT_QSTATS 1076 uint32_t et_stat[TX_NQSTATS]; 1077 #endif /* EFSYS_OPT_QSTATS */ 1078 }; 1079 1080 #define EFX_TXQ_MAGIC 0x05092005 1081 1082 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 1083 do { \ 1084 (_dst)[0] = (_src)[0]; \ 1085 (_dst)[1] = (_src)[1]; \ 1086 (_dst)[2] = (_src)[2]; \ 1087 (_dst)[3] = (_src)[3]; \ 1088 (_dst)[4] = (_src)[4]; \ 1089 (_dst)[5] = (_src)[5]; \ 1090 _NOTE(CONSTANTCONDITION) \ 1091 } while (B_FALSE) 1092 1093 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 1094 do { \ 1095 uint16_t *_d = (uint16_t *)(_dst); \ 1096 _d[0] = 0xffff; \ 1097 _d[1] = 0xffff; \ 1098 _d[2] = 0xffff; \ 1099 _NOTE(CONSTANTCONDITION) \ 1100 } while (B_FALSE) 1101 1102 #if EFSYS_OPT_CHECK_REG 1103 #define EFX_CHECK_REG(_enp, _reg) \ 1104 do { \ 1105 const char *name = #_reg; \ 1106 char min = name[4]; \ 1107 char max = name[5]; \ 1108 char rev; \ 1109 \ 1110 switch ((_enp)->en_family) { \ 1111 case EFX_FAMILY_SIENA: \ 1112 rev = 'C'; \ 1113 break; \ 1114 \ 1115 case EFX_FAMILY_HUNTINGTON: \ 1116 rev = 'D'; \ 1117 break; \ 1118 \ 1119 case EFX_FAMILY_MEDFORD: \ 1120 rev = 'E'; \ 1121 break; \ 1122 \ 1123 case EFX_FAMILY_MEDFORD2: \ 1124 rev = 'F'; \ 1125 break; \ 1126 \ 1127 case EFX_FAMILY_RIVERHEAD: \ 1128 rev = 'G'; \ 1129 break; \ 1130 \ 1131 default: \ 1132 rev = '?'; \ 1133 break; \ 1134 } \ 1135 \ 1136 EFSYS_ASSERT3S(rev, >=, min); \ 1137 EFSYS_ASSERT3S(rev, <=, max); \ 1138 \ 1139 _NOTE(CONSTANTCONDITION) \ 1140 } while (B_FALSE) 1141 #else 1142 #define EFX_CHECK_REG(_enp, _reg) do { \ 1143 _NOTE(CONSTANTCONDITION) \ 1144 } while (B_FALSE) 1145 #endif 1146 1147 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 1148 do { \ 1149 EFX_CHECK_REG((_enp), (_reg)); \ 1150 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 1151 (_edp), (_lock)); \ 1152 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 1153 uint32_t, _reg ## _OFST, \ 1154 uint32_t, (_edp)->ed_u32[0]); \ 1155 _NOTE(CONSTANTCONDITION) \ 1156 } while (B_FALSE) 1157 1158 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 1159 do { \ 1160 EFX_CHECK_REG((_enp), (_reg)); \ 1161 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 1162 uint32_t, _reg ## _OFST, \ 1163 uint32_t, (_edp)->ed_u32[0]); \ 1164 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 1165 (_edp), (_lock)); \ 1166 _NOTE(CONSTANTCONDITION) \ 1167 } while (B_FALSE) 1168 1169 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 1170 do { \ 1171 EFX_CHECK_REG((_enp), (_reg)); \ 1172 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 1173 (_eqp)); \ 1174 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 1175 uint32_t, _reg ## _OFST, \ 1176 uint32_t, (_eqp)->eq_u32[1], \ 1177 uint32_t, (_eqp)->eq_u32[0]); \ 1178 _NOTE(CONSTANTCONDITION) \ 1179 } while (B_FALSE) 1180 1181 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 1182 do { \ 1183 EFX_CHECK_REG((_enp), (_reg)); \ 1184 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 1185 uint32_t, _reg ## _OFST, \ 1186 uint32_t, (_eqp)->eq_u32[1], \ 1187 uint32_t, (_eqp)->eq_u32[0]); \ 1188 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 1189 (_eqp)); \ 1190 _NOTE(CONSTANTCONDITION) \ 1191 } while (B_FALSE) 1192 1193 #define EFX_BAR_READO(_enp, _reg, _eop) \ 1194 do { \ 1195 EFX_CHECK_REG((_enp), (_reg)); \ 1196 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 1197 (_eop), B_TRUE); \ 1198 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 1199 uint32_t, _reg ## _OFST, \ 1200 uint32_t, (_eop)->eo_u32[3], \ 1201 uint32_t, (_eop)->eo_u32[2], \ 1202 uint32_t, (_eop)->eo_u32[1], \ 1203 uint32_t, (_eop)->eo_u32[0]); \ 1204 _NOTE(CONSTANTCONDITION) \ 1205 } while (B_FALSE) 1206 1207 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 1208 do { \ 1209 EFX_CHECK_REG((_enp), (_reg)); \ 1210 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 1211 uint32_t, _reg ## _OFST, \ 1212 uint32_t, (_eop)->eo_u32[3], \ 1213 uint32_t, (_eop)->eo_u32[2], \ 1214 uint32_t, (_eop)->eo_u32[1], \ 1215 uint32_t, (_eop)->eo_u32[0]); \ 1216 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 1217 (_eop), B_TRUE); \ 1218 _NOTE(CONSTANTCONDITION) \ 1219 } while (B_FALSE) 1220 1221 /* 1222 * Accessors for memory BAR non-VI tables. 1223 * 1224 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 1225 * to ensure the correct runtime VI window size is used on Medford2. 1226 * 1227 * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control 1228 * window registers, to ensure the correct starting offset is used. 1229 * 1230 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 1231 */ 1232 1233 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 1234 do { \ 1235 EFX_CHECK_REG((_enp), (_reg)); \ 1236 EFSYS_BAR_READD((_enp)->en_esbp, \ 1237 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1238 (_edp), (_lock)); \ 1239 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 1240 uint32_t, (_index), \ 1241 uint32_t, _reg ## _OFST, \ 1242 uint32_t, (_edp)->ed_u32[0]); \ 1243 _NOTE(CONSTANTCONDITION) \ 1244 } while (B_FALSE) 1245 1246 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 1247 do { \ 1248 EFX_CHECK_REG((_enp), (_reg)); \ 1249 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1250 uint32_t, (_index), \ 1251 uint32_t, _reg ## _OFST, \ 1252 uint32_t, (_edp)->ed_u32[0]); \ 1253 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1254 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1255 (_edp), (_lock)); \ 1256 _NOTE(CONSTANTCONDITION) \ 1257 } while (B_FALSE) 1258 1259 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 1260 do { \ 1261 EFX_CHECK_REG((_enp), (_reg)); \ 1262 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 1263 uint32_t, (_index), \ 1264 uint32_t, _reg ## _OFST, \ 1265 uint32_t, (_edp)->ed_u32[0]); \ 1266 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1267 (_reg ## _OFST + \ 1268 (3 * sizeof (efx_dword_t)) + \ 1269 ((_index) * _reg ## _STEP)), \ 1270 (_edp), (_lock)); \ 1271 _NOTE(CONSTANTCONDITION) \ 1272 } while (B_FALSE) 1273 1274 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1275 do { \ 1276 EFX_CHECK_REG((_enp), (_reg)); \ 1277 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1278 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1279 (_eqp)); \ 1280 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1281 uint32_t, (_index), \ 1282 uint32_t, _reg ## _OFST, \ 1283 uint32_t, (_eqp)->eq_u32[1], \ 1284 uint32_t, (_eqp)->eq_u32[0]); \ 1285 _NOTE(CONSTANTCONDITION) \ 1286 } while (B_FALSE) 1287 1288 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1289 do { \ 1290 EFX_CHECK_REG((_enp), (_reg)); \ 1291 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1292 uint32_t, (_index), \ 1293 uint32_t, _reg ## _OFST, \ 1294 uint32_t, (_eqp)->eq_u32[1], \ 1295 uint32_t, (_eqp)->eq_u32[0]); \ 1296 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1297 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1298 (_eqp)); \ 1299 _NOTE(CONSTANTCONDITION) \ 1300 } while (B_FALSE) 1301 1302 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1303 do { \ 1304 EFX_CHECK_REG((_enp), (_reg)); \ 1305 EFSYS_BAR_READO((_enp)->en_esbp, \ 1306 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1307 (_eop), (_lock)); \ 1308 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1309 uint32_t, (_index), \ 1310 uint32_t, _reg ## _OFST, \ 1311 uint32_t, (_eop)->eo_u32[3], \ 1312 uint32_t, (_eop)->eo_u32[2], \ 1313 uint32_t, (_eop)->eo_u32[1], \ 1314 uint32_t, (_eop)->eo_u32[0]); \ 1315 _NOTE(CONSTANTCONDITION) \ 1316 } while (B_FALSE) 1317 1318 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1319 do { \ 1320 EFX_CHECK_REG((_enp), (_reg)); \ 1321 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1322 uint32_t, (_index), \ 1323 uint32_t, _reg ## _OFST, \ 1324 uint32_t, (_eop)->eo_u32[3], \ 1325 uint32_t, (_eop)->eo_u32[2], \ 1326 uint32_t, (_eop)->eo_u32[1], \ 1327 uint32_t, (_eop)->eo_u32[0]); \ 1328 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1329 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1330 (_eop), (_lock)); \ 1331 _NOTE(CONSTANTCONDITION) \ 1332 } while (B_FALSE) 1333 1334 /* 1335 * Accessors for memory BAR function control window registers. 1336 * 1337 * The function control window is located at an offset which can be 1338 * non-zero in case of Riverhead. 1339 */ 1340 1341 #if EFSYS_OPT_RIVERHEAD 1342 1343 #define EFX_BAR_FCW_READD(_enp, _reg, _edp) \ 1344 do { \ 1345 EFX_CHECK_REG((_enp), (_reg)); \ 1346 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST + \ 1347 (_enp)->en_arch.ef10.ena_fcw_base, \ 1348 (_edp), B_FALSE); \ 1349 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg, \ 1350 uint32_t, _reg ## _OFST, \ 1351 uint32_t, (_edp)->ed_u32[0]); \ 1352 _NOTE(CONSTANTCONDITION) \ 1353 } while (B_FALSE) 1354 1355 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp) \ 1356 do { \ 1357 EFX_CHECK_REG((_enp), (_reg)); \ 1358 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg, \ 1359 uint32_t, _reg ## _OFST, \ 1360 uint32_t, (_edp)->ed_u32[0]); \ 1361 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST + \ 1362 (_enp)->en_arch.ef10.ena_fcw_base, \ 1363 (_edp), B_FALSE); \ 1364 _NOTE(CONSTANTCONDITION) \ 1365 } while (B_FALSE) 1366 1367 #endif /* EFSYS_OPT_RIVERHEAD */ 1368 1369 /* 1370 * Accessors for memory BAR per-VI registers. 1371 * 1372 * The VI window size is 8KB for Medford and all earlier controllers. 1373 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1374 */ 1375 1376 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1377 do { \ 1378 EFX_CHECK_REG((_enp), (_reg)); \ 1379 EFSYS_BAR_READD((_enp)->en_esbp, \ 1380 ((_reg ## _OFST) + \ 1381 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1382 (_edp), (_lock)); \ 1383 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1384 uint32_t, (_index), \ 1385 uint32_t, _reg ## _OFST, \ 1386 uint32_t, (_edp)->ed_u32[0]); \ 1387 _NOTE(CONSTANTCONDITION) \ 1388 } while (B_FALSE) 1389 1390 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1391 do { \ 1392 EFX_CHECK_REG((_enp), (_reg)); \ 1393 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1394 uint32_t, (_index), \ 1395 uint32_t, _reg ## _OFST, \ 1396 uint32_t, (_edp)->ed_u32[0]); \ 1397 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1398 ((_reg ## _OFST) + \ 1399 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1400 (_edp), (_lock)); \ 1401 _NOTE(CONSTANTCONDITION) \ 1402 } while (B_FALSE) 1403 1404 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1405 do { \ 1406 EFX_CHECK_REG((_enp), (_reg)); \ 1407 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1408 uint32_t, (_index), \ 1409 uint32_t, _reg ## _OFST, \ 1410 uint32_t, (_edp)->ed_u32[0]); \ 1411 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1412 ((_reg ## _OFST) + \ 1413 (2 * sizeof (efx_dword_t)) + \ 1414 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1415 (_edp), (_lock)); \ 1416 _NOTE(CONSTANTCONDITION) \ 1417 } while (B_FALSE) 1418 1419 /* 1420 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1421 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1422 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1423 * the need for locking in the host, and are the only ones known to be safe to 1424 * use 128-bites write with. 1425 */ 1426 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1427 do { \ 1428 EFX_CHECK_REG((_enp), (_reg)); \ 1429 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1430 const char *, #_reg, \ 1431 uint32_t, (_index), \ 1432 uint32_t, _reg ## _OFST, \ 1433 uint32_t, (_eop)->eo_u32[3], \ 1434 uint32_t, (_eop)->eo_u32[2], \ 1435 uint32_t, (_eop)->eo_u32[1], \ 1436 uint32_t, (_eop)->eo_u32[0]); \ 1437 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1438 (_reg ## _OFST + \ 1439 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1440 (_eop)); \ 1441 _NOTE(CONSTANTCONDITION) \ 1442 } while (B_FALSE) 1443 1444 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size, \ 1445 _wptr, _owptr) \ 1446 do { \ 1447 unsigned int _new = (_wptr); \ 1448 unsigned int _old = (_owptr); \ 1449 \ 1450 if ((_new) >= (_old)) \ 1451 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1452 (_old) * (_desc_size), \ 1453 ((_new) - (_old)) * (_desc_size)); \ 1454 else \ 1455 /* \ 1456 * It is cheaper to sync entire map than sync \ 1457 * two parts especially when offset/size are \ 1458 * ignored and entire map is synced in any case.\ 1459 */ \ 1460 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1461 0, \ 1462 (_entries) * (_desc_size)); \ 1463 _NOTE(CONSTANTCONDITION) \ 1464 } while (B_FALSE) 1465 1466 LIBEFX_INTERNAL 1467 extern __checkReturn efx_rc_t 1468 efx_mac_select( 1469 __in efx_nic_t *enp); 1470 1471 LIBEFX_INTERNAL 1472 extern void 1473 efx_mac_multicast_hash_compute( 1474 __in_ecount(6*count) uint8_t const *addrs, 1475 __in int count, 1476 __out efx_oword_t *hash_low, 1477 __out efx_oword_t *hash_high); 1478 1479 LIBEFX_INTERNAL 1480 extern __checkReturn efx_rc_t 1481 efx_phy_probe( 1482 __in efx_nic_t *enp); 1483 1484 LIBEFX_INTERNAL 1485 extern void 1486 efx_phy_unprobe( 1487 __in efx_nic_t *enp); 1488 1489 #if EFSYS_OPT_VPD 1490 1491 /* VPD utility functions */ 1492 1493 LIBEFX_INTERNAL 1494 extern __checkReturn efx_rc_t 1495 efx_vpd_hunk_length( 1496 __in_bcount(size) caddr_t data, 1497 __in size_t size, 1498 __out size_t *lengthp); 1499 1500 LIBEFX_INTERNAL 1501 extern __checkReturn efx_rc_t 1502 efx_vpd_hunk_verify( 1503 __in_bcount(size) caddr_t data, 1504 __in size_t size, 1505 __out_opt boolean_t *cksummedp); 1506 1507 LIBEFX_INTERNAL 1508 extern __checkReturn efx_rc_t 1509 efx_vpd_hunk_reinit( 1510 __in_bcount(size) caddr_t data, 1511 __in size_t size, 1512 __in boolean_t wantpid); 1513 1514 LIBEFX_INTERNAL 1515 extern __checkReturn efx_rc_t 1516 efx_vpd_hunk_get( 1517 __in_bcount(size) caddr_t data, 1518 __in size_t size, 1519 __in efx_vpd_tag_t tag, 1520 __in efx_vpd_keyword_t keyword, 1521 __out unsigned int *payloadp, 1522 __out uint8_t *paylenp); 1523 1524 LIBEFX_INTERNAL 1525 extern __checkReturn efx_rc_t 1526 efx_vpd_hunk_next( 1527 __in_bcount(size) caddr_t data, 1528 __in size_t size, 1529 __out efx_vpd_tag_t *tagp, 1530 __out efx_vpd_keyword_t *keyword, 1531 __out_opt unsigned int *payloadp, 1532 __out_opt uint8_t *paylenp, 1533 __inout unsigned int *contp); 1534 1535 LIBEFX_INTERNAL 1536 extern __checkReturn efx_rc_t 1537 efx_vpd_hunk_set( 1538 __in_bcount(size) caddr_t data, 1539 __in size_t size, 1540 __in efx_vpd_value_t *evvp); 1541 1542 #endif /* EFSYS_OPT_VPD */ 1543 1544 #if EFSYS_OPT_MCDI 1545 1546 LIBEFX_INTERNAL 1547 extern __checkReturn efx_rc_t 1548 efx_mcdi_set_workaround( 1549 __in efx_nic_t *enp, 1550 __in uint32_t type, 1551 __in boolean_t enabled, 1552 __out_opt uint32_t *flagsp); 1553 1554 LIBEFX_INTERNAL 1555 extern __checkReturn efx_rc_t 1556 efx_mcdi_get_workarounds( 1557 __in efx_nic_t *enp, 1558 __out_opt uint32_t *implementedp, 1559 __out_opt uint32_t *enabledp); 1560 1561 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1562 1563 LIBEFX_INTERNAL 1564 extern __checkReturn efx_rc_t 1565 efx_mcdi_intf_from_pcie( 1566 __in uint32_t pcie_intf, 1567 __out efx_pcie_interface_t *efx_intf); 1568 1569 LIBEFX_INTERNAL 1570 extern __checkReturn efx_rc_t 1571 efx_mcdi_intf_to_pcie( 1572 __in efx_pcie_interface_t efx_intf, 1573 __out uint32_t *pcie_intf); 1574 1575 LIBEFX_INTERNAL 1576 extern __checkReturn efx_rc_t 1577 efx_mcdi_init_evq( 1578 __in efx_nic_t *enp, 1579 __in unsigned int instance, 1580 __in efsys_mem_t *esmp, 1581 __in size_t nevs, 1582 __in uint32_t irq, 1583 __in uint32_t target_evq, 1584 __in uint32_t us, 1585 __in uint32_t flags, 1586 __in boolean_t low_latency); 1587 1588 LIBEFX_INTERNAL 1589 extern __checkReturn efx_rc_t 1590 efx_mcdi_fini_evq( 1591 __in efx_nic_t *enp, 1592 __in uint32_t instance); 1593 1594 typedef struct efx_mcdi_init_rxq_params_s { 1595 boolean_t disable_scatter; 1596 boolean_t want_inner_classes; 1597 uint32_t buf_size; 1598 uint32_t ps_buf_size; 1599 uint32_t es_bufs_per_desc; 1600 uint32_t es_max_dma_len; 1601 uint32_t es_buf_stride; 1602 uint32_t hol_block_timeout; 1603 uint32_t prefix_id; 1604 } efx_mcdi_init_rxq_params_t; 1605 1606 LIBEFX_INTERNAL 1607 extern __checkReturn efx_rc_t 1608 efx_mcdi_init_rxq( 1609 __in efx_nic_t *enp, 1610 __in uint32_t ndescs, 1611 __in efx_evq_t *eep, 1612 __in uint32_t label, 1613 __in uint32_t instance, 1614 __in efsys_mem_t *esmp, 1615 __in const efx_mcdi_init_rxq_params_t *params); 1616 1617 LIBEFX_INTERNAL 1618 extern __checkReturn efx_rc_t 1619 efx_mcdi_fini_rxq( 1620 __in efx_nic_t *enp, 1621 __in uint32_t instance); 1622 1623 LIBEFX_INTERNAL 1624 extern __checkReturn efx_rc_t 1625 efx_mcdi_init_txq( 1626 __in efx_nic_t *enp, 1627 __in uint32_t ndescs, 1628 __in uint32_t target_evq, 1629 __in uint32_t label, 1630 __in uint32_t instance, 1631 __in uint16_t flags, 1632 __in efsys_mem_t *esmp); 1633 1634 LIBEFX_INTERNAL 1635 extern __checkReturn efx_rc_t 1636 efx_mcdi_fini_txq( 1637 __in efx_nic_t *enp, 1638 __in uint32_t instance); 1639 1640 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1641 1642 #endif /* EFSYS_OPT_MCDI */ 1643 1644 #if EFSYS_OPT_MAC_STATS 1645 1646 /* 1647 * Closed range of stats (i.e. the first and the last are included). 1648 * The last must be greater or equal (if the range is one item only) to 1649 * the first. 1650 */ 1651 struct efx_mac_stats_range { 1652 efx_mac_stat_t first; 1653 efx_mac_stat_t last; 1654 }; 1655 1656 typedef enum efx_stats_action_e { 1657 EFX_STATS_CLEAR, 1658 EFX_STATS_UPLOAD, 1659 EFX_STATS_ENABLE_NOEVENTS, 1660 EFX_STATS_ENABLE_EVENTS, 1661 EFX_STATS_DISABLE, 1662 } efx_stats_action_t; 1663 1664 LIBEFX_INTERNAL 1665 extern efx_rc_t 1666 efx_mac_stats_mask_add_ranges( 1667 __inout_bcount(mask_size) uint32_t *maskp, 1668 __in size_t mask_size, 1669 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1670 __in unsigned int rng_count); 1671 1672 LIBEFX_INTERNAL 1673 extern __checkReturn efx_rc_t 1674 efx_mcdi_mac_stats( 1675 __in efx_nic_t *enp, 1676 __in uint32_t vport_id, 1677 __in_opt efsys_mem_t *esmp, 1678 __in efx_stats_action_t action, 1679 __in uint16_t period_ms); 1680 1681 #endif /* EFSYS_OPT_MAC_STATS */ 1682 1683 #if EFSYS_OPT_PCI 1684 1685 /* 1686 * Find the next extended capability in a PCI device's config space 1687 * with specified capability id. 1688 * Passing 0 offset makes the function search from the start. 1689 * If search succeeds, found capability is in modified offset. 1690 * 1691 * Returns ENOENT if a capability is not found. 1692 */ 1693 LIBEFX_INTERNAL 1694 extern __checkReturn efx_rc_t 1695 efx_pci_config_find_next_ext_cap( 1696 __in efsys_pci_config_t *espcp, 1697 __in const efx_pci_ops_t *epop, 1698 __in uint16_t cap_id, 1699 __inout size_t *offsetp); 1700 1701 /* 1702 * Get the next extended capability in a PCI device's config space. 1703 * Passing 0 offset makes the function get the first capability. 1704 * If search succeeds, the capability is in modified offset. 1705 * 1706 * Returns ENOENT if there is no next capability. 1707 */ 1708 LIBEFX_INTERNAL 1709 extern __checkReturn efx_rc_t 1710 efx_pci_config_next_ext_cap( 1711 __in efsys_pci_config_t *espcp, 1712 __in const efx_pci_ops_t *epop, 1713 __inout size_t *offsetp); 1714 1715 /* 1716 * Find the next Xilinx capabilities table location by searching 1717 * PCI extended capabilities. 1718 * 1719 * Returns ENOENT if a table location is not found. 1720 */ 1721 LIBEFX_INTERNAL 1722 extern __checkReturn efx_rc_t 1723 efx_pci_find_next_xilinx_cap_table( 1724 __in efsys_pci_config_t *espcp, 1725 __in const efx_pci_ops_t *epop, 1726 __inout size_t *pci_cap_offsetp, 1727 __out unsigned int *xilinx_tbl_barp, 1728 __out efsys_dma_addr_t *xilinx_tbl_offsetp); 1729 1730 /* 1731 * Read a Xilinx extended PCI capability that gives the location 1732 * of a Xilinx capabilities table. 1733 * 1734 * Returns ENOENT if the extended PCI capability does not contain 1735 * Xilinx capabilities table locator. 1736 */ 1737 LIBEFX_INTERNAL 1738 extern __checkReturn efx_rc_t 1739 efx_pci_read_ext_cap_xilinx_table( 1740 __in efsys_pci_config_t *espcp, 1741 __in const efx_pci_ops_t *epop, 1742 __in size_t cap_offset, 1743 __out unsigned int *barp, 1744 __out efsys_dma_addr_t *offsetp); 1745 1746 /* 1747 * Find a capability with specified format_id in a Xilinx capabilities table. 1748 * Searching is started from provided offset, taking skip_first into account. 1749 * If search succeeds, found capability is in modified offset. 1750 * 1751 * Returns ENOENT if an entry with specified format id is not found. 1752 */ 1753 LIBEFX_INTERNAL 1754 extern __checkReturn efx_rc_t 1755 efx_pci_xilinx_cap_tbl_find( 1756 __in efsys_bar_t *esbp, 1757 __in uint32_t format_id, 1758 __in boolean_t skip_first, 1759 __inout efsys_dma_addr_t *entry_offsetp); 1760 1761 #endif /* EFSYS_OPT_PCI */ 1762 1763 #if EFSYS_OPT_MAE 1764 1765 struct efx_mae_match_spec_s { 1766 efx_mae_rule_type_t emms_type; 1767 uint32_t emms_prio; 1768 union emms_mask_value_pairs { 1769 uint8_t action[ 1770 MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN]; 1771 uint8_t outer[MAE_ENC_FIELD_PAIRS_LEN]; 1772 } emms_mask_value_pairs; 1773 uint8_t emms_outer_rule_recirc_id; 1774 boolean_t emms_outer_rule_do_ct; 1775 }; 1776 1777 typedef enum efx_mae_action_e { 1778 /* These actions are strictly ordered. */ 1779 EFX_MAE_ACTION_DECAP, 1780 EFX_MAE_ACTION_VLAN_POP, 1781 EFX_MAE_ACTION_SET_DST_MAC, 1782 EFX_MAE_ACTION_SET_SRC_MAC, 1783 EFX_MAE_ACTION_DECR_IP_TTL, 1784 EFX_MAE_ACTION_NAT, 1785 EFX_MAE_ACTION_VLAN_PUSH, 1786 EFX_MAE_ACTION_COUNT, 1787 EFX_MAE_ACTION_ENCAP, 1788 1789 /* 1790 * These actions are not strictly ordered and can 1791 * be passed by a client in any order (before DELIVER). 1792 * However, these enumerants must be kept compactly 1793 * in the end of the enumeration (before DELIVER). 1794 */ 1795 EFX_MAE_ACTION_FLAG, 1796 EFX_MAE_ACTION_MARK, 1797 1798 /* DELIVER is always the last action. */ 1799 EFX_MAE_ACTION_DELIVER, 1800 1801 EFX_MAE_NACTIONS 1802 } efx_mae_action_t; 1803 1804 /* MAE VLAN_POP action can handle 1 or 2 tags. */ 1805 #define EFX_MAE_VLAN_POP_MAX_NTAGS (2) 1806 1807 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */ 1808 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS (2) 1809 1810 typedef struct efx_mae_action_vlan_push_s { 1811 uint16_t emavp_tpid_be; 1812 uint16_t emavp_tci_be; 1813 } efx_mae_action_vlan_push_t; 1814 1815 /* 1816 * Helper efx_mae_action_set_clear_fw_rsrc_ids() is responsible 1817 * to initialise every field in this structure to INVALID value. 1818 */ 1819 typedef struct efx_mae_actions_rsrc_s { 1820 efx_mae_mac_id_t emar_dst_mac_id; 1821 efx_mae_mac_id_t emar_src_mac_id; 1822 efx_mae_eh_id_t emar_eh_id; 1823 efx_counter_t emar_counter_id; 1824 } efx_mae_actions_rsrc_t; 1825 1826 struct efx_mae_actions_s { 1827 /* Bitmap of actions in spec, indexed by action type */ 1828 uint32_t ema_actions; 1829 1830 unsigned int ema_n_vlan_tags_to_pop; 1831 unsigned int ema_n_vlan_tags_to_push; 1832 efx_mae_action_vlan_push_t ema_vlan_push_descs[ 1833 EFX_MAE_VLAN_PUSH_MAX_NTAGS]; 1834 unsigned int ema_n_count_actions; 1835 uint32_t ema_mark_value; 1836 efx_mport_sel_t ema_deliver_mport; 1837 1838 /* 1839 * Always keep this at the end of the struct since 1840 * efx_mae_action_set_specs_equal() relies on that 1841 * to make sure that resource IDs are not compared. 1842 */ 1843 efx_mae_actions_rsrc_t ema_rsrc; 1844 1845 /* 1846 * A copy of encp->enc_mae_aset_v2_supported. 1847 * It is set by efx_mae_action_set_spec_init(). 1848 * This value is ignored on spec comparisons. 1849 */ 1850 boolean_t ema_v2_is_supported; 1851 }; 1852 1853 #endif /* EFSYS_OPT_MAE */ 1854 1855 #if EFSYS_OPT_VIRTIO 1856 1857 #define EFX_VQ_MAGIC 0x026011950 1858 1859 typedef enum efx_virtio_vq_state_e { 1860 EFX_VIRTIO_VQ_STATE_UNKNOWN = 0, 1861 EFX_VIRTIO_VQ_STATE_INITIALIZED, 1862 EFX_VIRTIO_VQ_STATE_STARTED, 1863 EFX_VIRTIO_VQ_NSTATES 1864 } efx_virtio_vq_state_t; 1865 1866 struct efx_virtio_vq_s { 1867 uint32_t evv_magic; 1868 efx_nic_t *evv_enp; 1869 efx_virtio_vq_state_t evv_state; 1870 uint32_t evv_vi_index; 1871 efx_virtio_vq_type_t evv_type; 1872 uint16_t evv_target_vf; 1873 }; 1874 1875 #endif /* EFSYS_OPT_VIRTIO */ 1876 1877 #ifdef __cplusplus 1878 } 1879 #endif 1880 1881 #endif /* _SYS_EFX_IMPL_H */ 1882