1 /* $NetBSD: dwlpx_pci.c,v 1.21 2021/06/25 03:46:30 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 1997 by Matthew Jacob
5 * NASA AMES Research Center.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice immediately at the beginning of the file, without modification,
13 * this list of conditions, and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
34
35 __KERNEL_RCSID(0, "$NetBSD: dwlpx_pci.c,v 1.21 2021/06/25 03:46:30 thorpej Exp $");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/device.h>
41
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 #include <alpha/tlsb/tlsbreg.h>
45 #include <alpha/pci/dwlpxreg.h>
46 #include <alpha/pci/dwlpxvar.h>
47
48 #define KV(_addr) ((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
49
50 static int dwlpx_bus_maxdevs(void *, int);
51 static pcitag_t dwlpx_make_tag(void *, int, int, int);
52 static void dwlpx_decompose_tag(void *, pcitag_t, int *, int *,
53 int *);
54 static pcireg_t dwlpx_conf_read(void *, pcitag_t, int);
55 static void dwlpx_conf_write(void *, pcitag_t, int, pcireg_t);
56
57 void
dwlpx_pci_init(pci_chipset_tag_t pc,void * v)58 dwlpx_pci_init(pci_chipset_tag_t pc, void *v)
59 {
60 pc->pc_conf_v = v;
61 pc->pc_bus_maxdevs = dwlpx_bus_maxdevs;
62 pc->pc_make_tag = dwlpx_make_tag;
63 pc->pc_decompose_tag = dwlpx_decompose_tag;
64 pc->pc_conf_read = dwlpx_conf_read;
65 pc->pc_conf_write = dwlpx_conf_write;
66 }
67
68 static int
dwlpx_bus_maxdevs(void * cpv,int busno)69 dwlpx_bus_maxdevs(void *cpv, int busno)
70 {
71 return DWLPX_MAXDEV;
72 }
73
74 static pcitag_t
dwlpx_make_tag(void * cpv,int b,int d,int f)75 dwlpx_make_tag(void *cpv, int b, int d, int f)
76 {
77 pcitag_t tag;
78 int hpcdev, pci_idsel;
79
80 pci_idsel = (1 << ((d & 0x3) + 2));
81 hpcdev = d >> 2;
82 tag = (b << 24) | (hpcdev << 22) | (pci_idsel << 16) | (f << 13);
83 return (tag);
84 }
85
86 static void
dwlpx_decompose_tag(void * cpv,pcitag_t tag,int * bp,int * dp,int * fp)87 dwlpx_decompose_tag(void *cpv, pcitag_t tag, int *bp, int *dp, int *fp)
88 {
89
90 if (bp != NULL)
91 *bp = (tag >> 24) & 0xff;
92 if (dp != NULL) {
93 int j, i = (tag >> 18) & 0xf;
94 j = -1;
95 while (i != 0) {
96 j++;
97 i >>= 1;
98 }
99 j += (((tag >> 22) & 3) << 2);
100 *dp = j;
101 }
102 if (fp != NULL)
103 *fp = (tag >> 13) & 0x7;
104 }
105
106 static pcireg_t
dwlpx_conf_read(void * cpv,pcitag_t tag,int offset)107 dwlpx_conf_read(void *cpv, pcitag_t tag, int offset)
108 {
109 struct dwlpx_config *ccp = cpv;
110 struct dwlpx_softc *sc;
111 pcireg_t *dp, data = (pcireg_t) -1;
112 unsigned long paddr;
113 int secondary, i, s = 0;
114 uint32_t rvp;
115
116 if ((unsigned int)offset >= PCI_CONF_SIZE)
117 return (data);
118
119 if (ccp == NULL) {
120 panic("NULL ccp in dwlpx_conf_read");
121 }
122 sc = ccp->cc_sc;
123 secondary = tag >> 24;
124 if (secondary) {
125 tag &= 0x1fffff;
126 tag |= (secondary << 21);
127
128 #if 0
129 printf("read secondary %d reg %x (tag %x)",
130 secondary, offset, tag);
131 #endif
132
133 alpha_pal_draina();
134 s = splhigh();
135 /*
136 * Set up HPCs for type 1 cycles.
137 */
138 for (i = 0; i < sc->dwlpx_nhpc; i++) {
139 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
140 PCIA_CTL_T1CYC;
141 alpha_mb();
142 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
143 alpha_mb();
144 }
145 }
146 paddr = (unsigned long) tag;
147 paddr |= DWLPX_PCI_CONF;
148 paddr |= ((unsigned long) ((offset >> 2) << 7));
149 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34);
150 paddr |= (((u_long) sc->dwlpx_node - 4) << 36);
151 paddr |= (1LL << 39);
152 paddr |= (3LL << 3); /* 32 Bit PCI byte enables */
153
154 dp = (pcireg_t *)KV(paddr);
155 if (badaddr(dp, sizeof (*dp)) == 0) {
156 data = *dp;
157 }
158 if (secondary) {
159 alpha_pal_draina();
160 for (i = 0; i < sc->dwlpx_nhpc; i++) {
161 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
162 ~PCIA_CTL_T1CYC;
163 alpha_mb();
164 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
165 alpha_mb();
166 }
167 (void) splx(s);
168 #if 0
169 printf("=%x\n", data);
170 #endif
171 }
172 return (data);
173 }
174
175 static void
dwlpx_conf_write(void * cpv,pcitag_t tag,int offset,pcireg_t data)176 dwlpx_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
177 {
178 struct dwlpx_config *ccp = cpv;
179 struct dwlpx_softc *sc;
180 pcireg_t *dp;
181 unsigned long paddr;
182 int secondary, i, s = 0;
183 uint32_t rvp;
184
185 if ((unsigned int)offset >= PCI_CONF_SIZE)
186 return;
187
188 if (ccp == NULL) {
189 panic("NULL ccp in dwlpx_conf_write");
190 }
191 sc = ccp->cc_sc;
192 secondary = tag >> 24;
193 if (secondary) {
194 tag &= 0x1fffff;
195 tag |= (secondary << 21);
196 #if 0
197 printf("write secondary %d reg %x (tag %x) with %x\n",
198 secondary, offset, tag, data);
199 #endif
200
201 alpha_pal_draina();
202 s = splhigh();
203 /*
204 * Set up HPCs for type 1 cycles.
205 */
206 for (i = 0; i < sc->dwlpx_nhpc; i++) {
207 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) |
208 PCIA_CTL_T1CYC;
209 alpha_mb();
210 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
211 alpha_mb();
212 }
213 }
214 paddr = (unsigned long) tag;
215 paddr |= DWLPX_PCI_CONF;
216 paddr |= ((unsigned long) ((offset >> 2) << 7));
217 paddr |= (((unsigned long) sc->dwlpx_hosenum) << 34);
218 paddr |= (((u_long) sc->dwlpx_node - 4) << 36);
219 paddr |= (1LL << 39);
220 paddr |= (3LL << 3); /* 32 bit PCI byte enables */
221
222 dp = (pcireg_t *)KV(paddr);
223 *dp = data;
224 alpha_mb();
225 if (secondary) {
226 alpha_pal_draina();
227 for (i = 0; i < sc->dwlpx_nhpc; i++) {
228 rvp = REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) &
229 ~PCIA_CTL_T1CYC;
230 alpha_mb();
231 REGVAL(PCIA_CTL(i) + ccp->cc_sysbase) = rvp;
232 alpha_mb();
233 }
234 (void) splx(s);
235 }
236 }
237