1 /* $NetBSD: exynos3250.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * Author: Tomasz Figa <t.figa@samsung.com> 7 * 8 * Device Tree binding constants for Samsung Exynos3250 clock controllers. 9 */ 10 11 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 12 #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H 13 14 /* 15 * Let each exported clock get a unique index, which is used on DT-enabled 16 * platforms to lookup the clock from a clock specifier. These indices are 17 * therefore considered an ABI and so must not be changed. This implies 18 * that new clocks should be added either in free spaces between clock groups 19 * or at the end. 20 */ 21 22 23 /* 24 * Main CMU 25 */ 26 27 #define CLK_OSCSEL 1 28 #define CLK_FIN_PLL 2 29 #define CLK_FOUT_APLL 3 30 #define CLK_FOUT_VPLL 4 31 #define CLK_FOUT_UPLL 5 32 #define CLK_FOUT_MPLL 6 33 #define CLK_ARM_CLK 7 34 35 /* Muxes */ 36 #define CLK_MOUT_MPLL_USER_L 16 37 #define CLK_MOUT_GDL 17 38 #define CLK_MOUT_MPLL_USER_R 18 39 #define CLK_MOUT_GDR 19 40 #define CLK_MOUT_EBI 20 41 #define CLK_MOUT_ACLK_200 21 42 #define CLK_MOUT_ACLK_160 22 43 #define CLK_MOUT_ACLK_100 23 44 #define CLK_MOUT_ACLK_266_1 24 45 #define CLK_MOUT_ACLK_266_0 25 46 #define CLK_MOUT_ACLK_266 26 47 #define CLK_MOUT_VPLL 27 48 #define CLK_MOUT_EPLL_USER 28 49 #define CLK_MOUT_EBI_1 29 50 #define CLK_MOUT_UPLL 30 51 #define CLK_MOUT_ACLK_400_MCUISP_SUB 31 52 #define CLK_MOUT_MPLL 32 53 #define CLK_MOUT_ACLK_400_MCUISP 33 54 #define CLK_MOUT_VPLLSRC 34 55 #define CLK_MOUT_CAM1 35 56 #define CLK_MOUT_CAM_BLK 36 57 #define CLK_MOUT_MFC 37 58 #define CLK_MOUT_MFC_1 38 59 #define CLK_MOUT_MFC_0 39 60 #define CLK_MOUT_G3D 40 61 #define CLK_MOUT_G3D_1 41 62 #define CLK_MOUT_G3D_0 42 63 #define CLK_MOUT_MIPI0 43 64 #define CLK_MOUT_FIMD0 44 65 #define CLK_MOUT_UART_ISP 45 66 #define CLK_MOUT_SPI1_ISP 46 67 #define CLK_MOUT_SPI0_ISP 47 68 #define CLK_MOUT_TSADC 48 69 #define CLK_MOUT_MMC1 49 70 #define CLK_MOUT_MMC0 50 71 #define CLK_MOUT_UART1 51 72 #define CLK_MOUT_UART0 52 73 #define CLK_MOUT_SPI1 53 74 #define CLK_MOUT_SPI0 54 75 #define CLK_MOUT_AUDIO 55 76 #define CLK_MOUT_MPLL_USER_C 56 77 #define CLK_MOUT_HPM 57 78 #define CLK_MOUT_CORE 58 79 #define CLK_MOUT_APLL 59 80 #define CLK_MOUT_ACLK_266_SUB 60 81 #define CLK_MOUT_UART2 61 82 #define CLK_MOUT_MMC2 62 83 84 /* Dividers */ 85 #define CLK_DIV_GPL 64 86 #define CLK_DIV_GDL 65 87 #define CLK_DIV_GPR 66 88 #define CLK_DIV_GDR 67 89 #define CLK_DIV_MPLL_PRE 68 90 #define CLK_DIV_ACLK_400_MCUISP 69 91 #define CLK_DIV_EBI 70 92 #define CLK_DIV_ACLK_200 71 93 #define CLK_DIV_ACLK_160 72 94 #define CLK_DIV_ACLK_100 73 95 #define CLK_DIV_ACLK_266 74 96 #define CLK_DIV_CAM1 75 97 #define CLK_DIV_CAM_BLK 76 98 #define CLK_DIV_MFC 77 99 #define CLK_DIV_G3D 78 100 #define CLK_DIV_MIPI0_PRE 79 101 #define CLK_DIV_MIPI0 80 102 #define CLK_DIV_FIMD0 81 103 #define CLK_DIV_UART_ISP 82 104 #define CLK_DIV_SPI1_ISP_PRE 83 105 #define CLK_DIV_SPI1_ISP 84 106 #define CLK_DIV_SPI0_ISP_PRE 85 107 #define CLK_DIV_SPI0_ISP 86 108 #define CLK_DIV_TSADC_PRE 87 109 #define CLK_DIV_TSADC 88 110 #define CLK_DIV_MMC1_PRE 89 111 #define CLK_DIV_MMC1 90 112 #define CLK_DIV_MMC0_PRE 91 113 #define CLK_DIV_MMC0 92 114 #define CLK_DIV_UART1 93 115 #define CLK_DIV_UART0 94 116 #define CLK_DIV_SPI1_PRE 95 117 #define CLK_DIV_SPI1 96 118 #define CLK_DIV_SPI0_PRE 97 119 #define CLK_DIV_SPI0 98 120 #define CLK_DIV_PCM 99 121 #define CLK_DIV_AUDIO 100 122 #define CLK_DIV_I2S 101 123 #define CLK_DIV_CORE2 102 124 #define CLK_DIV_APLL 103 125 #define CLK_DIV_PCLK_DBG 104 126 #define CLK_DIV_ATB 105 127 #define CLK_DIV_COREM 106 128 #define CLK_DIV_CORE 107 129 #define CLK_DIV_HPM 108 130 #define CLK_DIV_COPY 109 131 #define CLK_DIV_UART2 110 132 #define CLK_DIV_MMC2_PRE 111 133 #define CLK_DIV_MMC2 112 134 135 /* Gates */ 136 #define CLK_ASYNC_G3D 128 137 #define CLK_ASYNC_MFCL 129 138 #define CLK_PPMULEFT 130 139 #define CLK_GPIO_LEFT 131 140 #define CLK_ASYNC_ISPMX 132 141 #define CLK_ASYNC_FSYSD 133 142 #define CLK_ASYNC_LCD0X 134 143 #define CLK_ASYNC_CAMX 135 144 #define CLK_PPMURIGHT 136 145 #define CLK_GPIO_RIGHT 137 146 #define CLK_MONOCNT 138 147 #define CLK_TZPC6 139 148 #define CLK_PROVISIONKEY1 140 149 #define CLK_PROVISIONKEY0 141 150 #define CLK_CMU_ISPPART 142 151 #define CLK_TMU_APBIF 143 152 #define CLK_KEYIF 144 153 #define CLK_RTC 145 154 #define CLK_WDT 146 155 #define CLK_MCT 147 156 #define CLK_SECKEY 148 157 #define CLK_TZPC5 149 158 #define CLK_TZPC4 150 159 #define CLK_TZPC3 151 160 #define CLK_TZPC2 152 161 #define CLK_TZPC1 153 162 #define CLK_TZPC0 154 163 #define CLK_CMU_COREPART 155 164 #define CLK_CMU_TOPPART 156 165 #define CLK_PMU_APBIF 157 166 #define CLK_SYSREG 158 167 #define CLK_CHIP_ID 159 168 #define CLK_QEJPEG 160 169 #define CLK_PIXELASYNCM1 161 170 #define CLK_PIXELASYNCM0 162 171 #define CLK_PPMUCAMIF 163 172 #define CLK_QEM2MSCALER 164 173 #define CLK_QEGSCALER1 165 174 #define CLK_QEGSCALER0 166 175 #define CLK_SMMUJPEG 167 176 #define CLK_SMMUM2M2SCALER 168 177 #define CLK_SMMUGSCALER1 169 178 #define CLK_SMMUGSCALER0 170 179 #define CLK_JPEG 171 180 #define CLK_M2MSCALER 172 181 #define CLK_GSCALER1 173 182 #define CLK_GSCALER0 174 183 #define CLK_QEMFC 175 184 #define CLK_PPMUMFC_L 176 185 #define CLK_SMMUMFC_L 177 186 #define CLK_MFC 178 187 #define CLK_SMMUG3D 179 188 #define CLK_QEG3D 180 189 #define CLK_PPMUG3D 181 190 #define CLK_G3D 182 191 #define CLK_QE_CH1_LCD 183 192 #define CLK_QE_CH0_LCD 184 193 #define CLK_PPMULCD0 185 194 #define CLK_SMMUFIMD0 186 195 #define CLK_DSIM0 187 196 #define CLK_FIMD0 188 197 #define CLK_CAM1 189 198 #define CLK_UART_ISP_TOP 190 199 #define CLK_SPI1_ISP_TOP 191 200 #define CLK_SPI0_ISP_TOP 192 201 #define CLK_TSADC 193 202 #define CLK_PPMUFILE 194 203 #define CLK_USBOTG 195 204 #define CLK_USBHOST 196 205 #define CLK_SROMC 197 206 #define CLK_SDMMC1 198 207 #define CLK_SDMMC0 199 208 #define CLK_PDMA1 200 209 #define CLK_PDMA0 201 210 #define CLK_PWM 202 211 #define CLK_PCM 203 212 #define CLK_I2S 204 213 #define CLK_SPI1 205 214 #define CLK_SPI0 206 215 #define CLK_I2C7 207 216 #define CLK_I2C6 208 217 #define CLK_I2C5 209 218 #define CLK_I2C4 210 219 #define CLK_I2C3 211 220 #define CLK_I2C2 212 221 #define CLK_I2C1 213 222 #define CLK_I2C0 214 223 #define CLK_UART1 215 224 #define CLK_UART0 216 225 #define CLK_BLOCK_LCD 217 226 #define CLK_BLOCK_G3D 218 227 #define CLK_BLOCK_MFC 219 228 #define CLK_BLOCK_CAM 220 229 #define CLK_SMIES 221 230 #define CLK_UART2 222 231 #define CLK_SDMMC2 223 232 233 /* Special clocks */ 234 #define CLK_SCLK_JPEG 224 235 #define CLK_SCLK_M2MSCALER 225 236 #define CLK_SCLK_GSCALER1 226 237 #define CLK_SCLK_GSCALER0 227 238 #define CLK_SCLK_MFC 228 239 #define CLK_SCLK_G3D 229 240 #define CLK_SCLK_MIPIDPHY2L 230 241 #define CLK_SCLK_MIPI0 231 242 #define CLK_SCLK_FIMD0 232 243 #define CLK_SCLK_CAM1 233 244 #define CLK_SCLK_UART_ISP 234 245 #define CLK_SCLK_SPI1_ISP 235 246 #define CLK_SCLK_SPI0_ISP 236 247 #define CLK_SCLK_UPLL 237 248 #define CLK_SCLK_TSADC 238 249 #define CLK_SCLK_EBI 239 250 #define CLK_SCLK_MMC1 240 251 #define CLK_SCLK_MMC0 241 252 #define CLK_SCLK_I2S 242 253 #define CLK_SCLK_PCM 243 254 #define CLK_SCLK_SPI1 244 255 #define CLK_SCLK_SPI0 245 256 #define CLK_SCLK_UART1 246 257 #define CLK_SCLK_UART0 247 258 #define CLK_SCLK_UART2 248 259 #define CLK_SCLK_MMC2 249 260 261 /* 262 * Total number of clocks of main CMU. 263 * NOTE: Must be equal to last clock ID increased by one. 264 */ 265 #define CLK_NR_CLKS 250 266 267 /* 268 * CMU DMC 269 */ 270 271 #define CLK_FOUT_BPLL 1 272 #define CLK_FOUT_EPLL 2 273 274 /* Muxes */ 275 #define CLK_MOUT_MPLL_MIF 8 276 #define CLK_MOUT_BPLL 9 277 #define CLK_MOUT_DPHY 10 278 #define CLK_MOUT_DMC_BUS 11 279 #define CLK_MOUT_EPLL 12 280 281 /* Dividers */ 282 #define CLK_DIV_DMC 16 283 #define CLK_DIV_DPHY 17 284 #define CLK_DIV_DMC_PRE 18 285 #define CLK_DIV_DMCP 19 286 #define CLK_DIV_DMCD 20 287 288 /* 289 * Total number of clocks of main CMU. 290 * NOTE: Must be equal to last clock ID increased by one. 291 */ 292 #define NR_CLKS_DMC 21 293 294 /* 295 * CMU ISP 296 */ 297 298 /* Dividers */ 299 300 #define CLK_DIV_ISP1 1 301 #define CLK_DIV_ISP0 2 302 #define CLK_DIV_MCUISP1 3 303 #define CLK_DIV_MCUISP0 4 304 #define CLK_DIV_MPWM 5 305 306 /* Gates */ 307 308 #define CLK_UART_ISP 8 309 #define CLK_WDT_ISP 9 310 #define CLK_PWM_ISP 10 311 #define CLK_I2C1_ISP 11 312 #define CLK_I2C0_ISP 12 313 #define CLK_MPWM_ISP 13 314 #define CLK_MCUCTL_ISP 14 315 #define CLK_PPMUISPX 15 316 #define CLK_PPMUISPMX 16 317 #define CLK_QE_LITE1 17 318 #define CLK_QE_LITE0 18 319 #define CLK_QE_FD 19 320 #define CLK_QE_DRC 20 321 #define CLK_QE_ISP 21 322 #define CLK_CSIS1 22 323 #define CLK_SMMU_LITE1 23 324 #define CLK_SMMU_LITE0 24 325 #define CLK_SMMU_FD 25 326 #define CLK_SMMU_DRC 26 327 #define CLK_SMMU_ISP 27 328 #define CLK_GICISP 28 329 #define CLK_CSIS0 29 330 #define CLK_MCUISP 30 331 #define CLK_LITE1 31 332 #define CLK_LITE0 32 333 #define CLK_FD 33 334 #define CLK_DRC 34 335 #define CLK_ISP 35 336 #define CLK_QE_ISPCX 36 337 #define CLK_QE_SCALERP 37 338 #define CLK_QE_SCALERC 38 339 #define CLK_SMMU_SCALERP 39 340 #define CLK_SMMU_SCALERC 40 341 #define CLK_SCALERP 41 342 #define CLK_SCALERC 42 343 #define CLK_SPI1_ISP 43 344 #define CLK_SPI0_ISP 44 345 #define CLK_SMMU_ISPCX 45 346 #define CLK_ASYNCAXIM 46 347 #define CLK_SCLK_MPWM_ISP 47 348 349 /* 350 * Total number of clocks of CMU_ISP. 351 * NOTE: Must be equal to last clock ID increased by one. 352 */ 353 #define NR_CLKS_ISP 48 354 355 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ 356