1 /* $NetBSD: esp_podule.c,v 1.1 2013/07/11 13:44:50 kiyohara Exp $ */
2 /*
3 * Copyright (c) 2013 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: esp_podule.c,v 1.1 2013/07/11 13:44:50 kiyohara Exp $");
29
30 #include <sys/param.h>
31 #include <sys/buf.h>
32 #include <sys/bus.h>
33 #include <sys/device.h>
34
35 #include <dev/scsipi/scsi_all.h>
36 #include <dev/scsipi/scsipi_all.h>
37 #include <dev/scsipi/scsiconf.h>
38
39 #include <dev/ic/ncr53c9xreg.h>
40 #include <dev/ic/ncr53c9xvar.h>
41
42 #include <dev/podulebus/podulebus.h>
43 #include <dev/podulebus/podules.h>
44
45 struct esp_podule_softc {
46 struct ncr53c9x_softc sc_ncr53c9x;
47
48 bus_space_tag_t sc_iot;
49 bus_space_handle_t sc_ioh;
50
51 struct ncr53c9x_glue sc_esp_glue;
52
53 int sc_active; /* Pseudo-DMA state vars */
54 int sc_tc;
55 int sc_datain;
56 size_t sc_dmasize;
57 size_t sc_dmatrans;
58 uint8_t **sc_dmaaddr;
59 size_t *sc_dmalen;
60 };
61
62 static int esp_podule_match(device_t, cfdata_t, void *);
63 static void esp_podule_attach(device_t, device_t, void *);
64
65 static int esp_podule_dma_isintr(struct ncr53c9x_softc *);
66 static void esp_podule_dma_reset(struct ncr53c9x_softc *);
67 static int esp_podule_dma_intr(struct ncr53c9x_softc *);
68 static int esp_podule_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *,
69 int, size_t *);
70 static void esp_podule_dma_go(struct ncr53c9x_softc *);
71 static void esp_podule_dma_stop(struct ncr53c9x_softc *);
72 static int esp_podule_dma_isactive(struct ncr53c9x_softc *);
73
74 static uint8_t castle_read_reg(struct ncr53c9x_softc *, int);
75 static void castle_write_reg(struct ncr53c9x_softc *, int, uint8_t);
76
77 CFATTACH_DECL_NEW(esp_podule, sizeof(struct esp_podule_softc),
78 esp_podule_match, esp_podule_attach, NULL, NULL);
79
80 static struct ncr53c9x_glue esp_podule_glue = {
81 NULL,
82 NULL,
83
84 esp_podule_dma_isintr,
85 esp_podule_dma_reset,
86 esp_podule_dma_intr,
87 esp_podule_dma_setup,
88 esp_podule_dma_go,
89 esp_podule_dma_stop,
90 esp_podule_dma_isactive,
91 NULL
92 };
93
94 #define PODULE_DEVICE(m, p, read, write) \
95 { MANUFACTURER_ ## m, PODULE_ ## m ## _ ## p, read, write }
96 static struct {
97 int manufacturer;
98 int product;
99 uint8_t (*read_reg)(struct ncr53c9x_softc *, int);
100 void (*write_reg)(struct ncr53c9x_softc *, int, uint8_t);
101 } devices[] = {
102 PODULE_DEVICE(CASTLE, SCSI16, castle_read_reg, castle_write_reg),
103 };
104
105
106 static int
esp_podule_match(device_t parent,cfdata_t cf,void * aux)107 esp_podule_match(device_t parent, cfdata_t cf, void *aux)
108 {
109 struct podulebus_attach_args *pa = aux;
110 int i;
111
112 for (i = 0; i < __arraycount(devices); i++)
113 if (pa->pa_manufacturer == devices[i].manufacturer &&
114 pa->pa_product == devices[i].product)
115 return 1;
116
117 return 0;
118 }
119
120 static void
esp_podule_attach(device_t parent,device_t self,void * aux)121 esp_podule_attach(device_t parent, device_t self, void *aux)
122 {
123 struct esp_podule_softc *esc = device_private(self);
124 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
125 struct podulebus_attach_args *pa = aux;
126 int i;
127
128 for (i = 0; i < __arraycount(devices); i++)
129 if (pa->pa_manufacturer == devices[i].manufacturer &&
130 pa->pa_product == devices[i].product)
131 break;
132 if (i == __arraycount(devices)) {
133 aprint_error(": lost manufacturer 0x%04x, product 0x%04x\n",
134 pa->pa_manufacturer, pa->pa_product);
135 return;
136 }
137
138 sc->sc_dev = self;
139 esc->sc_esp_glue = esp_podule_glue;
140 esc->sc_esp_glue.gl_read_reg = devices[i].read_reg;
141 esc->sc_esp_glue.gl_write_reg = devices[i].write_reg;
142 sc->sc_glue = &esc->sc_esp_glue;
143
144 esc->sc_iot = pa->pa_slow_t;
145 bus_space_map(esc->sc_iot, pa->pa_slow_base, 0x4000, 0, &esc->sc_ioh);
146 sc->sc_freq = 2; /* XXXX ??? */
147
148 /* Get current ID */
149 sc->sc_id = NCR_READ_REG(sc, NCR_CFG1) & NCRCFG1_BUSID;
150
151 sc->sc_cfg1 = sc->sc_id;
152 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_DREQ | NCRCFG2_FE;
153 sc->sc_rev = NCR_VARIANT_NCR53C96; /* XXXX ??? */
154
155 sc->sc_minsync = 1000 / sc->sc_freq;
156
157 sc->sc_maxxfer = 64 * 1024;
158
159 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
160 device_xname(self), "intr");
161 podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr53c9x_intr, sc,
162 &sc->sc_intrcnt);
163
164 sc->sc_adapter.adapt_minphys = minphys;
165 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
166 ncr53c9x_attach(sc);
167 }
168
169
170 static int
esp_podule_dma_isintr(struct ncr53c9x_softc * sc)171 esp_podule_dma_isintr(struct ncr53c9x_softc *sc)
172 {
173
174 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT;
175 }
176
177 static void
esp_podule_dma_reset(struct ncr53c9x_softc * sc)178 esp_podule_dma_reset(struct ncr53c9x_softc *sc)
179 {
180 struct esp_podule_softc *esc = (struct esp_podule_softc *)sc;
181
182 esc->sc_active = 0;
183 esc->sc_tc = 0;
184 }
185
186 static int
esp_podule_dma_intr(struct ncr53c9x_softc * sc)187 esp_podule_dma_intr(struct ncr53c9x_softc *sc)
188 {
189 struct esp_podule_softc *esc = (struct esp_podule_softc *)sc;
190 uint8_t *p;
191 u_int espphase, espstat, espintr;
192 int cnt;
193
194 if (esc->sc_active == 0) {
195 printf("%s: dma_intr--inactive DMA\n",
196 device_xname(sc->sc_dev));
197 return -1;
198 }
199
200 if ((sc->sc_espintr & NCRINTR_BS) == 0) {
201 esc->sc_active = 0;
202 return 0;
203 }
204
205 cnt = *esc->sc_dmalen;
206 if (*esc->sc_dmalen == 0) {
207 printf("%s: data interrupt, but no count left\n",
208 device_xname(sc->sc_dev));
209 }
210
211 p = *esc->sc_dmaaddr;
212 espphase = sc->sc_phase;
213 espstat = (u_int)sc->sc_espstat;
214 espintr = (u_int)sc->sc_espintr;
215 do {
216 if (esc->sc_datain) {
217 *p++ = NCR_READ_REG(sc, NCR_FIFO);
218 cnt--;
219 if (espphase == DATA_IN_PHASE)
220 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS);
221 else
222 esc->sc_active = 0;
223 } else {
224 if ((espphase == DATA_OUT_PHASE) ||
225 (espphase == MESSAGE_OUT_PHASE)) {
226 NCR_WRITE_REG(sc, NCR_FIFO, *p++);
227 cnt--;
228 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS);
229 } else
230 esc->sc_active = 0;
231 }
232
233 if (esc->sc_active) {
234 while ((NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) == 0)
235 ;
236 espstat = NCR_READ_REG(sc, NCR_STAT);
237 espintr = NCR_READ_REG(sc, NCR_INTR);
238 espphase = (espintr & NCRINTR_DIS) ?
239 /* Disconnected */ BUSFREE_PHASE :
240 espstat & PHASE_MASK;
241 }
242 } while (esc->sc_active && espintr);
243 sc->sc_phase = espphase;
244 sc->sc_espstat = (uint8_t)espstat;
245 sc->sc_espintr = (uint8_t)espintr;
246 *esc->sc_dmaaddr = p;
247 *esc->sc_dmalen = cnt;
248
249 if (*esc->sc_dmalen == 0)
250 esc->sc_tc = NCRSTAT_TC;
251 sc->sc_espstat |= esc->sc_tc;
252
253 return 0;
254 }
255
256 static int
esp_podule_dma_setup(struct ncr53c9x_softc * sc,uint8_t ** addr,size_t * len,int datain,size_t * dmasize)257 esp_podule_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
258 int datain, size_t *dmasize)
259 {
260 struct esp_podule_softc *esc = (struct esp_podule_softc *)sc;
261
262 esc->sc_dmaaddr = addr;
263 esc->sc_dmalen = len;
264 esc->sc_datain = datain;
265 esc->sc_dmasize = *dmasize;
266 esc->sc_tc = 0;
267
268 return 0;
269 }
270
271 static void
esp_podule_dma_go(struct ncr53c9x_softc * sc)272 esp_podule_dma_go(struct ncr53c9x_softc *sc)
273 {
274 struct esp_podule_softc *esc = (struct esp_podule_softc *)sc;
275
276 if (esc->sc_datain == 0) {
277 NCR_WRITE_REG(sc, NCR_FIFO, **esc->sc_dmaaddr);
278 (*esc->sc_dmalen)--;
279 (*esc->sc_dmaaddr)++;
280 }
281
282 esc->sc_active = 1;
283 }
284
285 static void
esp_podule_dma_stop(struct ncr53c9x_softc * sc)286 esp_podule_dma_stop(struct ncr53c9x_softc *sc)
287 {
288 /* Nothing */
289 }
290
291 static int
esp_podule_dma_isactive(struct ncr53c9x_softc * sc)292 esp_podule_dma_isactive(struct ncr53c9x_softc *sc)
293 {
294 struct esp_podule_softc *esc = (struct esp_podule_softc *)sc;
295
296 return esc->sc_active;
297 }
298
299 /*
300 * Functions for access to Castle SCSI registers.
301 */
302 #define CASTLE_ESP_OFFSET 0xf00
303 #define CASTLE_ESP_READ(sc, r) \
304 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, CASTLE_ESP_OFFSET + ((r) << 2))
305 #define CASTLE_ESP_WRITE(sc, r, v) \
306 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, \
307 CASTLE_ESP_OFFSET + ((r) << 2), (v))
308
309 static uint8_t
castle_read_reg(struct ncr53c9x_softc * sc,int reg)310 castle_read_reg(struct ncr53c9x_softc *sc, int reg)
311 {
312 struct esp_podule_softc *esc = (struct esp_podule_softc *)sc;
313 uint8_t val;
314
315 val = CASTLE_ESP_READ(esc, reg);
316 return val;
317 }
318
319 static void
castle_write_reg(struct ncr53c9x_softc * sc,int reg,uint8_t val)320 castle_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
321 {
322 struct esp_podule_softc *esc = (struct esp_podule_softc *)sc;
323
324 if (reg == NCR_CMD && val == (NCRCMD_TRANS | NCRCMD_DMA))
325 val &= ~NCRCMD_DMA; /* DMA not support */
326 CASTLE_ESP_WRITE(esc, reg, val);
327 }
328