1 /* $NetBSD: xhci_pci.c,v 1.33 2023/01/24 08:45:47 mlelstv Exp $ */
2 /* OpenBSD: xhci_pci.c,v 1.4 2014/07/12 17:38:51 yuo Exp */
3
4 /*
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Lennart Augustsson (lennart@augustsson.net) at
10 * Carlstedt Research & Technology.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: xhci_pci.c,v 1.33 2023/01/24 08:45:47 mlelstv Exp $");
36
37 #ifdef _KERNEL_OPT
38 #include "opt_xhci_pci.h"
39 #endif
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/device.h>
45 #include <sys/proc.h>
46 #include <sys/queue.h>
47
48 #include <sys/bus.h>
49
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcidevs.h>
52
53 #include <dev/usb/usb.h>
54 #include <dev/usb/usbdi.h>
55 #include <dev/usb/usbdivar.h>
56 #include <dev/usb/usb_mem.h>
57
58 #include <dev/usb/xhcireg.h>
59 #include <dev/usb/xhcivar.h>
60
61 struct xhci_pci_softc {
62 struct xhci_softc sc_xhci;
63 pci_chipset_tag_t sc_pc;
64 pcitag_t sc_tag;
65 void *sc_ih;
66 pci_intr_handle_t *sc_pihp;
67 };
68
69 static int
xhci_pci_match(device_t parent,cfdata_t match,void * aux)70 xhci_pci_match(device_t parent, cfdata_t match, void *aux)
71 {
72 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
73
74 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
75 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
76 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_XHCI)
77 return 1;
78
79 return 0;
80 }
81
82 static int
xhci_pci_port_route(struct xhci_pci_softc * psc)83 xhci_pci_port_route(struct xhci_pci_softc *psc)
84 {
85 struct xhci_softc * const sc = &psc->sc_xhci;
86
87 pcireg_t val;
88
89 /*
90 * Check USB3 Port Routing Mask register that indicates the ports
91 * can be changed from OS, and turn on by USB3 Port SS Enable register.
92 */
93 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3PRM);
94 aprint_debug_dev(sc->sc_dev,
95 "USB3PRM / USB3.0 configurable ports: 0x%08x\n", val);
96
97 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB3_PSSEN, val);
98 val = pci_conf_read(psc->sc_pc, psc->sc_tag,PCI_XHCI_INTEL_USB3_PSSEN);
99 aprint_debug_dev(sc->sc_dev,
100 "USB3_PSSEN / Enabled USB3.0 ports under xHCI: 0x%08x\n", val);
101
102 /*
103 * Check USB2 Port Routing Mask register that indicates the USB2.0
104 * ports to be controlled by xHCI HC, and switch them to xHCI HC.
105 */
106 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_USB2PRM);
107 aprint_debug_dev(sc->sc_dev,
108 "XUSB2PRM / USB2.0 ports can switch from EHCI to xHCI:"
109 "0x%08x\n", val);
110 pci_conf_write(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR, val);
111 val = pci_conf_read(psc->sc_pc, psc->sc_tag, PCI_XHCI_INTEL_XUSB2PR);
112 aprint_debug_dev(sc->sc_dev,
113 "XUSB2PR / USB2.0 ports under xHCI: 0x%08x\n", val);
114
115 return 0;
116 }
117
118 static void
xhci_pci_attach(device_t parent,device_t self,void * aux)119 xhci_pci_attach(device_t parent, device_t self, void *aux)
120 {
121 struct xhci_pci_softc * const psc = device_private(self);
122 struct xhci_softc * const sc = &psc->sc_xhci;
123 struct pci_attach_args *const pa = (struct pci_attach_args *)aux;
124 const pci_chipset_tag_t pc = pa->pa_pc;
125 const pcitag_t tag = pa->pa_tag;
126 char const *intrstr;
127 pcireg_t csr, memtype, usbrev;
128 uint32_t hccparams;
129 int counts[PCI_INTR_TYPE_SIZE];
130 char intrbuf[PCI_INTRSTR_LEN];
131 bus_addr_t memaddr;
132 int flags, msixoff;
133 int err;
134
135 sc->sc_dev = self;
136
137 pci_aprint_devinfo(pa, "USB Controller");
138
139 /* Check for quirks */
140 sc->sc_quirks = 0;
141
142 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
143 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) {
144 /*
145 * Enable address decoding for memory range in case BIOS or
146 * UEFI didn't set it.
147 */
148 csr = pci_conf_read(pa->pa_pc, pa->pa_tag,
149 PCI_COMMAND_STATUS_REG);
150 csr |= PCI_COMMAND_MEM_ENABLE;
151 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
152 csr);
153 }
154
155 /* map MMIO registers */
156 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_CBMEM);
157 if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM) {
158 sc->sc_ios = 0;
159 aprint_error_dev(self, "BAR not 64 or 32-bit MMIO\n");
160 return;
161 }
162
163 sc->sc_iot = pa->pa_memt;
164 if (pci_mapreg_info(pa->pa_pc, pa->pa_tag, PCI_CBMEM, memtype,
165 &memaddr, &sc->sc_ios, &flags) != 0) {
166 sc->sc_ios = 0;
167 aprint_error_dev(self, "can't get map info\n");
168 return;
169 }
170
171 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff,
172 NULL)) {
173 pcireg_t msixtbl;
174 uint32_t table_offset;
175 int bir;
176
177 msixtbl = pci_conf_read(pa->pa_pc, pa->pa_tag,
178 msixoff + PCI_MSIX_TBLOFFSET);
179 table_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK;
180 bir = msixtbl & PCI_MSIX_TBLBIR_MASK;
181 /* Shrink map area for MSI-X table */
182 if (bir == PCI_MAPREG_NUM(PCI_CBMEM))
183 sc->sc_ios = table_offset;
184 }
185 if (bus_space_map(sc->sc_iot, memaddr, sc->sc_ios, flags,
186 &sc->sc_ioh)) {
187 sc->sc_ios = 0;
188 aprint_error_dev(self, "can't map mem space\n");
189 return;
190 }
191
192 psc->sc_pc = pc;
193 psc->sc_tag = tag;
194
195 hccparams = bus_space_read_4(sc->sc_iot, sc->sc_ioh, XHCI_HCCPARAMS);
196
197 if (XHCI_HCC_AC64(hccparams) != 0) {
198 aprint_verbose_dev(self, "64-bit DMA");
199 if (pci_dma64_available(pa)) {
200 sc->sc_bus.ub_dmatag = pa->pa_dmat64;
201 aprint_verbose("\n");
202 } else {
203 aprint_verbose(" - limited\n");
204 sc->sc_bus.ub_dmatag = pa->pa_dmat;
205 }
206 } else {
207 aprint_verbose_dev(self, "32-bit DMA\n");
208 sc->sc_bus.ub_dmatag = pa->pa_dmat;
209 }
210
211 /* Enable the device. */
212 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
213 csr | PCI_COMMAND_MASTER_ENABLE);
214
215 for (int i = 0; i < PCI_INTR_TYPE_SIZE; i++) {
216 counts[i] = 1;
217 }
218 #ifdef XHCI_DISABLE_MSI
219 counts[PCI_INTR_TYPE_MSI] = 0;
220 #endif
221 #ifdef XHCI_DISABLE_MSIX
222 counts[PCI_INTR_TYPE_MSIX] = 0;
223 #endif
224
225 /* Allocate and establish the interrupt. */
226 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) {
227 aprint_error_dev(self, "can't allocate handler\n");
228 goto fail;
229 }
230 intrstr = pci_intr_string(pc, psc->sc_pihp[0], intrbuf,
231 sizeof(intrbuf));
232 pci_intr_setattr(pc, &psc->sc_pihp[0], PCI_INTR_MPSAFE, true);
233 psc->sc_ih = pci_intr_establish_xname(pc, psc->sc_pihp[0], IPL_USB,
234 xhci_intr, sc, device_xname(sc->sc_dev));
235 if (psc->sc_ih == NULL) {
236 pci_intr_release(pc, psc->sc_pihp, 1);
237 psc->sc_pihp = NULL;
238 aprint_error_dev(self, "couldn't establish interrupt");
239 if (intrstr != NULL)
240 aprint_error(" at %s", intrstr);
241 aprint_error("\n");
242 goto fail;
243 }
244 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
245
246 usbrev = pci_conf_read(pc, tag, PCI_USBREV) & PCI_USBREV_MASK;
247 switch (usbrev) {
248 case PCI_USBREV_3_0:
249 sc->sc_bus.ub_revision = USBREV_3_0;
250 break;
251 case PCI_USBREV_3_1:
252 sc->sc_bus.ub_revision = USBREV_3_1;
253 break;
254 default:
255 if (usbrev < PCI_USBREV_3_0) {
256 aprint_error_dev(self, "Unknown revision (%02x). Set to 3.0.\n",
257 usbrev);
258 sc->sc_bus.ub_revision = USBREV_3_0;
259 } else {
260 /* Default to the latest revision */
261 aprint_normal_dev(self,
262 "Unknown revision (%02x). Set to 3.1.\n", usbrev);
263 sc->sc_bus.ub_revision = USBREV_3_1;
264 }
265 break;
266 }
267
268 /* Intel chipset requires SuperSpeed enable and USB2 port routing */
269 switch (PCI_VENDOR(pa->pa_id)) {
270 case PCI_VENDOR_INTEL:
271 sc->sc_quirks |= XHCI_QUIRK_INTEL;
272 break;
273 default:
274 break;
275 }
276
277 err = xhci_init(sc);
278 if (err) {
279 aprint_error_dev(self, "init failed, error=%d\n", err);
280 goto fail;
281 }
282
283 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0)
284 xhci_pci_port_route(psc);
285
286 if (!pmf_device_register1(self, xhci_suspend, xhci_resume,
287 xhci_shutdown))
288 aprint_error_dev(self, "couldn't establish power handler\n");
289
290 /* Attach usb buses. */
291 if (sc->sc_usb3nports != 0)
292 sc->sc_child =
293 config_found(self, &sc->sc_bus, usbctlprint, CFARGS_NONE);
294
295 if (sc->sc_usb2nports != 0)
296 sc->sc_child2 =
297 config_found(self, &sc->sc_bus2, usbctlprint, CFARGS_NONE);
298
299 return;
300
301 fail:
302 if (psc->sc_ih != NULL) {
303 pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
304 psc->sc_ih = NULL;
305 }
306 if (psc->sc_pihp != NULL) {
307 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1);
308 psc->sc_pihp = NULL;
309 }
310 if (sc->sc_ios) {
311 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
312 sc->sc_ios = 0;
313 }
314 return;
315 }
316
317 static int
xhci_pci_detach(device_t self,int flags)318 xhci_pci_detach(device_t self, int flags)
319 {
320 struct xhci_pci_softc * const psc = device_private(self);
321 struct xhci_softc * const sc = &psc->sc_xhci;
322 int rv;
323
324 if (sc->sc_ios != 0) {
325 rv = xhci_detach(sc, flags);
326 if (rv)
327 return rv;
328
329 pmf_device_deregister(self);
330
331 xhci_shutdown(self, flags);
332
333 #if 0
334 /* Disable interrupts, so we don't get any spurious ones. */
335 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
336 OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
337 #endif
338 }
339
340 if (psc->sc_ih != NULL) {
341 pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
342 psc->sc_ih = NULL;
343 }
344 if (psc->sc_pihp != NULL) {
345 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1);
346 psc->sc_pihp = NULL;
347 }
348 if (sc->sc_ios) {
349 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios);
350 sc->sc_ios = 0;
351 }
352
353 return 0;
354 }
355
356 CFATTACH_DECL3_NEW(xhci_pci, sizeof(struct xhci_pci_softc),
357 xhci_pci_match, xhci_pci_attach, xhci_pci_detach, xhci_activate, NULL,
358 xhci_childdet, DVF_DETACH_SHUTDOWN);
359