1 /* $NetBSD: qat_c2xxx.c,v 1.2 2022/05/24 08:35:47 knakahara Exp $ */
2
3 /*
4 * Copyright (c) 2019 Internet Initiative Japan, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Copyright(c) 2007-2013 Intel Corporation. All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 *
36 * * Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * * Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in
40 * the documentation and/or other materials provided with the
41 * distribution.
42 * * Neither the name of Intel Corporation nor the names of its
43 * contributors may be used to endorse or promote products derived
44 * from this software without specific prior written permission.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 */
58
59 #include <sys/cdefs.h>
60 __KERNEL_RCSID(0, "$NetBSD: qat_c2xxx.c,v 1.2 2022/05/24 08:35:47 knakahara Exp $");
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
67
68 #include "qatreg.h"
69 #include "qat_hw15reg.h"
70 #include "qat_c2xxxreg.h"
71 #include "qatvar.h"
72 #include "qat_hw15var.h"
73
74 static uint32_t
qat_c2xxx_get_accel_mask(struct qat_softc * sc)75 qat_c2xxx_get_accel_mask(struct qat_softc *sc)
76 {
77 pcireg_t fusectl;
78
79 fusectl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, FUSECTL_REG);
80
81 return ((~fusectl) & ACCEL_MASK_C2XXX);
82 }
83
84 static uint32_t
qat_c2xxx_get_ae_mask(struct qat_softc * sc)85 qat_c2xxx_get_ae_mask(struct qat_softc *sc)
86 {
87 pcireg_t fusectl;
88
89 fusectl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, FUSECTL_REG);
90 if (fusectl & (
91 FUSECTL_C2XXX_PKE_DISABLE |
92 FUSECTL_C2XXX_ATH_DISABLE |
93 FUSECTL_C2XXX_CPH_DISABLE)) {
94 return 0;
95 } else {
96 return ((~fusectl) & AE_MASK_C2XXX);
97 }
98 }
99
100 static enum qat_sku
qat_c2xxx_get_sku(struct qat_softc * sc)101 qat_c2xxx_get_sku(struct qat_softc *sc)
102 {
103 pcireg_t fusectl;
104
105 fusectl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, FUSECTL_REG);
106
107 switch (sc->sc_ae_num) {
108 case 1:
109 if (fusectl & FUSECTL_C2XXX_LOW_SKU)
110 return QAT_SKU_3;
111 else if (fusectl & FUSECTL_C2XXX_MID_SKU)
112 return QAT_SKU_2;
113 break;
114 case MAX_AE_C2XXX:
115 return QAT_SKU_1;
116 }
117
118 return QAT_SKU_UNKNOWN;
119 }
120
121 static uint32_t
qat_c2xxx_get_accel_cap(struct qat_softc * sc)122 qat_c2xxx_get_accel_cap(struct qat_softc *sc)
123 {
124 return QAT_ACCEL_CAP_CRYPTO_SYMMETRIC |
125 QAT_ACCEL_CAP_CRYPTO_ASYMMETRIC |
126 QAT_ACCEL_CAP_CIPHER |
127 QAT_ACCEL_CAP_AUTHENTICATION;
128 }
129
130 static const char *
qat_c2xxx_get_fw_uof_name(struct qat_softc * sc)131 qat_c2xxx_get_fw_uof_name(struct qat_softc *sc)
132 {
133 if (sc->sc_rev < QAT_REVID_C2XXX_B0)
134 return AE_FW_UOF_NAME_C2XXX_A0;
135
136 /* QAT_REVID_C2XXX_B0 and QAT_REVID_C2XXX_C0 */
137 return AE_FW_UOF_NAME_C2XXX_B0;
138 }
139
140 static void
qat_c2xxx_enable_intr(struct qat_softc * sc)141 qat_c2xxx_enable_intr(struct qat_softc *sc)
142 {
143
144 qat_misc_write_4(sc, EP_SMIA_C2XXX, EP_SMIA_MASK_C2XXX);
145 }
146
147 static void
qat_c2xxx_init_etr_intr(struct qat_softc * sc,int bank)148 qat_c2xxx_init_etr_intr(struct qat_softc *sc, int bank)
149 {
150 /*
151 * For now, all rings within the bank are setup such that the generation
152 * of flag interrupts will be triggered when ring leaves the empty
153 * state. Note that in order for the ring interrupt to generate an IRQ
154 * the interrupt must also be enabled for the ring.
155 */
156 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL,
157 ETR_INT_SRCSEL_MASK_0_C2XXX);
158 qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL_2,
159 ETR_INT_SRCSEL_MASK_X_C2XXX);
160 }
161
162 const struct qat_hw qat_hw_c2xxx = {
163 .qhw_sram_bar_id = BAR_SRAM_ID_C2XXX,
164 .qhw_misc_bar_id = BAR_PMISC_ID_C2XXX,
165 .qhw_etr_bar_id = BAR_ETR_ID_C2XXX,
166 .qhw_cap_global_offset = CAP_GLOBAL_OFFSET_C2XXX,
167 .qhw_ae_offset = AE_OFFSET_C2XXX,
168 .qhw_ae_local_offset = AE_LOCAL_OFFSET_C2XXX,
169 .qhw_etr_bundle_size = ETR_BUNDLE_SIZE_C2XXX,
170 .qhw_num_banks = ETR_MAX_BANKS_C2XXX,
171 .qhw_num_ap_banks = ETR_MAX_AP_BANKS_C2XXX,
172 .qhw_num_rings_per_bank = ETR_MAX_RINGS_PER_BANK,
173 .qhw_num_accel = MAX_ACCEL_C2XXX,
174 #if 0
175 .qhw_num_engines = MAX_AE_C2XXX,
176 #else
177 /*
178 * Workaround:
179 * C2xxx qat has two engines, however it doesn't have arbiter which
180 * C3xxx qat has. So, we don't use secondary engine for C2xxx qat.
181 */
182 .qhw_num_engines = 1,
183 #endif
184 .qhw_tx_rx_gap = ETR_TX_RX_GAP_C2XXX,
185 .qhw_tx_rings_mask = ETR_TX_RINGS_MASK_C2XXX,
186 .qhw_msix_ae_vec_gap = MSIX_AE_VEC_GAP_C2XXX,
187 .qhw_fw_auth = false,
188 .qhw_fw_req_size = FW_REQ_DEFAULT_SZ_HW15,
189 .qhw_fw_resp_size = FW_REQ_DEFAULT_SZ_HW15,
190 .qhw_ring_asym_tx = 2,
191 .qhw_ring_asym_rx = 3,
192 .qhw_ring_sym_tx = 4,
193 .qhw_ring_sym_rx = 5,
194 .qhw_mof_fwname = AE_FW_MOF_NAME_C2XXX,
195 .qhw_mmp_fwname = AE_FW_MMP_NAME_C2XXX,
196 .qhw_prod_type = AE_FW_PROD_TYPE_C2XXX,
197 .qhw_get_accel_mask = qat_c2xxx_get_accel_mask,
198 .qhw_get_ae_mask = qat_c2xxx_get_ae_mask,
199 .qhw_get_sku = qat_c2xxx_get_sku,
200 .qhw_get_accel_cap = qat_c2xxx_get_accel_cap,
201 .qhw_get_fw_uof_name = qat_c2xxx_get_fw_uof_name,
202 .qhw_enable_intr = qat_c2xxx_enable_intr,
203 .qhw_init_etr_intr = qat_c2xxx_init_etr_intr,
204 .qhw_init_admin_comms = qat_adm_ring_init,
205 .qhw_send_admin_init = qat_adm_ring_send_init,
206 .qhw_crypto_setup_desc = qat_hw15_crypto_setup_desc,
207 .qhw_crypto_setup_req_params = qat_hw15_crypto_setup_req_params,
208 .qhw_crypto_opaque_offset =
209 offsetof(struct fw_la_resp, comn_resp.opaque_data),
210 };
211