1 /* $NetBSD: igmareg.h,v 1.1 2014/01/21 14:52:07 mlelstv Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Michael van Elst 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef IGMAREG_H 20 #define IGMAREG_H 21 22 /* North display */ 23 24 #define CPU_VGA_CNTRL 0x41000 25 #define PCH_VGA_CNTRL 0x71400 26 #define VGA_CNTRL_DISABLE (1L << 31) 27 #define VGA_2X_MODE (1L << 29) 28 #define VGA_PIPE_B_SELECT (1L << 29) 29 30 #define PF_WINPOS(i) (0x68070+i*0x800) 31 #define PF_WINPOS_VAL(x,y) ((x) << 16 | (y)) 32 #define PF_WINSZ(i) (0x68074+i*0x800) 33 #define PF_WINSZ_VAL(w,h) ((w) << 16 | (h)) 34 #define PF_WINSZ_GET_WIDTH(r) (((r) >> 16) & 0x1fff) 35 #define PF_WINSZ_GET_HEIGHT(r) (((r) >> 0) & 0xfff) 36 #define PF_CTRL(i) (0x68080+i*0x800) 37 #define PF_CTRL_I965 (0x61230) 38 #define PF_ENABLE (1L << 31) 39 40 #define PIPE_HTOTAL(i) (0x60000+i*0x1000) 41 #define PIPE_HOTAL_VAL(t,a) (((t)-1) << 16 | ((a)-1)) 42 #define PIPE_HTOTAL_GET_TOTAL(r) ((((r) >> 16) & 0x1fff)+1) 43 #define PIPE_HTOTAL_GET_ACTIVE(r) ((((r) >> 0) & 0x1fff)+1) 44 #define PIPE_HBLANK(i) (0x60004+i*0x1000) 45 #define PIPE_HBLANK_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 46 #define PIPE_HSYNC(i) (0x60008+i*0x1000) 47 #define PIPE_HSYNC_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 48 #define PIPE_VTOTAL(i) (0x6000c+i*0x1000) 49 #define PIPE_VTOTAL_VAL(t,a) (((t)-1) << 16 | ((a)-1)) 50 #define PIPE_VTOTAL_GET_TOTAL(r) ((((r) >> 16) & 0xfff)+1) 51 #define PIPE_VTOTAL_GET_ACTIVE(r) ((((r) >> 0) & 0xfff)+1) 52 #define PIPE_VBLANK(i) (0x60010+i*0x1000) 53 #define PIPE_VBLANK_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 54 #define PIPE_VSYNC(i) (0x60014+i*0x1000) 55 #define PIPE_VSYNC_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 56 #define PIPE_SRCSZ(i) (0x6001c+i*0x1000) 57 #define PIPE_SRCSZ_VAL(w,h) (((w)-1) << 16 | ((h)-1)) 58 #define PIPE_VSHIFT(i) (0x60028+i*0x1000) 59 #define PIPE_DATAM1(i) (0x60030+i*0x1000) 60 #define PIPE_DATAM2(i) (0x60034+i*0x1000) 61 #define PIPE_DATAN1(i) (0x60038+i*0x1000) 62 #define PIPE_DATAN2(i) (0x6003c+i*0x1000) 63 #define PIPE_DPLINKM1(i) (0x60040+i*0x1000) 64 #define PIPE_DPLINKM2(i) (0x60044+i*0x1000) 65 #define PIPE_DPLINKN1(i) (0x60048+i*0x1000) 66 #define PIPE_DPLINKN2(i) (0x6004c+i*0x1000) 67 #define PIPE_CONF(i) (0x70080+i*0x1000) 68 #define PIPE_CONF_ENABLE (1L << 31) 69 #define PIPE_CONF_STATE (1L << 30) 70 #define PIPE_CONF_GAMMA8 (0L << 24) 71 #define PIPE_CONF_GAMMA10 (1L << 24) 72 #define PIPE_CONF_GAMMA12 (2L << 24) 73 #define PIPE_CONF_PFPD (0L << 21) 74 #define PIPE_CONF_PFID (1L << 21) 75 #define PIPE_CONF_IFID (3L << 21) 76 #define PIPE_CONF_IFID_DBL (4L << 21) 77 #define PIPE_CONF_PFID_DBL (5L << 21) 78 #define PIPE_CONF_POWERSAVE (1L << 20) 79 #define PIPE_CONF_MSA1 (0L << 18) 80 #define PIPE_CONF_MSA2 (1L << 18) 81 #define PIPE_CONF_MSA3 (2L << 18) 82 #define PIPE_CONF_MSA4 (3L << 18) 83 #define PIPE_CONF_ROT0 (0L << 14) 84 #define PIPE_CONF_ROT90 (1L << 14) 85 #define PIPE_CONF_ROT180 (2L << 14) 86 #define PIPE_CONF_ROT270 (3L << 14) 87 #define PIPE_CONF_CE (1L << 13) 88 #define PIPE_CONF_8BPP (0L << 5) 89 #define PIPE_CONF_6BPP (2L << 5) 90 #define PIPE_CONF_DITHER (4L << 2) 91 #define PIPE_CONF_DITHERST1 (5L << 2) 92 #define PIPE_CONF_DITHERST2 (6L << 2) 93 #define PIPE_CONF_DITHERT (7L << 2) 94 #define CUR_CNTR(i) (0x70080+i*0x1000) 95 #define CUR_BASE(i) (0x70084+i*0x1000) 96 #define PRI_CTRL(i) (0x70180+i*0x1000) 97 #define PRI_CTRL_ENABLE (1L << 31) 98 #define PRI_CTRL_GAMMA (1L << 30) 99 #define PRI_CTRL_IND8 (2L << 26) 100 #define PRI_CTRL_BGR565 (5L << 26) 101 #define PRI_CTRL_BGR (6L << 26) 102 #define PRI_CTRL_RGB10 (8L << 26) 103 #define PRI_CTRL_BGR10 (10L << 26) 104 #define PRI_CTRL_RGBFP (12L << 26) 105 #define PRI_CTRL_RGB (14L << 26) 106 #define PRI_CTRL_PIXFMTMSK (31L << 26) 107 #define PRI_CTRL_CSC (1L << 24) 108 #define PRI_CTRL_ROT180 (1L << 15) 109 #define PRI_CTRL_NOTRICKLE (1L << 14) 110 #define PRI_CTRL_TILED (1L << 10) 111 #define PRI_CTRL_ASYNC (1L << 9) 112 #define PRI_LINOFF(i) (0x70184+i*0x1000) 113 #define PRI_STRIDE(i) (0x70188+i*0x1000) 114 #define PRI_SURF(i) (0x7019c+i*0x1000) 115 #define PRI_TILEOFF(i) (0x701a4+i*0x1000) 116 #define FDI_TX_CTL(i) (0x60100+i*0x1000) 117 118 #define FW_BLC_SELF (0x20e0) 119 #define FW_BLC_SELF_EN (1L << 15) 120 121 /* South display */ 122 123 #define DREF_CTL (0xc6200) 124 #define RAWCLK_FREQ (0xc6204) 125 #define DPLL_SEL (0xc7000) 126 127 #define DAC_CTL (0xe1100) 128 #define HDMI_CTL (0xe1140) 129 #define HDMI_BUF_CTL (0xfd024) 130 #define LVDS_CTL (0xe1180) 131 #define PCH_DP_CTL(i) (0xe4100+i*0x100) 132 133 #define PCH_DPLL_CTL(i) (0xc6014+i*0x0008) 134 #define PCH_DPLL_FP0(i) (0xc6040+i*0x0008) 135 #define PCH_DPLL_FP1(i) (0xc6044+i*0x0008) 136 #define TRANS_HTOTAL(i) (0xe0000+i*0x1000) 137 #define TRANS_HOTAL_VAL(t,a) (((t)-1) << 16 | ((a)-1)) 138 #define TRANS_HBLANK(i) (0xe0004+i*0x1000) 139 #define TRANS_HBLANK_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 140 #define TRANS_HSYNC(i) (0xe0008+i*0x1000) 141 #define TRANS_HSYNC_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 142 #define TRANS_VTOTAL(i) (0xe000c+i*0x1000) 143 #define TRANS_VTOTAL_VAL(t,a) (((t)-1) << 16 | ((a)-1)) 144 #define TRANS_VBLANK(i) (0xe0010+i*0x1000) 145 #define TRANS_VBLANK_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 146 #define TRANS_VSYNC(i) (0xe0014+i*0x1000) 147 #define TRANS_VSYNC_VAL(e,s) (((e)-1) << 16 | ((s)-1)) 148 #define TRANS_CONF(i) (0xf0008+i*0x1000) 149 #define FDI_RX_CTL(i) (0xf000c+i*0x1000) 150 151 #define OLD_BLC_PWM_CTL2 (0x61250) 152 #define OLD_BLC_PWM_CTL (0x61254) 153 #define BLM_PWM_ENABLE (1L << 31) 154 #define BLM_PIPE(p) ((p) << 29) 155 #define BLM_PHASEIN_INTST (1L << 26) 156 #define BLM_PHASEIN_ENABLE (1L << 25) 157 #define BLM_PHASEIN_INTEN (1L << 24) 158 #define BLM_PHASEIN_TIME(t) ((t) << 16) 159 #define BLM_PHASEIN_COUNT(c) ((c) << 8) 160 #define BLM_PHASEIN_INCR(i) ((i) << 0) 161 #define CPU_BLC_PWM_CTL2 (0x48250) 162 #define CPU_BLC_PWM_CTL (0x48254) 163 #define HSW_BLC_PWM_CTL (0x48350) 164 #define BACKLIGHT_VAL(f,l,v) ((f) << 17 | (l) << 16 | (v)) 165 #define BACKLIGHT_GET_FREQ(r) (((r) >> 17) & 0x7fff) 166 #define BACKLIGHT_GET_LEGACY(r) (((r) >> 16) & 0x1) 167 #define BACKLIGHT_GET_CYCLE(r) (((r) >> 0) & 0xffff) 168 169 #define GMBUS_NUM_PORTS 6 170 #define OLD_GPIOA (0x5010) 171 #define OLD_GPIOB (0x5014) 172 #define OLD_GPIOC (0x5018) 173 #define OLD_GPIOD (0x501c) 174 #define OLD_GPIOE (0x5020) 175 #define OLD_GPIOF (0x5024) 176 #define PCH_GPIOA (0xc5010) 177 #define PCH_GPIOB (0xc5014) 178 #define PCH_GPIOC (0xc5018) 179 #define PCH_GPIOD (0xc501c) 180 #define PCH_GPIOE (0xc5020) 181 #define PCH_GPIOF (0xc5024) 182 #define GPIO_CLOCK_DIR_MASK (1 << 0) 183 #define GPIO_CLOCK_DIR_IN (0 << 1) 184 #define GPIO_CLOCK_DIR_OUT (1 << 1) 185 #define GPIO_CLOCK_VAL_MASK (1 << 2) 186 #define GPIO_CLOCK_VAL_OUT (1 << 3) 187 #define GPIO_CLOCK_VAL_IN (1 << 4) 188 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 189 #define GPIO_DATA_DIR_MASK (1 << 8) 190 #define GPIO_DATA_DIR_IN (0 << 9) 191 #define GPIO_DATA_DIR_OUT (1 << 9) 192 #define GPIO_DATA_VAL_MASK (1 << 10) 193 #define GPIO_DATA_VAL_OUT (1 << 11) 194 #define GPIO_DATA_VAL_IN (1 << 12) 195 #define GPIO_DATA_PULLUP_DISABLE (1 << 13) 196 197 #endif 198