1 /* $NetBSD: if_rtwn.c,v 1.21 2023/08/01 07:04:15 mrg Exp $ */
2 /* $OpenBSD: if_rtwn.c,v 1.5 2015/06/14 08:02:47 stsp Exp $ */
3 #define IEEE80211_NO_HT
4 /*-
5 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 /*
22 * Driver for Realtek RTL8188CE
23 */
24
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: if_rtwn.c,v 1.21 2023/08/01 07:04:15 mrg Exp $");
27
28 #include <sys/param.h>
29 #include <sys/sockio.h>
30 #include <sys/mbuf.h>
31 #include <sys/kernel.h>
32 #include <sys/socket.h>
33 #include <sys/systm.h>
34 #include <sys/callout.h>
35 #include <sys/conf.h>
36 #include <sys/device.h>
37 #include <sys/endian.h>
38 #include <sys/mutex.h>
39
40 #include <sys/bus.h>
41 #include <sys/intr.h>
42
43 #include <net/bpf.h>
44 #include <net/if.h>
45 #include <net/if_arp.h>
46 #include <net/if_dl.h>
47 #include <net/if_ether.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50
51 #include <netinet/in.h>
52
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_radiotap.h>
55
56 #include <dev/firmload.h>
57
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcivar.h>
60 #include <dev/pci/pcidevs.h>
61
62 #include <dev/ic/rtwnreg.h>
63 #include <dev/ic/rtwn_data.h>
64 #include <dev/pci/if_rtwnreg.h>
65
66 #ifdef RTWN_DEBUG
67 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0)
68 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0)
69 int rtwn_debug = 0;
70 #else
71 #define DPRINTF(x)
72 #define DPRINTFN(n, x)
73 #endif
74
75 /*
76 * PCI configuration space registers.
77 */
78 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */
79 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */
80
81 #define RTWN_INT_ENABLE_TX \
82 (R92C_IMR_VODOK | R92C_IMR_VIDOK | R92C_IMR_BEDOK | \
83 R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \
84 R92C_IMR_HIGHDOK | R92C_IMR_BDOK)
85 #define RTWN_INT_ENABLE_RX \
86 (R92C_IMR_ROK | R92C_IMR_RDU | R92C_IMR_RXFOVW)
87 #define RTWN_INT_ENABLE (RTWN_INT_ENABLE_TX | RTWN_INT_ENABLE_RX)
88
89 static const struct rtwn_device {
90 pci_vendor_id_t rd_vendor;
91 pci_product_id_t rd_product;
92 } rtwn_devices[] = {
93 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8188CE },
94 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8192CE }
95 };
96
97 static int rtwn_match(device_t, cfdata_t, void *);
98 static void rtwn_attach(device_t, device_t, void *);
99 static int rtwn_detach(device_t, int);
100 static int rtwn_activate(device_t, enum devact);
101
102 CFATTACH_DECL_NEW(rtwn, sizeof(struct rtwn_softc), rtwn_match,
103 rtwn_attach, rtwn_detach, rtwn_activate);
104
105 static int rtwn_alloc_rx_list(struct rtwn_softc *);
106 static void rtwn_reset_rx_list(struct rtwn_softc *);
107 static void rtwn_free_rx_list(struct rtwn_softc *);
108 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc_pci *,
109 bus_addr_t, size_t, int);
110 static int rtwn_alloc_tx_list(struct rtwn_softc *, int);
111 static void rtwn_reset_tx_list(struct rtwn_softc *, int);
112 static void rtwn_free_tx_list(struct rtwn_softc *, int);
113 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t);
114 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t);
115 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t);
116 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t);
117 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t);
118 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t);
119 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int);
120 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t);
121 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t);
122 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t);
123 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t);
124 static void rtwn_efuse_read(struct rtwn_softc *);
125 static int rtwn_read_chipid(struct rtwn_softc *);
126 static void rtwn_efuse_switch_power(struct rtwn_softc *);
127 static void rtwn_read_rom(struct rtwn_softc *);
128 static int rtwn_media_change(struct ifnet *);
129 static int rtwn_ra_init(struct rtwn_softc *);
130 static int rtwn_get_nettype(struct rtwn_softc *);
131 static void rtwn_set_nettype0_msr(struct rtwn_softc *, uint8_t);
132 static void rtwn_tsf_sync_enable(struct rtwn_softc *);
133 static void rtwn_set_led(struct rtwn_softc *, int, int);
134 static void rtwn_calib_to(void *);
135 static void rtwn_next_scan(void *);
136 static void rtwn_newassoc(struct ieee80211_node *, int);
137 static int rtwn_reset(struct ifnet *);
138 static int rtwn_newstate(struct ieee80211com *, enum ieee80211_state,
139 int);
140 static int rtwn_wme_update(struct ieee80211com *);
141 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t);
142 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *);
143 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc_pci *,
144 struct rtwn_rx_data *, int);
145 static int rtwn_tx(struct rtwn_softc *, struct mbuf *,
146 struct ieee80211_node *);
147 static void rtwn_tx_done(struct rtwn_softc *, int);
148 static void rtwn_start(struct ifnet *);
149 static void rtwn_watchdog(struct ifnet *);
150 static int rtwn_ioctl(struct ifnet *, u_long, void *);
151 static int rtwn_power_on(struct rtwn_softc *);
152 static int rtwn_llt_init(struct rtwn_softc *);
153 static void rtwn_fw_reset(struct rtwn_softc *);
154 static int rtwn_fw_loadpage(struct rtwn_softc *, int, uint8_t *, int);
155 static int rtwn_load_firmware(struct rtwn_softc *);
156 static int rtwn_dma_init(struct rtwn_softc *);
157 static void rtwn_mac_init(struct rtwn_softc *);
158 static void rtwn_bb_init(struct rtwn_softc *);
159 static void rtwn_rf_init(struct rtwn_softc *);
160 static void rtwn_cam_init(struct rtwn_softc *);
161 static void rtwn_pa_bias_init(struct rtwn_softc *);
162 static void rtwn_rxfilter_init(struct rtwn_softc *);
163 static void rtwn_edca_init(struct rtwn_softc *);
164 static void rtwn_write_txpower(struct rtwn_softc *, int,
165 uint16_t[RTWN_RIDX_COUNT]);
166 static void rtwn_get_txpower(struct rtwn_softc *, int,
167 struct ieee80211_channel *, struct ieee80211_channel *,
168 uint16_t[RTWN_RIDX_COUNT]);
169 static void rtwn_set_txpower(struct rtwn_softc *,
170 struct ieee80211_channel *, struct ieee80211_channel *);
171 static void rtwn_set_chan(struct rtwn_softc *,
172 struct ieee80211_channel *, struct ieee80211_channel *);
173 static void rtwn_iq_calib(struct rtwn_softc *);
174 static void rtwn_lc_calib(struct rtwn_softc *);
175 static void rtwn_temp_calib(struct rtwn_softc *);
176 static int rtwn_init(struct ifnet *);
177 static void rtwn_init_task(void *);
178 static void rtwn_stop(struct ifnet *, int);
179 static int rtwn_intr(void *);
180 static void rtwn_softintr(void *);
181
182 /* Aliases. */
183 #define rtwn_bb_write rtwn_write_4
184 #define rtwn_bb_read rtwn_read_4
185
186 static const struct rtwn_device *
rtwn_lookup(const struct pci_attach_args * pa)187 rtwn_lookup(const struct pci_attach_args *pa)
188 {
189 const struct rtwn_device *rd;
190 int i;
191
192 for (i = 0; i < __arraycount(rtwn_devices); i++) {
193 rd = &rtwn_devices[i];
194 if (PCI_VENDOR(pa->pa_id) == rd->rd_vendor &&
195 PCI_PRODUCT(pa->pa_id) == rd->rd_product)
196 return rd;
197 }
198 return NULL;
199 }
200
201 static int
rtwn_match(device_t parent,cfdata_t match,void * aux)202 rtwn_match(device_t parent, cfdata_t match, void *aux)
203 {
204 struct pci_attach_args *pa = aux;
205
206 if (rtwn_lookup(pa) != NULL)
207 return 1;
208 return 0;
209 }
210
211 static void
rtwn_attach(device_t parent,device_t self,void * aux)212 rtwn_attach(device_t parent, device_t self, void *aux)
213 {
214 struct rtwn_softc *sc = device_private(self);
215 struct pci_attach_args *pa = aux;
216 struct ieee80211com *ic = &sc->sc_ic;
217 struct ifnet *ifp = GET_IFP(sc);
218 int i, error;
219 pcireg_t memtype;
220 const char *intrstr;
221 char intrbuf[PCI_INTRSTR_LEN];
222
223 sc->sc_dev = self;
224 sc->sc_dmat = pa->pa_dmat;
225 sc->sc_pc = pa->pa_pc;
226 sc->sc_tag = pa->pa_tag;
227
228 pci_aprint_devinfo(pa, NULL);
229
230 callout_init(&sc->scan_to, 0);
231 callout_setfunc(&sc->scan_to, rtwn_next_scan, sc);
232 callout_init(&sc->calib_to, 0);
233 callout_setfunc(&sc->calib_to, rtwn_calib_to, sc);
234
235 sc->sc_soft_ih = softint_establish(SOFTINT_NET, rtwn_softintr, sc);
236 sc->init_task = softint_establish(SOFTINT_NET, rtwn_init_task, sc);
237
238 /* Power up the device */
239 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
240
241 /* Map control/status registers. */
242 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RTWN_PCI_MMBA);
243 error = pci_mapreg_map(pa, RTWN_PCI_MMBA, memtype, 0, &sc->sc_st,
244 &sc->sc_sh, NULL, &sc->sc_mapsize);
245 if (error != 0) {
246 aprint_error_dev(self, "can't map mem space\n");
247 return;
248 }
249
250 /* Install interrupt handler. */
251 if (pci_intr_alloc(pa, &sc->sc_pihp, NULL, 0)) {
252 aprint_error_dev(self, "can't map interrupt\n");
253 return;
254 }
255 intrstr = pci_intr_string(sc->sc_pc, sc->sc_pihp[0], intrbuf,
256 sizeof(intrbuf));
257 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, sc->sc_pihp[0], IPL_NET,
258 rtwn_intr, sc, device_xname(self));
259 if (sc->sc_ih == NULL) {
260 aprint_error_dev(self, "can't establish interrupt");
261 if (intrstr != NULL)
262 aprint_error(" at %s", intrstr);
263 aprint_error("\n");
264 return;
265 }
266 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
267
268 error = rtwn_read_chipid(sc);
269 if (error != 0) {
270 aprint_error_dev(self, "unsupported test or unknown chip\n");
271 return;
272 }
273
274 /* Disable PCIe Active State Power Management (ASPM). */
275 if (pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS,
276 &sc->sc_cap_off, NULL)) {
277 uint32_t lcsr = pci_conf_read(sc->sc_pc, sc->sc_tag,
278 sc->sc_cap_off + PCIE_LCSR);
279 lcsr &= ~(PCIE_LCSR_ASPM_L0S | PCIE_LCSR_ASPM_L1);
280 pci_conf_write(sc->sc_pc, sc->sc_tag,
281 sc->sc_cap_off + PCIE_LCSR, lcsr);
282 }
283
284 /* Allocate Tx/Rx buffers. */
285 error = rtwn_alloc_rx_list(sc);
286 if (error != 0) {
287 aprint_error_dev(self, "could not allocate Rx buffers\n");
288 return;
289 }
290 for (i = 0; i < RTWN_NTXQUEUES; i++) {
291 error = rtwn_alloc_tx_list(sc, i);
292 if (error != 0) {
293 aprint_error_dev(self,
294 "could not allocate Tx buffers\n");
295 return;
296 }
297 }
298
299 /* Determine number of Tx/Rx chains. */
300 if (sc->chip & RTWN_CHIP_92C) {
301 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2;
302 sc->nrxchains = 2;
303 } else {
304 sc->ntxchains = 1;
305 sc->nrxchains = 1;
306 }
307 rtwn_read_rom(sc);
308
309 aprint_normal_dev(self, "MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n",
310 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE",
311 sc->ntxchains, sc->nrxchains, ether_sprintf(ic->ic_myaddr));
312
313 /*
314 * Setup the 802.11 device.
315 */
316 ic->ic_ifp = ifp;
317 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */
318 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */
319 ic->ic_state = IEEE80211_S_INIT;
320
321 /* Set device capabilities. */
322 ic->ic_caps =
323 IEEE80211_C_MONITOR | /* Monitor mode supported. */
324 IEEE80211_C_IBSS | /* IBSS mode supported */
325 IEEE80211_C_HOSTAP | /* HostAp mode supported */
326 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */
327 IEEE80211_C_SHSLOT | /* Short slot time supported. */
328 IEEE80211_C_WME | /* 802.11e */
329 IEEE80211_C_WPA; /* WPA/RSN. */
330
331 #ifndef IEEE80211_NO_HT
332 /* Set HT capabilities. */
333 ic->ic_htcaps =
334 IEEE80211_HTCAP_CBW20_40 |
335 IEEE80211_HTCAP_DSSSCCK40;
336 /* Set supported HT rates. */
337 for (i = 0; i < sc->nrxchains; i++)
338 ic->ic_sup_mcs[i] = 0xff;
339 #endif
340
341 /* Set supported .11b and .11g rates. */
342 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
343 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
344
345 /* Set supported .11b and .11g channels (1 through 14). */
346 for (i = 1; i <= 14; i++) {
347 ic->ic_channels[i].ic_freq =
348 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
349 ic->ic_channels[i].ic_flags =
350 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
351 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
352 }
353
354 ifp->if_softc = sc;
355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
356 ifp->if_init = rtwn_init;
357 ifp->if_ioctl = rtwn_ioctl;
358 ifp->if_start = rtwn_start;
359 ifp->if_watchdog = rtwn_watchdog;
360 IFQ_SET_READY(&ifp->if_snd);
361 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
362
363 if_initialize(ifp);
364 ieee80211_ifattach(ic);
365 /* Use common softint-based if_input */
366 ifp->if_percpuq = if_percpuq_create(ifp);
367 if_register(ifp);
368
369 /* override default methods */
370 ic->ic_newassoc = rtwn_newassoc;
371 ic->ic_reset = rtwn_reset;
372 ic->ic_wme.wme_update = rtwn_wme_update;
373
374 /* Override state transition machine. */
375 sc->sc_newstate = ic->ic_newstate;
376 ic->ic_newstate = rtwn_newstate;
377 ieee80211_media_init(ic, rtwn_media_change, ieee80211_media_status);
378
379 bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
380 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
381 &sc->sc_drvbpf);
382
383 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
384 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
385 sc->sc_rxtap.wr_ihdr.it_present = htole32(RTWN_RX_RADIOTAP_PRESENT);
386
387 sc->sc_txtap_len = sizeof(sc->sc_txtapu);
388 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
389 sc->sc_txtap.wt_ihdr.it_present = htole32(RTWN_TX_RADIOTAP_PRESENT);
390
391 ieee80211_announce(ic);
392
393 if (!pmf_device_register(self, NULL, NULL))
394 aprint_error_dev(self, "couldn't establish power handler\n");
395 }
396
397 static int
rtwn_detach(device_t self,int flags)398 rtwn_detach(device_t self, int flags)
399 {
400 struct rtwn_softc *sc = device_private(self);
401 struct ieee80211com *ic = &sc->sc_ic;
402 struct ifnet *ifp = GET_IFP(sc);
403 int s, i;
404
405 callout_stop(&sc->scan_to);
406 callout_stop(&sc->calib_to);
407
408 s = splnet();
409
410 if (ifp->if_softc != NULL) {
411 rtwn_stop(ifp, 0);
412
413 pmf_device_deregister(self);
414 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
415 bpf_detach(ifp);
416 ieee80211_ifdetach(ic);
417 if_detach(ifp);
418 }
419
420 /* Free Tx/Rx buffers. */
421 for (i = 0; i < RTWN_NTXQUEUES; i++)
422 rtwn_free_tx_list(sc, i);
423 rtwn_free_rx_list(sc);
424
425 splx(s);
426
427 callout_destroy(&sc->scan_to);
428 callout_destroy(&sc->calib_to);
429
430 if (sc->init_task != NULL)
431 softint_disestablish(sc->init_task);
432 if (sc->sc_soft_ih != NULL)
433 softint_disestablish(sc->sc_soft_ih);
434
435 if (sc->sc_ih != NULL) {
436 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
437 pci_intr_release(sc->sc_pc, sc->sc_pihp, 1);
438 }
439
440 return 0;
441 }
442
443 static int
rtwn_activate(device_t self,enum devact act)444 rtwn_activate(device_t self, enum devact act)
445 {
446 struct rtwn_softc *sc = device_private(self);
447 struct ifnet *ifp = GET_IFP(sc);
448
449 switch (act) {
450 case DVACT_DEACTIVATE:
451 if (ifp->if_flags & IFF_RUNNING)
452 rtwn_stop(ifp, 0);
453 return 0;
454 default:
455 return EOPNOTSUPP;
456 }
457 }
458
459 static void
rtwn_setup_rx_desc(struct rtwn_softc * sc,struct r92c_rx_desc_pci * desc,bus_addr_t addr,size_t len,int idx)460 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc_pci *desc,
461 bus_addr_t addr, size_t len, int idx)
462 {
463
464 memset(desc, 0, sizeof(*desc));
465 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) |
466 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0));
467 desc->rxbufaddr = htole32(addr);
468 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize,
469 BUS_SPACE_BARRIER_WRITE);
470 desc->rxdw0 |= htole32(R92C_RXDW0_OWN);
471 }
472
473 static int
rtwn_alloc_rx_list(struct rtwn_softc * sc)474 rtwn_alloc_rx_list(struct rtwn_softc *sc)
475 {
476 struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
477 struct rtwn_rx_data *rx_data;
478 const size_t size = sizeof(struct r92c_rx_desc_pci) * RTWN_RX_LIST_COUNT;
479 int i, error = 0;
480
481 /* Allocate Rx descriptors. */
482 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT,
483 &rx_ring->map);
484 if (error != 0) {
485 aprint_error_dev(sc->sc_dev,
486 "could not create rx desc DMA map\n");
487 rx_ring->map = NULL;
488 goto fail;
489 }
490
491 error = bus_dmamem_alloc(sc->sc_dmat, size, 0, 0, &rx_ring->seg, 1,
492 &rx_ring->nsegs, BUS_DMA_NOWAIT);
493 if (error != 0) {
494 aprint_error_dev(sc->sc_dev, "could not allocate rx desc\n");
495 goto fail;
496 }
497
498 error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs,
499 size, (void **)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
500 if (error != 0) {
501 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs);
502 rx_ring->desc = NULL;
503 aprint_error_dev(sc->sc_dev, "could not map rx desc\n");
504 goto fail;
505 }
506 memset(rx_ring->desc, 0, size);
507
508 error = bus_dmamap_load_raw(sc->sc_dmat, rx_ring->map, &rx_ring->seg,
509 1, size, BUS_DMA_NOWAIT);
510 if (error != 0) {
511 aprint_error_dev(sc->sc_dev, "could not load rx desc\n");
512 goto fail;
513 }
514
515 /* Allocate Rx buffers. */
516 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
517 rx_data = &rx_ring->rx_data[i];
518
519 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
520 0, BUS_DMA_NOWAIT, &rx_data->map);
521 if (error != 0) {
522 aprint_error_dev(sc->sc_dev,
523 "could not create rx buf DMA map\n");
524 goto fail;
525 }
526
527 MGETHDR(rx_data->m, M_DONTWAIT, MT_DATA);
528 if (__predict_false(rx_data->m == NULL)) {
529 aprint_error_dev(sc->sc_dev,
530 "couldn't allocate rx mbuf\n");
531 error = ENOMEM;
532 goto fail;
533 }
534 MCLGET(rx_data->m, M_DONTWAIT);
535 if (__predict_false(!(rx_data->m->m_flags & M_EXT))) {
536 aprint_error_dev(sc->sc_dev,
537 "couldn't allocate rx mbuf cluster\n");
538 m_free(rx_data->m);
539 rx_data->m = NULL;
540 error = ENOMEM;
541 goto fail;
542 }
543
544 error = bus_dmamap_load(sc->sc_dmat, rx_data->map,
545 mtod(rx_data->m, void *), MCLBYTES, NULL,
546 BUS_DMA_NOWAIT | BUS_DMA_READ);
547 if (error != 0) {
548 aprint_error_dev(sc->sc_dev,
549 "could not load rx buf DMA map\n");
550 goto fail;
551 }
552
553 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES,
554 BUS_DMASYNC_PREREAD);
555
556 rtwn_setup_rx_desc(sc, &rx_ring->desc[i],
557 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i);
558 }
559 fail: if (error != 0)
560 rtwn_free_rx_list(sc);
561 return error;
562 }
563
564 static void
rtwn_reset_rx_list(struct rtwn_softc * sc)565 rtwn_reset_rx_list(struct rtwn_softc *sc)
566 {
567 struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
568 struct rtwn_rx_data *rx_data;
569 int i;
570
571 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
572 rx_data = &rx_ring->rx_data[i];
573 rtwn_setup_rx_desc(sc, &rx_ring->desc[i],
574 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, i);
575 }
576 }
577
578 static void
rtwn_free_rx_list(struct rtwn_softc * sc)579 rtwn_free_rx_list(struct rtwn_softc *sc)
580 {
581 struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
582 struct rtwn_rx_data *rx_data;
583 int i, s;
584
585 s = splnet();
586
587 if (rx_ring->map) {
588 if (rx_ring->desc) {
589 bus_dmamap_unload(sc->sc_dmat, rx_ring->map);
590 bus_dmamem_unmap(sc->sc_dmat, rx_ring->desc,
591 sizeof (struct r92c_rx_desc_pci) * RTWN_RX_LIST_COUNT);
592 bus_dmamem_free(sc->sc_dmat, &rx_ring->seg,
593 rx_ring->nsegs);
594 rx_ring->desc = NULL;
595 }
596 bus_dmamap_destroy(sc->sc_dmat, rx_ring->map);
597 rx_ring->map = NULL;
598 }
599
600 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
601 rx_data = &rx_ring->rx_data[i];
602
603 if (rx_data->m != NULL) {
604 bus_dmamap_unload(sc->sc_dmat, rx_data->map);
605 m_freem(rx_data->m);
606 rx_data->m = NULL;
607 }
608 bus_dmamap_destroy(sc->sc_dmat, rx_data->map);
609 rx_data->map = NULL;
610 }
611
612 splx(s);
613 }
614
615 static int
rtwn_alloc_tx_list(struct rtwn_softc * sc,int qid)616 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid)
617 {
618 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
619 struct rtwn_tx_data *tx_data;
620 const size_t size = sizeof(struct r92c_tx_desc_pci) * RTWN_TX_LIST_COUNT;
621 int i = 0, error = 0;
622
623 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT,
624 &tx_ring->map);
625 if (error != 0) {
626 aprint_error_dev(sc->sc_dev,
627 "could not create tx ring DMA map\n");
628 goto fail;
629 }
630
631 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0,
632 &tx_ring->seg, 1, &tx_ring->nsegs, BUS_DMA_NOWAIT);
633 if (error != 0) {
634 aprint_error_dev(sc->sc_dev,
635 "could not allocate tx ring DMA memory\n");
636 goto fail;
637 }
638
639 error = bus_dmamem_map(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs,
640 size, (void **)&tx_ring->desc, BUS_DMA_NOWAIT);
641 if (error != 0) {
642 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg, tx_ring->nsegs);
643 aprint_error_dev(sc->sc_dev, "can't map tx ring DMA memory\n");
644 goto fail;
645 }
646 memset(tx_ring->desc, 0, size);
647
648 error = bus_dmamap_load(sc->sc_dmat, tx_ring->map, tx_ring->desc,
649 size, NULL, BUS_DMA_NOWAIT);
650 if (error != 0) {
651 aprint_error_dev(sc->sc_dev,
652 "could not load tx ring DMA map\n");
653 goto fail;
654 }
655
656 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
657 struct r92c_tx_desc_pci *desc = &tx_ring->desc[i];
658
659 /* setup tx desc */
660 desc->nextdescaddr = htole32(tx_ring->map->dm_segs[0].ds_addr
661 + sizeof(*desc) * ((i + 1) % RTWN_TX_LIST_COUNT));
662
663 tx_data = &tx_ring->tx_data[i];
664 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
665 0, BUS_DMA_NOWAIT, &tx_data->map);
666 if (error != 0) {
667 aprint_error_dev(sc->sc_dev,
668 "could not create tx buf DMA map\n");
669 goto fail;
670 }
671 tx_data->m = NULL;
672 tx_data->ni = NULL;
673 }
674
675 fail:
676 if (error != 0)
677 rtwn_free_tx_list(sc, qid);
678 return error;
679 }
680
681 static void
rtwn_reset_tx_list(struct rtwn_softc * sc,int qid)682 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid)
683 {
684 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
685 int i;
686
687 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
688 struct r92c_tx_desc_pci *desc = &tx_ring->desc[i];
689 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i];
690
691 memset(desc, 0, sizeof(*desc) -
692 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) +
693 sizeof(desc->nextdescaddr)));
694
695 if (tx_data->m != NULL) {
696 bus_dmamap_unload(sc->sc_dmat, tx_data->map);
697 m_freem(tx_data->m);
698 tx_data->m = NULL;
699 ieee80211_free_node(tx_data->ni);
700 tx_data->ni = NULL;
701 }
702 }
703
704 sc->qfullmsk &= ~(1 << qid);
705 tx_ring->queued = 0;
706 tx_ring->cur = 0;
707 }
708
709 static void
rtwn_free_tx_list(struct rtwn_softc * sc,int qid)710 rtwn_free_tx_list(struct rtwn_softc *sc, int qid)
711 {
712 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
713 struct rtwn_tx_data *tx_data;
714 int i;
715
716 if (tx_ring->map != NULL) {
717 if (tx_ring->desc != NULL) {
718 bus_dmamap_unload(sc->sc_dmat, tx_ring->map);
719 bus_dmamem_unmap(sc->sc_dmat, tx_ring->desc,
720 sizeof (struct r92c_tx_desc_pci) * RTWN_TX_LIST_COUNT);
721 bus_dmamem_free(sc->sc_dmat, &tx_ring->seg,
722 tx_ring->nsegs);
723 }
724 bus_dmamap_destroy(sc->sc_dmat, tx_ring->map);
725 }
726
727 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
728 tx_data = &tx_ring->tx_data[i];
729
730 if (tx_data->m != NULL) {
731 bus_dmamap_unload(sc->sc_dmat, tx_data->map);
732 m_freem(tx_data->m);
733 tx_data->m = NULL;
734 }
735 bus_dmamap_destroy(sc->sc_dmat, tx_data->map);
736 }
737
738 sc->qfullmsk &= ~(1 << qid);
739 tx_ring->queued = 0;
740 tx_ring->cur = 0;
741 }
742
743 static void
rtwn_write_1(struct rtwn_softc * sc,uint16_t addr,uint8_t val)744 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val)
745 {
746 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val);
747 }
748
749 static void
rtwn_write_2(struct rtwn_softc * sc,uint16_t addr,uint16_t val)750 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val)
751 {
752 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, htole16(val));
753 }
754
755 static void
rtwn_write_4(struct rtwn_softc * sc,uint16_t addr,uint32_t val)756 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val)
757 {
758 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, htole32(val));
759 }
760
761 static uint8_t
rtwn_read_1(struct rtwn_softc * sc,uint16_t addr)762 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr)
763 {
764 return bus_space_read_1(sc->sc_st, sc->sc_sh, addr);
765 }
766
767 static uint16_t
rtwn_read_2(struct rtwn_softc * sc,uint16_t addr)768 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr)
769 {
770 return le16toh(bus_space_read_2(sc->sc_st, sc->sc_sh, addr));
771 }
772
773 static uint32_t
rtwn_read_4(struct rtwn_softc * sc,uint16_t addr)774 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr)
775 {
776 return le32toh(bus_space_read_4(sc->sc_st, sc->sc_sh, addr));
777 }
778
779 static int
rtwn_fw_cmd(struct rtwn_softc * sc,uint8_t id,const void * buf,int len)780 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len)
781 {
782 struct r92c_fw_cmd cmd;
783 uint8_t *cp;
784 int fwcur;
785 int ntries;
786
787 DPRINTFN(3, ("%s: %s: id=0x%02x, buf=%p, len=%d\n",
788 device_xname(sc->sc_dev), __func__, id, buf, len));
789
790 fwcur = sc->fwcur;
791 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
792
793 /* Wait for current FW box to be empty. */
794 for (ntries = 0; ntries < 100; ntries++) {
795 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
796 break;
797 DELAY(1);
798 }
799 if (ntries == 100) {
800 aprint_error_dev(sc->sc_dev,
801 "could not send firmware command %d\n", id);
802 return ETIMEDOUT;
803 }
804
805 memset(&cmd, 0, sizeof(cmd));
806 KASSERT(len <= sizeof(cmd.msg));
807 memcpy(cmd.msg, buf, len);
808
809 /* Write the first word last since that will trigger the FW. */
810 cp = (uint8_t *)&cmd;
811 if (len >= 4) {
812 cmd.id = id | R92C_CMD_FLAG_EXT;
813 rtwn_write_2(sc, R92C_HMEBOX_EXT(fwcur), cp[1] + (cp[2] << 8));
814 rtwn_write_4(sc, R92C_HMEBOX(fwcur),
815 cp[0] + (cp[3] << 8) + (cp[4] << 16) + (cp[5] << 24));
816 } else {
817 cmd.id = id;
818 rtwn_write_4(sc, R92C_HMEBOX(fwcur),
819 cp[0] + (cp[1] << 8) + (cp[2] << 16) + (cp[3] << 24));
820 }
821
822 /* Give firmware some time for processing. */
823 DELAY(2000);
824
825 return 0;
826 }
827
828 static void
rtwn_rf_write(struct rtwn_softc * sc,int chain,uint8_t addr,uint32_t val)829 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
830 {
831
832 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
833 SM(R92C_LSSI_PARAM_ADDR, addr) | SM(R92C_LSSI_PARAM_DATA, val));
834 }
835
836 static uint32_t
rtwn_rf_read(struct rtwn_softc * sc,int chain,uint8_t addr)837 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr)
838 {
839 uint32_t reg[R92C_MAX_CHAINS], val;
840
841 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
842 if (chain != 0)
843 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
844
845 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
846 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
847 DELAY(1000);
848
849 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
850 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
851 R92C_HSSI_PARAM2_READ_EDGE);
852 DELAY(1000);
853
854 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
855 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
856 DELAY(1000);
857
858 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
859 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
860 else
861 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
862 return MS(val, R92C_LSSI_READBACK_DATA);
863 }
864
865 static int
rtwn_llt_write(struct rtwn_softc * sc,uint32_t addr,uint32_t data)866 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data)
867 {
868 int ntries;
869
870 rtwn_write_4(sc, R92C_LLT_INIT,
871 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
872 SM(R92C_LLT_INIT_ADDR, addr) |
873 SM(R92C_LLT_INIT_DATA, data));
874 /* Wait for write operation to complete. */
875 for (ntries = 0; ntries < 20; ntries++) {
876 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
877 R92C_LLT_INIT_OP_NO_ACTIVE)
878 return 0;
879 DELAY(5);
880 }
881 return ETIMEDOUT;
882 }
883
884 static uint8_t
rtwn_efuse_read_1(struct rtwn_softc * sc,uint16_t addr)885 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr)
886 {
887 uint32_t reg;
888 int ntries;
889
890 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
891 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
892 reg &= ~R92C_EFUSE_CTRL_VALID;
893 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
894 /* Wait for read operation to complete. */
895 for (ntries = 0; ntries < 100; ntries++) {
896 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
897 if (reg & R92C_EFUSE_CTRL_VALID)
898 return MS(reg, R92C_EFUSE_CTRL_DATA);
899 DELAY(5);
900 }
901 aprint_error_dev(sc->sc_dev,
902 "could not read efuse byte at address 0x%x\n", addr);
903 return 0xff;
904 }
905
906 static void
rtwn_efuse_read(struct rtwn_softc * sc)907 rtwn_efuse_read(struct rtwn_softc *sc)
908 {
909 uint8_t *rom = (uint8_t *)&sc->rom;
910 uint32_t reg;
911 uint16_t addr = 0;
912 uint8_t off, msk;
913 int i;
914
915 rtwn_efuse_switch_power(sc);
916
917 memset(&sc->rom, 0xff, sizeof(sc->rom));
918 while (addr < 512) {
919 reg = rtwn_efuse_read_1(sc, addr);
920 if (reg == 0xff)
921 break;
922 addr++;
923 off = reg >> 4;
924 msk = reg & 0xf;
925 for (i = 0; i < 4; i++) {
926 if (msk & (1 << i))
927 continue;
928 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr);
929 addr++;
930 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr);
931 addr++;
932 }
933 }
934 #ifdef RTWN_DEBUG
935 if (rtwn_debug >= 2) {
936 /* Dump ROM content. */
937 printf("\n");
938 for (i = 0; i < sizeof(sc->rom); i++)
939 printf("%02x:", rom[i]);
940 printf("\n");
941 }
942 #endif
943 }
944
945 static void
rtwn_efuse_switch_power(struct rtwn_softc * sc)946 rtwn_efuse_switch_power(struct rtwn_softc *sc)
947 {
948 uint32_t reg;
949
950 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL);
951 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
952 rtwn_write_2(sc, R92C_SYS_ISO_CTRL,
953 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
954 }
955 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
956 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
957 rtwn_write_2(sc, R92C_SYS_FUNC_EN,
958 reg | R92C_SYS_FUNC_EN_ELDR);
959 }
960 reg = rtwn_read_2(sc, R92C_SYS_CLKR);
961 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
962 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
963 rtwn_write_2(sc, R92C_SYS_CLKR,
964 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
965 }
966 }
967
968 /* rtwn_read_chipid: reg=0x40073b chipid=0x0 */
969 static int
rtwn_read_chipid(struct rtwn_softc * sc)970 rtwn_read_chipid(struct rtwn_softc *sc)
971 {
972 uint32_t reg;
973
974 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
975
976 reg = rtwn_read_4(sc, R92C_SYS_CFG);
977 DPRINTF(("%s: version=0x%08x\n", device_xname(sc->sc_dev), reg));
978 if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
979 /* Unsupported test chip. */
980 return EIO;
981
982 if (reg & R92C_SYS_CFG_TYPE_92C) {
983 sc->chip |= RTWN_CHIP_92C;
984 /* Check if it is a castrated 8192C. */
985 if (MS(rtwn_read_4(sc, R92C_HPON_FSM),
986 R92C_HPON_FSM_CHIP_BONDING_ID) ==
987 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
988 sc->chip |= RTWN_CHIP_92C_1T2R;
989 }
990 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
991 sc->chip |= RTWN_CHIP_UMC;
992 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
993 sc->chip |= RTWN_CHIP_UMC_A_CUT;
994 } else if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) != 0) {
995 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 1)
996 sc->chip |= RTWN_CHIP_UMC | RTWN_CHIP_UMC_B_CUT;
997 else
998 /* Unsupported unknown chip. */
999 return EIO;
1000 }
1001 return 0;
1002 }
1003
1004 static void
rtwn_read_rom(struct rtwn_softc * sc)1005 rtwn_read_rom(struct rtwn_softc *sc)
1006 {
1007 struct ieee80211com *ic = &sc->sc_ic;
1008 struct r92c_rom *rom = &sc->rom;
1009
1010 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1011
1012 /* Read full ROM image. */
1013 rtwn_efuse_read(sc);
1014
1015 if (rom->id != 0x8129) {
1016 aprint_error_dev(sc->sc_dev, "invalid EEPROM ID 0x%x\n",
1017 rom->id);
1018 }
1019
1020 /* XXX Weird but this is what the vendor driver does. */
1021 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa);
1022 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1023 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1024
1025 DPRINTF(("PA setting=0x%x, board=0x%x, regulatory=%d\n",
1026 sc->pa_setting, sc->board_type, sc->regulatory));
1027
1028 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr);
1029 }
1030
1031 static int
rtwn_media_change(struct ifnet * ifp)1032 rtwn_media_change(struct ifnet *ifp)
1033 {
1034 int error;
1035
1036 error = ieee80211_media_change(ifp);
1037 if (error != ENETRESET)
1038 return error;
1039
1040 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1041 (IFF_UP | IFF_RUNNING)) {
1042 rtwn_stop(ifp, 0);
1043 error = rtwn_init(ifp);
1044 }
1045 return error;
1046 }
1047
1048 /*
1049 * Initialize rate adaptation in firmware.
1050 */
1051 static int
rtwn_ra_init(struct rtwn_softc * sc)1052 rtwn_ra_init(struct rtwn_softc *sc)
1053 {
1054 static const uint8_t map[] = {
1055 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
1056 };
1057 struct ieee80211com *ic = &sc->sc_ic;
1058 struct ieee80211_node *ni = ic->ic_bss;
1059 struct ieee80211_rateset *rs = &ni->ni_rates;
1060 struct r92c_fw_cmd_macid_cfg cmd;
1061 uint32_t rates, basicrates;
1062 uint8_t mode;
1063 int maxrate, maxbasicrate, error, i, j;
1064
1065 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1066
1067 /* Get normal and basic rates mask. */
1068 rates = basicrates = 0;
1069 maxrate = maxbasicrate = 0;
1070 for (i = 0; i < rs->rs_nrates; i++) {
1071 /* Convert 802.11 rate to HW rate index. */
1072 for (j = 0; j < __arraycount(map); j++)
1073 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j])
1074 break;
1075 if (j == __arraycount(map)) /* Unknown rate, skip. */
1076 continue;
1077 rates |= 1 << j;
1078 if (j > maxrate)
1079 maxrate = j;
1080 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1081 basicrates |= 1 << j;
1082 if (j > maxbasicrate)
1083 maxbasicrate = j;
1084 }
1085 }
1086 if (ic->ic_curmode == IEEE80211_MODE_11B)
1087 mode = R92C_RAID_11B;
1088 else
1089 mode = R92C_RAID_11BG;
1090 DPRINTF(("%s: mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
1091 device_xname(sc->sc_dev), mode, rates, basicrates));
1092 if (basicrates == 0)
1093 basicrates |= 1; /* add 1Mbps */
1094
1095 /* Set rates mask for group addressed frames. */
1096 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID;
1097 cmd.mask = htole32((mode << 28) | basicrates);
1098 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1099 if (error != 0) {
1100 aprint_error_dev(sc->sc_dev,
1101 "could not add broadcast station\n");
1102 return error;
1103 }
1104 /* Set initial MRR rate. */
1105 DPRINTF(("%s: maxbasicrate=%d\n", device_xname(sc->sc_dev),
1106 maxbasicrate));
1107 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), maxbasicrate);
1108
1109 /* Set rates mask for unicast frames. */
1110 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID;
1111 cmd.mask = htole32((mode << 28) | rates);
1112 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1113 if (error != 0) {
1114 aprint_error_dev(sc->sc_dev, "could not add BSS station\n");
1115 return error;
1116 }
1117 /* Set initial MRR rate. */
1118 DPRINTF(("%s: maxrate=%d\n", device_xname(sc->sc_dev), maxrate));
1119 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), maxrate);
1120
1121 /* Configure Automatic Rate Fallback Register. */
1122 if (ic->ic_curmode == IEEE80211_MODE_11B) {
1123 if (rates & 0x0c)
1124 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d));
1125 else
1126 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f));
1127 } else
1128 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5));
1129
1130 /* Indicate highest supported rate. */
1131 ni->ni_txrate = rs->rs_nrates - 1;
1132 return 0;
1133 }
1134
1135 static int
rtwn_get_nettype(struct rtwn_softc * sc)1136 rtwn_get_nettype(struct rtwn_softc *sc)
1137 {
1138 struct ieee80211com *ic = &sc->sc_ic;
1139 int type;
1140
1141 switch (ic->ic_opmode) {
1142 case IEEE80211_M_STA:
1143 type = R92C_CR_NETTYPE_INFRA;
1144 break;
1145
1146 case IEEE80211_M_HOSTAP:
1147 type = R92C_CR_NETTYPE_AP;
1148 break;
1149
1150 case IEEE80211_M_IBSS:
1151 type = R92C_CR_NETTYPE_ADHOC;
1152 break;
1153
1154 default:
1155 type = R92C_CR_NETTYPE_NOLINK;
1156 break;
1157 }
1158
1159 return type;
1160 }
1161
1162 static void
rtwn_set_nettype0_msr(struct rtwn_softc * sc,uint8_t type)1163 rtwn_set_nettype0_msr(struct rtwn_softc *sc, uint8_t type)
1164 {
1165 uint32_t reg;
1166
1167 reg = rtwn_read_4(sc, R92C_CR);
1168 reg = RW(reg, R92C_CR_NETTYPE, type);
1169 rtwn_write_4(sc, R92C_CR, reg);
1170 }
1171
1172 static void
rtwn_tsf_sync_enable(struct rtwn_softc * sc)1173 rtwn_tsf_sync_enable(struct rtwn_softc *sc)
1174 {
1175 struct ieee80211_node *ni = sc->sc_ic.ic_bss;
1176 uint64_t tsf;
1177
1178 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1179
1180 /* Enable TSF synchronization. */
1181 rtwn_write_1(sc, R92C_BCN_CTRL,
1182 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1183
1184 rtwn_write_1(sc, R92C_BCN_CTRL,
1185 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1186
1187 /* Set initial TSF. */
1188 tsf = ni->ni_tstamp.tsf;
1189 tsf = le64toh(tsf);
1190 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU));
1191 tsf -= IEEE80211_DUR_TU;
1192 rtwn_write_4(sc, R92C_TSFTR + 0, (uint32_t)tsf);
1193 rtwn_write_4(sc, R92C_TSFTR + 4, (uint32_t)(tsf >> 32));
1194
1195 rtwn_write_1(sc, R92C_BCN_CTRL,
1196 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1197 }
1198
1199 static void
rtwn_set_led(struct rtwn_softc * sc,int led,int on)1200 rtwn_set_led(struct rtwn_softc *sc, int led, int on)
1201 {
1202 uint8_t reg;
1203
1204 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1205
1206 if (led == RTWN_LED_LINK) {
1207 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1208 if (!on)
1209 reg |= R92C_LEDCFG2_DIS;
1210 else
1211 reg |= R92C_LEDCFG2_EN;
1212 rtwn_write_1(sc, R92C_LEDCFG2, reg);
1213 sc->ledlink = on; /* Save LED state. */
1214 }
1215 }
1216
1217 static void
rtwn_calib_to(void * arg)1218 rtwn_calib_to(void *arg)
1219 {
1220 struct rtwn_softc *sc = arg;
1221 struct r92c_fw_cmd_rssi cmd;
1222 int s;
1223
1224 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1225
1226 s = splnet();
1227
1228 if (sc->sc_ic.ic_state != IEEE80211_S_RUN)
1229 goto restart_timer;
1230
1231 if (sc->avg_pwdb != -1) {
1232 /* Indicate Rx signal strength to FW for rate adaptation. */
1233 memset(&cmd, 0, sizeof(cmd));
1234 cmd.macid = 0; /* BSS. */
1235 cmd.pwdb = sc->avg_pwdb;
1236 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb));
1237 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd));
1238 }
1239
1240 /* Do temperature compensation. */
1241 rtwn_temp_calib(sc);
1242
1243 restart_timer:
1244 callout_schedule(&sc->calib_to, mstohz(2000));
1245
1246 splx(s);
1247 }
1248
1249 static void
rtwn_next_scan(void * arg)1250 rtwn_next_scan(void *arg)
1251 {
1252 struct rtwn_softc *sc = arg;
1253 struct ieee80211com *ic = &sc->sc_ic;
1254 int s;
1255
1256 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1257
1258 s = splnet();
1259 if (ic->ic_state == IEEE80211_S_SCAN)
1260 ieee80211_next_scan(ic);
1261 splx(s);
1262 }
1263
1264 static void
rtwn_newassoc(struct ieee80211_node * ni,int isnew)1265 rtwn_newassoc(struct ieee80211_node *ni, int isnew)
1266 {
1267
1268 DPRINTF(("%s: new node %s\n", __func__, ether_sprintf(ni->ni_macaddr)));
1269
1270 /* start with lowest Tx rate */
1271 ni->ni_txrate = 0;
1272 }
1273
1274 static int
rtwn_reset(struct ifnet * ifp)1275 rtwn_reset(struct ifnet *ifp)
1276 {
1277 struct rtwn_softc *sc = ifp->if_softc;
1278 struct ieee80211com *ic = &sc->sc_ic;
1279
1280 if (ic->ic_opmode != IEEE80211_M_MONITOR)
1281 return ENETRESET;
1282
1283 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1284
1285 return 0;
1286 }
1287
1288 static int
rtwn_newstate(struct ieee80211com * ic,enum ieee80211_state nstate,int arg)1289 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1290 {
1291 struct rtwn_softc *sc = IC2IFP(ic)->if_softc;
1292 struct ieee80211_node *ni;
1293 enum ieee80211_state ostate = ic->ic_state;
1294 uint32_t reg;
1295 int s;
1296
1297 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1298
1299 s = splnet();
1300
1301 callout_stop(&sc->scan_to);
1302 callout_stop(&sc->calib_to);
1303
1304 if (ostate != nstate) {
1305 DPRINTF(("%s: %s -> %s\n", __func__,
1306 ieee80211_state_name[ostate],
1307 ieee80211_state_name[nstate]));
1308 }
1309
1310 switch (ostate) {
1311 case IEEE80211_S_INIT:
1312 break;
1313
1314 case IEEE80211_S_SCAN:
1315 if (nstate != IEEE80211_S_SCAN) {
1316 /*
1317 * End of scanning
1318 */
1319 /* flush 4-AC Queue after site_survey */
1320 rtwn_write_1(sc, R92C_TXPAUSE, 0x0);
1321
1322 /* Allow Rx from our BSSID only. */
1323 rtwn_write_4(sc, R92C_RCR,
1324 rtwn_read_4(sc, R92C_RCR) |
1325 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1326 }
1327 break;
1328
1329 case IEEE80211_S_AUTH:
1330 case IEEE80211_S_ASSOC:
1331 break;
1332
1333 case IEEE80211_S_RUN:
1334 /* Turn link LED off. */
1335 rtwn_set_led(sc, RTWN_LED_LINK, 0);
1336
1337 /* Set media status to 'No Link'. */
1338 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1339
1340 /* Stop Rx of data frames. */
1341 rtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1342
1343 /* Rest TSF. */
1344 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1345
1346 /* Disable TSF synchronization. */
1347 rtwn_write_1(sc, R92C_BCN_CTRL,
1348 rtwn_read_1(sc, R92C_BCN_CTRL) |
1349 R92C_BCN_CTRL_DIS_TSF_UDT0);
1350
1351 /* Back to 20MHz mode */
1352 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1353
1354 /* Reset EDCA parameters. */
1355 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1356 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1357 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1358 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1359
1360 /* flush all cam entries */
1361 rtwn_cam_init(sc);
1362 break;
1363 }
1364
1365 switch (nstate) {
1366 case IEEE80211_S_INIT:
1367 /* Turn link LED off. */
1368 rtwn_set_led(sc, RTWN_LED_LINK, 0);
1369 break;
1370
1371 case IEEE80211_S_SCAN:
1372 if (ostate != IEEE80211_S_SCAN) {
1373 /*
1374 * Begin of scanning
1375 */
1376
1377 /* Set gain for scanning. */
1378 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1379 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1380 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1381
1382 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1383 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1384 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1385
1386 /* Allow Rx from any BSSID. */
1387 rtwn_write_4(sc, R92C_RCR,
1388 rtwn_read_4(sc, R92C_RCR) &
1389 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1390
1391 /* Stop Rx of data frames. */
1392 rtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1393
1394 /* Disable update TSF */
1395 rtwn_write_1(sc, R92C_BCN_CTRL,
1396 rtwn_read_1(sc, R92C_BCN_CTRL) |
1397 R92C_BCN_CTRL_DIS_TSF_UDT0);
1398 }
1399
1400 /* Make link LED blink during scan. */
1401 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink);
1402
1403 /* Pause AC Tx queues. */
1404 rtwn_write_1(sc, R92C_TXPAUSE,
1405 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1406
1407 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1408
1409 /* Start periodic scan. */
1410 callout_schedule(&sc->scan_to, mstohz(200));
1411 break;
1412
1413 case IEEE80211_S_AUTH:
1414 /* Set initial gain under link. */
1415 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1416 #ifdef doaslinux
1417 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1418 #else
1419 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1420 #endif
1421 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1422
1423 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1424 #ifdef doaslinux
1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1426 #else
1427 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1428 #endif
1429 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1430
1431 /* Set media status to 'No Link'. */
1432 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1433
1434 /* Allow Rx from any BSSID. */
1435 rtwn_write_4(sc, R92C_RCR,
1436 rtwn_read_4(sc, R92C_RCR) &
1437 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1438
1439 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1440 break;
1441
1442 case IEEE80211_S_ASSOC:
1443 break;
1444
1445 case IEEE80211_S_RUN:
1446 ni = ic->ic_bss;
1447
1448 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1449
1450 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1451 /* Back to 20Mhz mode */
1452 rtwn_set_chan(sc, ic->ic_curchan, NULL);
1453
1454 /* Set media status to 'No Link'. */
1455 rtwn_set_nettype0_msr(sc, R92C_CR_NETTYPE_NOLINK);
1456
1457 /* Enable Rx of data frames. */
1458 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1459
1460 /* Allow Rx from any BSSID. */
1461 rtwn_write_4(sc, R92C_RCR,
1462 rtwn_read_4(sc, R92C_RCR) &
1463 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1464
1465 /* Accept Rx data/control/management frames */
1466 rtwn_write_4(sc, R92C_RCR,
1467 rtwn_read_4(sc, R92C_RCR) |
1468 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF);
1469
1470 /* Turn link LED on. */
1471 rtwn_set_led(sc, RTWN_LED_LINK, 1);
1472 break;
1473 }
1474
1475 /* Set media status to 'Associated'. */
1476 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc));
1477
1478 /* Set BSSID. */
1479 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
1480 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
1481
1482 if (ic->ic_curmode == IEEE80211_MODE_11B)
1483 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
1484 else /* 802.11b/g */
1485 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
1486
1487 /* Enable Rx of data frames. */
1488 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1489
1490 /* Flush all AC queues. */
1491 rtwn_write_1(sc, R92C_TXPAUSE, 0);
1492
1493 /* Set beacon interval. */
1494 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
1495
1496 switch (ic->ic_opmode) {
1497 case IEEE80211_M_STA:
1498 /* Allow Rx from our BSSID only. */
1499 rtwn_write_4(sc, R92C_RCR,
1500 rtwn_read_4(sc, R92C_RCR) |
1501 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1502
1503 /* Enable TSF synchronization. */
1504 rtwn_tsf_sync_enable(sc);
1505 break;
1506
1507 case IEEE80211_M_HOSTAP:
1508 rtwn_write_2(sc, R92C_BCNTCFG, 0x000f);
1509
1510 /* Allow Rx from any BSSID. */
1511 rtwn_write_4(sc, R92C_RCR,
1512 rtwn_read_4(sc, R92C_RCR) &
1513 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1514
1515 /* Reset TSF timer to zero. */
1516 reg = rtwn_read_4(sc, R92C_TCR);
1517 reg &= ~0x01;
1518 rtwn_write_4(sc, R92C_TCR, reg);
1519 reg |= 0x01;
1520 rtwn_write_4(sc, R92C_TCR, reg);
1521 break;
1522
1523 case IEEE80211_M_MONITOR:
1524 default:
1525 break;
1526 }
1527
1528 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
1529 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
1530 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
1531 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
1532 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
1533 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
1534
1535 /* Initialize rate adaptation. */
1536 rtwn_ra_init(sc);
1537
1538 /* Turn link LED on. */
1539 rtwn_set_led(sc, RTWN_LED_LINK, 1);
1540
1541 /* Reset average RSSI. */
1542 sc->avg_pwdb = -1;
1543
1544 /* Reset temperature calibration state machine. */
1545 sc->thcal_state = 0;
1546 sc->thcal_lctemp = 0;
1547
1548 /* Start periodic calibration. */
1549 callout_schedule(&sc->calib_to, mstohz(2000));
1550 break;
1551 }
1552
1553 (void)sc->sc_newstate(ic, nstate, arg);
1554
1555 splx(s);
1556
1557 return 0;
1558 }
1559
1560 static int
rtwn_wme_update(struct ieee80211com * ic)1561 rtwn_wme_update(struct ieee80211com *ic)
1562 {
1563 static const uint16_t aci2reg[WME_NUM_AC] = {
1564 R92C_EDCA_BE_PARAM,
1565 R92C_EDCA_BK_PARAM,
1566 R92C_EDCA_VI_PARAM,
1567 R92C_EDCA_VO_PARAM
1568 };
1569 struct rtwn_softc *sc = IC2IFP(ic)->if_softc;
1570 const struct wmeParams *wmep;
1571 int s, aci, aifs, slottime;
1572
1573 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1574
1575 s = splnet();
1576 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1577 for (aci = 0; aci < WME_NUM_AC; aci++) {
1578 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[aci];
1579 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */
1580 aifs = wmep->wmep_aifsn * slottime + 10;
1581 rtwn_write_4(sc, aci2reg[aci],
1582 SM(R92C_EDCA_PARAM_TXOP, wmep->wmep_txopLimit) |
1583 SM(R92C_EDCA_PARAM_ECWMIN, wmep->wmep_logcwmin) |
1584 SM(R92C_EDCA_PARAM_ECWMAX, wmep->wmep_logcwmax) |
1585 SM(R92C_EDCA_PARAM_AIFS, aifs));
1586 }
1587 splx(s);
1588
1589 return 0;
1590 }
1591
1592 static void
rtwn_update_avgrssi(struct rtwn_softc * sc,int rate,int8_t rssi)1593 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi)
1594 {
1595 int pwdb;
1596
1597 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1598
1599 /* Convert antenna signal to percentage. */
1600 if (rssi <= -100 || rssi >= 20)
1601 pwdb = 0;
1602 else if (rssi >= 0)
1603 pwdb = 100;
1604 else
1605 pwdb = 100 + rssi;
1606 if (rate <= 3) {
1607 /* CCK gain is smaller than OFDM/MCS gain. */
1608 pwdb += 6;
1609 if (pwdb > 100)
1610 pwdb = 100;
1611 if (pwdb <= 14)
1612 pwdb -= 4;
1613 else if (pwdb <= 26)
1614 pwdb -= 8;
1615 else if (pwdb <= 34)
1616 pwdb -= 6;
1617 else if (pwdb <= 42)
1618 pwdb -= 2;
1619 }
1620 if (sc->avg_pwdb == -1) /* Init. */
1621 sc->avg_pwdb = pwdb;
1622 else if (sc->avg_pwdb < pwdb)
1623 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
1624 else
1625 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
1626 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb));
1627 }
1628
1629 static int8_t
rtwn_get_rssi(struct rtwn_softc * sc,int rate,void * physt)1630 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt)
1631 {
1632 static const int8_t cckoff[] = { 16, -12, -26, -46 };
1633 struct r92c_rx_phystat *phy;
1634 struct r92c_rx_cck *cck;
1635 uint8_t rpt;
1636 int8_t rssi;
1637
1638 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1639
1640 if (rate <= 3) {
1641 cck = (struct r92c_rx_cck *)physt;
1642 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) {
1643 rpt = (cck->agc_rpt >> 5) & 0x3;
1644 rssi = (cck->agc_rpt & 0x1f) << 1;
1645 } else {
1646 rpt = (cck->agc_rpt >> 6) & 0x3;
1647 rssi = cck->agc_rpt & 0x3e;
1648 }
1649 rssi = cckoff[rpt] - rssi;
1650 } else { /* OFDM/HT. */
1651 phy = (struct r92c_rx_phystat *)physt;
1652 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1653 }
1654 return rssi;
1655 }
1656
1657 static void
rtwn_rx_frame(struct rtwn_softc * sc,struct r92c_rx_desc_pci * rx_desc,struct rtwn_rx_data * rx_data,int desc_idx)1658 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc_pci *rx_desc,
1659 struct rtwn_rx_data *rx_data, int desc_idx)
1660 {
1661 struct ieee80211com *ic = &sc->sc_ic;
1662 struct ifnet *ifp = IC2IFP(ic);
1663 struct ieee80211_frame *wh;
1664 struct ieee80211_node *ni;
1665 struct r92c_rx_phystat *phy = NULL;
1666 uint32_t rxdw0, rxdw3;
1667 struct mbuf *m, *m1;
1668 uint8_t rate;
1669 int8_t rssi = 0;
1670 int infosz, pktlen, shift, totlen, error, s;
1671
1672 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1673
1674 rxdw0 = le32toh(rx_desc->rxdw0);
1675 rxdw3 = le32toh(rx_desc->rxdw3);
1676
1677 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) {
1678 /*
1679 * This should not happen since we setup our Rx filter
1680 * to not receive these frames.
1681 */
1682 if_statinc(ifp, if_ierrors);
1683 return;
1684 }
1685
1686 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
1687 /*
1688 * XXX: This will drop most control packets. Do we really
1689 * want this in IEEE80211_M_MONITOR mode?
1690 */
1691 if (__predict_false(pktlen < (int)sizeof(struct ieee80211_frame_ack))) {
1692 ic->ic_stats.is_rx_tooshort++;
1693 if_statinc(ifp, if_ierrors);
1694 return;
1695 }
1696 if (__predict_false(pktlen > MCLBYTES)) {
1697 if_statinc(ifp, if_ierrors);
1698 return;
1699 }
1700
1701 rate = MS(rxdw3, R92C_RXDW3_RATE);
1702 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
1703 if (infosz > sizeof(struct r92c_rx_phystat))
1704 infosz = sizeof(struct r92c_rx_phystat);
1705 shift = MS(rxdw0, R92C_RXDW0_SHIFT);
1706 totlen = pktlen + infosz + shift;
1707
1708 /* Get RSSI from PHY status descriptor if present. */
1709 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
1710 phy = mtod(rx_data->m, struct r92c_rx_phystat *);
1711 rssi = rtwn_get_rssi(sc, rate, phy);
1712 /* Update our average RSSI. */
1713 rtwn_update_avgrssi(sc, rate, rssi);
1714 }
1715
1716 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n",
1717 pktlen, rate, infosz, shift, rssi));
1718
1719 MGETHDR(m1, M_DONTWAIT, MT_DATA);
1720 if (__predict_false(m1 == NULL)) {
1721 ic->ic_stats.is_rx_nobuf++;
1722 if_statinc(ifp, if_ierrors);
1723 return;
1724 }
1725 MCLGET(m1, M_DONTWAIT);
1726 if (__predict_false(!(m1->m_flags & M_EXT))) {
1727 m_freem(m1);
1728 ic->ic_stats.is_rx_nobuf++;
1729 if_statinc(ifp, if_ierrors);
1730 return;
1731 }
1732
1733 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, totlen,
1734 BUS_DMASYNC_POSTREAD);
1735
1736 bus_dmamap_unload(sc->sc_dmat, rx_data->map);
1737 error = bus_dmamap_load(sc->sc_dmat, rx_data->map, mtod(m1, void *),
1738 MCLBYTES, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ);
1739 if (error != 0) {
1740 m_freem(m1);
1741
1742 if (bus_dmamap_load_mbuf(sc->sc_dmat, rx_data->map,
1743 rx_data->m, BUS_DMA_NOWAIT))
1744 panic("%s: could not load old RX mbuf",
1745 device_xname(sc->sc_dev));
1746
1747 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES,
1748 BUS_DMASYNC_PREREAD);
1749
1750 /* Physical address may have changed. */
1751 rtwn_setup_rx_desc(sc, rx_desc,
1752 rx_data->map->dm_segs[0].ds_addr, MCLBYTES, desc_idx);
1753
1754 if_statinc(ifp, if_ierrors);
1755 return;
1756 }
1757
1758 /* Finalize mbuf. */
1759 m = rx_data->m;
1760 rx_data->m = m1;
1761 m->m_pkthdr.len = m->m_len = totlen;
1762 m_set_rcvif(m, ifp);
1763
1764 bus_dmamap_sync(sc->sc_dmat, rx_data->map, 0, MCLBYTES,
1765 BUS_DMASYNC_PREREAD);
1766
1767 /* Update RX descriptor. */
1768 rtwn_setup_rx_desc(sc, rx_desc, rx_data->map->dm_segs[0].ds_addr,
1769 MCLBYTES, desc_idx);
1770
1771 /* Get ieee80211 frame header. */
1772 if (rxdw0 & R92C_RXDW0_PHYST)
1773 m_adj(m, infosz + shift);
1774 else
1775 m_adj(m, shift);
1776 wh = mtod(m, struct ieee80211_frame *);
1777
1778 s = splnet();
1779
1780 if (__predict_false(sc->sc_drvbpf != NULL)) {
1781 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
1782
1783 tap->wr_flags = 0;
1784 /* Map HW rate index to 802.11 rate. */
1785 tap->wr_flags = 2;
1786 if (!(rxdw3 & R92C_RXDW3_HT)) {
1787 switch (rate) {
1788 /* CCK. */
1789 case 0: tap->wr_rate = 2; break;
1790 case 1: tap->wr_rate = 4; break;
1791 case 2: tap->wr_rate = 11; break;
1792 case 3: tap->wr_rate = 22; break;
1793 /* OFDM. */
1794 case 4: tap->wr_rate = 12; break;
1795 case 5: tap->wr_rate = 18; break;
1796 case 6: tap->wr_rate = 24; break;
1797 case 7: tap->wr_rate = 36; break;
1798 case 8: tap->wr_rate = 48; break;
1799 case 9: tap->wr_rate = 72; break;
1800 case 10: tap->wr_rate = 96; break;
1801 case 11: tap->wr_rate = 108; break;
1802 }
1803 } else if (rate >= 12) { /* MCS0~15. */
1804 /* Bit 7 set means HT MCS instead of rate. */
1805 tap->wr_rate = 0x80 | (rate - 12);
1806 }
1807 tap->wr_dbm_antsignal = rssi;
1808 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
1809 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
1810
1811 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m, BPF_D_IN);
1812 }
1813
1814 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
1815
1816 /* push the frame up to the 802.11 stack */
1817 ieee80211_input(ic, m, ni, rssi, 0);
1818
1819 /* Node is no longer needed. */
1820 ieee80211_free_node(ni);
1821
1822 splx(s);
1823 }
1824
1825 static int
rtwn_tx(struct rtwn_softc * sc,struct mbuf * m,struct ieee80211_node * ni)1826 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1827 {
1828 struct ieee80211com *ic = &sc->sc_ic;
1829 struct ieee80211_frame *wh;
1830 struct ieee80211_key *k = NULL;
1831 struct rtwn_tx_ring *tx_ring;
1832 struct rtwn_tx_data *data;
1833 struct r92c_tx_desc_pci *txd;
1834 uint16_t qos, seq;
1835 uint8_t raid, type, tid, qid;
1836 int hasqos, error;
1837
1838 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
1839
1840 wh = mtod(m, struct ieee80211_frame *);
1841 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1842
1843 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1844 k = ieee80211_crypto_encap(ic, ni, m);
1845 if (k == NULL)
1846 return ENOBUFS;
1847
1848 wh = mtod(m, struct ieee80211_frame *);
1849 }
1850
1851 if ((hasqos = ieee80211_has_qos(wh))) {
1852 /* data frames in 11n mode */
1853 qos = ieee80211_get_qos(wh);
1854 tid = qos & IEEE80211_QOS_TID;
1855 qid = TID_TO_WME_AC(tid);
1856 } else if (type != IEEE80211_FC0_TYPE_DATA) {
1857 /* Use AC_VO for management frames. */
1858 tid = 0; /* compiler happy */
1859 qid = RTWN_VO_QUEUE;
1860 } else {
1861 /* non-qos data frames */
1862 tid = R92C_TXDW1_QSEL_BE;
1863 qid = RTWN_BE_QUEUE;
1864 }
1865
1866 /* Grab a Tx buffer from the ring. */
1867 tx_ring = &sc->tx_ring[qid];
1868 data = &tx_ring->tx_data[tx_ring->cur];
1869 if (data->m != NULL) {
1870 m_freem(m);
1871 return ENOBUFS;
1872 }
1873
1874 /* Fill Tx descriptor. */
1875 txd = &tx_ring->desc[tx_ring->cur];
1876 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) {
1877 m_freem(m);
1878 return ENOBUFS;
1879 }
1880
1881 txd->txdw0 = htole32(
1882 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) |
1883 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1884 R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1885 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1886 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
1887
1888 txd->txdw1 = 0;
1889 txd->txdw4 = 0;
1890 txd->txdw5 = 0;
1891 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1892 type == IEEE80211_FC0_TYPE_DATA) {
1893 if (ic->ic_curmode == IEEE80211_MODE_11B)
1894 raid = R92C_RAID_11B;
1895 else
1896 raid = R92C_RAID_11BG;
1897
1898 txd->txdw1 |= htole32(
1899 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) |
1900 SM(R92C_TXDW1_QSEL, tid) |
1901 SM(R92C_TXDW1_RAID, raid) |
1902 R92C_TXDW1_AGGBK);
1903
1904 if (ic->ic_flags & IEEE80211_F_USEPROT) {
1905 /* for 11g */
1906 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1907 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1908 R92C_TXDW4_HWRTSEN);
1909 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1910 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1911 R92C_TXDW4_HWRTSEN);
1912 }
1913 }
1914 /* Send RTS at OFDM24. */
1915 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
1916 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf));
1917 /* Send data at OFDM54. */
1918 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
1919 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f));
1920 } else if (type == IEEE80211_FC0_TYPE_MGT) {
1921 txd->txdw1 |= htole32(
1922 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) |
1923 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1924 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1925
1926 /* Force CCK1. */
1927 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1928 /* Use 1Mbps */
1929 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
1930 } else {
1931 txd->txdw1 |= htole32(
1932 SM(R92C_TXDW1_MACID, RTWN_MACID_BC) |
1933 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1934
1935 /* Force CCK1. */
1936 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1937 /* Use 1Mbps */
1938 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
1939 }
1940
1941 /* Set sequence number (already little endian). */
1942 seq = LE_READ_2(&wh->i_seq[0]) >> IEEE80211_SEQ_SEQ_SHIFT;
1943 txd->txdseq = htole16(seq);
1944
1945 if (!hasqos) {
1946 /* Use HW sequence numbering for non-QoS frames. */
1947 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ);
1948 txd->txdseq |= htole16(0x8000); /* WTF? */
1949 } else
1950 txd->txdw4 |= htole32(R92C_TXDW4_QOS);
1951
1952 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m,
1953 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
1954 if (error && error != EFBIG) {
1955 aprint_error_dev(sc->sc_dev, "can't map mbuf (error %d)\n",
1956 error);
1957 m_freem(m);
1958 return error;
1959 }
1960 if (error != 0) {
1961 /* Too many DMA segments, linearize mbuf. */
1962 struct mbuf *newm = m_defrag(m, M_DONTWAIT);
1963 if (newm == NULL) {
1964 aprint_error_dev(sc->sc_dev, "can't defrag mbuf\n");
1965 m_freem(m);
1966 return ENOBUFS;
1967 }
1968 m = newm;
1969
1970 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m,
1971 BUS_DMA_NOWAIT | BUS_DMA_WRITE);
1972 if (error != 0) {
1973 aprint_error_dev(sc->sc_dev,
1974 "can't map mbuf (error %d)\n", error);
1975 m_freem(m);
1976 return error;
1977 }
1978 }
1979
1980 txd->txbufaddr = htole32(data->map->dm_segs[0].ds_addr);
1981 txd->txbufsize = htole16(m->m_pkthdr.len);
1982 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize,
1983 BUS_SPACE_BARRIER_WRITE);
1984 txd->txdw0 |= htole32(R92C_TXDW0_OWN);
1985
1986 bus_dmamap_sync(sc->sc_dmat, tx_ring->map, 0,
1987 sizeof(*txd) * RTWN_TX_LIST_COUNT, BUS_DMASYNC_PREWRITE);
1988 bus_dmamap_sync(sc->sc_dmat, data->map, 0, m->m_pkthdr.len,
1989 BUS_DMASYNC_PREWRITE);
1990
1991 data->m = m;
1992 data->ni = ni;
1993
1994 if (__predict_false(sc->sc_drvbpf != NULL)) {
1995 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap;
1996
1997 tap->wt_flags = 0;
1998 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1999 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2000 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
2001 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2002
2003 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m, BPF_D_OUT);
2004 }
2005
2006 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT;
2007 tx_ring->queued++;
2008
2009 if (tx_ring->queued > RTWN_TX_LIST_HIMARK)
2010 sc->qfullmsk |= (1 << qid);
2011
2012 /* Kick TX. */
2013 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid));
2014
2015 return 0;
2016 }
2017
2018 static void
rtwn_tx_done(struct rtwn_softc * sc,int qid)2019 rtwn_tx_done(struct rtwn_softc *sc, int qid)
2020 {
2021 struct ieee80211com *ic = &sc->sc_ic;
2022 struct ifnet *ifp = IC2IFP(ic);
2023 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
2024 struct rtwn_tx_data *tx_data;
2025 struct r92c_tx_desc_pci *tx_desc;
2026 int i, s;
2027
2028 DPRINTFN(3, ("%s: %s: qid=%d\n", device_xname(sc->sc_dev), __func__,
2029 qid));
2030
2031 s = splnet();
2032
2033 bus_dmamap_sync(sc->sc_dmat, tx_ring->map,
2034 0, sizeof(*tx_desc) * RTWN_TX_LIST_COUNT,
2035 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2036
2037 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
2038 tx_data = &tx_ring->tx_data[i];
2039 if (tx_data->m == NULL)
2040 continue;
2041
2042 tx_desc = &tx_ring->desc[i];
2043 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN)
2044 continue;
2045
2046 bus_dmamap_unload(sc->sc_dmat, tx_data->map);
2047 m_freem(tx_data->m);
2048 tx_data->m = NULL;
2049 ieee80211_free_node(tx_data->ni);
2050 tx_data->ni = NULL;
2051
2052 if_statinc(ifp, if_opackets);
2053 sc->sc_tx_timer = 0;
2054 tx_ring->queued--;
2055 }
2056
2057 if (tx_ring->queued < RTWN_TX_LIST_LOMARK)
2058 sc->qfullmsk &= ~(1 << qid);
2059
2060 splx(s);
2061 }
2062
2063 static void
rtwn_start(struct ifnet * ifp)2064 rtwn_start(struct ifnet *ifp)
2065 {
2066 struct rtwn_softc *sc = ifp->if_softc;
2067 struct ieee80211com *ic = &sc->sc_ic;
2068 struct ether_header *eh;
2069 struct ieee80211_node *ni;
2070 struct mbuf *m;
2071
2072 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2073 return;
2074
2075 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2076
2077 for (;;) {
2078 if (sc->qfullmsk != 0) {
2079 ifp->if_flags |= IFF_OACTIVE;
2080 break;
2081 }
2082 /* Send pending management frames first. */
2083 IF_DEQUEUE(&ic->ic_mgtq, m);
2084 if (m != NULL) {
2085 ni = M_GETCTX(m, struct ieee80211_node *);
2086 M_CLEARCTX(m);
2087 goto sendit;
2088 }
2089 if (ic->ic_state != IEEE80211_S_RUN)
2090 break;
2091
2092 /* Encapsulate and send data frames. */
2093 IFQ_DEQUEUE(&ifp->if_snd, m);
2094 if (m == NULL)
2095 break;
2096
2097 if (m->m_len < (int)sizeof(*eh) &&
2098 (m = m_pullup(m, sizeof(*eh))) == NULL) {
2099 if_statinc(ifp, if_oerrors);
2100 continue;
2101 }
2102 eh = mtod(m, struct ether_header *);
2103 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
2104 if (ni == NULL) {
2105 m_freem(m);
2106 if_statinc(ifp, if_oerrors);
2107 continue;
2108 }
2109
2110 bpf_mtap(ifp, m, BPF_D_OUT);
2111
2112 if ((m = ieee80211_encap(ic, m, ni)) == NULL) {
2113 ieee80211_free_node(ni);
2114 if_statinc(ifp, if_oerrors);
2115 continue;
2116 }
2117 sendit:
2118 bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT);
2119
2120 if (rtwn_tx(sc, m, ni) != 0) {
2121 ieee80211_free_node(ni);
2122 if_statinc(ifp, if_oerrors);
2123 continue;
2124 }
2125
2126 sc->sc_tx_timer = 5;
2127 ifp->if_timer = 1;
2128 }
2129
2130 DPRINTFN(3, ("%s: %s done\n", device_xname(sc->sc_dev), __func__));
2131 }
2132
2133 static void
rtwn_watchdog(struct ifnet * ifp)2134 rtwn_watchdog(struct ifnet *ifp)
2135 {
2136 struct rtwn_softc *sc = ifp->if_softc;
2137 struct ieee80211com *ic = &sc->sc_ic;
2138
2139 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2140
2141 ifp->if_timer = 0;
2142
2143 if (sc->sc_tx_timer > 0) {
2144 if (--sc->sc_tx_timer == 0) {
2145 aprint_error_dev(sc->sc_dev, "device timeout\n");
2146 softint_schedule(sc->init_task);
2147 if_statinc(ifp, if_oerrors);
2148 return;
2149 }
2150 ifp->if_timer = 1;
2151 }
2152 ieee80211_watchdog(ic);
2153 }
2154
2155 static int
rtwn_ioctl(struct ifnet * ifp,u_long cmd,void * data)2156 rtwn_ioctl(struct ifnet *ifp, u_long cmd, void *data)
2157 {
2158 struct rtwn_softc *sc = ifp->if_softc;
2159 struct ieee80211com *ic = &sc->sc_ic;
2160 int s, error = 0;
2161
2162 DPRINTFN(3, ("%s: %s: cmd=0x%08lx, data=%p\n", device_xname(sc->sc_dev),
2163 __func__, cmd, data));
2164
2165 s = splnet();
2166
2167 switch (cmd) {
2168 case SIOCSIFFLAGS:
2169 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
2170 break;
2171 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
2172 case IFF_UP | IFF_RUNNING:
2173 break;
2174 case IFF_UP:
2175 error = rtwn_init(ifp);
2176 if (error != 0)
2177 ifp->if_flags &= ~IFF_UP;
2178 break;
2179 case IFF_RUNNING:
2180 rtwn_stop(ifp, 1);
2181 break;
2182 case 0:
2183 break;
2184 }
2185 break;
2186
2187 case SIOCADDMULTI:
2188 case SIOCDELMULTI:
2189 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
2190 /* setup multicast filter, etc */
2191 error = 0;
2192 }
2193 break;
2194
2195 case SIOCS80211CHANNEL:
2196 error = ieee80211_ioctl(ic, cmd, data);
2197 if (error == ENETRESET &&
2198 ic->ic_opmode == IEEE80211_M_MONITOR) {
2199 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
2200 (IFF_UP | IFF_RUNNING)) {
2201 rtwn_set_chan(sc, ic->ic_curchan, NULL);
2202 }
2203 error = 0;
2204 }
2205 break;
2206
2207 default:
2208 error = ieee80211_ioctl(ic, cmd, data);
2209 break;
2210 }
2211
2212 if (error == ENETRESET) {
2213 error = 0;
2214 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
2215 (IFF_UP | IFF_RUNNING)) {
2216 rtwn_stop(ifp, 0);
2217 error = rtwn_init(ifp);
2218 }
2219 }
2220
2221 splx(s);
2222
2223 DPRINTFN(3, ("%s: %s: error=%d\n", device_xname(sc->sc_dev), __func__,
2224 error));
2225
2226 return error;
2227 }
2228
2229 static int
rtwn_power_on(struct rtwn_softc * sc)2230 rtwn_power_on(struct rtwn_softc *sc)
2231 {
2232 uint32_t reg;
2233 int ntries;
2234
2235 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2236
2237 /* Wait for autoload done bit. */
2238 for (ntries = 0; ntries < 1000; ntries++) {
2239 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
2240 break;
2241 DELAY(5);
2242 }
2243 if (ntries == 1000) {
2244 aprint_error_dev(sc->sc_dev,
2245 "timeout waiting for chip autoload\n");
2246 return ETIMEDOUT;
2247 }
2248
2249 /* Unlock ISO/CLK/Power control register. */
2250 rtwn_write_1(sc, R92C_RSV_CTRL, 0);
2251
2252 /* TODO: check if we need this for 8188CE */
2253 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) {
2254 /* bt coex */
2255 reg = rtwn_read_4(sc, R92C_APS_FSMCO);
2256 reg |= (R92C_APS_FSMCO_SOP_ABG |
2257 R92C_APS_FSMCO_SOP_AMB |
2258 R92C_APS_FSMCO_XOP_BTCK);
2259 rtwn_write_4(sc, R92C_APS_FSMCO, reg);
2260 }
2261
2262 /* Move SPS into PWM mode. */
2263 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
2264 DELAY(100);
2265
2266 /* Set low byte to 0x0f, leave others unchanged. */
2267 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL,
2268 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f);
2269
2270 /* TODO: check if we need this for 8188CE */
2271 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) {
2272 /* bt coex */
2273 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL);
2274 reg &= ~0x00024800; /* XXX magic from linux */
2275 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg);
2276 }
2277
2278 rtwn_write_2(sc, R92C_SYS_ISO_CTRL,
2279 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) |
2280 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR);
2281 DELAY(200);
2282
2283 /* TODO: linux does additional btcoex stuff here */
2284
2285 /* Auto enable WLAN. */
2286 rtwn_write_2(sc, R92C_APS_FSMCO,
2287 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
2288 for (ntries = 0; ntries < 1000; ntries++) {
2289 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
2290 R92C_APS_FSMCO_APFM_ONMAC))
2291 break;
2292 DELAY(5);
2293 }
2294 if (ntries == 1000) {
2295 aprint_error_dev(sc->sc_dev,
2296 "timeout waiting for MAC auto ON\n");
2297 return ETIMEDOUT;
2298 }
2299
2300 /* Enable radio, GPIO and LED functions. */
2301 rtwn_write_2(sc, R92C_APS_FSMCO,
2302 R92C_APS_FSMCO_AFSM_PCIE |
2303 R92C_APS_FSMCO_PDN_EN |
2304 R92C_APS_FSMCO_PFM_ALDN);
2305
2306 /* Release RF digital isolation. */
2307 rtwn_write_2(sc, R92C_SYS_ISO_CTRL,
2308 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
2309
2310 if (sc->chip & RTWN_CHIP_92C)
2311 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77);
2312 else
2313 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22);
2314
2315 rtwn_write_4(sc, R92C_INT_MIG, 0);
2316
2317 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) {
2318 /* bt coex */
2319 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2);
2320 reg &= 0xfd; /* XXX magic from linux */
2321 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg);
2322 }
2323
2324 rtwn_write_1(sc, R92C_GPIO_MUXCFG,
2325 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL);
2326
2327 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
2328 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) {
2329 aprint_error_dev(sc->sc_dev,
2330 "radio is disabled by hardware switch\n");
2331 return EPERM; /* :-) */
2332 }
2333
2334 /* Initialize MAC. */
2335 reg = rtwn_read_1(sc, R92C_APSD_CTRL);
2336 rtwn_write_1(sc, R92C_APSD_CTRL,
2337 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
2338 for (ntries = 0; ntries < 200; ntries++) {
2339 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
2340 R92C_APSD_CTRL_OFF_STATUS))
2341 break;
2342 DELAY(500);
2343 }
2344 if (ntries == 200) {
2345 aprint_error_dev(sc->sc_dev,
2346 "timeout waiting for MAC initialization\n");
2347 return ETIMEDOUT;
2348 }
2349
2350 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
2351 reg = rtwn_read_2(sc, R92C_CR);
2352 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
2353 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
2354 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
2355 R92C_CR_ENSEC;
2356 rtwn_write_2(sc, R92C_CR, reg);
2357
2358 rtwn_write_1(sc, 0xfe10, 0x19);
2359
2360 return 0;
2361 }
2362
2363 static int
rtwn_llt_init(struct rtwn_softc * sc)2364 rtwn_llt_init(struct rtwn_softc *sc)
2365 {
2366 int i, error;
2367
2368 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2369
2370 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */
2371 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) {
2372 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0)
2373 return error;
2374 }
2375 /* NB: 0xff indicates end-of-list. */
2376 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0)
2377 return error;
2378 /*
2379 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1]
2380 * as ring buffer.
2381 */
2382 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) {
2383 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0)
2384 return error;
2385 }
2386 /* Make the last page point to the beginning of the ring buffer. */
2387 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1);
2388 return error;
2389 }
2390
2391 static void
rtwn_fw_reset(struct rtwn_softc * sc)2392 rtwn_fw_reset(struct rtwn_softc *sc)
2393 {
2394 uint16_t reg;
2395 int ntries;
2396
2397 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2398
2399 /* Tell 8051 to reset itself. */
2400 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
2401
2402 /* Wait until 8051 resets by itself. */
2403 for (ntries = 0; ntries < 100; ntries++) {
2404 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
2405 if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
2406 goto sleep;
2407 DELAY(50);
2408 }
2409 /* Force 8051 reset. */
2410 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
2411 sleep:
2412 CLR(sc->sc_flags, RTWN_FLAG_FW_LOADED);
2413 #if 0
2414 /*
2415 * We must sleep for one second to let the firmware settle.
2416 * Accessing registers too early will hang the whole system.
2417 */
2418 tsleep(®, 0, "rtwnrst", hz);
2419 #else
2420 DELAY(1000 * 1000);
2421 #endif
2422 }
2423
2424 static int
rtwn_fw_loadpage(struct rtwn_softc * sc,int page,uint8_t * buf,int len)2425 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, uint8_t *buf, int len)
2426 {
2427 uint32_t reg;
2428 int off, mlen, error = 0, i;
2429
2430 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2431
2432 reg = rtwn_read_4(sc, R92C_MCUFWDL);
2433 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
2434 rtwn_write_4(sc, R92C_MCUFWDL, reg);
2435
2436 DELAY(5);
2437
2438 off = R92C_FW_START_ADDR;
2439 while (len > 0) {
2440 if (len > 196)
2441 mlen = 196;
2442 else if (len > 4)
2443 mlen = 4;
2444 else
2445 mlen = 1;
2446 for (i = 0; i < mlen; i++)
2447 rtwn_write_1(sc, off++, buf[i]);
2448 buf += mlen;
2449 len -= mlen;
2450 }
2451
2452 return error;
2453 }
2454
2455 static int
rtwn_load_firmware(struct rtwn_softc * sc)2456 rtwn_load_firmware(struct rtwn_softc *sc)
2457 {
2458 firmware_handle_t fwh;
2459 const struct r92c_fw_hdr *hdr;
2460 const char *name;
2461 u_char *fw, *ptr;
2462 size_t len;
2463 uint32_t reg;
2464 int mlen, ntries, page, error;
2465
2466 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2467
2468 /* Read firmware image from the filesystem. */
2469 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) ==
2470 RTWN_CHIP_UMC_A_CUT)
2471 name = "rtl8192cfwU.bin";
2472 else if (sc->chip & RTWN_CHIP_UMC_B_CUT)
2473 name = "rtl8192cfwU_B.bin";
2474 else
2475 name = "rtl8192cfw.bin";
2476 DPRINTF(("%s: firmware: %s\n", device_xname(sc->sc_dev), name));
2477 if ((error = firmware_open("if_rtwn", name, &fwh)) != 0) {
2478 aprint_error_dev(sc->sc_dev,
2479 "could not read firmware %s (error %d)\n", name, error);
2480 return error;
2481 }
2482 const size_t fwlen = len = firmware_get_size(fwh);
2483 fw = firmware_malloc(len);
2484 if (fw == NULL) {
2485 aprint_error_dev(sc->sc_dev,
2486 "failed to allocate firmware memory (size=%zu)\n", len);
2487 firmware_close(fwh);
2488 return ENOMEM;
2489 }
2490 error = firmware_read(fwh, 0, fw, len);
2491 firmware_close(fwh);
2492 if (error != 0) {
2493 aprint_error_dev(sc->sc_dev,
2494 "failed to read firmware (error %d)\n", error);
2495 firmware_free(fw, fwlen);
2496 return error;
2497 }
2498
2499 if (len < sizeof(*hdr)) {
2500 aprint_error_dev(sc->sc_dev, "firmware too short\n");
2501 error = EINVAL;
2502 goto fail;
2503 }
2504 ptr = fw;
2505 hdr = (const struct r92c_fw_hdr *)ptr;
2506 /* Check if there is a valid FW header and skip it. */
2507 if ((le16toh(hdr->signature) >> 4) == 0x88c ||
2508 (le16toh(hdr->signature) >> 4) == 0x92c) {
2509 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n",
2510 le16toh(hdr->version), le16toh(hdr->subversion),
2511 hdr->month, hdr->date, hdr->hour, hdr->minute));
2512 ptr += sizeof(*hdr);
2513 len -= sizeof(*hdr);
2514 }
2515
2516 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
2517 rtwn_fw_reset(sc);
2518
2519 /* Enable FW download. */
2520 rtwn_write_2(sc, R92C_SYS_FUNC_EN,
2521 rtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2522 R92C_SYS_FUNC_EN_CPUEN);
2523 rtwn_write_1(sc, R92C_MCUFWDL,
2524 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
2525 rtwn_write_1(sc, R92C_MCUFWDL + 2,
2526 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
2527
2528 /* Reset the FWDL checksum. */
2529 rtwn_write_1(sc, R92C_MCUFWDL,
2530 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
2531
2532 /* download firmware */
2533 for (page = 0; len > 0; page++) {
2534 mlen = MIN(len, R92C_FW_PAGE_SIZE);
2535 error = rtwn_fw_loadpage(sc, page, ptr, mlen);
2536 if (error != 0) {
2537 aprint_error_dev(sc->sc_dev,
2538 "could not load firmware page %d\n", page);
2539 goto fail;
2540 }
2541 ptr += mlen;
2542 len -= mlen;
2543 }
2544
2545 /* Disable FW download. */
2546 rtwn_write_1(sc, R92C_MCUFWDL,
2547 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
2548 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
2549
2550 /* Wait for checksum report. */
2551 for (ntries = 0; ntries < 1000; ntries++) {
2552 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
2553 break;
2554 DELAY(5);
2555 }
2556 if (ntries == 1000) {
2557 aprint_error_dev(sc->sc_dev,
2558 "timeout waiting for checksum report\n");
2559 error = ETIMEDOUT;
2560 goto fail;
2561 }
2562
2563 reg = rtwn_read_4(sc, R92C_MCUFWDL);
2564 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
2565 rtwn_write_4(sc, R92C_MCUFWDL, reg);
2566
2567 /* Wait for firmware readiness. */
2568 for (ntries = 0; ntries < 1000; ntries++) {
2569 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
2570 break;
2571 DELAY(5);
2572 }
2573 if (ntries == 1000) {
2574 aprint_error_dev(sc->sc_dev,
2575 "timeout waiting for firmware readiness\n");
2576 error = ETIMEDOUT;
2577 goto fail;
2578 }
2579 SET(sc->sc_flags, RTWN_FLAG_FW_LOADED);
2580
2581 fail:
2582 firmware_free(fw, fwlen);
2583 return error;
2584 }
2585
2586 static int
rtwn_dma_init(struct rtwn_softc * sc)2587 rtwn_dma_init(struct rtwn_softc *sc)
2588 {
2589 uint32_t reg;
2590 int error;
2591
2592 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2593
2594 /* Initialize LLT table. */
2595 error = rtwn_llt_init(sc);
2596 if (error != 0)
2597 return error;
2598
2599 /* Set number of pages for normal priority queue. */
2600 rtwn_write_2(sc, R92C_RQPN_NPQ, 0);
2601 rtwn_write_4(sc, R92C_RQPN,
2602 /* Set number of pages for public queue. */
2603 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) |
2604 /* Set number of pages for high priority queue. */
2605 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) |
2606 /* Set number of pages for low priority queue. */
2607 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) |
2608 /* Load values. */
2609 R92C_RQPN_LD);
2610
2611 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2612 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2613 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
2614 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
2615 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
2616
2617 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL);
2618 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2619 reg |= 0xF771;
2620 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2621
2622 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13));
2623
2624 /* Configure Tx DMA. */
2625 rtwn_write_4(sc, R92C_BKQ_DESA,
2626 sc->tx_ring[RTWN_BK_QUEUE].map->dm_segs[0].ds_addr);
2627 rtwn_write_4(sc, R92C_BEQ_DESA,
2628 sc->tx_ring[RTWN_BE_QUEUE].map->dm_segs[0].ds_addr);
2629 rtwn_write_4(sc, R92C_VIQ_DESA,
2630 sc->tx_ring[RTWN_VI_QUEUE].map->dm_segs[0].ds_addr);
2631 rtwn_write_4(sc, R92C_VOQ_DESA,
2632 sc->tx_ring[RTWN_VO_QUEUE].map->dm_segs[0].ds_addr);
2633 rtwn_write_4(sc, R92C_BCNQ_DESA,
2634 sc->tx_ring[RTWN_BEACON_QUEUE].map->dm_segs[0].ds_addr);
2635 rtwn_write_4(sc, R92C_MGQ_DESA,
2636 sc->tx_ring[RTWN_MGNT_QUEUE].map->dm_segs[0].ds_addr);
2637 rtwn_write_4(sc, R92C_HQ_DESA,
2638 sc->tx_ring[RTWN_HIGH_QUEUE].map->dm_segs[0].ds_addr);
2639
2640 /* Configure Rx DMA. */
2641 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.map->dm_segs[0].ds_addr);
2642
2643 /* Set Tx/Rx transfer page boundary. */
2644 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
2645
2646 /* Set Tx/Rx transfer page size. */
2647 rtwn_write_1(sc, R92C_PBP,
2648 SM(R92C_PBP_PSRX, R92C_PBP_128) |
2649 SM(R92C_PBP_PSTX, R92C_PBP_128));
2650 return 0;
2651 }
2652
2653 static void
rtwn_mac_init(struct rtwn_softc * sc)2654 rtwn_mac_init(struct rtwn_softc *sc)
2655 {
2656 int i;
2657
2658 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2659
2660 /* Write MAC initialization values. */
2661 for (i = 0; i < __arraycount(rtl8192ce_mac); i++)
2662 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val);
2663 }
2664
2665 static void
rtwn_bb_init(struct rtwn_softc * sc)2666 rtwn_bb_init(struct rtwn_softc *sc)
2667 {
2668 const struct rtwn_bb_prog *prog;
2669 uint32_t reg;
2670 int i;
2671
2672 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2673
2674 /* Enable BB and RF. */
2675 rtwn_write_2(sc, R92C_SYS_FUNC_EN,
2676 rtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2677 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
2678 R92C_SYS_FUNC_EN_DIO_RF);
2679
2680 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
2681
2682 rtwn_write_1(sc, R92C_RF_CTRL,
2683 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
2684
2685 rtwn_write_1(sc, R92C_SYS_FUNC_EN,
2686 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA |
2687 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST |
2688 R92C_SYS_FUNC_EN_BBRSTB);
2689
2690 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
2691
2692 rtwn_write_4(sc, R92C_LEDCFG0,
2693 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000);
2694
2695 /* Select BB programming. */
2696 prog = (sc->chip & RTWN_CHIP_92C) ?
2697 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t;
2698
2699 /* Write BB initialization values. */
2700 for (i = 0; i < prog->count; i++) {
2701 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
2702 DELAY(1);
2703 }
2704
2705 if (sc->chip & RTWN_CHIP_92C_1T2R) {
2706 /* 8192C 1T only configuration. */
2707 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2708 reg = (reg & ~0x00000003) | 0x2;
2709 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
2710
2711 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2712 reg = (reg & ~0x00300033) | 0x00200022;
2713 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
2714
2715 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2716 reg = (reg & ~0xff000000) | 0x45 << 24;
2717 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
2718
2719 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2720 reg = (reg & ~0x000000ff) | 0x23;
2721 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
2722
2723 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2724 reg = (reg & ~0x00000030) | 1 << 4;
2725 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
2726
2727 reg = rtwn_bb_read(sc, 0xe74);
2728 reg = (reg & ~0x0c000000) | 2 << 26;
2729 rtwn_bb_write(sc, 0xe74, reg);
2730 reg = rtwn_bb_read(sc, 0xe78);
2731 reg = (reg & ~0x0c000000) | 2 << 26;
2732 rtwn_bb_write(sc, 0xe78, reg);
2733 reg = rtwn_bb_read(sc, 0xe7c);
2734 reg = (reg & ~0x0c000000) | 2 << 26;
2735 rtwn_bb_write(sc, 0xe7c, reg);
2736 reg = rtwn_bb_read(sc, 0xe80);
2737 reg = (reg & ~0x0c000000) | 2 << 26;
2738 rtwn_bb_write(sc, 0xe80, reg);
2739 reg = rtwn_bb_read(sc, 0xe88);
2740 reg = (reg & ~0x0c000000) | 2 << 26;
2741 rtwn_bb_write(sc, 0xe88, reg);
2742 }
2743
2744 /* Write AGC values. */
2745 for (i = 0; i < prog->agccount; i++) {
2746 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
2747 prog->agcvals[i]);
2748 DELAY(1);
2749 }
2750
2751 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
2752 R92C_HSSI_PARAM2_CCK_HIPWR)
2753 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
2754 }
2755
2756 static void
rtwn_rf_init(struct rtwn_softc * sc)2757 rtwn_rf_init(struct rtwn_softc *sc)
2758 {
2759 const struct rtwn_rf_prog *prog;
2760 uint32_t reg, type;
2761 int i, j, idx, off;
2762
2763 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2764
2765 /* Select RF programming based on board type. */
2766 if (!(sc->chip & RTWN_CHIP_92C)) {
2767 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2768 prog = rtl8188ce_rf_prog;
2769 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2770 prog = rtl8188ru_rf_prog;
2771 else
2772 prog = rtl8188cu_rf_prog;
2773 } else
2774 prog = rtl8192ce_rf_prog;
2775
2776 for (i = 0; i < sc->nrxchains; i++) {
2777 /* Save RF_ENV control type. */
2778 idx = i / 2;
2779 off = (i % 2) * 16;
2780 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2781 type = (reg >> off) & 0x10;
2782
2783 /* Set RF_ENV enable. */
2784 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2785 reg |= 0x100000;
2786 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2787 DELAY(1);
2788 /* Set RF_ENV output high. */
2789 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2790 reg |= 0x10;
2791 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2792 DELAY(1);
2793 /* Set address and data lengths of RF registers. */
2794 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2795 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
2796 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2797 DELAY(1);
2798 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2799 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
2800 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2801 DELAY(1);
2802
2803 /* Write RF initialization values for this chain. */
2804 for (j = 0; j < prog[i].count; j++) {
2805 if (prog[i].regs[j] >= 0xf9 &&
2806 prog[i].regs[j] <= 0xfe) {
2807 /*
2808 * These are fake RF registers offsets that
2809 * indicate a delay is required.
2810 */
2811 DELAY(50);
2812 continue;
2813 }
2814 rtwn_rf_write(sc, i, prog[i].regs[j],
2815 prog[i].vals[j]);
2816 DELAY(1);
2817 }
2818
2819 /* Restore RF_ENV control type. */
2820 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2821 reg &= ~(0x10 << off) | (type << off);
2822 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
2823
2824 /* Cache RF register CHNLBW. */
2825 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW);
2826 }
2827
2828 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) ==
2829 RTWN_CHIP_UMC_A_CUT) {
2830 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
2831 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
2832 }
2833 }
2834
2835 static void
rtwn_cam_init(struct rtwn_softc * sc)2836 rtwn_cam_init(struct rtwn_softc *sc)
2837 {
2838
2839 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2840
2841 /* Invalidate all CAM entries. */
2842 rtwn_write_4(sc, R92C_CAMCMD, R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
2843 }
2844
2845 static void
rtwn_pa_bias_init(struct rtwn_softc * sc)2846 rtwn_pa_bias_init(struct rtwn_softc *sc)
2847 {
2848 uint8_t reg;
2849 int i;
2850
2851 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2852
2853 for (i = 0; i < sc->nrxchains; i++) {
2854 if (sc->pa_setting & (1 << i))
2855 continue;
2856 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
2857 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
2858 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
2859 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
2860 }
2861 if (!(sc->pa_setting & 0x10)) {
2862 reg = rtwn_read_1(sc, 0x16);
2863 reg = (reg & ~0xf0) | 0x90;
2864 rtwn_write_1(sc, 0x16, reg);
2865 }
2866 }
2867
2868 static void
rtwn_rxfilter_init(struct rtwn_softc * sc)2869 rtwn_rxfilter_init(struct rtwn_softc *sc)
2870 {
2871
2872 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2873
2874 /* Initialize Rx filter. */
2875 /* TODO: use better filter for monitor mode. */
2876 rtwn_write_4(sc, R92C_RCR,
2877 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB |
2878 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL |
2879 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS);
2880 /* Accept all multicast frames. */
2881 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
2882 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
2883 /* Accept all management frames. */
2884 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
2885 /* Reject all control frames. */
2886 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
2887 /* Accept all data frames. */
2888 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2889 }
2890
2891 static void
rtwn_edca_init(struct rtwn_softc * sc)2892 rtwn_edca_init(struct rtwn_softc *sc)
2893 {
2894
2895 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2896
2897 /* set spec SIFS (used in NAV) */
2898 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010);
2899 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010);
2900
2901 /* set SIFS CCK/OFDM */
2902 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010);
2903 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e);
2904
2905 /* TXOP */
2906 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
2907 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
2908 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322);
2909 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222);
2910 }
2911
2912 static void
rtwn_write_txpower(struct rtwn_softc * sc,int chain,uint16_t power[RTWN_RIDX_COUNT])2913 rtwn_write_txpower(struct rtwn_softc *sc, int chain,
2914 uint16_t power[RTWN_RIDX_COUNT])
2915 {
2916 uint32_t reg;
2917
2918 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2919
2920 /* Write per-CCK rate Tx power. */
2921 if (chain == 0) {
2922 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2923 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
2924 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
2925 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2926 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
2927 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
2928 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
2929 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2930 } else {
2931 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2932 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
2933 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
2934 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
2935 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
2936 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2937 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
2938 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2939 }
2940 /* Write per-OFDM rate Tx power. */
2941 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
2942 SM(R92C_TXAGC_RATE06, power[ 4]) |
2943 SM(R92C_TXAGC_RATE09, power[ 5]) |
2944 SM(R92C_TXAGC_RATE12, power[ 6]) |
2945 SM(R92C_TXAGC_RATE18, power[ 7]));
2946 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
2947 SM(R92C_TXAGC_RATE24, power[ 8]) |
2948 SM(R92C_TXAGC_RATE36, power[ 9]) |
2949 SM(R92C_TXAGC_RATE48, power[10]) |
2950 SM(R92C_TXAGC_RATE54, power[11]));
2951 /* Write per-MCS Tx power. */
2952 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
2953 SM(R92C_TXAGC_MCS00, power[12]) |
2954 SM(R92C_TXAGC_MCS01, power[13]) |
2955 SM(R92C_TXAGC_MCS02, power[14]) |
2956 SM(R92C_TXAGC_MCS03, power[15]));
2957 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
2958 SM(R92C_TXAGC_MCS04, power[16]) |
2959 SM(R92C_TXAGC_MCS05, power[17]) |
2960 SM(R92C_TXAGC_MCS06, power[18]) |
2961 SM(R92C_TXAGC_MCS07, power[19]));
2962 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
2963 SM(R92C_TXAGC_MCS08, power[20]) |
2964 SM(R92C_TXAGC_MCS09, power[21]) |
2965 SM(R92C_TXAGC_MCS10, power[22]) |
2966 SM(R92C_TXAGC_MCS11, power[23]));
2967 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
2968 SM(R92C_TXAGC_MCS12, power[24]) |
2969 SM(R92C_TXAGC_MCS13, power[25]) |
2970 SM(R92C_TXAGC_MCS14, power[26]) |
2971 SM(R92C_TXAGC_MCS15, power[27]));
2972 }
2973
2974 static void
rtwn_get_txpower(struct rtwn_softc * sc,int chain,struct ieee80211_channel * c,struct ieee80211_channel * extc,uint16_t power[RTWN_RIDX_COUNT])2975 rtwn_get_txpower(struct rtwn_softc *sc, int chain,
2976 struct ieee80211_channel *c, struct ieee80211_channel *extc,
2977 uint16_t power[RTWN_RIDX_COUNT])
2978 {
2979 struct ieee80211com *ic = &sc->sc_ic;
2980 struct r92c_rom *rom = &sc->rom;
2981 uint16_t cckpow, ofdmpow, htpow, diff, maxpwr;
2982 const struct rtwn_txpwr *base;
2983 int ridx, chan, group;
2984
2985 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
2986
2987 /* Determine channel group. */
2988 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
2989 if (chan <= 3)
2990 group = 0;
2991 else if (chan <= 9)
2992 group = 1;
2993 else
2994 group = 2;
2995
2996 /* Get original Tx power based on board type and RF chain. */
2997 if (!(sc->chip & RTWN_CHIP_92C)) {
2998 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2999 base = &rtl8188ru_txagc[chain];
3000 else
3001 base = &rtl8192cu_txagc[chain];
3002 } else
3003 base = &rtl8192cu_txagc[chain];
3004
3005 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0]));
3006 if (sc->regulatory == 0) {
3007 for (ridx = 0; ridx <= 3; ridx++)
3008 power[ridx] = base->pwr[0][ridx];
3009 }
3010 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) {
3011 if (sc->regulatory == 3) {
3012 power[ridx] = base->pwr[0][ridx];
3013 /* Apply vendor limits. */
3014 if (extc != NULL)
3015 maxpwr = rom->ht40_max_pwr[group];
3016 else
3017 maxpwr = rom->ht20_max_pwr[group];
3018 maxpwr = (maxpwr >> (chain * 4)) & 0xf;
3019 if (power[ridx] > maxpwr)
3020 power[ridx] = maxpwr;
3021 } else if (sc->regulatory == 1) {
3022 if (extc == NULL)
3023 power[ridx] = base->pwr[group][ridx];
3024 } else if (sc->regulatory != 2)
3025 power[ridx] = base->pwr[0][ridx];
3026 }
3027
3028 /* Compute per-CCK rate Tx power. */
3029 cckpow = rom->cck_tx_pwr[chain][group];
3030 for (ridx = 0; ridx <= 3; ridx++) {
3031 power[ridx] += cckpow;
3032 if (power[ridx] > R92C_MAX_TX_PWR)
3033 power[ridx] = R92C_MAX_TX_PWR;
3034 }
3035
3036 htpow = rom->ht40_1s_tx_pwr[chain][group];
3037 if (sc->ntxchains > 1) {
3038 /* Apply reduction for 2 spatial streams. */
3039 diff = rom->ht40_2s_tx_pwr_diff[group];
3040 diff = (diff >> (chain * 4)) & 0xf;
3041 htpow = (htpow > diff) ? htpow - diff : 0;
3042 }
3043
3044 /* Compute per-OFDM rate Tx power. */
3045 diff = rom->ofdm_tx_pwr_diff[group];
3046 diff = (diff >> (chain * 4)) & 0xf;
3047 ofdmpow = htpow + diff; /* HT->OFDM correction. */
3048 for (ridx = 4; ridx <= 11; ridx++) {
3049 power[ridx] += ofdmpow;
3050 if (power[ridx] > R92C_MAX_TX_PWR)
3051 power[ridx] = R92C_MAX_TX_PWR;
3052 }
3053
3054 /* Compute per-MCS Tx power. */
3055 if (extc == NULL) {
3056 diff = rom->ht20_tx_pwr_diff[group];
3057 diff = (diff >> (chain * 4)) & 0xf;
3058 htpow += diff; /* HT40->HT20 correction. */
3059 }
3060 for (ridx = 12; ridx <= 27; ridx++) {
3061 power[ridx] += htpow;
3062 if (power[ridx] > R92C_MAX_TX_PWR)
3063 power[ridx] = R92C_MAX_TX_PWR;
3064 }
3065 #ifdef RTWN_DEBUG
3066 if (rtwn_debug >= 4) {
3067 /* Dump per-rate Tx power values. */
3068 printf("Tx power for chain %d:\n", chain);
3069 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++)
3070 printf("Rate %d = %u\n", ridx, power[ridx]);
3071 }
3072 #endif
3073 }
3074
3075 static void
rtwn_set_txpower(struct rtwn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)3076 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c,
3077 struct ieee80211_channel *extc)
3078 {
3079 uint16_t power[RTWN_RIDX_COUNT];
3080 int i;
3081
3082 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3083
3084 for (i = 0; i < sc->ntxchains; i++) {
3085 /* Compute per-rate Tx power values. */
3086 rtwn_get_txpower(sc, i, c, extc, power);
3087 /* Write per-rate Tx power values to hardware. */
3088 rtwn_write_txpower(sc, i, power);
3089 }
3090 }
3091
3092 static void
rtwn_set_chan(struct rtwn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)3093 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c,
3094 struct ieee80211_channel *extc)
3095 {
3096 struct ieee80211com *ic = &sc->sc_ic;
3097 u_int chan;
3098 int i;
3099
3100 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3101
3102 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
3103
3104 /* Set Tx power for this new channel. */
3105 rtwn_set_txpower(sc, c, extc);
3106
3107 for (i = 0; i < sc->nrxchains; i++) {
3108 rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
3109 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
3110 }
3111 #ifndef IEEE80211_NO_HT
3112 if (extc != NULL) {
3113 uint32_t reg;
3114
3115 /* Is secondary channel below or above primary? */
3116 int prichlo = c->ic_freq < extc->ic_freq;
3117
3118 rtwn_write_1(sc, R92C_BWOPMODE,
3119 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
3120
3121 reg = rtwn_read_1(sc, R92C_RRSR + 2);
3122 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
3123 rtwn_write_1(sc, R92C_RRSR + 2, reg);
3124
3125 rtwn_bb_write(sc, R92C_FPGA0_RFMOD,
3126 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
3127 rtwn_bb_write(sc, R92C_FPGA1_RFMOD,
3128 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
3129
3130 /* Set CCK side band. */
3131 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);
3132 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
3133 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
3134
3135 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);
3136 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
3137 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
3138
3139 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
3140 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
3141 ~R92C_FPGA0_ANAPARAM2_CBW20);
3142
3143 reg = rtwn_bb_read(sc, 0x818);
3144 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
3145 rtwn_bb_write(sc, 0x818, reg);
3146
3147 /* Select 40MHz bandwidth. */
3148 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3149 (sc->rf_chnlbw[0] & ~0xfff) | chan);
3150 } else
3151 #endif
3152 {
3153 rtwn_write_1(sc, R92C_BWOPMODE,
3154 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
3155
3156 rtwn_bb_write(sc, R92C_FPGA0_RFMOD,
3157 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
3158 rtwn_bb_write(sc, R92C_FPGA1_RFMOD,
3159 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
3160
3161 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
3162 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
3163 R92C_FPGA0_ANAPARAM2_CBW20);
3164
3165 /* Select 20MHz bandwidth. */
3166 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3167 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan);
3168 }
3169 }
3170
3171 static void
rtwn_iq_calib(struct rtwn_softc * sc)3172 rtwn_iq_calib(struct rtwn_softc *sc)
3173 {
3174
3175 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3176
3177 /* XXX */
3178 }
3179
3180 static void
rtwn_lc_calib(struct rtwn_softc * sc)3181 rtwn_lc_calib(struct rtwn_softc *sc)
3182 {
3183 uint32_t rf_ac[2];
3184 uint8_t txmode;
3185 int i;
3186
3187 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3188
3189 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
3190 if ((txmode & 0x70) != 0) {
3191 /* Disable all continuous Tx. */
3192 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
3193
3194 /* Set RF mode to standby mode. */
3195 for (i = 0; i < sc->nrxchains; i++) {
3196 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC);
3197 rtwn_rf_write(sc, i, R92C_RF_AC,
3198 RW(rf_ac[i], R92C_RF_AC_MODE,
3199 R92C_RF_AC_MODE_STANDBY));
3200 }
3201 } else {
3202 /* Block all Tx queues. */
3203 rtwn_write_1(sc, R92C_TXPAUSE, 0xff);
3204 }
3205 /* Start calibration. */
3206 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3207 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
3208
3209 /* Give calibration the time to complete. */
3210 DELAY(100);
3211
3212 /* Restore configuration. */
3213 if ((txmode & 0x70) != 0) {
3214 /* Restore Tx mode. */
3215 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
3216 /* Restore RF mode. */
3217 for (i = 0; i < sc->nrxchains; i++)
3218 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
3219 } else {
3220 /* Unblock all Tx queues. */
3221 rtwn_write_1(sc, R92C_TXPAUSE, 0x00);
3222 }
3223 }
3224
3225 static void
rtwn_temp_calib(struct rtwn_softc * sc)3226 rtwn_temp_calib(struct rtwn_softc *sc)
3227 {
3228 int temp;
3229
3230 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3231
3232 if (sc->thcal_state == 0) {
3233 /* Start measuring temperature. */
3234 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60);
3235 sc->thcal_state = 1;
3236 return;
3237 }
3238 sc->thcal_state = 0;
3239
3240 /* Read measured temperature. */
3241 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f;
3242 if (temp == 0) /* Read failed, skip. */
3243 return;
3244 DPRINTFN(2, ("temperature=%d\n", temp));
3245
3246 /*
3247 * Redo IQ and LC calibration if temperature changed significantly
3248 * since last calibration.
3249 */
3250 if (sc->thcal_lctemp == 0) {
3251 /* First calibration is performed in rtwn_init(). */
3252 sc->thcal_lctemp = temp;
3253 } else if (abs(temp - sc->thcal_lctemp) > 1) {
3254 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n",
3255 sc->thcal_lctemp, temp));
3256 rtwn_iq_calib(sc);
3257 rtwn_lc_calib(sc);
3258 /* Record temperature of last calibration. */
3259 sc->thcal_lctemp = temp;
3260 }
3261 }
3262
3263 static int
rtwn_init(struct ifnet * ifp)3264 rtwn_init(struct ifnet *ifp)
3265 {
3266 struct rtwn_softc *sc = ifp->if_softc;
3267 struct ieee80211com *ic = &sc->sc_ic;
3268 uint32_t reg;
3269 int i, error;
3270
3271 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3272
3273 /* Init firmware commands ring. */
3274 sc->fwcur = 0;
3275
3276 /* Power on adapter. */
3277 error = rtwn_power_on(sc);
3278 if (error != 0) {
3279 aprint_error_dev(sc->sc_dev, "could not power on adapter\n");
3280 goto fail;
3281 }
3282
3283 /* Initialize DMA. */
3284 error = rtwn_dma_init(sc);
3285 if (error != 0) {
3286 aprint_error_dev(sc->sc_dev, "could not initialize DMA\n");
3287 goto fail;
3288 }
3289
3290 /* Set info size in Rx descriptors (in 64-bit words). */
3291 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
3292
3293 /* Disable interrupts. */
3294 rtwn_write_4(sc, R92C_HISR, 0xffffffff);
3295 rtwn_write_4(sc, R92C_HIMR, 0x00000000);
3296
3297 /* Set MAC address. */
3298 IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl));
3299 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3300 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]);
3301
3302 /* Set initial network type. */
3303 rtwn_set_nettype0_msr(sc, rtwn_get_nettype(sc));
3304
3305 rtwn_rxfilter_init(sc);
3306
3307 reg = rtwn_read_4(sc, R92C_RRSR);
3308 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL);
3309 rtwn_write_4(sc, R92C_RRSR, reg);
3310
3311 /* Set short/long retry limits. */
3312 rtwn_write_2(sc, R92C_RL,
3313 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07));
3314
3315 /* Initialize EDCA parameters. */
3316 rtwn_edca_init(sc);
3317
3318 /* Set data and response automatic rate fallback retry counts. */
3319 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000);
3320 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504);
3321 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000);
3322 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504);
3323
3324 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80);
3325
3326 /* Set ACK timeout. */
3327 rtwn_write_1(sc, R92C_ACKTO, 0x40);
3328
3329 /* Initialize beacon parameters. */
3330 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
3331 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
3332 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
3333 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
3334
3335 /* Setup AMPDU aggregation. */
3336 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
3337 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
3338
3339 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
3340 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0);
3341
3342 rtwn_write_4(sc, R92C_PIFS, 0x1c);
3343 rtwn_write_4(sc, R92C_MCUTST_1, 0x0);
3344
3345 /* Load 8051 microcode. */
3346 error = rtwn_load_firmware(sc);
3347 if (error != 0)
3348 goto fail;
3349
3350 /* Initialize MAC/BB/RF blocks. */
3351 rtwn_mac_init(sc);
3352 rtwn_bb_init(sc);
3353 rtwn_rf_init(sc);
3354
3355 /* Turn CCK and OFDM blocks on. */
3356 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3357 reg |= R92C_RFMOD_CCK_EN;
3358 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3359 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3360 reg |= R92C_RFMOD_OFDM_EN;
3361 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3362
3363 /* Clear per-station keys table. */
3364 rtwn_cam_init(sc);
3365
3366 /* Enable hardware sequence numbering. */
3367 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
3368
3369 /* Perform LO and IQ calibrations. */
3370 rtwn_iq_calib(sc);
3371 /* Perform LC calibration. */
3372 rtwn_lc_calib(sc);
3373
3374 rtwn_pa_bias_init(sc);
3375
3376 /* Initialize GPIO setting. */
3377 rtwn_write_1(sc, R92C_GPIO_MUXCFG,
3378 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
3379
3380 /* Fix for lower temperature. */
3381 rtwn_write_1(sc, 0x15, 0xe9);
3382
3383 /* Set default channel. */
3384 rtwn_set_chan(sc, ic->ic_curchan, NULL);
3385
3386 /* Clear pending interrupts. */
3387 rtwn_write_4(sc, R92C_HISR, 0xffffffff);
3388
3389 /* Enable interrupts. */
3390 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE);
3391
3392 /* We're ready to go. */
3393 ifp->if_flags &= ~IFF_OACTIVE;
3394 ifp->if_flags |= IFF_RUNNING;
3395
3396 if (ic->ic_opmode == IEEE80211_M_MONITOR)
3397 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
3398 else
3399 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
3400
3401 return 0;
3402
3403 fail:
3404 rtwn_stop(ifp, 1);
3405 return error;
3406 }
3407
3408 static void
rtwn_init_task(void * arg)3409 rtwn_init_task(void *arg)
3410 {
3411 struct rtwn_softc *sc = arg;
3412 struct ifnet *ifp = GET_IFP(sc);
3413 int s;
3414
3415 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3416
3417 s = splnet();
3418
3419 rtwn_stop(ifp, 0);
3420
3421 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP)
3422 rtwn_init(ifp);
3423
3424 splx(s);
3425 }
3426
3427 static void
rtwn_stop(struct ifnet * ifp,int disable)3428 rtwn_stop(struct ifnet *ifp, int disable)
3429 {
3430 struct rtwn_softc *sc = ifp->if_softc;
3431 struct ieee80211com *ic = &sc->sc_ic;
3432 uint16_t reg;
3433 int s, i;
3434
3435 DPRINTFN(3, ("%s: %s\n", device_xname(sc->sc_dev), __func__));
3436
3437 sc->sc_tx_timer = 0;
3438 ifp->if_timer = 0;
3439 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3440
3441 callout_stop(&sc->scan_to);
3442 callout_stop(&sc->calib_to);
3443
3444 s = splnet();
3445
3446 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3447
3448 /* Disable interrupts. */
3449 rtwn_write_4(sc, R92C_HIMR, 0x00000000);
3450
3451 /* Pause MAC TX queue */
3452 rtwn_write_1(sc, R92C_TXPAUSE, 0xff);
3453
3454 rtwn_write_1(sc, R92C_RF_CTRL, 0x00);
3455
3456 /* Reset BB state machine */
3457 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN);
3458 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST;
3459 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);
3460 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST;
3461 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);
3462
3463 reg = rtwn_read_2(sc, R92C_CR);
3464 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3465 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3466 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
3467 R92C_CR_ENSEC);
3468 rtwn_write_2(sc, R92C_CR, reg);
3469
3470 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
3471 rtwn_fw_reset(sc);
3472
3473 /* Reset MAC and Enable 8051 */
3474 rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1, 0x54);
3475
3476 /* TODO: linux does additional btcoex stuff here */
3477
3478 /* Disable AFE PLL */
3479 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */
3480 /* Enter PFM mode */
3481 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */
3482 /* Gated AFE DIG_CLOCK */
3483 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */
3484 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e);
3485 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN);
3486
3487 for (i = 0; i < RTWN_NTXQUEUES; i++)
3488 rtwn_reset_tx_list(sc, i);
3489 rtwn_reset_rx_list(sc);
3490
3491 splx(s);
3492 }
3493
3494 static int
rtwn_intr(void * xsc)3495 rtwn_intr(void *xsc)
3496 {
3497 struct rtwn_softc *sc = xsc;
3498 uint32_t status;
3499
3500 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED))
3501 return 0;
3502
3503 status = rtwn_read_4(sc, R92C_HISR);
3504 if (status == 0 || status == 0xffffffff)
3505 return 0;
3506
3507 /* Disable interrupts. */
3508 rtwn_write_4(sc, R92C_HIMR, 0x00000000);
3509
3510 softint_schedule(sc->sc_soft_ih);
3511 return 1;
3512 }
3513
3514 static void
rtwn_softintr(void * xsc)3515 rtwn_softintr(void *xsc)
3516 {
3517 struct rtwn_softc *sc = xsc;
3518 uint32_t status;
3519 int i, s;
3520
3521 if (!ISSET(sc->sc_flags, RTWN_FLAG_FW_LOADED))
3522 return;
3523
3524 status = rtwn_read_4(sc, R92C_HISR);
3525 if (status == 0 || status == 0xffffffff)
3526 goto out;
3527
3528 /* Ack interrupts. */
3529 rtwn_write_4(sc, R92C_HISR, status);
3530
3531 /* Vendor driver treats RX errors like ROK... */
3532 if (status & RTWN_INT_ENABLE_RX) {
3533 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
3534 struct r92c_rx_desc_pci *rx_desc = &sc->rx_ring.desc[i];
3535 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i];
3536
3537 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN)
3538 continue;
3539
3540 rtwn_rx_frame(sc, rx_desc, rx_data, i);
3541 }
3542 }
3543
3544 if (status & R92C_IMR_BDOK)
3545 rtwn_tx_done(sc, RTWN_BEACON_QUEUE);
3546 if (status & R92C_IMR_HIGHDOK)
3547 rtwn_tx_done(sc, RTWN_HIGH_QUEUE);
3548 if (status & R92C_IMR_MGNTDOK)
3549 rtwn_tx_done(sc, RTWN_MGNT_QUEUE);
3550 if (status & R92C_IMR_BKDOK)
3551 rtwn_tx_done(sc, RTWN_BK_QUEUE);
3552 if (status & R92C_IMR_BEDOK)
3553 rtwn_tx_done(sc, RTWN_BE_QUEUE);
3554 if (status & R92C_IMR_VIDOK)
3555 rtwn_tx_done(sc, RTWN_VI_QUEUE);
3556 if (status & R92C_IMR_VODOK)
3557 rtwn_tx_done(sc, RTWN_VO_QUEUE);
3558 if ((status & RTWN_INT_ENABLE_TX) && sc->qfullmsk == 0) {
3559 struct ifnet *ifp = GET_IFP(sc);
3560 s = splnet();
3561 ifp->if_flags &= ~IFF_OACTIVE;
3562 rtwn_start(ifp);
3563 splx(s);
3564 }
3565
3566 out:
3567 /* Enable interrupts. */
3568 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE);
3569 }
3570