1 /* $NetBSD: hdaudio_pci.h,v 1.2 2022/03/21 09:12:09 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2010 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Precedence Technologies Ltd 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _HDAUDIO_PCI_H 32 #define _HDAUDIO_PCI_H 33 34 /* NVIDIA specific registers */ 35 #define HDAUDIO_NV_REG_SNOOP 0x4c 36 #define HDAUDIO_NV_SNOOP_MASK 0x00ff0000 37 #define HDAUDIO_NV_SNOOP_ENABLE 0x000f0000 38 39 /* Intel ICH specific registers */ 40 #define HDAUDIO_INTEL_REG_ICH_TCSEL 0x44 41 #define HDAUDIO_INTEL_ICH_TCSEL_MASK __BITS(2,0) 42 #define HDAUDIO_INTEL_ICH_TCSEL_TC0 0 43 44 /* Intel 100 Series Chipset Family Platform Controller Hub (PCH) */ 45 #define HDAUDIO_INTEL_REG_PCH_CGCTL 0x48 46 #define HDAUDIO_INTEL_PCH_CGCTL_MISCBDCGE __BIT(6) 47 #define HDAUDIO_INTEL_REG_PCH_DEVC 0x78 48 #define HDAUDIO_INTEL_PCH_DEVC_NSNPEN __BIT(11) 49 50 #endif /* !_HDAUDIO_PCI_H */ 51