xref: /netbsd-src/sys/dev/marvell/marvellreg.h (revision 258d35a1f0de13599e28695bc9700915f7359b54)
1 /*	$NetBSD: marvellreg.h,v 1.11 2017/01/09 14:06:35 kiyohara Exp $	*/
2 /*
3  * Copyright (c) 2009 KIYOHARA Takashi
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  * POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #ifndef _DEV_MARVELL_MARVELLREG_H_
29 #define _DEV_MARVELL_MARVELLREG_H_
30 
31 #include <dev/pci/pcidevs.h>
32 
33 #define MARVELL_DISCOVERY		PCI_PRODUCT_MARVELL_GT64260
34 #define MARVELL_DISCOVERY_II		PCI_PRODUCT_MARVELL_MV64360
35 #define MARVELL_DISCOVERY_III		PCI_PRODUCT_MARVELL_MV64460
36 #if 0
37 #define MARVELL_DISCOVERY_LT		/* XXXX: 0x???? */
38 #define MARVELL_DISCOVERY_V		/* XXXX: 0x6450 ? */
39 #define MARVELL_DISCOVERY_VI		/* XXXX: 0x6460 ? */
40 #endif
41 
42 #define MARVELL_ORION_1_88F1181		PCI_PRODUCT_MARVELL_88F1181
43 #define MARVELL_ORION_1_88F5082		PCI_PRODUCT_MARVELL_88F5082
44 #define MARVELL_ORION_1_88F5180N	PCI_PRODUCT_MARVELL_88F5180N
45 #define MARVELL_ORION_1_88F5181		PCI_PRODUCT_MARVELL_88F5181
46 #define MARVELL_ORION_1_88F5182		PCI_PRODUCT_MARVELL_88F5182
47 #define MARVELL_ORION_1_88F6082		PCI_PRODUCT_MARVELL_88F6082
48 #define MARVELL_ORION_1_88F6183		PCI_PRODUCT_MARVELL_88F6183
49 #define MARVELL_ORION_1_88W8660		PCI_PRODUCT_MARVELL_88W8660
50 
51 #define MARVELL_ORION_2_88F1281		PCI_PRODUCT_MARVELL_88F1281
52 #define MARVELL_ORION_2_88F5281		PCI_PRODUCT_MARVELL_88F5281
53 
54 #define MARVELL_KIRKWOOD_88F6180	PCI_PRODUCT_MARVELL_88F6180
55 #define MARVELL_KIRKWOOD_88F6192	PCI_PRODUCT_MARVELL_88F6192
56 #define MARVELL_KIRKWOOD_88F6281	PCI_PRODUCT_MARVELL_88F6281
57 #define MARVELL_KIRKWOOD_88F6282	PCI_PRODUCT_MARVELL_88F6282
58 
59 #define MARVELL_MV78XX0_MV78100		PCI_PRODUCT_MARVELL_MV78100
60 #define MARVELL_MV78XX0_MV78200		PCI_PRODUCT_MARVELL_MV78200
61 
62 #define MARVELL_DOVE_88AP510		PCI_PRODUCT_MARVELL_88AP510
63 
64 #define MARVELL_ARMADAXP_MV78130	PCI_PRODUCT_MARVELL_MV78130
65 #define MARVELL_ARMADAXP_MV78160	PCI_PRODUCT_MARVELL_MV78160
66 #define MARVELL_ARMADAXP_MV78230	PCI_PRODUCT_MARVELL_MV78230
67 #define MARVELL_ARMADAXP_MV78260	PCI_PRODUCT_MARVELL_MV78260
68 #define MARVELL_ARMADAXP_MV78460	PCI_PRODUCT_MARVELL_MV78460
69 
70 #define MARVELL_ARMADA370_MV6707	PCI_PRODUCT_MARVELL_MV6707
71 #define MARVELL_ARMADA370_MV6710	PCI_PRODUCT_MARVELL_MV6710
72 #define MARVELL_ARMADA370_MV6W11	PCI_PRODUCT_MARVELL_MV6W11
73 
74 #define MARVELL_DISCOVERY_REVA	0x10
75 #define MARVELL_DISCOVERY_REVB	0x20
76 
77 #define MARVELL_ATTR_MASK		0xff
78 #define MARVELL_ATTR_SDRAM_CFU_SHARE	0x10 /* shared and snoop enabled.*/
79 #define MARVELL_ATTR_SDRAM_CFU_L2_DEP	0x20 /* enable L2 deposit */
80 #ifdef AURORA_IO_CACHE_COHERENCY
81 #define MARVELL_ATTR_SDRAM_CS0		(0x0e | MARVELL_ATTR_SDRAM_CFU_SHARE)
82 #define MARVELL_ATTR_SDRAM_CS1		(0x0d | MARVELL_ATTR_SDRAM_CFU_SHARE)
83 #define MARVELL_ATTR_SDRAM_CS2		(0x0b | MARVELL_ATTR_SDRAM_CFU_SHARE)
84 #define MARVELL_ATTR_SDRAM_CS3		(0x07 | MARVELL_ATTR_SDRAM_CFU_SHARE)
85 #else
86 #define MARVELL_ATTR_SDRAM_CS0		0x0e
87 #define MARVELL_ATTR_SDRAM_CS1		0x0d
88 #define MARVELL_ATTR_SDRAM_CS2		0x0b
89 #define MARVELL_ATTR_SDRAM_CS3		0x07
90 #endif
91 #define MARVELL_ATTR_AXI_DDR		0x00
92 
93 #endif	/* _DEV_MARVELL_MARVELLREG_H_ */
94