1 /* $NetBSD: wdc_isa.c,v 1.62 2022/09/25 17:09:36 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Onno van der Linden.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: wdc_isa.c,v 1.62 2022/09/25 17:09:36 thorpej Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/device.h>
38
39 #include <sys/bus.h>
40 #include <sys/intr.h>
41
42 #include <dev/isa/isavar.h>
43 #include <dev/isa/isadmavar.h>
44
45 #include <dev/ic/wdcreg.h>
46 #include <dev/ata/atavar.h>
47 #include <dev/ic/wdcvar.h>
48
49 #define WDC_ISA_REG_NPORTS 8
50 #define WDC_ISA_AUXREG_OFFSET 0x206
51 #define WDC_ISA_AUXREG_NPORTS 1 /* XXX "fdc" owns ports 0x3f7/0x377 */
52
53 /* options passed via the 'flags' config keyword */
54 #define WDC_OPTIONS_32 0x01 /* try to use 32bit data I/O */
55 #define WDC_OPTIONS_ATA_NOSTREAM 0x04
56 #define WDC_OPTIONS_ATAPI_NOSTREAM 0x08
57
58 struct wdc_isa_softc {
59 struct wdc_softc sc_wdcdev;
60 struct ata_channel *wdc_chanlist[1];
61 struct ata_channel ata_channel;
62 struct wdc_regs wdc_regs;
63 isa_chipset_tag_t sc_ic;
64 void *sc_ih;
65 int sc_drq;
66 };
67
68 static int wdc_isa_probe(device_t , cfdata_t, void *);
69 static void wdc_isa_attach(device_t, device_t, void *);
70 static int wdc_isa_detach(device_t, int);
71
72 CFATTACH_DECL3_NEW(wdc_isa, sizeof(struct wdc_isa_softc),
73 wdc_isa_probe, wdc_isa_attach, wdc_isa_detach, NULL, NULL,
74 wdc_childdetached, DVF_DETACH_SHUTDOWN);
75
76 #if 0
77 static void wdc_isa_dma_setup(struct wdc_isa_softc *);
78 static int wdc_isa_dma_init(void*, int, int, void *, size_t, int);
79 static void wdc_isa_dma_start(void*, int, int);
80 static int wdc_isa_dma_finish(void*, int, int, int);
81 #endif
82
83 static int
wdc_isa_probe(device_t parent,cfdata_t match,void * aux)84 wdc_isa_probe(device_t parent, cfdata_t match, void *aux)
85 {
86 struct isa_attach_args *ia = aux;
87 struct wdc_regs wdr;
88 int result = 0, i;
89
90 if (ia->ia_nio < 1)
91 return (0);
92 if (ia->ia_nirq < 1)
93 return (0);
94
95 if (ISA_DIRECT_CONFIG(ia))
96 return (0);
97
98 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
99 return (0);
100 if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ)
101 return (0);
102 if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq == ISA_UNKNOWN_DRQ)
103 ia->ia_ndrq = 0;
104
105 wdr.cmd_iot = ia->ia_iot;
106
107 if (bus_space_map(wdr.cmd_iot, ia->ia_io[0].ir_addr,
108 WDC_ISA_REG_NPORTS, 0, &wdr.cmd_baseioh))
109 goto out;
110
111 for (i = 0; i < WDC_ISA_REG_NPORTS; i++) {
112 if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i,
113 i == 0 ? 4 : 1, &wdr.cmd_iohs[i]) != 0)
114 goto outunmap;
115 }
116 wdc_init_shadow_regs(&wdr);
117
118 wdr.ctl_iot = ia->ia_iot;
119 if (bus_space_map(wdr.ctl_iot, ia->ia_io[0].ir_addr +
120 WDC_ISA_AUXREG_OFFSET, WDC_ISA_AUXREG_NPORTS, 0, &wdr.ctl_ioh))
121 goto outunmap;
122
123 result = wdcprobe(&wdr);
124 if (result) {
125 ia->ia_nio = 1;
126 ia->ia_io[0].ir_size = WDC_ISA_REG_NPORTS;
127
128 ia->ia_nirq = 1;
129
130 ia->ia_niomem = 0;
131 }
132
133 bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_ISA_AUXREG_NPORTS);
134 outunmap:
135 bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_ISA_REG_NPORTS);
136 out:
137 return (result);
138 }
139
140 static int
wdc_isa_detach(device_t self,int flags)141 wdc_isa_detach(device_t self, int flags)
142 {
143 struct wdc_isa_softc *sc = device_private(self);
144 struct wdc_regs *wdr = &sc->wdc_regs;
145 int rc;
146
147 if ((rc = wdcdetach(self, flags)) != 0)
148 return rc;
149
150 isa_intr_disestablish(sc->sc_ic, sc->sc_ih);
151
152 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, WDC_ISA_AUXREG_NPORTS);
153 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, WDC_ISA_REG_NPORTS);
154
155 return 0;
156 }
157
158 static void
wdc_isa_attach(device_t parent,device_t self,void * aux)159 wdc_isa_attach(device_t parent, device_t self, void *aux)
160 {
161 struct wdc_isa_softc *sc = device_private(self);
162 struct wdc_regs *wdr;
163 struct isa_attach_args *ia = aux;
164 int wdc_cf_flags = device_cfdata(self)->cf_flags;
165 int i;
166
167 sc->sc_wdcdev.sc_atac.atac_dev = self;
168 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs;
169 wdr->cmd_iot = ia->ia_iot;
170 wdr->ctl_iot = ia->ia_iot;
171 sc->sc_ic = ia->ia_ic;
172 if (bus_space_map(wdr->cmd_iot, ia->ia_io[0].ir_addr,
173 WDC_ISA_REG_NPORTS, 0, &wdr->cmd_baseioh) ||
174 bus_space_map(wdr->ctl_iot,
175 ia->ia_io[0].ir_addr + WDC_ISA_AUXREG_OFFSET,
176 WDC_ISA_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) {
177 aprint_error(": couldn't map registers\n");
178 return;
179 }
180
181 for (i = 0; i < WDC_ISA_REG_NPORTS; i++) {
182 if (bus_space_subregion(wdr->cmd_iot,
183 wdr->cmd_baseioh, i, i == 0 ? 4 : 1,
184 &wdr->cmd_iohs[i]) != 0) {
185 aprint_error(": couldn't subregion registers\n");
186 return;
187 }
188 }
189
190 wdr->data32iot = wdr->cmd_iot;
191 wdr->data32ioh = wdr->cmd_iohs[0];
192
193 #if 0
194 if (ia->ia_ndrq > 0 && ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ) {
195 sc->sc_drq = ia->ia_drq[0].ir_drq;
196
197 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
198 sc->sc_wdcdev.dma_arg = sc;
199 sc->sc_wdcdev.dma_init = wdc_isa_dma_init;
200 sc->sc_wdcdev.dma_start = wdc_isa_dma_start;
201 sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish;
202 wdc_isa_dma_setup(sc);
203 }
204 #endif
205 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA;
206 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
207 if (wdc_cf_flags & WDC_OPTIONS_32)
208 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32;
209 if (wdc_cf_flags & WDC_OPTIONS_ATA_NOSTREAM)
210 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATA_NOSTREAM;
211 if (wdc_cf_flags & WDC_OPTIONS_ATAPI_NOSTREAM)
212 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATAPI_NOSTREAM;
213
214 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
215 sc->wdc_chanlist[0] = &sc->ata_channel;
216 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
217 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
218 sc->sc_wdcdev.wdc_maxdrives = 2;
219 sc->ata_channel.ch_channel = 0;
220 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
221
222 wdc_init_shadow_regs(wdr);
223
224 aprint_normal("\n");
225
226 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq,
227 IST_EDGE, IPL_BIO, wdcintr, &sc->ata_channel);
228
229 wdcattach(&sc->ata_channel);
230 }
231
232 #if 0
233 static void
234 wdc_isa_dma_setup(struct wdc_isa_softc *sc)
235 {
236 bus_size_t maxsize;
237
238 if ((maxsize = isa_dmamaxsize(sc->sc_ic, sc->sc_drq)) < MAXPHYS) {
239 aprint_error_dev(sc_wdcdev.sc_atac.atac_dev,
240 "max DMA size %lu is less than required %d\n",
241 (u_long)maxsize, MAXPHYS);
242 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
243 return;
244 }
245
246 if (isa_drq_alloc(sc->sc_ic, sc->sc_drq) != 0) {
247 aprint_error_dev(sc_wdcdev.sc_atac.atac_dev,
248 "can't reserve drq %d\n", sc->sc_drq);
249 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
250 return;
251 }
252
253 if (isa_dmamap_create(sc->sc_ic, sc->sc_drq,
254 MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) {
255 aprint_error_dev(sc_wdcdev.sc_atac.atac_dev,
256 "can't create map for drq %d\n", sc->sc_drq);
257 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
258 }
259 }
260
261 static int
262 wdc_isa_dma_init(void *v, int channel, int drive, void *databuf,
263 size_t datalen, int read)
264 {
265 struct wdc_isa_softc *sc = v;
266
267 isa_dmastart(sc->sc_ic, sc->sc_drq, databuf, datalen, NULL,
268 (read ? DMAMODE_READ : DMAMODE_WRITE) | DMAMODE_DEMAND,
269 BUS_DMA_NOWAIT);
270 return 0;
271 }
272
273 static void
274 wdc_isa_dma_start(void *v, int channel, int drive)
275 {
276 /* nothing to do */
277 }
278
279 static int
280 wdc_isa_dma_finish(void *v, int channel, int drive, int read)
281 {
282 struct wdc_isa_softc *sc = v;
283
284 isa_dmadone(sc->sc_ic, sc->sc_drq);
285 return 0;
286 }
287 #endif
288