1 /* $NetBSD: dcn10_hw_sequencer.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_HWSS_DCN10_H__ 29 #define __DC_HWSS_DCN10_H__ 30 31 #include "core_types.h" 32 #include "hw_sequencer_private.h" 33 34 struct dc; 35 36 void dcn10_hw_sequencer_construct(struct dc *dc); 37 38 int dcn10_get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx); 39 void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx); 40 enum dc_status dcn10_enable_stream_timing( 41 struct pipe_ctx *pipe_ctx, 42 struct dc_state *context, 43 struct dc *dc); 44 void dcn10_optimize_bandwidth( 45 struct dc *dc, 46 struct dc_state *context); 47 void dcn10_prepare_bandwidth( 48 struct dc *dc, 49 struct dc_state *context); 50 void dcn10_pipe_control_lock( 51 struct dc *dc, 52 struct pipe_ctx *pipe, 53 bool lock); 54 void dcn10_blank_pixel_data( 55 struct dc *dc, 56 struct pipe_ctx *pipe_ctx, 57 bool blank); 58 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx, 59 struct dc_link_settings *link_settings); 60 void dcn10_program_output_csc(struct dc *dc, 61 struct pipe_ctx *pipe_ctx, 62 enum dc_color_space colorspace, 63 uint16_t *matrix, 64 int opp_id); 65 bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 66 const struct dc_stream_state *stream); 67 bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 68 const struct dc_plane_state *plane_state); 69 void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx); 70 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx); 71 void dcn10_reset_hw_ctx_wrap( 72 struct dc *dc, 73 struct dc_state *context); 74 void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx); 75 void dcn10_apply_ctx_for_surface( 76 struct dc *dc, 77 const struct dc_stream_state *stream, 78 int num_planes, 79 struct dc_state *context); 80 void dcn10_hubp_pg_control( 81 struct dce_hwseq *hws, 82 unsigned int hubp_inst, 83 bool power_on); 84 void dcn10_dpp_pg_control( 85 struct dce_hwseq *hws, 86 unsigned int dpp_inst, 87 bool power_on); 88 void dcn10_enable_power_gating_plane( 89 struct dce_hwseq *hws, 90 bool enable); 91 void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx); 92 void dcn10_disable_vga( 93 struct dce_hwseq *hws); 94 void dcn10_program_pipe( 95 struct dc *dc, 96 struct pipe_ctx *pipe_ctx, 97 struct dc_state *context); 98 void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx); 99 void dcn10_init_hw(struct dc *dc); 100 void dcn10_init_pipes(struct dc *dc, struct dc_state *context); 101 enum dc_status dce110_apply_ctx_to_hw( 102 struct dc *dc, 103 struct dc_state *context); 104 void dcn10_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx); 105 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data); 106 void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx); 107 void dce110_power_down(struct dc *dc); 108 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context); 109 void dcn10_enable_timing_synchronization( 110 struct dc *dc, 111 int group_index, 112 int group_size, 113 struct pipe_ctx *grouped_pipes[]); 114 void dcn10_enable_per_frame_crtc_position_reset( 115 struct dc *dc, 116 int group_size, 117 struct pipe_ctx *grouped_pipes[]); 118 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx); 119 void dcn10_send_immediate_sdp_message(struct pipe_ctx *pipe_ctx, 120 const uint8_t *custom_sdp_message, 121 unsigned int sdp_message_size); 122 void dce110_blank_stream(struct pipe_ctx *pipe_ctx); 123 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx); 124 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx); 125 bool dcn10_dummy_display_power_gating( 126 struct dc *dc, 127 uint8_t controller_id, 128 struct dc_bios *dcb, 129 enum pipe_gating_control power_gating); 130 void dcn10_set_drr(struct pipe_ctx **pipe_ctx, 131 int num_pipes, unsigned int vmin, unsigned int vmax, 132 unsigned int vmid, unsigned int vmid_frame_number); 133 void dcn10_get_position(struct pipe_ctx **pipe_ctx, 134 int num_pipes, 135 struct crtc_position *position); 136 void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, 137 int num_pipes, const struct dc_static_screen_params *params); 138 void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc); 139 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 140 void dcn10_log_hw_state(struct dc *dc, 141 struct dc_log_buffer_ctx *log_ctx); 142 void dcn10_get_hw_state(struct dc *dc, 143 char *pBuf, 144 unsigned int bufSize, 145 unsigned int mask); 146 void dcn10_clear_status_bits(struct dc *dc, unsigned int mask); 147 void dcn10_wait_for_mpcc_disconnect( 148 struct dc *dc, 149 struct resource_pool *res_pool, 150 struct pipe_ctx *pipe_ctx); 151 void dce110_edp_backlight_control( 152 struct dc_link *link, 153 bool enable); 154 void dce110_edp_power_control( 155 struct dc_link *link, 156 bool power_up); 157 void dce110_edp_wait_for_hpd_ready( 158 struct dc_link *link, 159 bool power_up); 160 void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx); 161 void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx); 162 void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx); 163 void dcn10_setup_periodic_interrupt( 164 struct dc *dc, 165 struct pipe_ctx *pipe_ctx, 166 enum vline_select vline); 167 enum dc_status dcn10_set_clock(struct dc *dc, 168 enum dc_clock_type clock_type, 169 uint32_t clk_khz, 170 uint32_t stepping); 171 void dcn10_get_clock(struct dc *dc, 172 enum dc_clock_type clock_type, 173 struct dc_clock_config *clock_cfg); 174 bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx); 175 void dcn10_bios_golden_init(struct dc *dc); 176 void dcn10_plane_atomic_power_down(struct dc *dc, 177 struct dpp *dpp, 178 struct hubp *hubp); 179 void dcn10_get_surface_visual_confirm_color( 180 const struct pipe_ctx *pipe_ctx, 181 struct tg_color *color); 182 void dcn10_get_hdr_visual_confirm_color( 183 struct pipe_ctx *pipe_ctx, 184 struct tg_color *color); 185 void dcn10_set_hdr_multiplier(struct pipe_ctx *pipe_ctx); 186 void dcn10_verify_allow_pstate_change_high(struct dc *dc); 187 188 #endif /* __DC_HWSS_DCN10_H__ */ 189