1 /* $NetBSD: dce_10_0_d.h,v 1.3 2021/12/18 23:45:09 riastradh Exp $ */ 2 3 /* 4 * DCE_10_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef DCE_10_0_D_H 27 #define DCE_10_0_D_H 28 29 #define mmPIPE0_PG_CONFIG 0x2c0 30 #define mmPIPE0_PG_ENABLE 0x2c1 31 #define mmPIPE0_PG_STATUS 0x2c2 32 #define mmPIPE1_PG_CONFIG 0x2c3 33 #define mmPIPE1_PG_ENABLE 0x2c4 34 #define mmPIPE1_PG_STATUS 0x2c5 35 #define mmPIPE2_PG_CONFIG 0x2c6 36 #define mmPIPE2_PG_ENABLE 0x2c7 37 #define mmPIPE2_PG_STATUS 0x2c8 38 #define mmPIPE3_PG_CONFIG 0x2c9 39 #define mmPIPE3_PG_ENABLE 0x2ca 40 #define mmPIPE3_PG_STATUS 0x2cb 41 #define mmPIPE4_PG_CONFIG 0x2cc 42 #define mmPIPE4_PG_ENABLE 0x2cd 43 #define mmPIPE4_PG_STATUS 0x2ce 44 #define mmPIPE5_PG_CONFIG 0x2cf 45 #define mmPIPE5_PG_ENABLE 0x2d0 46 #define mmPIPE5_PG_STATUS 0x2d1 47 #define mmDC_IP_REQUEST_CNTL 0x2d2 48 #define mmDC_PGFSM_CONFIG_REG 0x2d3 49 #define mmDC_PGFSM_WRITE_REG 0x2d4 50 #define mmDC_PGCNTL_STATUS_REG 0x2d5 51 #define mmDCPG_TEST_DEBUG_INDEX 0x2d6 52 #define mmDCPG_TEST_DEBUG_DATA 0x2d7 53 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 54 #define mmBL1_PWM_USER_LEVEL 0x1629 55 #define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a 56 #define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b 57 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c 58 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d 59 #define mmBL1_PWM_ABM_CNTL 0x162e 60 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f 61 #define mmBL1_PWM_GRP2_REG_LOCK 0x1630 62 #define mmDC_ABM1_CNTL 0x1638 63 #define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 64 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a 65 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b 66 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c 67 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d 68 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e 69 #define mmDC_ABM1_ACE_THRES_12 0x163f 70 #define mmDC_ABM1_ACE_THRES_34 0x1640 71 #define mmDC_ABM1_ACE_CNTL_MISC 0x1641 72 #define mmDC_ABM1_DEBUG_MISC 0x1649 73 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a 74 #define mmDC_ABM1_HG_MISC_CTRL 0x164b 75 #define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c 76 #define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d 77 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e 78 #define mmDC_ABM1_LS_PIXEL_COUNT 0x164f 79 #define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 80 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 81 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 82 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 83 #define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 84 #define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 85 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 86 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 87 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 88 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 89 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a 90 #define mmDC_ABM1_HG_RESULT_1 0x165b 91 #define mmDC_ABM1_HG_RESULT_2 0x165c 92 #define mmDC_ABM1_HG_RESULT_3 0x165d 93 #define mmDC_ABM1_HG_RESULT_4 0x165e 94 #define mmDC_ABM1_HG_RESULT_5 0x165f 95 #define mmDC_ABM1_HG_RESULT_6 0x1660 96 #define mmDC_ABM1_HG_RESULT_7 0x1661 97 #define mmDC_ABM1_HG_RESULT_8 0x1662 98 #define mmDC_ABM1_HG_RESULT_9 0x1663 99 #define mmDC_ABM1_HG_RESULT_10 0x1664 100 #define mmDC_ABM1_HG_RESULT_11 0x1665 101 #define mmDC_ABM1_HG_RESULT_12 0x1666 102 #define mmDC_ABM1_HG_RESULT_13 0x1667 103 #define mmDC_ABM1_HG_RESULT_14 0x1668 104 #define mmDC_ABM1_HG_RESULT_15 0x1669 105 #define mmDC_ABM1_HG_RESULT_16 0x166a 106 #define mmDC_ABM1_HG_RESULT_17 0x166b 107 #define mmDC_ABM1_HG_RESULT_18 0x166c 108 #define mmDC_ABM1_HG_RESULT_19 0x166d 109 #define mmDC_ABM1_HG_RESULT_20 0x166e 110 #define mmDC_ABM1_HG_RESULT_21 0x166f 111 #define mmDC_ABM1_HG_RESULT_22 0x1670 112 #define mmDC_ABM1_HG_RESULT_23 0x1671 113 #define mmDC_ABM1_HG_RESULT_24 0x1672 114 #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b 115 #define mmDC_ABM1_BL_MASTER_LOCK 0x169c 116 #define mmABM_TEST_DEBUG_INDEX 0x169e 117 #define mmABM_TEST_DEBUG_DATA 0x169f 118 #define mmCRTC_DCFE_CLOCK_CONTROL 0x1b7c 119 #define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1b7c 120 #define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1d7c 121 #define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x1f7c 122 #define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x417c 123 #define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x437c 124 #define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x457c 125 #define mmCRTC6_CRTC_DCFE_CLOCK_CONTROL 0x477c 126 #define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d 127 #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d 128 #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d 129 #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d 130 #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d 131 #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d 132 #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d 133 #define mmCRTC6_CRTC_H_BLANK_EARLY_NUM 0x477d 134 #define mmDCFE_DBG_SEL 0x1b7e 135 #define mmCRTC0_DCFE_DBG_SEL 0x1b7e 136 #define mmCRTC1_DCFE_DBG_SEL 0x1d7e 137 #define mmCRTC2_DCFE_DBG_SEL 0x1f7e 138 #define mmCRTC3_DCFE_DBG_SEL 0x417e 139 #define mmCRTC4_DCFE_DBG_SEL 0x437e 140 #define mmCRTC5_DCFE_DBG_SEL 0x457e 141 #define mmCRTC6_DCFE_DBG_SEL 0x477e 142 #define mmDCFE_MEM_PWR_CTRL 0x1b7f 143 #define mmCRTC0_DCFE_MEM_PWR_CTRL 0x1b7f 144 #define mmCRTC1_DCFE_MEM_PWR_CTRL 0x1d7f 145 #define mmCRTC2_DCFE_MEM_PWR_CTRL 0x1f7f 146 #define mmCRTC3_DCFE_MEM_PWR_CTRL 0x417f 147 #define mmCRTC4_DCFE_MEM_PWR_CTRL 0x437f 148 #define mmCRTC5_DCFE_MEM_PWR_CTRL 0x457f 149 #define mmCRTC6_DCFE_MEM_PWR_CTRL 0x477f 150 #define mmDCFE_MEM_PWR_CTRL2 0x1bb8 151 #define mmCRTC0_DCFE_MEM_PWR_CTRL2 0x1bb8 152 #define mmCRTC1_DCFE_MEM_PWR_CTRL2 0x1db8 153 #define mmCRTC2_DCFE_MEM_PWR_CTRL2 0x1fb8 154 #define mmCRTC3_DCFE_MEM_PWR_CTRL2 0x41b8 155 #define mmCRTC4_DCFE_MEM_PWR_CTRL2 0x43b8 156 #define mmCRTC5_DCFE_MEM_PWR_CTRL2 0x45b8 157 #define mmCRTC6_DCFE_MEM_PWR_CTRL2 0x47b8 158 #define mmDCFE_MEM_PWR_STATUS 0x1bb9 159 #define mmCRTC0_DCFE_MEM_PWR_STATUS 0x1bb9 160 #define mmCRTC1_DCFE_MEM_PWR_STATUS 0x1db9 161 #define mmCRTC2_DCFE_MEM_PWR_STATUS 0x1fb9 162 #define mmCRTC3_DCFE_MEM_PWR_STATUS 0x41b9 163 #define mmCRTC4_DCFE_MEM_PWR_STATUS 0x43b9 164 #define mmCRTC5_DCFE_MEM_PWR_STATUS 0x45b9 165 #define mmCRTC6_DCFE_MEM_PWR_STATUS 0x47b9 166 #define mmCRTC_H_TOTAL 0x1b80 167 #define mmCRTC0_CRTC_H_TOTAL 0x1b80 168 #define mmCRTC1_CRTC_H_TOTAL 0x1d80 169 #define mmCRTC2_CRTC_H_TOTAL 0x1f80 170 #define mmCRTC3_CRTC_H_TOTAL 0x4180 171 #define mmCRTC4_CRTC_H_TOTAL 0x4380 172 #define mmCRTC5_CRTC_H_TOTAL 0x4580 173 #define mmCRTC6_CRTC_H_TOTAL 0x4780 174 #define mmCRTC_H_BLANK_START_END 0x1b81 175 #define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 176 #define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 177 #define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 178 #define mmCRTC3_CRTC_H_BLANK_START_END 0x4181 179 #define mmCRTC4_CRTC_H_BLANK_START_END 0x4381 180 #define mmCRTC5_CRTC_H_BLANK_START_END 0x4581 181 #define mmCRTC6_CRTC_H_BLANK_START_END 0x4781 182 #define mmCRTC_H_SYNC_A 0x1b82 183 #define mmCRTC0_CRTC_H_SYNC_A 0x1b82 184 #define mmCRTC1_CRTC_H_SYNC_A 0x1d82 185 #define mmCRTC2_CRTC_H_SYNC_A 0x1f82 186 #define mmCRTC3_CRTC_H_SYNC_A 0x4182 187 #define mmCRTC4_CRTC_H_SYNC_A 0x4382 188 #define mmCRTC5_CRTC_H_SYNC_A 0x4582 189 #define mmCRTC6_CRTC_H_SYNC_A 0x4782 190 #define mmCRTC_H_SYNC_A_CNTL 0x1b83 191 #define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 192 #define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 193 #define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 194 #define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 195 #define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 196 #define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 197 #define mmCRTC6_CRTC_H_SYNC_A_CNTL 0x4783 198 #define mmCRTC_H_SYNC_B 0x1b84 199 #define mmCRTC0_CRTC_H_SYNC_B 0x1b84 200 #define mmCRTC1_CRTC_H_SYNC_B 0x1d84 201 #define mmCRTC2_CRTC_H_SYNC_B 0x1f84 202 #define mmCRTC3_CRTC_H_SYNC_B 0x4184 203 #define mmCRTC4_CRTC_H_SYNC_B 0x4384 204 #define mmCRTC5_CRTC_H_SYNC_B 0x4584 205 #define mmCRTC6_CRTC_H_SYNC_B 0x4784 206 #define mmCRTC_H_SYNC_B_CNTL 0x1b85 207 #define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 208 #define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 209 #define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 210 #define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 211 #define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 212 #define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 213 #define mmCRTC6_CRTC_H_SYNC_B_CNTL 0x4785 214 #define mmCRTC_VBI_END 0x1b86 215 #define mmCRTC0_CRTC_VBI_END 0x1b86 216 #define mmCRTC1_CRTC_VBI_END 0x1d86 217 #define mmCRTC2_CRTC_VBI_END 0x1f86 218 #define mmCRTC3_CRTC_VBI_END 0x4186 219 #define mmCRTC4_CRTC_VBI_END 0x4386 220 #define mmCRTC5_CRTC_VBI_END 0x4586 221 #define mmCRTC6_CRTC_VBI_END 0x4786 222 #define mmCRTC_V_TOTAL 0x1b87 223 #define mmCRTC0_CRTC_V_TOTAL 0x1b87 224 #define mmCRTC1_CRTC_V_TOTAL 0x1d87 225 #define mmCRTC2_CRTC_V_TOTAL 0x1f87 226 #define mmCRTC3_CRTC_V_TOTAL 0x4187 227 #define mmCRTC4_CRTC_V_TOTAL 0x4387 228 #define mmCRTC5_CRTC_V_TOTAL 0x4587 229 #define mmCRTC6_CRTC_V_TOTAL 0x4787 230 #define mmCRTC_V_TOTAL_MIN 0x1b88 231 #define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 232 #define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 233 #define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 234 #define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 235 #define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 236 #define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 237 #define mmCRTC6_CRTC_V_TOTAL_MIN 0x4788 238 #define mmCRTC_V_TOTAL_MAX 0x1b89 239 #define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 240 #define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 241 #define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 242 #define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 243 #define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 244 #define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 245 #define mmCRTC6_CRTC_V_TOTAL_MAX 0x4789 246 #define mmCRTC_V_TOTAL_CONTROL 0x1b8a 247 #define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a 248 #define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a 249 #define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a 250 #define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a 251 #define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a 252 #define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a 253 #define mmCRTC6_CRTC_V_TOTAL_CONTROL 0x478a 254 #define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b 255 #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b 256 #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b 257 #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b 258 #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b 259 #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b 260 #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b 261 #define mmCRTC6_CRTC_V_TOTAL_INT_STATUS 0x478b 262 #define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c 263 #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c 264 #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c 265 #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c 266 #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c 267 #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c 268 #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c 269 #define mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS 0x478c 270 #define mmCRTC_V_BLANK_START_END 0x1b8d 271 #define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d 272 #define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d 273 #define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d 274 #define mmCRTC3_CRTC_V_BLANK_START_END 0x418d 275 #define mmCRTC4_CRTC_V_BLANK_START_END 0x438d 276 #define mmCRTC5_CRTC_V_BLANK_START_END 0x458d 277 #define mmCRTC6_CRTC_V_BLANK_START_END 0x478d 278 #define mmCRTC_V_SYNC_A 0x1b8e 279 #define mmCRTC0_CRTC_V_SYNC_A 0x1b8e 280 #define mmCRTC1_CRTC_V_SYNC_A 0x1d8e 281 #define mmCRTC2_CRTC_V_SYNC_A 0x1f8e 282 #define mmCRTC3_CRTC_V_SYNC_A 0x418e 283 #define mmCRTC4_CRTC_V_SYNC_A 0x438e 284 #define mmCRTC5_CRTC_V_SYNC_A 0x458e 285 #define mmCRTC6_CRTC_V_SYNC_A 0x478e 286 #define mmCRTC_V_SYNC_A_CNTL 0x1b8f 287 #define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f 288 #define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f 289 #define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f 290 #define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f 291 #define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f 292 #define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f 293 #define mmCRTC6_CRTC_V_SYNC_A_CNTL 0x478f 294 #define mmCRTC_V_SYNC_B 0x1b90 295 #define mmCRTC0_CRTC_V_SYNC_B 0x1b90 296 #define mmCRTC1_CRTC_V_SYNC_B 0x1d90 297 #define mmCRTC2_CRTC_V_SYNC_B 0x1f90 298 #define mmCRTC3_CRTC_V_SYNC_B 0x4190 299 #define mmCRTC4_CRTC_V_SYNC_B 0x4390 300 #define mmCRTC5_CRTC_V_SYNC_B 0x4590 301 #define mmCRTC6_CRTC_V_SYNC_B 0x4790 302 #define mmCRTC_V_SYNC_B_CNTL 0x1b91 303 #define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 304 #define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 305 #define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 306 #define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 307 #define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 308 #define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 309 #define mmCRTC6_CRTC_V_SYNC_B_CNTL 0x4791 310 #define mmCRTC_DTMTEST_CNTL 0x1b92 311 #define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 312 #define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 313 #define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 314 #define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 315 #define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 316 #define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 317 #define mmCRTC6_CRTC_DTMTEST_CNTL 0x4792 318 #define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 319 #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 320 #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 321 #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 322 #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 323 #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 324 #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 325 #define mmCRTC6_CRTC_DTMTEST_STATUS_POSITION 0x4793 326 #define mmCRTC_TRIGA_CNTL 0x1b94 327 #define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 328 #define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 329 #define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 330 #define mmCRTC3_CRTC_TRIGA_CNTL 0x4194 331 #define mmCRTC4_CRTC_TRIGA_CNTL 0x4394 332 #define mmCRTC5_CRTC_TRIGA_CNTL 0x4594 333 #define mmCRTC6_CRTC_TRIGA_CNTL 0x4794 334 #define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 335 #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 336 #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 337 #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 338 #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 339 #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 340 #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 341 #define mmCRTC6_CRTC_TRIGA_MANUAL_TRIG 0x4795 342 #define mmCRTC_TRIGB_CNTL 0x1b96 343 #define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 344 #define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 345 #define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 346 #define mmCRTC3_CRTC_TRIGB_CNTL 0x4196 347 #define mmCRTC4_CRTC_TRIGB_CNTL 0x4396 348 #define mmCRTC5_CRTC_TRIGB_CNTL 0x4596 349 #define mmCRTC6_CRTC_TRIGB_CNTL 0x4796 350 #define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 351 #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 352 #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 353 #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 354 #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 355 #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 356 #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 357 #define mmCRTC6_CRTC_TRIGB_MANUAL_TRIG 0x4797 358 #define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 359 #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 360 #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 361 #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 362 #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 363 #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 364 #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 365 #define mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 366 #define mmCRTC_FLOW_CONTROL 0x1b99 367 #define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 368 #define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 369 #define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 370 #define mmCRTC3_CRTC_FLOW_CONTROL 0x4199 371 #define mmCRTC4_CRTC_FLOW_CONTROL 0x4399 372 #define mmCRTC5_CRTC_FLOW_CONTROL 0x4599 373 #define mmCRTC6_CRTC_FLOW_CONTROL 0x4799 374 #define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a 375 #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a 376 #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a 377 #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a 378 #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a 379 #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a 380 #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a 381 #define mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE 0x479a 382 #define mmCRTC_AVSYNC_COUNTER 0x1b9b 383 #define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b 384 #define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b 385 #define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b 386 #define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b 387 #define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b 388 #define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b 389 #define mmCRTC6_CRTC_AVSYNC_COUNTER 0x479b 390 #define mmCRTC_CONTROL 0x1b9c 391 #define mmCRTC0_CRTC_CONTROL 0x1b9c 392 #define mmCRTC1_CRTC_CONTROL 0x1d9c 393 #define mmCRTC2_CRTC_CONTROL 0x1f9c 394 #define mmCRTC3_CRTC_CONTROL 0x419c 395 #define mmCRTC4_CRTC_CONTROL 0x439c 396 #define mmCRTC5_CRTC_CONTROL 0x459c 397 #define mmCRTC6_CRTC_CONTROL 0x479c 398 #define mmCRTC_BLANK_CONTROL 0x1b9d 399 #define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d 400 #define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d 401 #define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d 402 #define mmCRTC3_CRTC_BLANK_CONTROL 0x419d 403 #define mmCRTC4_CRTC_BLANK_CONTROL 0x439d 404 #define mmCRTC5_CRTC_BLANK_CONTROL 0x459d 405 #define mmCRTC6_CRTC_BLANK_CONTROL 0x479d 406 #define mmCRTC_INTERLACE_CONTROL 0x1b9e 407 #define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e 408 #define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e 409 #define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e 410 #define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e 411 #define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e 412 #define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e 413 #define mmCRTC6_CRTC_INTERLACE_CONTROL 0x479e 414 #define mmCRTC_INTERLACE_STATUS 0x1b9f 415 #define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f 416 #define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f 417 #define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f 418 #define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f 419 #define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f 420 #define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f 421 #define mmCRTC6_CRTC_INTERLACE_STATUS 0x479f 422 #define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 423 #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 424 #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 425 #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 426 #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 427 #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 428 #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 429 #define mmCRTC6_CRTC_FIELD_INDICATION_CONTROL 0x47a0 430 #define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 431 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 432 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 433 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 434 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 435 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 436 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 437 #define mmCRTC6_CRTC_PIXEL_DATA_READBACK0 0x47a1 438 #define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 439 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 440 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 441 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 442 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 443 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 444 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 445 #define mmCRTC6_CRTC_PIXEL_DATA_READBACK1 0x47a2 446 #define mmCRTC_STATUS 0x1ba3 447 #define mmCRTC0_CRTC_STATUS 0x1ba3 448 #define mmCRTC1_CRTC_STATUS 0x1da3 449 #define mmCRTC2_CRTC_STATUS 0x1fa3 450 #define mmCRTC3_CRTC_STATUS 0x41a3 451 #define mmCRTC4_CRTC_STATUS 0x43a3 452 #define mmCRTC5_CRTC_STATUS 0x45a3 453 #define mmCRTC6_CRTC_STATUS 0x47a3 454 #define mmCRTC_STATUS_POSITION 0x1ba4 455 #define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 456 #define mmCRTC1_CRTC_STATUS_POSITION 0x1da4 457 #define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 458 #define mmCRTC3_CRTC_STATUS_POSITION 0x41a4 459 #define mmCRTC4_CRTC_STATUS_POSITION 0x43a4 460 #define mmCRTC5_CRTC_STATUS_POSITION 0x45a4 461 #define mmCRTC6_CRTC_STATUS_POSITION 0x47a4 462 #define mmCRTC_NOM_VERT_POSITION 0x1ba5 463 #define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 464 #define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 465 #define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 466 #define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 467 #define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 468 #define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 469 #define mmCRTC6_CRTC_NOM_VERT_POSITION 0x47a5 470 #define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 471 #define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 472 #define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 473 #define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 474 #define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 475 #define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 476 #define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 477 #define mmCRTC6_CRTC_STATUS_FRAME_COUNT 0x47a6 478 #define mmCRTC_STATUS_VF_COUNT 0x1ba7 479 #define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 480 #define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 481 #define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 482 #define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 483 #define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 484 #define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 485 #define mmCRTC6_CRTC_STATUS_VF_COUNT 0x47a7 486 #define mmCRTC_STATUS_HV_COUNT 0x1ba8 487 #define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 488 #define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 489 #define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 490 #define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 491 #define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 492 #define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 493 #define mmCRTC6_CRTC_STATUS_HV_COUNT 0x47a8 494 #define mmCRTC_COUNT_CONTROL 0x1ba9 495 #define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 496 #define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 497 #define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 498 #define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 499 #define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 500 #define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 501 #define mmCRTC6_CRTC_COUNT_CONTROL 0x47a9 502 #define mmCRTC_COUNT_RESET 0x1baa 503 #define mmCRTC0_CRTC_COUNT_RESET 0x1baa 504 #define mmCRTC1_CRTC_COUNT_RESET 0x1daa 505 #define mmCRTC2_CRTC_COUNT_RESET 0x1faa 506 #define mmCRTC3_CRTC_COUNT_RESET 0x41aa 507 #define mmCRTC4_CRTC_COUNT_RESET 0x43aa 508 #define mmCRTC5_CRTC_COUNT_RESET 0x45aa 509 #define mmCRTC6_CRTC_COUNT_RESET 0x47aa 510 #define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab 511 #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab 512 #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab 513 #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab 514 #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab 515 #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab 516 #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab 517 #define mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab 518 #define mmCRTC_VERT_SYNC_CONTROL 0x1bac 519 #define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac 520 #define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac 521 #define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac 522 #define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac 523 #define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac 524 #define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac 525 #define mmCRTC6_CRTC_VERT_SYNC_CONTROL 0x47ac 526 #define mmCRTC_STEREO_STATUS 0x1bad 527 #define mmCRTC0_CRTC_STEREO_STATUS 0x1bad 528 #define mmCRTC1_CRTC_STEREO_STATUS 0x1dad 529 #define mmCRTC2_CRTC_STEREO_STATUS 0x1fad 530 #define mmCRTC3_CRTC_STEREO_STATUS 0x41ad 531 #define mmCRTC4_CRTC_STEREO_STATUS 0x43ad 532 #define mmCRTC5_CRTC_STEREO_STATUS 0x45ad 533 #define mmCRTC6_CRTC_STEREO_STATUS 0x47ad 534 #define mmCRTC_STEREO_CONTROL 0x1bae 535 #define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae 536 #define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae 537 #define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae 538 #define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae 539 #define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae 540 #define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae 541 #define mmCRTC6_CRTC_STEREO_CONTROL 0x47ae 542 #define mmCRTC_SNAPSHOT_STATUS 0x1baf 543 #define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf 544 #define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf 545 #define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf 546 #define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af 547 #define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af 548 #define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af 549 #define mmCRTC6_CRTC_SNAPSHOT_STATUS 0x47af 550 #define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 551 #define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 552 #define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 553 #define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 554 #define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 555 #define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 556 #define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 557 #define mmCRTC6_CRTC_SNAPSHOT_CONTROL 0x47b0 558 #define mmCRTC_SNAPSHOT_POSITION 0x1bb1 559 #define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 560 #define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 561 #define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 562 #define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 563 #define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 564 #define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 565 #define mmCRTC6_CRTC_SNAPSHOT_POSITION 0x47b1 566 #define mmCRTC_SNAPSHOT_FRAME 0x1bb2 567 #define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 568 #define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 569 #define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 570 #define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 571 #define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 572 #define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 573 #define mmCRTC6_CRTC_SNAPSHOT_FRAME 0x47b2 574 #define mmCRTC_START_LINE_CONTROL 0x1bb3 575 #define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 576 #define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 577 #define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 578 #define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 579 #define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 580 #define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 581 #define mmCRTC6_CRTC_START_LINE_CONTROL 0x47b3 582 #define mmCRTC_INTERRUPT_CONTROL 0x1bb4 583 #define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 584 #define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 585 #define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 586 #define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 587 #define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 588 #define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 589 #define mmCRTC6_CRTC_INTERRUPT_CONTROL 0x47b4 590 #define mmCRTC_UPDATE_LOCK 0x1bb5 591 #define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 592 #define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 593 #define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 594 #define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 595 #define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 596 #define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 597 #define mmCRTC6_CRTC_UPDATE_LOCK 0x47b5 598 #define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 599 #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 600 #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 601 #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 602 #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 603 #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 604 #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 605 #define mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL 0x47b6 606 #define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 607 #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 608 #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 609 #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 610 #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 611 #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 612 #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 613 #define mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47b7 614 #define mmCRTC_TEST_PATTERN_CONTROL 0x1bba 615 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba 616 #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba 617 #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba 618 #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba 619 #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba 620 #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba 621 #define mmCRTC6_CRTC_TEST_PATTERN_CONTROL 0x47ba 622 #define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb 623 #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb 624 #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb 625 #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb 626 #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb 627 #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb 628 #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb 629 #define mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS 0x47bb 630 #define mmCRTC_TEST_PATTERN_COLOR 0x1bbc 631 #define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc 632 #define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc 633 #define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc 634 #define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc 635 #define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc 636 #define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc 637 #define mmCRTC6_CRTC_TEST_PATTERN_COLOR 0x47bc 638 #define mmMASTER_UPDATE_LOCK 0x1bbd 639 #define mmCRTC0_MASTER_UPDATE_LOCK 0x1bbd 640 #define mmCRTC1_MASTER_UPDATE_LOCK 0x1dbd 641 #define mmCRTC2_MASTER_UPDATE_LOCK 0x1fbd 642 #define mmCRTC3_MASTER_UPDATE_LOCK 0x41bd 643 #define mmCRTC4_MASTER_UPDATE_LOCK 0x43bd 644 #define mmCRTC5_MASTER_UPDATE_LOCK 0x45bd 645 #define mmCRTC6_MASTER_UPDATE_LOCK 0x47bd 646 #define mmMASTER_UPDATE_MODE 0x1bbe 647 #define mmCRTC0_MASTER_UPDATE_MODE 0x1bbe 648 #define mmCRTC1_MASTER_UPDATE_MODE 0x1dbe 649 #define mmCRTC2_MASTER_UPDATE_MODE 0x1fbe 650 #define mmCRTC3_MASTER_UPDATE_MODE 0x41be 651 #define mmCRTC4_MASTER_UPDATE_MODE 0x43be 652 #define mmCRTC5_MASTER_UPDATE_MODE 0x45be 653 #define mmCRTC6_MASTER_UPDATE_MODE 0x47be 654 #define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf 655 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf 656 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf 657 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf 658 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf 659 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf 660 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf 661 #define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT 0x47bf 662 #define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 663 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 664 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 665 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 666 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 667 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 668 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 669 #define mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0 670 #define mmCRTC_MVP_STATUS 0x1bc1 671 #define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 672 #define mmCRTC1_CRTC_MVP_STATUS 0x1dc1 673 #define mmCRTC2_CRTC_MVP_STATUS 0x1fc1 674 #define mmCRTC3_CRTC_MVP_STATUS 0x41c1 675 #define mmCRTC4_CRTC_MVP_STATUS 0x43c1 676 #define mmCRTC5_CRTC_MVP_STATUS 0x45c1 677 #define mmCRTC6_CRTC_MVP_STATUS 0x47c1 678 #define mmCRTC_MASTER_EN 0x1bc2 679 #define mmCRTC0_CRTC_MASTER_EN 0x1bc2 680 #define mmCRTC1_CRTC_MASTER_EN 0x1dc2 681 #define mmCRTC2_CRTC_MASTER_EN 0x1fc2 682 #define mmCRTC3_CRTC_MASTER_EN 0x41c2 683 #define mmCRTC4_CRTC_MASTER_EN 0x43c2 684 #define mmCRTC5_CRTC_MASTER_EN 0x45c2 685 #define mmCRTC6_CRTC_MASTER_EN 0x47c2 686 #define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 687 #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 688 #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 689 #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 690 #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 691 #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 692 #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 693 #define mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT 0x47c3 694 #define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 695 #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 696 #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 697 #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 698 #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 699 #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 700 #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 701 #define mmCRTC6_CRTC_V_UPDATE_INT_STATUS 0x47c4 702 #define mmCRTC_OVERSCAN_COLOR 0x1bc8 703 #define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 704 #define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 705 #define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 706 #define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 707 #define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 708 #define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 709 #define mmCRTC6_CRTC_OVERSCAN_COLOR 0x47c8 710 #define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 711 #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 712 #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 713 #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 714 #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 715 #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 716 #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 717 #define mmCRTC6_CRTC_OVERSCAN_COLOR_EXT 0x47c9 718 #define mmCRTC_BLANK_DATA_COLOR 0x1bca 719 #define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca 720 #define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca 721 #define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca 722 #define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca 723 #define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca 724 #define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca 725 #define mmCRTC6_CRTC_BLANK_DATA_COLOR 0x47ca 726 #define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb 727 #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb 728 #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb 729 #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb 730 #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb 731 #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb 732 #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb 733 #define mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT 0x47cb 734 #define mmCRTC_BLACK_COLOR 0x1bcc 735 #define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc 736 #define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc 737 #define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc 738 #define mmCRTC3_CRTC_BLACK_COLOR 0x41cc 739 #define mmCRTC4_CRTC_BLACK_COLOR 0x43cc 740 #define mmCRTC5_CRTC_BLACK_COLOR 0x45cc 741 #define mmCRTC6_CRTC_BLACK_COLOR 0x47cc 742 #define mmCRTC_BLACK_COLOR_EXT 0x1bcd 743 #define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd 744 #define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd 745 #define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd 746 #define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd 747 #define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd 748 #define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd 749 #define mmCRTC6_CRTC_BLACK_COLOR_EXT 0x47cd 750 #define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce 751 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce 752 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce 753 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce 754 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce 755 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce 756 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce 757 #define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION 0x47ce 758 #define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf 759 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf 760 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf 761 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf 762 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf 763 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf 764 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf 765 #define mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x47cf 766 #define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 767 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 768 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 769 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 770 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 771 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 772 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 773 #define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION 0x47d0 774 #define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 775 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 776 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 777 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 778 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 779 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 780 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 781 #define mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x47d1 782 #define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 783 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 784 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 785 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 786 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 787 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 788 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 789 #define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION 0x47d2 790 #define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 791 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 792 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 793 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 794 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 795 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 796 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 797 #define mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x47d3 798 #define mmCRTC_CRC_CNTL 0x1bd4 799 #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 800 #define mmCRTC1_CRTC_CRC_CNTL 0x1dd4 801 #define mmCRTC2_CRTC_CRC_CNTL 0x1fd4 802 #define mmCRTC3_CRTC_CRC_CNTL 0x41d4 803 #define mmCRTC4_CRTC_CRC_CNTL 0x43d4 804 #define mmCRTC5_CRTC_CRC_CNTL 0x45d4 805 #define mmCRTC6_CRTC_CRC_CNTL 0x47d4 806 #define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 807 #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 808 #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 809 #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 810 #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 811 #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 812 #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 813 #define mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL 0x47d5 814 #define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 815 #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 816 #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 817 #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 818 #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 819 #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 820 #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 821 #define mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL 0x47d6 822 #define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 823 #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 824 #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 825 #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 826 #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 827 #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 828 #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 829 #define mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL 0x47d7 830 #define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 831 #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 832 #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 833 #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 834 #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 835 #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 836 #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 837 #define mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL 0x47d8 838 #define mmCRTC_CRC0_DATA_RG 0x1bd9 839 #define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 840 #define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 841 #define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 842 #define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 843 #define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 844 #define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 845 #define mmCRTC6_CRTC_CRC0_DATA_RG 0x47d9 846 #define mmCRTC_CRC0_DATA_B 0x1bda 847 #define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda 848 #define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda 849 #define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda 850 #define mmCRTC3_CRTC_CRC0_DATA_B 0x41da 851 #define mmCRTC4_CRTC_CRC0_DATA_B 0x43da 852 #define mmCRTC5_CRTC_CRC0_DATA_B 0x45da 853 #define mmCRTC6_CRTC_CRC0_DATA_B 0x47da 854 #define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb 855 #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb 856 #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb 857 #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb 858 #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db 859 #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db 860 #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db 861 #define mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL 0x47db 862 #define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc 863 #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc 864 #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc 865 #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc 866 #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc 867 #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc 868 #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc 869 #define mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL 0x47dc 870 #define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd 871 #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd 872 #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd 873 #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd 874 #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd 875 #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd 876 #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd 877 #define mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL 0x47dd 878 #define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde 879 #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde 880 #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde 881 #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde 882 #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de 883 #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de 884 #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de 885 #define mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL 0x47de 886 #define mmCRTC_CRC1_DATA_RG 0x1bdf 887 #define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf 888 #define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf 889 #define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf 890 #define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df 891 #define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df 892 #define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df 893 #define mmCRTC6_CRTC_CRC1_DATA_RG 0x47df 894 #define mmCRTC_CRC1_DATA_B 0x1be0 895 #define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 896 #define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 897 #define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 898 #define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 899 #define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 900 #define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 901 #define mmCRTC6_CRTC_CRC1_DATA_B 0x47e0 902 #define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 903 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 904 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1de1 905 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x1fe1 906 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 907 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x43e1 908 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x45e1 909 #define mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL 0x47e1 910 #define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 911 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 912 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1de2 913 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1fe2 914 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 915 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x43e2 916 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x45e2 917 #define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x47e2 918 #define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 919 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 920 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1de3 921 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1fe3 922 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 923 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x43e3 924 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x45e3 925 #define mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x47e3 926 #define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 927 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 928 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1de4 929 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1fe4 930 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 931 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x43e4 932 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x45e4 933 #define mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x47e4 934 #define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 935 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 936 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1de5 937 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1fe5 938 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 939 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x43e5 940 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x45e5 941 #define mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x47e5 942 #define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 943 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 944 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1de6 945 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1fe6 946 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 947 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x43e6 948 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x45e6 949 #define mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x47e6 950 #define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 951 #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 952 #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 953 #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 954 #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 955 #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 956 #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 957 #define mmCRTC6_CRTC_STATIC_SCREEN_CONTROL 0x47e7 958 #define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 959 #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 960 #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 961 #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 962 #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 963 #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 964 #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 965 #define mmCRTC6_CRTC_3D_STRUCTURE_CONTROL 0x4778 966 #define mmCRTC_GSL_VSYNC_GAP 0x1b79 967 #define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 968 #define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 969 #define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 970 #define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 971 #define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 972 #define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 973 #define mmCRTC6_CRTC_GSL_VSYNC_GAP 0x4779 974 #define mmCRTC_GSL_WINDOW 0x1b7a 975 #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a 976 #define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a 977 #define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a 978 #define mmCRTC3_CRTC_GSL_WINDOW 0x417a 979 #define mmCRTC4_CRTC_GSL_WINDOW 0x437a 980 #define mmCRTC5_CRTC_GSL_WINDOW 0x457a 981 #define mmCRTC6_CRTC_GSL_WINDOW 0x477a 982 #define mmCRTC_GSL_CONTROL 0x1b7b 983 #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b 984 #define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b 985 #define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b 986 #define mmCRTC3_CRTC_GSL_CONTROL 0x417b 987 #define mmCRTC4_CRTC_GSL_CONTROL 0x437b 988 #define mmCRTC5_CRTC_GSL_CONTROL 0x457b 989 #define mmCRTC6_CRTC_GSL_CONTROL 0x477b 990 #define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 991 #define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 992 #define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 993 #define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 994 #define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 995 #define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 996 #define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 997 #define mmCRTC6_CRTC_TEST_DEBUG_INDEX 0x47c6 998 #define mmCRTC_TEST_DEBUG_DATA 0x1bc7 999 #define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 1000 #define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 1001 #define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 1002 #define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 1003 #define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 1004 #define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 1005 #define mmCRTC6_CRTC_TEST_DEBUG_DATA 0x47c7 1006 #define mmDAC_ENABLE 0x16aa 1007 #define mmDAC_SOURCE_SELECT 0x16ab 1008 #define mmDAC_CRC_EN 0x16ac 1009 #define mmDAC_CRC_CONTROL 0x16ad 1010 #define mmDAC_CRC_SIG_RGB_MASK 0x16ae 1011 #define mmDAC_CRC_SIG_CONTROL_MASK 0x16af 1012 #define mmDAC_CRC_SIG_RGB 0x16b0 1013 #define mmDAC_CRC_SIG_CONTROL 0x16b1 1014 #define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 1015 #define mmDAC_STEREOSYNC_SELECT 0x16b3 1016 #define mmDAC_AUTODETECT_CONTROL 0x16b4 1017 #define mmDAC_AUTODETECT_CONTROL2 0x16b5 1018 #define mmDAC_AUTODETECT_CONTROL3 0x16b6 1019 #define mmDAC_AUTODETECT_STATUS 0x16b7 1020 #define mmDAC_AUTODETECT_INT_CONTROL 0x16b8 1021 #define mmDAC_FORCE_OUTPUT_CNTL 0x16b9 1022 #define mmDAC_FORCE_DATA 0x16ba 1023 #define mmDAC_POWERDOWN 0x16bb 1024 #define mmDAC_CONTROL 0x16bc 1025 #define mmDAC_COMPARATOR_ENABLE 0x16bd 1026 #define mmDAC_COMPARATOR_OUTPUT 0x16be 1027 #define mmDAC_PWR_CNTL 0x16bf 1028 #define mmDAC_DFT_CONFIG 0x16c0 1029 #define mmDAC_FIFO_STATUS 0x16c1 1030 #define mmDAC_TEST_DEBUG_INDEX 0x16c2 1031 #define mmDAC_TEST_DEBUG_DATA 0x16c3 1032 #define mmPERFCOUNTER_CNTL 0x170 1033 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 1034 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364 1035 #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8 1036 #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24 1037 #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24 1038 #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24 1039 #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124 1040 #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324 1041 #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524 1042 #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724 1043 #define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0 1044 #define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68 1045 #define mmPERFCOUNTER_STATE 0x171 1046 #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 1047 #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x365 1048 #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9 1049 #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25 1050 #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25 1051 #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25 1052 #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125 1053 #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325 1054 #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525 1055 #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725 1056 #define mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1 1057 #define mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69 1058 #define mmPERFMON_CNTL 0x173 1059 #define mmDC_PERFMON0_PERFMON_CNTL 0x173 1060 #define mmDC_PERFMON1_PERFMON_CNTL 0x367 1061 #define mmDC_PERFMON2_PERFMON_CNTL 0x18cb 1062 #define mmDC_PERFMON3_PERFMON_CNTL 0x1b27 1063 #define mmDC_PERFMON4_PERFMON_CNTL 0x1d27 1064 #define mmDC_PERFMON5_PERFMON_CNTL 0x1f27 1065 #define mmDC_PERFMON6_PERFMON_CNTL 0x4127 1066 #define mmDC_PERFMON7_PERFMON_CNTL 0x4327 1067 #define mmDC_PERFMON8_PERFMON_CNTL 0x4527 1068 #define mmDC_PERFMON9_PERFMON_CNTL 0x4727 1069 #define mmDC_PERFMON10_PERFMON_CNTL 0x59a3 1070 #define mmDC_PERFMON11_PERFMON_CNTL 0x5f6b 1071 #define mmPERFMON_CNTL2 0x17a 1072 #define mmDC_PERFMON0_PERFMON_CNTL2 0x17a 1073 #define mmDC_PERFMON1_PERFMON_CNTL2 0x36e 1074 #define mmDC_PERFMON2_PERFMON_CNTL2 0x18d2 1075 #define mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e 1076 #define mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e 1077 #define mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e 1078 #define mmDC_PERFMON6_PERFMON_CNTL2 0x412e 1079 #define mmDC_PERFMON7_PERFMON_CNTL2 0x432e 1080 #define mmDC_PERFMON8_PERFMON_CNTL2 0x452e 1081 #define mmDC_PERFMON9_PERFMON_CNTL2 0x472e 1082 #define mmDC_PERFMON10_PERFMON_CNTL2 0x59aa 1083 #define mmDC_PERFMON11_PERFMON_CNTL2 0x5f72 1084 #define mmPERFMON_CVALUE_INT_MISC 0x172 1085 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 1086 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366 1087 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca 1088 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26 1089 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26 1090 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26 1091 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126 1092 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326 1093 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526 1094 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726 1095 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2 1096 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a 1097 #define mmPERFMON_CVALUE_LOW 0x174 1098 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 1099 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368 1100 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc 1101 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28 1102 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28 1103 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28 1104 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128 1105 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328 1106 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528 1107 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728 1108 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4 1109 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c 1110 #define mmPERFMON_HI 0x175 1111 #define mmDC_PERFMON0_PERFMON_HI 0x175 1112 #define mmDC_PERFMON1_PERFMON_HI 0x369 1113 #define mmDC_PERFMON2_PERFMON_HI 0x18cd 1114 #define mmDC_PERFMON3_PERFMON_HI 0x1b29 1115 #define mmDC_PERFMON4_PERFMON_HI 0x1d29 1116 #define mmDC_PERFMON5_PERFMON_HI 0x1f29 1117 #define mmDC_PERFMON6_PERFMON_HI 0x4129 1118 #define mmDC_PERFMON7_PERFMON_HI 0x4329 1119 #define mmDC_PERFMON8_PERFMON_HI 0x4529 1120 #define mmDC_PERFMON9_PERFMON_HI 0x4729 1121 #define mmDC_PERFMON10_PERFMON_HI 0x59a5 1122 #define mmDC_PERFMON11_PERFMON_HI 0x5f6d 1123 #define mmPERFMON_LOW 0x176 1124 #define mmDC_PERFMON0_PERFMON_LOW 0x176 1125 #define mmDC_PERFMON1_PERFMON_LOW 0x36a 1126 #define mmDC_PERFMON2_PERFMON_LOW 0x18ce 1127 #define mmDC_PERFMON3_PERFMON_LOW 0x1b2a 1128 #define mmDC_PERFMON4_PERFMON_LOW 0x1d2a 1129 #define mmDC_PERFMON5_PERFMON_LOW 0x1f2a 1130 #define mmDC_PERFMON6_PERFMON_LOW 0x412a 1131 #define mmDC_PERFMON7_PERFMON_LOW 0x432a 1132 #define mmDC_PERFMON8_PERFMON_LOW 0x452a 1133 #define mmDC_PERFMON9_PERFMON_LOW 0x472a 1134 #define mmDC_PERFMON10_PERFMON_LOW 0x59a6 1135 #define mmDC_PERFMON11_PERFMON_LOW 0x5f6e 1136 #define mmPERFMON_TEST_DEBUG_INDEX 0x177 1137 #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 1138 #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b 1139 #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf 1140 #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b 1141 #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b 1142 #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b 1143 #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b 1144 #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b 1145 #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b 1146 #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b 1147 #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7 1148 #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f 1149 #define mmPERFMON_TEST_DEBUG_DATA 0x178 1150 #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 1151 #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c 1152 #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0 1153 #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c 1154 #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c 1155 #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c 1156 #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c 1157 #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c 1158 #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c 1159 #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c 1160 #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8 1161 #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70 1162 #define mmREFCLK_CNTL 0x109 1163 #define mmDCCG_CBUS_WRCMD_DELAY 0x110 1164 #define mmDPREFCLK_CNTL 0x118 1165 #define mmAVSYNC_COUNTER_WRITE 0x12a 1166 #define mmAVSYNC_COUNTER_CONTROL 0x12b 1167 #define mmAVSYNC_COUNTER_READ 0x12f 1168 #define mmDCCG_GTC_CNTL 0x120 1169 #define mmDCCG_GTC_DTO_INCR 0x121 1170 #define mmDCCG_GTC_DTO_MODULO 0x122 1171 #define mmDCCG_GTC_CURRENT 0x123 1172 #define mmDCCG_DS_DTO_INCR 0x113 1173 #define mmDCCG_DS_DTO_MODULO 0x114 1174 #define mmDCCG_DS_CNTL 0x115 1175 #define mmDCCG_DS_HW_CAL_INTERVAL 0x116 1176 #define mmDCCG_DS_DEBUG_CNTL 0x112 1177 #define mmDMCU_SMU_INTERRUPT_CNTL 0x12c 1178 #define mmSMU_CONTROL 0x12d 1179 #define mmSMU_INTERRUPT_CONTROL 0x12e 1180 #define mmDAC_CLK_ENABLE 0x128 1181 #define mmDVO_CLK_ENABLE 0x129 1182 #define mmDCCG_GATE_DISABLE_CNTL 0x134 1183 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 1184 #define mmSCLK_CGTT_BLK_CTRL_REG 0x136 1185 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 1186 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b 1187 #define mmDCCG_CAC_STATUS 0x137 1188 #define mmPIXCLK1_RESYNC_CNTL 0x138 1189 #define mmPIXCLK2_RESYNC_CNTL 0x139 1190 #define mmPIXCLK0_RESYNC_CNTL 0x13a 1191 #define mmMICROSECOND_TIME_BASE_DIV 0x13b 1192 #define mmDCCG_DISP_CNTL_REG 0x13f 1193 #define mmMILLISECOND_TIME_BASE_DIV 0x130 1194 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 1195 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 1196 #define mmDCCG_PERFMON_CNTL 0x133 1197 #define mmDCCG_PERFMON_CNTL2 0x10e 1198 #define mmCRTC0_PIXEL_RATE_CNTL 0x140 1199 #define mmDP_DTO0_PHASE 0x141 1200 #define mmDP_DTO0_MODULO 0x142 1201 #define mmCRTC1_PIXEL_RATE_CNTL 0x144 1202 #define mmDP_DTO1_PHASE 0x145 1203 #define mmDP_DTO1_MODULO 0x146 1204 #define mmCRTC2_PIXEL_RATE_CNTL 0x148 1205 #define mmDP_DTO2_PHASE 0x149 1206 #define mmDP_DTO2_MODULO 0x14a 1207 #define mmCRTC3_PIXEL_RATE_CNTL 0x14c 1208 #define mmDP_DTO3_PHASE 0x14d 1209 #define mmDP_DTO3_MODULO 0x14e 1210 #define mmCRTC4_PIXEL_RATE_CNTL 0x150 1211 #define mmDP_DTO4_PHASE 0x151 1212 #define mmDP_DTO4_MODULO 0x152 1213 #define mmCRTC5_PIXEL_RATE_CNTL 0x154 1214 #define mmDP_DTO5_PHASE 0x155 1215 #define mmDP_DTO5_MODULO 0x156 1216 #define mmDCCG_SOFT_RESET 0x15f 1217 #define mmSYMCLKA_CLOCK_ENABLE 0x160 1218 #define mmSYMCLKB_CLOCK_ENABLE 0x161 1219 #define mmSYMCLKC_CLOCK_ENABLE 0x162 1220 #define mmSYMCLKD_CLOCK_ENABLE 0x163 1221 #define mmSYMCLKE_CLOCK_ENABLE 0x164 1222 #define mmSYMCLKF_CLOCK_ENABLE 0x165 1223 #define mmDPDBG_CLK_FORCE_CONTROL 0x10d 1224 #define mmDVOACLKD_CNTL 0x168 1225 #define mmDVOACLKC_MVP_CNTL 0x169 1226 #define mmDVOACLKC_CNTL 0x16a 1227 #define mmDCCG_AUDIO_DTO_SOURCE 0x16b 1228 #define mmDCCG_AUDIO_DTO0_PHASE 0x16c 1229 #define mmDCCG_AUDIO_DTO0_MODULE 0x16d 1230 #define mmDCCG_AUDIO_DTO1_PHASE 0x16e 1231 #define mmDCCG_AUDIO_DTO1_MODULE 0x16f 1232 #define mmDCCG_TEST_DEBUG_INDEX 0x17c 1233 #define mmDCCG_TEST_DEBUG_DATA 0x17d 1234 #define mmDCCG_TEST_CLK_SEL 0x17e 1235 #define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 1236 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 1237 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc 1238 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 1239 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 1240 #define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 1241 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 1242 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd 1243 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 1244 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 1245 #define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 1246 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 1247 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde 1248 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea 1249 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 1250 #define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 1251 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 1252 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf 1253 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb 1254 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 1255 #define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 1256 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 1257 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 1258 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec 1259 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 1260 #define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 1261 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 1262 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 1263 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed 1264 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 1265 #define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 1266 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 1267 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 1268 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee 1269 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa 1270 #define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 1271 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 1272 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 1273 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef 1274 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb 1275 #define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 1276 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 1277 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 1278 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 1279 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc 1280 #define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 1281 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 1282 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 1283 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 1284 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd 1285 #define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda 1286 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda 1287 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 1288 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 1289 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe 1290 #define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb 1291 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb 1292 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 1293 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 1294 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff 1295 #define mmPLL_MACRO_CNTL_RESERVED0 0x1700 1296 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 1297 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a 1298 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 1299 #define mmPLL_MACRO_CNTL_RESERVED1 0x1701 1300 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 1301 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b 1302 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 1303 #define mmPLL_MACRO_CNTL_RESERVED2 0x1702 1304 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 1305 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c 1306 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 1307 #define mmPLL_MACRO_CNTL_RESERVED3 0x1703 1308 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 1309 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d 1310 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 1311 #define mmPLL_MACRO_CNTL_RESERVED4 0x1704 1312 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 1313 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e 1314 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 1315 #define mmPLL_MACRO_CNTL_RESERVED5 0x1705 1316 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 1317 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f 1318 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 1319 #define mmPLL_MACRO_CNTL_RESERVED6 0x1706 1320 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 1321 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 1322 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a 1323 #define mmPLL_MACRO_CNTL_RESERVED7 0x1707 1324 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 1325 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 1326 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b 1327 #define mmPLL_MACRO_CNTL_RESERVED8 0x1708 1328 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 1329 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 1330 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c 1331 #define mmPLL_MACRO_CNTL_RESERVED9 0x1709 1332 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 1333 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 1334 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d 1335 #define mmPLL_MACRO_CNTL_RESERVED10 0x170a 1336 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a 1337 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 1338 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e 1339 #define mmPLL_MACRO_CNTL_RESERVED11 0x170b 1340 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b 1341 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 1342 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f 1343 #define mmPLL_MACRO_CNTL_RESERVED12 0x170c 1344 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c 1345 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 1346 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 1347 #define mmPLL_MACRO_CNTL_RESERVED13 0x170d 1348 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d 1349 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 1350 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 1351 #define mmPLL_MACRO_CNTL_RESERVED14 0x170e 1352 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e 1353 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 1354 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 1355 #define mmPLL_MACRO_CNTL_RESERVED15 0x170f 1356 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f 1357 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 1358 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 1359 #define mmPLL_MACRO_CNTL_RESERVED16 0x1710 1360 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 1361 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a 1362 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 1363 #define mmPLL_MACRO_CNTL_RESERVED17 0x1711 1364 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 1365 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b 1366 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 1367 #define mmPLL_MACRO_CNTL_RESERVED18 0x1712 1368 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 1369 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c 1370 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 1371 #define mmPLL_MACRO_CNTL_RESERVED19 0x1713 1372 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 1373 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d 1374 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 1375 #define mmPLL_MACRO_CNTL_RESERVED20 0x1714 1376 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 1377 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e 1378 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 1379 #define mmPLL_MACRO_CNTL_RESERVED21 0x1715 1380 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 1381 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f 1382 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 1383 #define mmPLL_MACRO_CNTL_RESERVED22 0x1716 1384 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 1385 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 1386 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a 1387 #define mmPLL_MACRO_CNTL_RESERVED23 0x1717 1388 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 1389 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 1390 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b 1391 #define mmPLL_MACRO_CNTL_RESERVED24 0x1718 1392 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 1393 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 1394 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c 1395 #define mmPLL_MACRO_CNTL_RESERVED25 0x1719 1396 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 1397 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 1398 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d 1399 #define mmPLL_MACRO_CNTL_RESERVED26 0x171a 1400 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a 1401 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 1402 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e 1403 #define mmPLL_MACRO_CNTL_RESERVED27 0x171b 1404 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b 1405 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 1406 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f 1407 #define mmPLL_MACRO_CNTL_RESERVED28 0x171c 1408 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c 1409 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 1410 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 1411 #define mmPLL_MACRO_CNTL_RESERVED29 0x171d 1412 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d 1413 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 1414 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 1415 #define mmPLL_MACRO_CNTL_RESERVED30 0x171e 1416 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e 1417 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 1418 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 1419 #define mmPLL_MACRO_CNTL_RESERVED31 0x171f 1420 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f 1421 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 1422 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 1423 #define mmPLL_MACRO_CNTL_RESERVED32 0x1720 1424 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 1425 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a 1426 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 1427 #define mmPLL_MACRO_CNTL_RESERVED33 0x1721 1428 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 1429 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b 1430 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 1431 #define mmPLL_MACRO_CNTL_RESERVED34 0x1722 1432 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 1433 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c 1434 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 1435 #define mmPLL_MACRO_CNTL_RESERVED35 0x1723 1436 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 1437 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d 1438 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 1439 #define mmPLL_MACRO_CNTL_RESERVED36 0x1724 1440 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 1441 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e 1442 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 1443 #define mmPLL_MACRO_CNTL_RESERVED37 0x1725 1444 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 1445 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f 1446 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 1447 #define mmPLL_MACRO_CNTL_RESERVED38 0x1726 1448 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 1449 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 1450 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a 1451 #define mmPLL_MACRO_CNTL_RESERVED39 0x1727 1452 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 1453 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 1454 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b 1455 #define mmPLL_MACRO_CNTL_RESERVED40 0x1728 1456 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 1457 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 1458 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c 1459 #define mmPLL_MACRO_CNTL_RESERVED41 0x1729 1460 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 1461 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 1462 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d 1463 #define mmDENTIST_DISPCLK_CNTL 0x124 1464 #define mmDCDEBUG_BUS_CLK1_SEL 0x16c4 1465 #define mmDCDEBUG_BUS_CLK2_SEL 0x16c5 1466 #define mmDCDEBUG_BUS_CLK3_SEL 0x16c6 1467 #define mmDCDEBUG_BUS_CLK4_SEL 0x16c7 1468 #define mmDCDEBUG_BUS_CLK5_SEL 0x16c8 1469 #define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 1470 #define mmDCDEBUG_OUT_CNTL 0x16ca 1471 #define mmDCDEBUG_OUT_DATA 0x16cb 1472 #define mmDMIF_ADDR_CONFIG 0x2f5 1473 #define mmDMIF_CONTROL 0x2f6 1474 #define mmDMIF_STATUS 0x2f7 1475 #define mmDMIF_HW_DEBUG 0x2f8 1476 #define mmDMIF_ARBITRATION_CONTROL 0x2f9 1477 #define mmPIPE0_ARBITRATION_CONTROL3 0x2fa 1478 #define mmPIPE1_ARBITRATION_CONTROL3 0x2fb 1479 #define mmPIPE2_ARBITRATION_CONTROL3 0x2fc 1480 #define mmPIPE3_ARBITRATION_CONTROL3 0x2fd 1481 #define mmPIPE4_ARBITRATION_CONTROL3 0x2fe 1482 #define mmPIPE5_ARBITRATION_CONTROL3 0x2ff 1483 #define mmPIPE6_ARBITRATION_CONTROL3 0x32a 1484 #define mmPIPE7_ARBITRATION_CONTROL3 0x32b 1485 #define mmDMIF_P_VMID 0x300 1486 #define mmDMIF_URG_OVERRIDE 0x329 1487 #define mmDMIF_TEST_DEBUG_INDEX 0x301 1488 #define mmDMIF_TEST_DEBUG_DATA 0x302 1489 #define ixDMIF_DEBUG02_CORE0 0x2 1490 #define ixDMIF_DEBUG02_CORE1 0xa 1491 #define mmDMIF_ADDR_CALC 0x303 1492 #define mmDMIF_STATUS2 0x304 1493 #define mmPIPE0_MAX_REQUESTS 0x305 1494 #define mmPIPE1_MAX_REQUESTS 0x306 1495 #define mmPIPE2_MAX_REQUESTS 0x307 1496 #define mmPIPE3_MAX_REQUESTS 0x308 1497 #define mmPIPE4_MAX_REQUESTS 0x309 1498 #define mmPIPE5_MAX_REQUESTS 0x30a 1499 #define mmPIPE6_MAX_REQUESTS 0x32c 1500 #define mmPIPE7_MAX_REQUESTS 0x32d 1501 #define mmLOW_POWER_TILING_CONTROL 0x30b 1502 #define mmMCIF_CONTROL 0x30c 1503 #define mmMCIF_WRITE_COMBINE_CONTROL 0x30d 1504 #define mmMCIF_TEST_DEBUG_INDEX 0x30e 1505 #define mmMCIF_TEST_DEBUG_DATA 0x30f 1506 #define ixIDDCCIF02_DBG_DCCIF_C 0x9 1507 #define ixIDDCCIF04_DBG_DCCIF_E 0xb 1508 #define ixIDDCCIF05_DBG_DCCIF_F 0xc 1509 #define mmMCIF_VMID 0x310 1510 #define mmMCIF_MEM_CONTROL 0x311 1511 #define mmCC_DC_PIPE_DIS 0x312 1512 #define mmMC_DC_INTERFACE_NACK_STATUS 0x313 1513 #define mmRBBMIF_TIMEOUT 0x314 1514 #define mmRBBMIF_STATUS 0x315 1515 #define mmRBBMIF_TIMEOUT_DIS 0x316 1516 #define mmRBBMIF_STATUS_FLAG 0x327 1517 #define mmDCI_MEM_PWR_STATUS 0x317 1518 #define mmDCI_MEM_PWR_STATUS2 0x318 1519 #define mmDCI_CLK_CNTL 0x319 1520 #define mmDCI_MEM_PWR_CNTL 0x31b 1521 #define mmDCI_MEM_PWR_CNTL2 0x31c 1522 #define mmDCI_MEM_PWR_CNTL3 0x31d 1523 #define mmDCI_SOFT_RESET 0x328 1524 #define mmDCI_TEST_DEBUG_INDEX 0x31e 1525 #define mmDCI_TEST_DEBUG_DATA 0x31f 1526 #define mmDCI_DEBUG_CONFIG 0x320 1527 #define mmPIPE0_DMIF_BUFFER_CONTROL 0x321 1528 #define mmPIPE1_DMIF_BUFFER_CONTROL 0x322 1529 #define mmPIPE2_DMIF_BUFFER_CONTROL 0x323 1530 #define mmPIPE3_DMIF_BUFFER_CONTROL 0x324 1531 #define mmPIPE4_DMIF_BUFFER_CONTROL 0x325 1532 #define mmPIPE5_DMIF_BUFFER_CONTROL 0x326 1533 #define mmDC_GENERICA 0x4800 1534 #define mmDC_GENERICB 0x4801 1535 #define mmDC_PAD_EXTERN_SIG 0x4802 1536 #define mmDC_REF_CLK_CNTL 0x4803 1537 #define mmDC_GPIO_DEBUG 0x4804 1538 #define mmUNIPHYA_LINK_CNTL 0x4805 1539 #define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 1540 #define mmUNIPHYB_LINK_CNTL 0x4807 1541 #define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 1542 #define mmUNIPHYC_LINK_CNTL 0x4809 1543 #define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a 1544 #define mmUNIPHYD_LINK_CNTL 0x480b 1545 #define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c 1546 #define mmUNIPHYE_LINK_CNTL 0x480d 1547 #define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e 1548 #define mmUNIPHYF_LINK_CNTL 0x480f 1549 #define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 1550 #define mmUNIPHYG_LINK_CNTL 0x4811 1551 #define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 1552 #define mmUNIPHY_IMPCAL_LINKA 0x4838 1553 #define mmUNIPHY_IMPCAL_LINKB 0x4839 1554 #define mmUNIPHY_IMPCAL_LINKC 0x483f 1555 #define mmUNIPHY_IMPCAL_LINKD 0x4840 1556 #define mmUNIPHY_IMPCAL_LINKE 0x4843 1557 #define mmUNIPHY_IMPCAL_LINKF 0x4844 1558 #define mmUNIPHY_IMPCAL_PERIOD 0x483a 1559 #define mmAUXP_IMPCAL 0x483b 1560 #define mmAUXN_IMPCAL 0x483c 1561 #define mmDCIO_IMPCAL_CNTL 0x483d 1562 #define mmUNIPHY_IMPCAL_PSW_AB 0x483e 1563 #define mmDCIO_IMPCAL_CNTL_CD 0x4841 1564 #define mmUNIPHY_IMPCAL_PSW_CD 0x4842 1565 #define mmDCIO_IMPCAL_CNTL_EF 0x4845 1566 #define mmUNIPHY_IMPCAL_PSW_EF 0x4846 1567 #define mmDCIO_WRCMD_DELAY 0x4816 1568 #define mmDC_PINSTRAPS 0x4818 1569 #define mmDC_DVODATA_CONFIG 0x481a 1570 #define mmLVTMA_PWRSEQ_CNTL 0x481b 1571 #define mmLVTMA_PWRSEQ_STATE 0x481c 1572 #define mmLVTMA_PWRSEQ_REF_DIV 0x481d 1573 #define mmLVTMA_PWRSEQ_DELAY1 0x481e 1574 #define mmLVTMA_PWRSEQ_DELAY2 0x481f 1575 #define mmBL_PWM_CNTL 0x4820 1576 #define mmBL_PWM_CNTL2 0x4821 1577 #define mmBL_PWM_PERIOD_CNTL 0x4822 1578 #define mmBL_PWM_GRP1_REG_LOCK 0x4823 1579 #define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 1580 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 1581 #define mmDCIO_GSL0_CNTL 0x4826 1582 #define mmDCIO_GSL1_CNTL 0x4827 1583 #define mmDCIO_GSL2_CNTL 0x4828 1584 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 1585 #define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a 1586 #define mmDC_GPU_TIMER_READ 0x482b 1587 #define mmDC_GPU_TIMER_READ_CNTL 0x482c 1588 #define mmDCIO_CLOCK_CNTL 0x482d 1589 #define mmDCIO_DEBUG 0x482f 1590 #define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 1591 #define mmDBG_OUT_CNTL 0x4834 1592 #define mmDCIO_DEBUG_CONFIG 0x4835 1593 #define mmDCIO_SOFT_RESET 0x4836 1594 #define mmDCIO_DPHY_SEL 0x4837 1595 #define mmDCIO_TEST_DEBUG_INDEX 0x4831 1596 #define mmDCIO_TEST_DEBUG_DATA 0x4832 1597 #define ixDCIO_DEBUG1 0x1 1598 #define ixDCIO_DEBUG2 0x2 1599 #define ixDCIO_DEBUG3 0x3 1600 #define ixDCIO_DEBUG4 0x4 1601 #define ixDCIO_DEBUG5 0x5 1602 #define ixDCIO_DEBUG6 0x6 1603 #define ixDCIO_DEBUG7 0x7 1604 #define ixDCIO_DEBUG8 0x8 1605 #define ixDCIO_DEBUG9 0x9 1606 #define ixDCIO_DEBUGA 0xa 1607 #define ixDCIO_DEBUGB 0xb 1608 #define ixDCIO_DEBUGC 0xc 1609 #define ixDCIO_DEBUGD 0xd 1610 #define ixDCIO_DEBUGE 0xe 1611 #define ixDCIO_DEBUGF 0xf 1612 #define ixDCIO_DEBUG10 0x10 1613 #define ixDCIO_DEBUG11 0x11 1614 #define ixDCIO_DEBUG12 0x12 1615 #define ixDCIO_DEBUG13 0x13 1616 #define ixDCIO_DEBUG14 0x14 1617 #define ixDCIO_DEBUG15 0x15 1618 #define ixDCIO_DEBUG16 0x16 1619 #define ixDCIO_DEBUG_ID 0x0 1620 #define mmDC_GPIO_GENERIC_MASK 0x4860 1621 #define mmDC_GPIO_GENERIC_A 0x4861 1622 #define mmDC_GPIO_GENERIC_EN 0x4862 1623 #define mmDC_GPIO_GENERIC_Y 0x4863 1624 #define mmDC_GPIO_DVODATA_MASK 0x4864 1625 #define mmDC_GPIO_DVODATA_A 0x4865 1626 #define mmDC_GPIO_DVODATA_EN 0x4866 1627 #define mmDC_GPIO_DVODATA_Y 0x4867 1628 #define mmDC_GPIO_DDC1_MASK 0x4868 1629 #define mmDC_GPIO_DDC1_A 0x4869 1630 #define mmDC_GPIO_DDC1_EN 0x486a 1631 #define mmDC_GPIO_DDC1_Y 0x486b 1632 #define mmDC_GPIO_DDC2_MASK 0x486c 1633 #define mmDC_GPIO_DDC2_A 0x486d 1634 #define mmDC_GPIO_DDC2_EN 0x486e 1635 #define mmDC_GPIO_DDC2_Y 0x486f 1636 #define mmDC_GPIO_DDC3_MASK 0x4870 1637 #define mmDC_GPIO_DDC3_A 0x4871 1638 #define mmDC_GPIO_DDC3_EN 0x4872 1639 #define mmDC_GPIO_DDC3_Y 0x4873 1640 #define mmDC_GPIO_DDC4_MASK 0x4874 1641 #define mmDC_GPIO_DDC4_A 0x4875 1642 #define mmDC_GPIO_DDC4_EN 0x4876 1643 #define mmDC_GPIO_DDC4_Y 0x4877 1644 #define mmDC_GPIO_DDC5_MASK 0x4878 1645 #define mmDC_GPIO_DDC5_A 0x4879 1646 #define mmDC_GPIO_DDC5_EN 0x487a 1647 #define mmDC_GPIO_DDC5_Y 0x487b 1648 #define mmDC_GPIO_DDC6_MASK 0x487c 1649 #define mmDC_GPIO_DDC6_A 0x487d 1650 #define mmDC_GPIO_DDC6_EN 0x487e 1651 #define mmDC_GPIO_DDC6_Y 0x487f 1652 #define mmDC_GPIO_DDCVGA_MASK 0x4880 1653 #define mmDC_GPIO_DDCVGA_A 0x4881 1654 #define mmDC_GPIO_DDCVGA_EN 0x4882 1655 #define mmDC_GPIO_DDCVGA_Y 0x4883 1656 #define mmDC_GPIO_SYNCA_MASK 0x4884 1657 #define mmDC_GPIO_SYNCA_A 0x4885 1658 #define mmDC_GPIO_SYNCA_EN 0x4886 1659 #define mmDC_GPIO_SYNCA_Y 0x4887 1660 #define mmDC_GPIO_GENLK_MASK 0x4888 1661 #define mmDC_GPIO_GENLK_A 0x4889 1662 #define mmDC_GPIO_GENLK_EN 0x488a 1663 #define mmDC_GPIO_GENLK_Y 0x488b 1664 #define mmDC_GPIO_HPD_MASK 0x488c 1665 #define mmDC_GPIO_HPD_A 0x488d 1666 #define mmDC_GPIO_HPD_EN 0x488e 1667 #define mmDC_GPIO_HPD_Y 0x488f 1668 #define mmDC_GPIO_PWRSEQ_MASK 0x4890 1669 #define mmDC_GPIO_PWRSEQ_A 0x4891 1670 #define mmDC_GPIO_PWRSEQ_EN 0x4892 1671 #define mmDC_GPIO_PWRSEQ_Y 0x4893 1672 #define mmDC_GPIO_PAD_STRENGTH_1 0x4894 1673 #define mmDC_GPIO_PAD_STRENGTH_2 0x4895 1674 #define mmPHY_AUX_CNTL 0x4897 1675 #define mmDC_GPIO_I2CPAD_A 0x4899 1676 #define mmDC_GPIO_I2CPAD_EN 0x489a 1677 #define mmDC_GPIO_I2CPAD_Y 0x489b 1678 #define mmDC_GPIO_I2CPAD_STRENGTH 0x489c 1679 #define mmDVO_STRENGTH_CONTROL 0x489d 1680 #define mmDVO_VREF_CONTROL 0x489e 1681 #define mmDVO_SKEW_ADJUST 0x489f 1682 #define mmDAC_MACRO_CNTL_RESERVED0 0x48b8 1683 #define mmDAC_MACRO_CNTL_RESERVED1 0x48b9 1684 #define mmDAC_MACRO_CNTL_RESERVED2 0x48ba 1685 #define mmDAC_MACRO_CNTL_RESERVED3 0x48bb 1686 #define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 1687 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 1688 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0 1689 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900 1690 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920 1691 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940 1692 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 1693 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980 1694 #define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 1695 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 1696 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1 1697 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901 1698 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921 1699 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941 1700 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 1701 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981 1702 #define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 1703 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 1704 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2 1705 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902 1706 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922 1707 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942 1708 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 1709 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982 1710 #define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 1711 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 1712 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3 1713 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903 1714 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923 1715 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943 1716 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 1717 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983 1718 #define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 1719 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 1720 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4 1721 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904 1722 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924 1723 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944 1724 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 1725 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984 1726 #define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 1727 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 1728 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5 1729 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905 1730 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925 1731 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945 1732 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 1733 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985 1734 #define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 1735 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 1736 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6 1737 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906 1738 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926 1739 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946 1740 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 1741 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986 1742 #define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 1743 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 1744 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7 1745 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907 1746 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927 1747 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947 1748 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 1749 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987 1750 #define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 1751 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 1752 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8 1753 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908 1754 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928 1755 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948 1756 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 1757 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988 1758 #define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 1759 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 1760 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9 1761 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909 1762 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929 1763 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949 1764 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 1765 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989 1766 #define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca 1767 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca 1768 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea 1769 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a 1770 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a 1771 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a 1772 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a 1773 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a 1774 #define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb 1775 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb 1776 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb 1777 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b 1778 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b 1779 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b 1780 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b 1781 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b 1782 #define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc 1783 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc 1784 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec 1785 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c 1786 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c 1787 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c 1788 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c 1789 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c 1790 #define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd 1791 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd 1792 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed 1793 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d 1794 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d 1795 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d 1796 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d 1797 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d 1798 #define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce 1799 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce 1800 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee 1801 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e 1802 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e 1803 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e 1804 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e 1805 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e 1806 #define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf 1807 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf 1808 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef 1809 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f 1810 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f 1811 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f 1812 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f 1813 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f 1814 #define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 1815 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 1816 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0 1817 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910 1818 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930 1819 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950 1820 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 1821 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990 1822 #define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 1823 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 1824 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1 1825 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911 1826 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931 1827 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951 1828 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 1829 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991 1830 #define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 1831 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 1832 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2 1833 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912 1834 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932 1835 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952 1836 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 1837 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992 1838 #define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 1839 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 1840 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3 1841 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913 1842 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933 1843 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953 1844 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 1845 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993 1846 #define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 1847 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 1848 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4 1849 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914 1850 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934 1851 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954 1852 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 1853 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994 1854 #define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 1855 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 1856 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5 1857 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915 1858 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935 1859 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955 1860 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 1861 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995 1862 #define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 1863 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 1864 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6 1865 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916 1866 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936 1867 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956 1868 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 1869 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996 1870 #define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 1871 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 1872 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7 1873 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917 1874 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937 1875 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957 1876 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 1877 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997 1878 #define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 1879 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 1880 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8 1881 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918 1882 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938 1883 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958 1884 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 1885 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998 1886 #define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 1887 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 1888 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9 1889 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919 1890 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939 1891 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959 1892 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 1893 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999 1894 #define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da 1895 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da 1896 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa 1897 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a 1898 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a 1899 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a 1900 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a 1901 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a 1902 #define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db 1903 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db 1904 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb 1905 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b 1906 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b 1907 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b 1908 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b 1909 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b 1910 #define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc 1911 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc 1912 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc 1913 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c 1914 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c 1915 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c 1916 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c 1917 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c 1918 #define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd 1919 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd 1920 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd 1921 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d 1922 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d 1923 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d 1924 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d 1925 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d 1926 #define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de 1927 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de 1928 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe 1929 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e 1930 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e 1931 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e 1932 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e 1933 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e 1934 #define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df 1935 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df 1936 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff 1937 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f 1938 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f 1939 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f 1940 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f 1941 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f 1942 #define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 1943 #define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 1944 #define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 1945 #define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 1946 #define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 1947 #define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 1948 #define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a 1949 #define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b 1950 #define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c 1951 #define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d 1952 #define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e 1953 #define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f 1954 #define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 1955 #define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 1956 #define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 1957 #define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 1958 #define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 1959 #define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 1960 #define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 1961 #define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 1962 #define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 1963 #define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 1964 #define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a 1965 #define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b 1966 #define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c 1967 #define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d 1968 #define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e 1969 #define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f 1970 #define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 1971 #define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 1972 #define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 1973 #define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 1974 #define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 1975 #define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 1976 #define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 1977 #define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 1978 #define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 1979 #define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 1980 #define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa 1981 #define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab 1982 #define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac 1983 #define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad 1984 #define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae 1985 #define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf 1986 #define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 1987 #define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 1988 #define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 1989 #define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 1990 #define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 1991 #define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 1992 #define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 1993 #define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 1994 #define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 1995 #define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 1996 #define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba 1997 #define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb 1998 #define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc 1999 #define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd 2000 #define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe 2001 #define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf 2002 #define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 2003 #define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 2004 #define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 2005 #define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 2006 #define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 2007 #define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 2008 #define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 2009 #define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 2010 #define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 2011 #define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 2012 #define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca 2013 #define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb 2014 #define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc 2015 #define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd 2016 #define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace 2017 #define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf 2018 #define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 2019 #define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 2020 #define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 2021 #define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 2022 #define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 2023 #define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 2024 #define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 2025 #define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 2026 #define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 2027 #define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 2028 #define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada 2029 #define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb 2030 #define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc 2031 #define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add 2032 #define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade 2033 #define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf 2034 #define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 2035 #define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 2036 #define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 2037 #define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 2038 #define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 2039 #define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 2040 #define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 2041 #define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 2042 #define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 2043 #define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 2044 #define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea 2045 #define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb 2046 #define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec 2047 #define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed 2048 #define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee 2049 #define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef 2050 #define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 2051 #define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 2052 #define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 2053 #define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 2054 #define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 2055 #define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 2056 #define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 2057 #define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 2058 #define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 2059 #define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 2060 #define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa 2061 #define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb 2062 #define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc 2063 #define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd 2064 #define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe 2065 #define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff 2066 #define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 2067 #define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 2068 #define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 2069 #define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 2070 #define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 2071 #define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 2072 #define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 2073 #define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 2074 #define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 2075 #define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 2076 #define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a 2077 #define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b 2078 #define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c 2079 #define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d 2080 #define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e 2081 #define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f 2082 #define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 2083 #define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 2084 #define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 2085 #define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 2086 #define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 2087 #define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 2088 #define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 2089 #define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 2090 #define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 2091 #define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 2092 #define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a 2093 #define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b 2094 #define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c 2095 #define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d 2096 #define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e 2097 #define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f 2098 #define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 2099 #define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 2100 #define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 2101 #define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 2102 #define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 2103 #define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 2104 #define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 2105 #define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 2106 #define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 2107 #define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 2108 #define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a 2109 #define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b 2110 #define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c 2111 #define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d 2112 #define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e 2113 #define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f 2114 #define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 2115 #define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 2116 #define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 2117 #define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 2118 #define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 2119 #define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 2120 #define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 2121 #define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 2122 #define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 2123 #define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 2124 #define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a 2125 #define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b 2126 #define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c 2127 #define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d 2128 #define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e 2129 #define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f 2130 #define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 2131 #define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 2132 #define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 2133 #define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 2134 #define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 2135 #define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 2136 #define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 2137 #define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 2138 #define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 2139 #define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 2140 #define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a 2141 #define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b 2142 #define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c 2143 #define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d 2144 #define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e 2145 #define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f 2146 #define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 2147 #define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 2148 #define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 2149 #define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 2150 #define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 2151 #define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 2152 #define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 2153 #define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 2154 #define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 2155 #define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 2156 #define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a 2157 #define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b 2158 #define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c 2159 #define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d 2160 #define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e 2161 #define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f 2162 #define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 2163 #define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 2164 #define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 2165 #define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 2166 #define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 2167 #define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 2168 #define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 2169 #define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 2170 #define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 2171 #define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 2172 #define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a 2173 #define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b 2174 #define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c 2175 #define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d 2176 #define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e 2177 #define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f 2178 #define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 2179 #define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 2180 #define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 2181 #define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 2182 #define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 2183 #define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 2184 #define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 2185 #define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 2186 #define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 2187 #define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 2188 #define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a 2189 #define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b 2190 #define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c 2191 #define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d 2192 #define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e 2193 #define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f 2194 #define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 2195 #define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 2196 #define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 2197 #define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 2198 #define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 2199 #define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 2200 #define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 2201 #define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 2202 #define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 2203 #define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 2204 #define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a 2205 #define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b 2206 #define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c 2207 #define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d 2208 #define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e 2209 #define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f 2210 #define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 2211 #define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 2212 #define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 2213 #define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 2214 #define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 2215 #define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 2216 #define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 2217 #define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 2218 #define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 2219 #define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 2220 #define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a 2221 #define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b 2222 #define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c 2223 #define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d 2224 #define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e 2225 #define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f 2226 #define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 2227 #define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 2228 #define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 2229 #define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 2230 #define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 2231 #define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 2232 #define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 2233 #define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 2234 #define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 2235 #define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 2236 #define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa 2237 #define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab 2238 #define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac 2239 #define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad 2240 #define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae 2241 #define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf 2242 #define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 2243 #define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 2244 #define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 2245 #define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 2246 #define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 2247 #define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 2248 #define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 2249 #define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 2250 #define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 2251 #define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 2252 #define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba 2253 #define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb 2254 #define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc 2255 #define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd 2256 #define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe 2257 #define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf 2258 #define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 2259 #define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 2260 #define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 2261 #define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 2262 #define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 2263 #define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 2264 #define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 2265 #define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 2266 #define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 2267 #define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 2268 #define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca 2269 #define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb 2270 #define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc 2271 #define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd 2272 #define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce 2273 #define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf 2274 #define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 2275 #define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 2276 #define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 2277 #define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 2278 #define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 2279 #define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 2280 #define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 2281 #define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 2282 #define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 2283 #define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 2284 #define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda 2285 #define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb 2286 #define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc 2287 #define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd 2288 #define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde 2289 #define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf 2290 #define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 2291 #define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 2292 #define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 2293 #define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 2294 #define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 2295 #define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 2296 #define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 2297 #define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 2298 #define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 2299 #define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 2300 #define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea 2301 #define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb 2302 #define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec 2303 #define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed 2304 #define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee 2305 #define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef 2306 #define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 2307 #define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 2308 #define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 2309 #define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 2310 #define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 2311 #define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 2312 #define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 2313 #define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 2314 #define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 2315 #define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 2316 #define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa 2317 #define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb 2318 #define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc 2319 #define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd 2320 #define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe 2321 #define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff 2322 #define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 2323 #define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 2324 #define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a 2325 #define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b 2326 #define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c 2327 #define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d 2328 #define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e 2329 #define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f 2330 #define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 2331 #define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 2332 #define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 2333 #define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 2334 #define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 2335 #define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 2336 #define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 2337 #define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 2338 #define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 2339 #define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 2340 #define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa 2341 #define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab 2342 #define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac 2343 #define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad 2344 #define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae 2345 #define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf 2346 #define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 2347 #define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 2348 #define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 2349 #define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 2350 #define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 2351 #define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 2352 #define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 2353 #define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 2354 #define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 2355 #define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 2356 #define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba 2357 #define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb 2358 #define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc 2359 #define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd 2360 #define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe 2361 #define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf 2362 #define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 2363 #define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 2364 #define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 2365 #define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 2366 #define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 2367 #define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 2368 #define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 2369 #define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 2370 #define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 2371 #define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 2372 #define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca 2373 #define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb 2374 #define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc 2375 #define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd 2376 #define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce 2377 #define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf 2378 #define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 2379 #define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 2380 #define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 2381 #define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 2382 #define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 2383 #define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 2384 #define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 2385 #define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 2386 #define mmGRPH_ENABLE 0x1a00 2387 #define mmDCP0_GRPH_ENABLE 0x1a00 2388 #define mmDCP1_GRPH_ENABLE 0x1c00 2389 #define mmDCP2_GRPH_ENABLE 0x1e00 2390 #define mmDCP3_GRPH_ENABLE 0x4000 2391 #define mmDCP4_GRPH_ENABLE 0x4200 2392 #define mmDCP5_GRPH_ENABLE 0x4400 2393 #define mmGRPH_CONTROL 0x1a01 2394 #define mmDCP0_GRPH_CONTROL 0x1a01 2395 #define mmDCP1_GRPH_CONTROL 0x1c01 2396 #define mmDCP2_GRPH_CONTROL 0x1e01 2397 #define mmDCP3_GRPH_CONTROL 0x4001 2398 #define mmDCP4_GRPH_CONTROL 0x4201 2399 #define mmDCP5_GRPH_CONTROL 0x4401 2400 #define mmGRPH_LUT_10BIT_BYPASS 0x1a02 2401 #define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 2402 #define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 2403 #define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 2404 #define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 2405 #define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 2406 #define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 2407 #define mmGRPH_SWAP_CNTL 0x1a03 2408 #define mmDCP0_GRPH_SWAP_CNTL 0x1a03 2409 #define mmDCP1_GRPH_SWAP_CNTL 0x1c03 2410 #define mmDCP2_GRPH_SWAP_CNTL 0x1e03 2411 #define mmDCP3_GRPH_SWAP_CNTL 0x4003 2412 #define mmDCP4_GRPH_SWAP_CNTL 0x4203 2413 #define mmDCP5_GRPH_SWAP_CNTL 0x4403 2414 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 2415 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 2416 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 2417 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 2418 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 2419 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 2420 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 2421 #define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 2422 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 2423 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 2424 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 2425 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 2426 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 2427 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 2428 #define mmGRPH_PITCH 0x1a06 2429 #define mmDCP0_GRPH_PITCH 0x1a06 2430 #define mmDCP1_GRPH_PITCH 0x1c06 2431 #define mmDCP2_GRPH_PITCH 0x1e06 2432 #define mmDCP3_GRPH_PITCH 0x4006 2433 #define mmDCP4_GRPH_PITCH 0x4206 2434 #define mmDCP5_GRPH_PITCH 0x4406 2435 #define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2436 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 2437 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 2438 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 2439 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 2440 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 2441 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 2442 #define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2443 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 2444 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 2445 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 2446 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 2447 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 2448 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 2449 #define mmGRPH_SURFACE_OFFSET_X 0x1a09 2450 #define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 2451 #define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 2452 #define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 2453 #define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 2454 #define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 2455 #define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 2456 #define mmGRPH_SURFACE_OFFSET_Y 0x1a0a 2457 #define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a 2458 #define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a 2459 #define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a 2460 #define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a 2461 #define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a 2462 #define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a 2463 #define mmGRPH_X_START 0x1a0b 2464 #define mmDCP0_GRPH_X_START 0x1a0b 2465 #define mmDCP1_GRPH_X_START 0x1c0b 2466 #define mmDCP2_GRPH_X_START 0x1e0b 2467 #define mmDCP3_GRPH_X_START 0x400b 2468 #define mmDCP4_GRPH_X_START 0x420b 2469 #define mmDCP5_GRPH_X_START 0x440b 2470 #define mmGRPH_Y_START 0x1a0c 2471 #define mmDCP0_GRPH_Y_START 0x1a0c 2472 #define mmDCP1_GRPH_Y_START 0x1c0c 2473 #define mmDCP2_GRPH_Y_START 0x1e0c 2474 #define mmDCP3_GRPH_Y_START 0x400c 2475 #define mmDCP4_GRPH_Y_START 0x420c 2476 #define mmDCP5_GRPH_Y_START 0x440c 2477 #define mmGRPH_X_END 0x1a0d 2478 #define mmDCP0_GRPH_X_END 0x1a0d 2479 #define mmDCP1_GRPH_X_END 0x1c0d 2480 #define mmDCP2_GRPH_X_END 0x1e0d 2481 #define mmDCP3_GRPH_X_END 0x400d 2482 #define mmDCP4_GRPH_X_END 0x420d 2483 #define mmDCP5_GRPH_X_END 0x440d 2484 #define mmGRPH_Y_END 0x1a0e 2485 #define mmDCP0_GRPH_Y_END 0x1a0e 2486 #define mmDCP1_GRPH_Y_END 0x1c0e 2487 #define mmDCP2_GRPH_Y_END 0x1e0e 2488 #define mmDCP3_GRPH_Y_END 0x400e 2489 #define mmDCP4_GRPH_Y_END 0x420e 2490 #define mmDCP5_GRPH_Y_END 0x440e 2491 #define mmINPUT_GAMMA_CONTROL 0x1a10 2492 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 2493 #define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 2494 #define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 2495 #define mmDCP3_INPUT_GAMMA_CONTROL 0x4010 2496 #define mmDCP4_INPUT_GAMMA_CONTROL 0x4210 2497 #define mmDCP5_INPUT_GAMMA_CONTROL 0x4410 2498 #define mmGRPH_UPDATE 0x1a11 2499 #define mmDCP0_GRPH_UPDATE 0x1a11 2500 #define mmDCP1_GRPH_UPDATE 0x1c11 2501 #define mmDCP2_GRPH_UPDATE 0x1e11 2502 #define mmDCP3_GRPH_UPDATE 0x4011 2503 #define mmDCP4_GRPH_UPDATE 0x4211 2504 #define mmDCP5_GRPH_UPDATE 0x4411 2505 #define mmGRPH_FLIP_CONTROL 0x1a12 2506 #define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 2507 #define mmDCP1_GRPH_FLIP_CONTROL 0x1c12 2508 #define mmDCP2_GRPH_FLIP_CONTROL 0x1e12 2509 #define mmDCP3_GRPH_FLIP_CONTROL 0x4012 2510 #define mmDCP4_GRPH_FLIP_CONTROL 0x4212 2511 #define mmDCP5_GRPH_FLIP_CONTROL 0x4412 2512 #define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 2513 #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 2514 #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 2515 #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 2516 #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 2517 #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 2518 #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 2519 #define mmGRPH_DFQ_CONTROL 0x1a14 2520 #define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 2521 #define mmDCP1_GRPH_DFQ_CONTROL 0x1c14 2522 #define mmDCP2_GRPH_DFQ_CONTROL 0x1e14 2523 #define mmDCP3_GRPH_DFQ_CONTROL 0x4014 2524 #define mmDCP4_GRPH_DFQ_CONTROL 0x4214 2525 #define mmDCP5_GRPH_DFQ_CONTROL 0x4414 2526 #define mmGRPH_DFQ_STATUS 0x1a15 2527 #define mmDCP0_GRPH_DFQ_STATUS 0x1a15 2528 #define mmDCP1_GRPH_DFQ_STATUS 0x1c15 2529 #define mmDCP2_GRPH_DFQ_STATUS 0x1e15 2530 #define mmDCP3_GRPH_DFQ_STATUS 0x4015 2531 #define mmDCP4_GRPH_DFQ_STATUS 0x4215 2532 #define mmDCP5_GRPH_DFQ_STATUS 0x4415 2533 #define mmGRPH_INTERRUPT_STATUS 0x1a16 2534 #define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 2535 #define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 2536 #define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 2537 #define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 2538 #define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 2539 #define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 2540 #define mmGRPH_INTERRUPT_CONTROL 0x1a17 2541 #define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 2542 #define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 2543 #define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 2544 #define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 2545 #define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 2546 #define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 2547 #define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 2548 #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 2549 #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 2550 #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 2551 #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 2552 #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 2553 #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 2554 #define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 2555 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 2556 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 2557 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 2558 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 2559 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 2560 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 2561 #define mmGRPH_COMPRESS_PITCH 0x1a1a 2562 #define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a 2563 #define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a 2564 #define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a 2565 #define mmDCP3_GRPH_COMPRESS_PITCH 0x401a 2566 #define mmDCP4_GRPH_COMPRESS_PITCH 0x421a 2567 #define mmDCP5_GRPH_COMPRESS_PITCH 0x441a 2568 #define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b 2569 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b 2570 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b 2571 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b 2572 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b 2573 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b 2574 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b 2575 #define mmOVL_ENABLE 0x1a1c 2576 #define mmDCP0_OVL_ENABLE 0x1a1c 2577 #define mmDCP1_OVL_ENABLE 0x1c1c 2578 #define mmDCP2_OVL_ENABLE 0x1e1c 2579 #define mmDCP3_OVL_ENABLE 0x401c 2580 #define mmDCP4_OVL_ENABLE 0x421c 2581 #define mmDCP5_OVL_ENABLE 0x441c 2582 #define mmOVL_CONTROL1 0x1a1d 2583 #define mmDCP0_OVL_CONTROL1 0x1a1d 2584 #define mmDCP1_OVL_CONTROL1 0x1c1d 2585 #define mmDCP2_OVL_CONTROL1 0x1e1d 2586 #define mmDCP3_OVL_CONTROL1 0x401d 2587 #define mmDCP4_OVL_CONTROL1 0x421d 2588 #define mmDCP5_OVL_CONTROL1 0x441d 2589 #define mmOVL_CONTROL2 0x1a1e 2590 #define mmDCP0_OVL_CONTROL2 0x1a1e 2591 #define mmDCP1_OVL_CONTROL2 0x1c1e 2592 #define mmDCP2_OVL_CONTROL2 0x1e1e 2593 #define mmDCP3_OVL_CONTROL2 0x401e 2594 #define mmDCP4_OVL_CONTROL2 0x421e 2595 #define mmDCP5_OVL_CONTROL2 0x441e 2596 #define mmOVL_SWAP_CNTL 0x1a1f 2597 #define mmDCP0_OVL_SWAP_CNTL 0x1a1f 2598 #define mmDCP1_OVL_SWAP_CNTL 0x1c1f 2599 #define mmDCP2_OVL_SWAP_CNTL 0x1e1f 2600 #define mmDCP3_OVL_SWAP_CNTL 0x401f 2601 #define mmDCP4_OVL_SWAP_CNTL 0x421f 2602 #define mmDCP5_OVL_SWAP_CNTL 0x441f 2603 #define mmOVL_SURFACE_ADDRESS 0x1a20 2604 #define mmDCP0_OVL_SURFACE_ADDRESS 0x1a20 2605 #define mmDCP1_OVL_SURFACE_ADDRESS 0x1c20 2606 #define mmDCP2_OVL_SURFACE_ADDRESS 0x1e20 2607 #define mmDCP3_OVL_SURFACE_ADDRESS 0x4020 2608 #define mmDCP4_OVL_SURFACE_ADDRESS 0x4220 2609 #define mmDCP5_OVL_SURFACE_ADDRESS 0x4420 2610 #define mmOVL_PITCH 0x1a21 2611 #define mmDCP0_OVL_PITCH 0x1a21 2612 #define mmDCP1_OVL_PITCH 0x1c21 2613 #define mmDCP2_OVL_PITCH 0x1e21 2614 #define mmDCP3_OVL_PITCH 0x4021 2615 #define mmDCP4_OVL_PITCH 0x4221 2616 #define mmDCP5_OVL_PITCH 0x4421 2617 #define mmOVL_SURFACE_ADDRESS_HIGH 0x1a22 2618 #define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1a22 2619 #define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1c22 2620 #define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x1e22 2621 #define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4022 2622 #define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4222 2623 #define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4422 2624 #define mmOVL_SURFACE_OFFSET_X 0x1a23 2625 #define mmDCP0_OVL_SURFACE_OFFSET_X 0x1a23 2626 #define mmDCP1_OVL_SURFACE_OFFSET_X 0x1c23 2627 #define mmDCP2_OVL_SURFACE_OFFSET_X 0x1e23 2628 #define mmDCP3_OVL_SURFACE_OFFSET_X 0x4023 2629 #define mmDCP4_OVL_SURFACE_OFFSET_X 0x4223 2630 #define mmDCP5_OVL_SURFACE_OFFSET_X 0x4423 2631 #define mmOVL_SURFACE_OFFSET_Y 0x1a24 2632 #define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1a24 2633 #define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1c24 2634 #define mmDCP2_OVL_SURFACE_OFFSET_Y 0x1e24 2635 #define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4024 2636 #define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4224 2637 #define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4424 2638 #define mmOVL_START 0x1a25 2639 #define mmDCP0_OVL_START 0x1a25 2640 #define mmDCP1_OVL_START 0x1c25 2641 #define mmDCP2_OVL_START 0x1e25 2642 #define mmDCP3_OVL_START 0x4025 2643 #define mmDCP4_OVL_START 0x4225 2644 #define mmDCP5_OVL_START 0x4425 2645 #define mmOVL_END 0x1a26 2646 #define mmDCP0_OVL_END 0x1a26 2647 #define mmDCP1_OVL_END 0x1c26 2648 #define mmDCP2_OVL_END 0x1e26 2649 #define mmDCP3_OVL_END 0x4026 2650 #define mmDCP4_OVL_END 0x4226 2651 #define mmDCP5_OVL_END 0x4426 2652 #define mmOVL_UPDATE 0x1a27 2653 #define mmDCP0_OVL_UPDATE 0x1a27 2654 #define mmDCP1_OVL_UPDATE 0x1c27 2655 #define mmDCP2_OVL_UPDATE 0x1e27 2656 #define mmDCP3_OVL_UPDATE 0x4027 2657 #define mmDCP4_OVL_UPDATE 0x4227 2658 #define mmDCP5_OVL_UPDATE 0x4427 2659 #define mmOVL_SURFACE_ADDRESS_INUSE 0x1a28 2660 #define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1a28 2661 #define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1c28 2662 #define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x1e28 2663 #define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4028 2664 #define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4228 2665 #define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4428 2666 #define mmOVL_DFQ_CONTROL 0x1a29 2667 #define mmDCP0_OVL_DFQ_CONTROL 0x1a29 2668 #define mmDCP1_OVL_DFQ_CONTROL 0x1c29 2669 #define mmDCP2_OVL_DFQ_CONTROL 0x1e29 2670 #define mmDCP3_OVL_DFQ_CONTROL 0x4029 2671 #define mmDCP4_OVL_DFQ_CONTROL 0x4229 2672 #define mmDCP5_OVL_DFQ_CONTROL 0x4429 2673 #define mmOVL_DFQ_STATUS 0x1a2a 2674 #define mmDCP0_OVL_DFQ_STATUS 0x1a2a 2675 #define mmDCP1_OVL_DFQ_STATUS 0x1c2a 2676 #define mmDCP2_OVL_DFQ_STATUS 0x1e2a 2677 #define mmDCP3_OVL_DFQ_STATUS 0x402a 2678 #define mmDCP4_OVL_DFQ_STATUS 0x422a 2679 #define mmDCP5_OVL_DFQ_STATUS 0x442a 2680 #define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b 2681 #define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1a2b 2682 #define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1c2b 2683 #define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1e2b 2684 #define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402b 2685 #define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x422b 2686 #define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x442b 2687 #define mmOVLSCL_EDGE_PIXEL_CNTL 0x1a2c 2688 #define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1a2c 2689 #define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1c2c 2690 #define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x1e2c 2691 #define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x402c 2692 #define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x422c 2693 #define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x442c 2694 #define mmPRESCALE_GRPH_CONTROL 0x1a2d 2695 #define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d 2696 #define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d 2697 #define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d 2698 #define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d 2699 #define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d 2700 #define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d 2701 #define mmPRESCALE_VALUES_GRPH_R 0x1a2e 2702 #define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e 2703 #define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e 2704 #define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e 2705 #define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e 2706 #define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e 2707 #define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e 2708 #define mmPRESCALE_VALUES_GRPH_G 0x1a2f 2709 #define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f 2710 #define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f 2711 #define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f 2712 #define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f 2713 #define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f 2714 #define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f 2715 #define mmPRESCALE_VALUES_GRPH_B 0x1a30 2716 #define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 2717 #define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 2718 #define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 2719 #define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 2720 #define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 2721 #define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 2722 #define mmPRESCALE_OVL_CONTROL 0x1a31 2723 #define mmDCP0_PRESCALE_OVL_CONTROL 0x1a31 2724 #define mmDCP1_PRESCALE_OVL_CONTROL 0x1c31 2725 #define mmDCP2_PRESCALE_OVL_CONTROL 0x1e31 2726 #define mmDCP3_PRESCALE_OVL_CONTROL 0x4031 2727 #define mmDCP4_PRESCALE_OVL_CONTROL 0x4231 2728 #define mmDCP5_PRESCALE_OVL_CONTROL 0x4431 2729 #define mmPRESCALE_VALUES_OVL_CB 0x1a32 2730 #define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1a32 2731 #define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1c32 2732 #define mmDCP2_PRESCALE_VALUES_OVL_CB 0x1e32 2733 #define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4032 2734 #define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4232 2735 #define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4432 2736 #define mmPRESCALE_VALUES_OVL_Y 0x1a33 2737 #define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1a33 2738 #define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1c33 2739 #define mmDCP2_PRESCALE_VALUES_OVL_Y 0x1e33 2740 #define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4033 2741 #define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4233 2742 #define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4433 2743 #define mmPRESCALE_VALUES_OVL_CR 0x1a34 2744 #define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1a34 2745 #define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1c34 2746 #define mmDCP2_PRESCALE_VALUES_OVL_CR 0x1e34 2747 #define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4034 2748 #define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4234 2749 #define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4434 2750 #define mmINPUT_CSC_CONTROL 0x1a35 2751 #define mmDCP0_INPUT_CSC_CONTROL 0x1a35 2752 #define mmDCP1_INPUT_CSC_CONTROL 0x1c35 2753 #define mmDCP2_INPUT_CSC_CONTROL 0x1e35 2754 #define mmDCP3_INPUT_CSC_CONTROL 0x4035 2755 #define mmDCP4_INPUT_CSC_CONTROL 0x4235 2756 #define mmDCP5_INPUT_CSC_CONTROL 0x4435 2757 #define mmINPUT_CSC_C11_C12 0x1a36 2758 #define mmDCP0_INPUT_CSC_C11_C12 0x1a36 2759 #define mmDCP1_INPUT_CSC_C11_C12 0x1c36 2760 #define mmDCP2_INPUT_CSC_C11_C12 0x1e36 2761 #define mmDCP3_INPUT_CSC_C11_C12 0x4036 2762 #define mmDCP4_INPUT_CSC_C11_C12 0x4236 2763 #define mmDCP5_INPUT_CSC_C11_C12 0x4436 2764 #define mmINPUT_CSC_C13_C14 0x1a37 2765 #define mmDCP0_INPUT_CSC_C13_C14 0x1a37 2766 #define mmDCP1_INPUT_CSC_C13_C14 0x1c37 2767 #define mmDCP2_INPUT_CSC_C13_C14 0x1e37 2768 #define mmDCP3_INPUT_CSC_C13_C14 0x4037 2769 #define mmDCP4_INPUT_CSC_C13_C14 0x4237 2770 #define mmDCP5_INPUT_CSC_C13_C14 0x4437 2771 #define mmINPUT_CSC_C21_C22 0x1a38 2772 #define mmDCP0_INPUT_CSC_C21_C22 0x1a38 2773 #define mmDCP1_INPUT_CSC_C21_C22 0x1c38 2774 #define mmDCP2_INPUT_CSC_C21_C22 0x1e38 2775 #define mmDCP3_INPUT_CSC_C21_C22 0x4038 2776 #define mmDCP4_INPUT_CSC_C21_C22 0x4238 2777 #define mmDCP5_INPUT_CSC_C21_C22 0x4438 2778 #define mmINPUT_CSC_C23_C24 0x1a39 2779 #define mmDCP0_INPUT_CSC_C23_C24 0x1a39 2780 #define mmDCP1_INPUT_CSC_C23_C24 0x1c39 2781 #define mmDCP2_INPUT_CSC_C23_C24 0x1e39 2782 #define mmDCP3_INPUT_CSC_C23_C24 0x4039 2783 #define mmDCP4_INPUT_CSC_C23_C24 0x4239 2784 #define mmDCP5_INPUT_CSC_C23_C24 0x4439 2785 #define mmINPUT_CSC_C31_C32 0x1a3a 2786 #define mmDCP0_INPUT_CSC_C31_C32 0x1a3a 2787 #define mmDCP1_INPUT_CSC_C31_C32 0x1c3a 2788 #define mmDCP2_INPUT_CSC_C31_C32 0x1e3a 2789 #define mmDCP3_INPUT_CSC_C31_C32 0x403a 2790 #define mmDCP4_INPUT_CSC_C31_C32 0x423a 2791 #define mmDCP5_INPUT_CSC_C31_C32 0x443a 2792 #define mmINPUT_CSC_C33_C34 0x1a3b 2793 #define mmDCP0_INPUT_CSC_C33_C34 0x1a3b 2794 #define mmDCP1_INPUT_CSC_C33_C34 0x1c3b 2795 #define mmDCP2_INPUT_CSC_C33_C34 0x1e3b 2796 #define mmDCP3_INPUT_CSC_C33_C34 0x403b 2797 #define mmDCP4_INPUT_CSC_C33_C34 0x423b 2798 #define mmDCP5_INPUT_CSC_C33_C34 0x443b 2799 #define mmOUTPUT_CSC_CONTROL 0x1a3c 2800 #define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c 2801 #define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c 2802 #define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c 2803 #define mmDCP3_OUTPUT_CSC_CONTROL 0x403c 2804 #define mmDCP4_OUTPUT_CSC_CONTROL 0x423c 2805 #define mmDCP5_OUTPUT_CSC_CONTROL 0x443c 2806 #define mmOUTPUT_CSC_C11_C12 0x1a3d 2807 #define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d 2808 #define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d 2809 #define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d 2810 #define mmDCP3_OUTPUT_CSC_C11_C12 0x403d 2811 #define mmDCP4_OUTPUT_CSC_C11_C12 0x423d 2812 #define mmDCP5_OUTPUT_CSC_C11_C12 0x443d 2813 #define mmOUTPUT_CSC_C13_C14 0x1a3e 2814 #define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e 2815 #define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e 2816 #define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e 2817 #define mmDCP3_OUTPUT_CSC_C13_C14 0x403e 2818 #define mmDCP4_OUTPUT_CSC_C13_C14 0x423e 2819 #define mmDCP5_OUTPUT_CSC_C13_C14 0x443e 2820 #define mmOUTPUT_CSC_C21_C22 0x1a3f 2821 #define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f 2822 #define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f 2823 #define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f 2824 #define mmDCP3_OUTPUT_CSC_C21_C22 0x403f 2825 #define mmDCP4_OUTPUT_CSC_C21_C22 0x423f 2826 #define mmDCP5_OUTPUT_CSC_C21_C22 0x443f 2827 #define mmOUTPUT_CSC_C23_C24 0x1a40 2828 #define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 2829 #define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 2830 #define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 2831 #define mmDCP3_OUTPUT_CSC_C23_C24 0x4040 2832 #define mmDCP4_OUTPUT_CSC_C23_C24 0x4240 2833 #define mmDCP5_OUTPUT_CSC_C23_C24 0x4440 2834 #define mmOUTPUT_CSC_C31_C32 0x1a41 2835 #define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 2836 #define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 2837 #define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 2838 #define mmDCP3_OUTPUT_CSC_C31_C32 0x4041 2839 #define mmDCP4_OUTPUT_CSC_C31_C32 0x4241 2840 #define mmDCP5_OUTPUT_CSC_C31_C32 0x4441 2841 #define mmOUTPUT_CSC_C33_C34 0x1a42 2842 #define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 2843 #define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 2844 #define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 2845 #define mmDCP3_OUTPUT_CSC_C33_C34 0x4042 2846 #define mmDCP4_OUTPUT_CSC_C33_C34 0x4242 2847 #define mmDCP5_OUTPUT_CSC_C33_C34 0x4442 2848 #define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 2849 #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 2850 #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 2851 #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 2852 #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 2853 #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 2854 #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 2855 #define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 2856 #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 2857 #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 2858 #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 2859 #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 2860 #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 2861 #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 2862 #define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 2863 #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 2864 #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 2865 #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 2866 #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 2867 #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 2868 #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 2869 #define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 2870 #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 2871 #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 2872 #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 2873 #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 2874 #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 2875 #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 2876 #define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 2877 #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 2878 #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 2879 #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 2880 #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 2881 #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 2882 #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 2883 #define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 2884 #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 2885 #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 2886 #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 2887 #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 2888 #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 2889 #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 2890 #define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 2891 #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 2892 #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 2893 #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 2894 #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 2895 #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 2896 #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 2897 #define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a 2898 #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a 2899 #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a 2900 #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a 2901 #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a 2902 #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a 2903 #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a 2904 #define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b 2905 #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b 2906 #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b 2907 #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b 2908 #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b 2909 #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b 2910 #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b 2911 #define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c 2912 #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c 2913 #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c 2914 #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c 2915 #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c 2916 #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c 2917 #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c 2918 #define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d 2919 #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d 2920 #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d 2921 #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d 2922 #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d 2923 #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d 2924 #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d 2925 #define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e 2926 #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e 2927 #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e 2928 #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e 2929 #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e 2930 #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e 2931 #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e 2932 #define mmDENORM_CONTROL 0x1a50 2933 #define mmDCP0_DENORM_CONTROL 0x1a50 2934 #define mmDCP1_DENORM_CONTROL 0x1c50 2935 #define mmDCP2_DENORM_CONTROL 0x1e50 2936 #define mmDCP3_DENORM_CONTROL 0x4050 2937 #define mmDCP4_DENORM_CONTROL 0x4250 2938 #define mmDCP5_DENORM_CONTROL 0x4450 2939 #define mmOUT_ROUND_CONTROL 0x1a51 2940 #define mmDCP0_OUT_ROUND_CONTROL 0x1a51 2941 #define mmDCP1_OUT_ROUND_CONTROL 0x1c51 2942 #define mmDCP2_OUT_ROUND_CONTROL 0x1e51 2943 #define mmDCP3_OUT_ROUND_CONTROL 0x4051 2944 #define mmDCP4_OUT_ROUND_CONTROL 0x4251 2945 #define mmDCP5_OUT_ROUND_CONTROL 0x4451 2946 #define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 2947 #define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 2948 #define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 2949 #define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 2950 #define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 2951 #define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 2952 #define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 2953 #define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c 2954 #define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c 2955 #define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c 2956 #define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c 2957 #define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c 2958 #define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c 2959 #define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c 2960 #define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d 2961 #define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d 2962 #define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d 2963 #define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d 2964 #define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d 2965 #define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d 2966 #define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d 2967 #define mmKEY_CONTROL 0x1a53 2968 #define mmDCP0_KEY_CONTROL 0x1a53 2969 #define mmDCP1_KEY_CONTROL 0x1c53 2970 #define mmDCP2_KEY_CONTROL 0x1e53 2971 #define mmDCP3_KEY_CONTROL 0x4053 2972 #define mmDCP4_KEY_CONTROL 0x4253 2973 #define mmDCP5_KEY_CONTROL 0x4453 2974 #define mmKEY_RANGE_ALPHA 0x1a54 2975 #define mmDCP0_KEY_RANGE_ALPHA 0x1a54 2976 #define mmDCP1_KEY_RANGE_ALPHA 0x1c54 2977 #define mmDCP2_KEY_RANGE_ALPHA 0x1e54 2978 #define mmDCP3_KEY_RANGE_ALPHA 0x4054 2979 #define mmDCP4_KEY_RANGE_ALPHA 0x4254 2980 #define mmDCP5_KEY_RANGE_ALPHA 0x4454 2981 #define mmKEY_RANGE_RED 0x1a55 2982 #define mmDCP0_KEY_RANGE_RED 0x1a55 2983 #define mmDCP1_KEY_RANGE_RED 0x1c55 2984 #define mmDCP2_KEY_RANGE_RED 0x1e55 2985 #define mmDCP3_KEY_RANGE_RED 0x4055 2986 #define mmDCP4_KEY_RANGE_RED 0x4255 2987 #define mmDCP5_KEY_RANGE_RED 0x4455 2988 #define mmKEY_RANGE_GREEN 0x1a56 2989 #define mmDCP0_KEY_RANGE_GREEN 0x1a56 2990 #define mmDCP1_KEY_RANGE_GREEN 0x1c56 2991 #define mmDCP2_KEY_RANGE_GREEN 0x1e56 2992 #define mmDCP3_KEY_RANGE_GREEN 0x4056 2993 #define mmDCP4_KEY_RANGE_GREEN 0x4256 2994 #define mmDCP5_KEY_RANGE_GREEN 0x4456 2995 #define mmKEY_RANGE_BLUE 0x1a57 2996 #define mmDCP0_KEY_RANGE_BLUE 0x1a57 2997 #define mmDCP1_KEY_RANGE_BLUE 0x1c57 2998 #define mmDCP2_KEY_RANGE_BLUE 0x1e57 2999 #define mmDCP3_KEY_RANGE_BLUE 0x4057 3000 #define mmDCP4_KEY_RANGE_BLUE 0x4257 3001 #define mmDCP5_KEY_RANGE_BLUE 0x4457 3002 #define mmDEGAMMA_CONTROL 0x1a58 3003 #define mmDCP0_DEGAMMA_CONTROL 0x1a58 3004 #define mmDCP1_DEGAMMA_CONTROL 0x1c58 3005 #define mmDCP2_DEGAMMA_CONTROL 0x1e58 3006 #define mmDCP3_DEGAMMA_CONTROL 0x4058 3007 #define mmDCP4_DEGAMMA_CONTROL 0x4258 3008 #define mmDCP5_DEGAMMA_CONTROL 0x4458 3009 #define mmGAMUT_REMAP_CONTROL 0x1a59 3010 #define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 3011 #define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 3012 #define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 3013 #define mmDCP3_GAMUT_REMAP_CONTROL 0x4059 3014 #define mmDCP4_GAMUT_REMAP_CONTROL 0x4259 3015 #define mmDCP5_GAMUT_REMAP_CONTROL 0x4459 3016 #define mmGAMUT_REMAP_C11_C12 0x1a5a 3017 #define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a 3018 #define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a 3019 #define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a 3020 #define mmDCP3_GAMUT_REMAP_C11_C12 0x405a 3021 #define mmDCP4_GAMUT_REMAP_C11_C12 0x425a 3022 #define mmDCP5_GAMUT_REMAP_C11_C12 0x445a 3023 #define mmGAMUT_REMAP_C13_C14 0x1a5b 3024 #define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b 3025 #define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b 3026 #define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b 3027 #define mmDCP3_GAMUT_REMAP_C13_C14 0x405b 3028 #define mmDCP4_GAMUT_REMAP_C13_C14 0x425b 3029 #define mmDCP5_GAMUT_REMAP_C13_C14 0x445b 3030 #define mmGAMUT_REMAP_C21_C22 0x1a5c 3031 #define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c 3032 #define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c 3033 #define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c 3034 #define mmDCP3_GAMUT_REMAP_C21_C22 0x405c 3035 #define mmDCP4_GAMUT_REMAP_C21_C22 0x425c 3036 #define mmDCP5_GAMUT_REMAP_C21_C22 0x445c 3037 #define mmGAMUT_REMAP_C23_C24 0x1a5d 3038 #define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d 3039 #define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d 3040 #define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d 3041 #define mmDCP3_GAMUT_REMAP_C23_C24 0x405d 3042 #define mmDCP4_GAMUT_REMAP_C23_C24 0x425d 3043 #define mmDCP5_GAMUT_REMAP_C23_C24 0x445d 3044 #define mmGAMUT_REMAP_C31_C32 0x1a5e 3045 #define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e 3046 #define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e 3047 #define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e 3048 #define mmDCP3_GAMUT_REMAP_C31_C32 0x405e 3049 #define mmDCP4_GAMUT_REMAP_C31_C32 0x425e 3050 #define mmDCP5_GAMUT_REMAP_C31_C32 0x445e 3051 #define mmGAMUT_REMAP_C33_C34 0x1a5f 3052 #define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f 3053 #define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f 3054 #define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f 3055 #define mmDCP3_GAMUT_REMAP_C33_C34 0x405f 3056 #define mmDCP4_GAMUT_REMAP_C33_C34 0x425f 3057 #define mmDCP5_GAMUT_REMAP_C33_C34 0x445f 3058 #define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 3059 #define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 3060 #define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 3061 #define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 3062 #define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 3063 #define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 3064 #define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 3065 #define mmDCP_RANDOM_SEEDS 0x1a61 3066 #define mmDCP0_DCP_RANDOM_SEEDS 0x1a61 3067 #define mmDCP1_DCP_RANDOM_SEEDS 0x1c61 3068 #define mmDCP2_DCP_RANDOM_SEEDS 0x1e61 3069 #define mmDCP3_DCP_RANDOM_SEEDS 0x4061 3070 #define mmDCP4_DCP_RANDOM_SEEDS 0x4261 3071 #define mmDCP5_DCP_RANDOM_SEEDS 0x4461 3072 #define mmDCP_FP_CONVERTED_FIELD 0x1a65 3073 #define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 3074 #define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 3075 #define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 3076 #define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 3077 #define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 3078 #define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 3079 #define mmCUR_CONTROL 0x1a66 3080 #define mmDCP0_CUR_CONTROL 0x1a66 3081 #define mmDCP1_CUR_CONTROL 0x1c66 3082 #define mmDCP2_CUR_CONTROL 0x1e66 3083 #define mmDCP3_CUR_CONTROL 0x4066 3084 #define mmDCP4_CUR_CONTROL 0x4266 3085 #define mmDCP5_CUR_CONTROL 0x4466 3086 #define mmCUR_SURFACE_ADDRESS 0x1a67 3087 #define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 3088 #define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 3089 #define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 3090 #define mmDCP3_CUR_SURFACE_ADDRESS 0x4067 3091 #define mmDCP4_CUR_SURFACE_ADDRESS 0x4267 3092 #define mmDCP5_CUR_SURFACE_ADDRESS 0x4467 3093 #define mmCUR_SIZE 0x1a68 3094 #define mmDCP0_CUR_SIZE 0x1a68 3095 #define mmDCP1_CUR_SIZE 0x1c68 3096 #define mmDCP2_CUR_SIZE 0x1e68 3097 #define mmDCP3_CUR_SIZE 0x4068 3098 #define mmDCP4_CUR_SIZE 0x4268 3099 #define mmDCP5_CUR_SIZE 0x4468 3100 #define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 3101 #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 3102 #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 3103 #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 3104 #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 3105 #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 3106 #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 3107 #define mmCUR_POSITION 0x1a6a 3108 #define mmDCP0_CUR_POSITION 0x1a6a 3109 #define mmDCP1_CUR_POSITION 0x1c6a 3110 #define mmDCP2_CUR_POSITION 0x1e6a 3111 #define mmDCP3_CUR_POSITION 0x406a 3112 #define mmDCP4_CUR_POSITION 0x426a 3113 #define mmDCP5_CUR_POSITION 0x446a 3114 #define mmCUR_HOT_SPOT 0x1a6b 3115 #define mmDCP0_CUR_HOT_SPOT 0x1a6b 3116 #define mmDCP1_CUR_HOT_SPOT 0x1c6b 3117 #define mmDCP2_CUR_HOT_SPOT 0x1e6b 3118 #define mmDCP3_CUR_HOT_SPOT 0x406b 3119 #define mmDCP4_CUR_HOT_SPOT 0x426b 3120 #define mmDCP5_CUR_HOT_SPOT 0x446b 3121 #define mmCUR_COLOR1 0x1a6c 3122 #define mmDCP0_CUR_COLOR1 0x1a6c 3123 #define mmDCP1_CUR_COLOR1 0x1c6c 3124 #define mmDCP2_CUR_COLOR1 0x1e6c 3125 #define mmDCP3_CUR_COLOR1 0x406c 3126 #define mmDCP4_CUR_COLOR1 0x426c 3127 #define mmDCP5_CUR_COLOR1 0x446c 3128 #define mmCUR_COLOR2 0x1a6d 3129 #define mmDCP0_CUR_COLOR2 0x1a6d 3130 #define mmDCP1_CUR_COLOR2 0x1c6d 3131 #define mmDCP2_CUR_COLOR2 0x1e6d 3132 #define mmDCP3_CUR_COLOR2 0x406d 3133 #define mmDCP4_CUR_COLOR2 0x426d 3134 #define mmDCP5_CUR_COLOR2 0x446d 3135 #define mmCUR_UPDATE 0x1a6e 3136 #define mmDCP0_CUR_UPDATE 0x1a6e 3137 #define mmDCP1_CUR_UPDATE 0x1c6e 3138 #define mmDCP2_CUR_UPDATE 0x1e6e 3139 #define mmDCP3_CUR_UPDATE 0x406e 3140 #define mmDCP4_CUR_UPDATE 0x426e 3141 #define mmDCP5_CUR_UPDATE 0x446e 3142 #define mmCUR_REQUEST_FILTER_CNTL 0x1a99 3143 #define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 3144 #define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 3145 #define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 3146 #define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 3147 #define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 3148 #define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 3149 #define mmCUR_STEREO_CONTROL 0x1a9a 3150 #define mmDCP0_CUR_STEREO_CONTROL 0x1a9a 3151 #define mmDCP1_CUR_STEREO_CONTROL 0x1c9a 3152 #define mmDCP2_CUR_STEREO_CONTROL 0x1e9a 3153 #define mmDCP3_CUR_STEREO_CONTROL 0x409a 3154 #define mmDCP4_CUR_STEREO_CONTROL 0x429a 3155 #define mmDCP5_CUR_STEREO_CONTROL 0x449a 3156 #define mmDC_LUT_RW_MODE 0x1a78 3157 #define mmDCP0_DC_LUT_RW_MODE 0x1a78 3158 #define mmDCP1_DC_LUT_RW_MODE 0x1c78 3159 #define mmDCP2_DC_LUT_RW_MODE 0x1e78 3160 #define mmDCP3_DC_LUT_RW_MODE 0x4078 3161 #define mmDCP4_DC_LUT_RW_MODE 0x4278 3162 #define mmDCP5_DC_LUT_RW_MODE 0x4478 3163 #define mmDC_LUT_RW_INDEX 0x1a79 3164 #define mmDCP0_DC_LUT_RW_INDEX 0x1a79 3165 #define mmDCP1_DC_LUT_RW_INDEX 0x1c79 3166 #define mmDCP2_DC_LUT_RW_INDEX 0x1e79 3167 #define mmDCP3_DC_LUT_RW_INDEX 0x4079 3168 #define mmDCP4_DC_LUT_RW_INDEX 0x4279 3169 #define mmDCP5_DC_LUT_RW_INDEX 0x4479 3170 #define mmDC_LUT_SEQ_COLOR 0x1a7a 3171 #define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a 3172 #define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a 3173 #define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a 3174 #define mmDCP3_DC_LUT_SEQ_COLOR 0x407a 3175 #define mmDCP4_DC_LUT_SEQ_COLOR 0x427a 3176 #define mmDCP5_DC_LUT_SEQ_COLOR 0x447a 3177 #define mmDC_LUT_PWL_DATA 0x1a7b 3178 #define mmDCP0_DC_LUT_PWL_DATA 0x1a7b 3179 #define mmDCP1_DC_LUT_PWL_DATA 0x1c7b 3180 #define mmDCP2_DC_LUT_PWL_DATA 0x1e7b 3181 #define mmDCP3_DC_LUT_PWL_DATA 0x407b 3182 #define mmDCP4_DC_LUT_PWL_DATA 0x427b 3183 #define mmDCP5_DC_LUT_PWL_DATA 0x447b 3184 #define mmDC_LUT_30_COLOR 0x1a7c 3185 #define mmDCP0_DC_LUT_30_COLOR 0x1a7c 3186 #define mmDCP1_DC_LUT_30_COLOR 0x1c7c 3187 #define mmDCP2_DC_LUT_30_COLOR 0x1e7c 3188 #define mmDCP3_DC_LUT_30_COLOR 0x407c 3189 #define mmDCP4_DC_LUT_30_COLOR 0x427c 3190 #define mmDCP5_DC_LUT_30_COLOR 0x447c 3191 #define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d 3192 #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d 3193 #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d 3194 #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d 3195 #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d 3196 #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d 3197 #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d 3198 #define mmDC_LUT_WRITE_EN_MASK 0x1a7e 3199 #define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e 3200 #define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e 3201 #define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e 3202 #define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e 3203 #define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e 3204 #define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e 3205 #define mmDC_LUT_AUTOFILL 0x1a7f 3206 #define mmDCP0_DC_LUT_AUTOFILL 0x1a7f 3207 #define mmDCP1_DC_LUT_AUTOFILL 0x1c7f 3208 #define mmDCP2_DC_LUT_AUTOFILL 0x1e7f 3209 #define mmDCP3_DC_LUT_AUTOFILL 0x407f 3210 #define mmDCP4_DC_LUT_AUTOFILL 0x427f 3211 #define mmDCP5_DC_LUT_AUTOFILL 0x447f 3212 #define mmDC_LUT_CONTROL 0x1a80 3213 #define mmDCP0_DC_LUT_CONTROL 0x1a80 3214 #define mmDCP1_DC_LUT_CONTROL 0x1c80 3215 #define mmDCP2_DC_LUT_CONTROL 0x1e80 3216 #define mmDCP3_DC_LUT_CONTROL 0x4080 3217 #define mmDCP4_DC_LUT_CONTROL 0x4280 3218 #define mmDCP5_DC_LUT_CONTROL 0x4480 3219 #define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 3220 #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 3221 #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 3222 #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 3223 #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 3224 #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 3225 #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 3226 #define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 3227 #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 3228 #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 3229 #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 3230 #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 3231 #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 3232 #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 3233 #define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 3234 #define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 3235 #define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 3236 #define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 3237 #define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 3238 #define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 3239 #define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 3240 #define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 3241 #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 3242 #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 3243 #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 3244 #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 3245 #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 3246 #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 3247 #define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 3248 #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 3249 #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 3250 #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 3251 #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 3252 #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 3253 #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 3254 #define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 3255 #define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 3256 #define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 3257 #define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 3258 #define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 3259 #define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 3260 #define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 3261 #define mmDCP_CRC_CONTROL 0x1a87 3262 #define mmDCP0_DCP_CRC_CONTROL 0x1a87 3263 #define mmDCP1_DCP_CRC_CONTROL 0x1c87 3264 #define mmDCP2_DCP_CRC_CONTROL 0x1e87 3265 #define mmDCP3_DCP_CRC_CONTROL 0x4087 3266 #define mmDCP4_DCP_CRC_CONTROL 0x4287 3267 #define mmDCP5_DCP_CRC_CONTROL 0x4487 3268 #define mmDCP_CRC_MASK 0x1a88 3269 #define mmDCP0_DCP_CRC_MASK 0x1a88 3270 #define mmDCP1_DCP_CRC_MASK 0x1c88 3271 #define mmDCP2_DCP_CRC_MASK 0x1e88 3272 #define mmDCP3_DCP_CRC_MASK 0x4088 3273 #define mmDCP4_DCP_CRC_MASK 0x4288 3274 #define mmDCP5_DCP_CRC_MASK 0x4488 3275 #define mmDCP_CRC_CURRENT 0x1a89 3276 #define mmDCP0_DCP_CRC_CURRENT 0x1a89 3277 #define mmDCP1_DCP_CRC_CURRENT 0x1c89 3278 #define mmDCP2_DCP_CRC_CURRENT 0x1e89 3279 #define mmDCP3_DCP_CRC_CURRENT 0x4089 3280 #define mmDCP4_DCP_CRC_CURRENT 0x4289 3281 #define mmDCP5_DCP_CRC_CURRENT 0x4489 3282 #define mmDCP_CRC_LAST 0x1a8b 3283 #define mmDCP0_DCP_CRC_LAST 0x1a8b 3284 #define mmDCP1_DCP_CRC_LAST 0x1c8b 3285 #define mmDCP2_DCP_CRC_LAST 0x1e8b 3286 #define mmDCP3_DCP_CRC_LAST 0x408b 3287 #define mmDCP4_DCP_CRC_LAST 0x428b 3288 #define mmDCP5_DCP_CRC_LAST 0x448b 3289 #define mmDCP_DEBUG 0x1a8d 3290 #define mmDCP0_DCP_DEBUG 0x1a8d 3291 #define mmDCP1_DCP_DEBUG 0x1c8d 3292 #define mmDCP2_DCP_DEBUG 0x1e8d 3293 #define mmDCP3_DCP_DEBUG 0x408d 3294 #define mmDCP4_DCP_DEBUG 0x428d 3295 #define mmDCP5_DCP_DEBUG 0x448d 3296 #define mmGRPH_FLIP_RATE_CNTL 0x1a8e 3297 #define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e 3298 #define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e 3299 #define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e 3300 #define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e 3301 #define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e 3302 #define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e 3303 #define mmDCP_GSL_CONTROL 0x1a90 3304 #define mmDCP0_DCP_GSL_CONTROL 0x1a90 3305 #define mmDCP1_DCP_GSL_CONTROL 0x1c90 3306 #define mmDCP2_DCP_GSL_CONTROL 0x1e90 3307 #define mmDCP3_DCP_GSL_CONTROL 0x4090 3308 #define mmDCP4_DCP_GSL_CONTROL 0x4290 3309 #define mmDCP5_DCP_GSL_CONTROL 0x4490 3310 #define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 3311 #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 3312 #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 3313 #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 3314 #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 3315 #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 3316 #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 3317 #define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1a92 3318 #define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1a92 3319 #define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1c92 3320 #define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x1e92 3321 #define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 3322 #define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4292 3323 #define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4492 3324 #define mmOVL_STEREOSYNC_FLIP 0x1a93 3325 #define mmDCP0_OVL_STEREOSYNC_FLIP 0x1a93 3326 #define mmDCP1_OVL_STEREOSYNC_FLIP 0x1c93 3327 #define mmDCP2_OVL_STEREOSYNC_FLIP 0x1e93 3328 #define mmDCP3_OVL_STEREOSYNC_FLIP 0x4093 3329 #define mmDCP4_OVL_STEREOSYNC_FLIP 0x4293 3330 #define mmDCP5_OVL_STEREOSYNC_FLIP 0x4493 3331 #define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 3332 #define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a94 3333 #define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c94 3334 #define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e94 3335 #define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 3336 #define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4294 3337 #define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4494 3338 #define mmDCP_TEST_DEBUG_INDEX 0x1a95 3339 #define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 3340 #define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 3341 #define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 3342 #define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 3343 #define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 3344 #define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 3345 #define mmDCP_TEST_DEBUG_DATA 0x1a96 3346 #define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 3347 #define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 3348 #define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 3349 #define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 3350 #define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 3351 #define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 3352 #define mmGRPH_STEREOSYNC_FLIP 0x1a97 3353 #define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 3354 #define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 3355 #define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 3356 #define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 3357 #define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 3358 #define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 3359 #define mmDCP_DEBUG2 0x1a98 3360 #define mmDCP0_DCP_DEBUG2 0x1a98 3361 #define mmDCP1_DCP_DEBUG2 0x1c98 3362 #define mmDCP2_DCP_DEBUG2 0x1e98 3363 #define mmDCP3_DCP_DEBUG2 0x4098 3364 #define mmDCP4_DCP_DEBUG2 0x4298 3365 #define mmDCP5_DCP_DEBUG2 0x4498 3366 #define mmHW_ROTATION 0x1a9e 3367 #define mmDCP0_HW_ROTATION 0x1a9e 3368 #define mmDCP1_HW_ROTATION 0x1c9e 3369 #define mmDCP2_HW_ROTATION 0x1e9e 3370 #define mmDCP3_HW_ROTATION 0x409e 3371 #define mmDCP4_HW_ROTATION 0x429e 3372 #define mmDCP5_HW_ROTATION 0x449e 3373 #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f 3374 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f 3375 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f 3376 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f 3377 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f 3378 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f 3379 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f 3380 #define mmREGAMMA_CONTROL 0x1aa0 3381 #define mmDCP0_REGAMMA_CONTROL 0x1aa0 3382 #define mmDCP1_REGAMMA_CONTROL 0x1ca0 3383 #define mmDCP2_REGAMMA_CONTROL 0x1ea0 3384 #define mmDCP3_REGAMMA_CONTROL 0x40a0 3385 #define mmDCP4_REGAMMA_CONTROL 0x42a0 3386 #define mmDCP5_REGAMMA_CONTROL 0x44a0 3387 #define mmREGAMMA_LUT_INDEX 0x1aa1 3388 #define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 3389 #define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 3390 #define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 3391 #define mmDCP3_REGAMMA_LUT_INDEX 0x40a1 3392 #define mmDCP4_REGAMMA_LUT_INDEX 0x42a1 3393 #define mmDCP5_REGAMMA_LUT_INDEX 0x44a1 3394 #define mmREGAMMA_LUT_DATA 0x1aa2 3395 #define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 3396 #define mmDCP1_REGAMMA_LUT_DATA 0x1ca2 3397 #define mmDCP2_REGAMMA_LUT_DATA 0x1ea2 3398 #define mmDCP3_REGAMMA_LUT_DATA 0x40a2 3399 #define mmDCP4_REGAMMA_LUT_DATA 0x42a2 3400 #define mmDCP5_REGAMMA_LUT_DATA 0x44a2 3401 #define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 3402 #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 3403 #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 3404 #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 3405 #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 3406 #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 3407 #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 3408 #define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 3409 #define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 3410 #define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 3411 #define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 3412 #define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 3413 #define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 3414 #define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 3415 #define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 3416 #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 3417 #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 3418 #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 3419 #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 3420 #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 3421 #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 3422 #define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 3423 #define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 3424 #define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 3425 #define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 3426 #define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 3427 #define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 3428 #define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 3429 #define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 3430 #define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 3431 #define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 3432 #define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 3433 #define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 3434 #define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 3435 #define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 3436 #define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 3437 #define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 3438 #define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 3439 #define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 3440 #define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 3441 #define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 3442 #define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 3443 #define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 3444 #define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 3445 #define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 3446 #define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 3447 #define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 3448 #define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 3449 #define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 3450 #define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa 3451 #define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa 3452 #define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa 3453 #define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa 3454 #define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa 3455 #define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa 3456 #define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa 3457 #define mmREGAMMA_CNTLA_REGION_6_7 0x1aab 3458 #define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab 3459 #define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab 3460 #define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab 3461 #define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab 3462 #define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab 3463 #define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab 3464 #define mmREGAMMA_CNTLA_REGION_8_9 0x1aac 3465 #define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac 3466 #define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac 3467 #define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac 3468 #define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac 3469 #define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac 3470 #define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac 3471 #define mmREGAMMA_CNTLA_REGION_10_11 0x1aad 3472 #define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad 3473 #define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad 3474 #define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead 3475 #define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad 3476 #define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad 3477 #define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad 3478 #define mmREGAMMA_CNTLA_REGION_12_13 0x1aae 3479 #define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae 3480 #define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae 3481 #define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae 3482 #define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae 3483 #define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae 3484 #define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae 3485 #define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf 3486 #define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf 3487 #define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf 3488 #define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf 3489 #define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af 3490 #define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af 3491 #define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af 3492 #define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 3493 #define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 3494 #define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 3495 #define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 3496 #define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 3497 #define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 3498 #define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 3499 #define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 3500 #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 3501 #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 3502 #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 3503 #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 3504 #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 3505 #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 3506 #define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 3507 #define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 3508 #define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 3509 #define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 3510 #define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 3511 #define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 3512 #define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 3513 #define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 3514 #define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 3515 #define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 3516 #define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 3517 #define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 3518 #define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 3519 #define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 3520 #define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 3521 #define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 3522 #define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 3523 #define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 3524 #define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 3525 #define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 3526 #define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 3527 #define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 3528 #define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 3529 #define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 3530 #define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 3531 #define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 3532 #define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 3533 #define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 3534 #define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 3535 #define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 3536 #define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 3537 #define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 3538 #define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 3539 #define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 3540 #define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 3541 #define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 3542 #define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 3543 #define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 3544 #define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 3545 #define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 3546 #define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 3547 #define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 3548 #define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 3549 #define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 3550 #define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 3551 #define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 3552 #define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 3553 #define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 3554 #define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 3555 #define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 3556 #define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 3557 #define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 3558 #define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 3559 #define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 3560 #define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 3561 #define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 3562 #define mmREGAMMA_CNTLB_REGION_12_13 0x1aba 3563 #define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba 3564 #define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba 3565 #define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba 3566 #define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba 3567 #define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba 3568 #define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba 3569 #define mmREGAMMA_CNTLB_REGION_14_15 0x1abb 3570 #define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb 3571 #define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb 3572 #define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb 3573 #define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb 3574 #define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb 3575 #define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb 3576 #define mmALPHA_CONTROL 0x1abc 3577 #define mmDCP0_ALPHA_CONTROL 0x1abc 3578 #define mmDCP1_ALPHA_CONTROL 0x1cbc 3579 #define mmDCP2_ALPHA_CONTROL 0x1ebc 3580 #define mmDCP3_ALPHA_CONTROL 0x40bc 3581 #define mmDCP4_ALPHA_CONTROL 0x42bc 3582 #define mmDCP5_ALPHA_CONTROL 0x44bc 3583 #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd 3584 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd 3585 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd 3586 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd 3587 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd 3588 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd 3589 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd 3590 #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe 3591 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe 3592 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe 3593 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe 3594 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be 3595 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be 3596 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be 3597 #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf 3598 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf 3599 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf 3600 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf 3601 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf 3602 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf 3603 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf 3604 #define mmDIG_FE_CNTL 0x4a00 3605 #define mmDIG0_DIG_FE_CNTL 0x4a00 3606 #define mmDIG1_DIG_FE_CNTL 0x4b00 3607 #define mmDIG2_DIG_FE_CNTL 0x4c00 3608 #define mmDIG3_DIG_FE_CNTL 0x4d00 3609 #define mmDIG4_DIG_FE_CNTL 0x4e00 3610 #define mmDIG5_DIG_FE_CNTL 0x4f00 3611 #define mmDIG6_DIG_FE_CNTL 0x5400 3612 #define mmDIG_OUTPUT_CRC_CNTL 0x4a01 3613 #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 3614 #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 3615 #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 3616 #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 3617 #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 3618 #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 3619 #define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 3620 #define mmDIG_OUTPUT_CRC_RESULT 0x4a02 3621 #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 3622 #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 3623 #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 3624 #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 3625 #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 3626 #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 3627 #define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 3628 #define mmDIG_CLOCK_PATTERN 0x4a03 3629 #define mmDIG0_DIG_CLOCK_PATTERN 0x4a03 3630 #define mmDIG1_DIG_CLOCK_PATTERN 0x4b03 3631 #define mmDIG2_DIG_CLOCK_PATTERN 0x4c03 3632 #define mmDIG3_DIG_CLOCK_PATTERN 0x4d03 3633 #define mmDIG4_DIG_CLOCK_PATTERN 0x4e03 3634 #define mmDIG5_DIG_CLOCK_PATTERN 0x4f03 3635 #define mmDIG6_DIG_CLOCK_PATTERN 0x5403 3636 #define mmDIG_TEST_PATTERN 0x4a04 3637 #define mmDIG0_DIG_TEST_PATTERN 0x4a04 3638 #define mmDIG1_DIG_TEST_PATTERN 0x4b04 3639 #define mmDIG2_DIG_TEST_PATTERN 0x4c04 3640 #define mmDIG3_DIG_TEST_PATTERN 0x4d04 3641 #define mmDIG4_DIG_TEST_PATTERN 0x4e04 3642 #define mmDIG5_DIG_TEST_PATTERN 0x4f04 3643 #define mmDIG6_DIG_TEST_PATTERN 0x5404 3644 #define mmDIG_RANDOM_PATTERN_SEED 0x4a05 3645 #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 3646 #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 3647 #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 3648 #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 3649 #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 3650 #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 3651 #define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 3652 #define mmDIG_FIFO_STATUS 0x4a06 3653 #define mmDIG0_DIG_FIFO_STATUS 0x4a06 3654 #define mmDIG1_DIG_FIFO_STATUS 0x4b06 3655 #define mmDIG2_DIG_FIFO_STATUS 0x4c06 3656 #define mmDIG3_DIG_FIFO_STATUS 0x4d06 3657 #define mmDIG4_DIG_FIFO_STATUS 0x4e06 3658 #define mmDIG5_DIG_FIFO_STATUS 0x4f06 3659 #define mmDIG6_DIG_FIFO_STATUS 0x5406 3660 #define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 3661 #define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 3662 #define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 3663 #define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 3664 #define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 3665 #define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 3666 #define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 3667 #define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 3668 #define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 3669 #define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 3670 #define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 3671 #define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 3672 #define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 3673 #define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 3674 #define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 3675 #define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 3676 #define mmHDMI_CONTROL 0x4a09 3677 #define mmDIG0_HDMI_CONTROL 0x4a09 3678 #define mmDIG1_HDMI_CONTROL 0x4b09 3679 #define mmDIG2_HDMI_CONTROL 0x4c09 3680 #define mmDIG3_HDMI_CONTROL 0x4d09 3681 #define mmDIG4_HDMI_CONTROL 0x4e09 3682 #define mmDIG5_HDMI_CONTROL 0x4f09 3683 #define mmDIG6_HDMI_CONTROL 0x5409 3684 #define mmHDMI_STATUS 0x4a0a 3685 #define mmDIG0_HDMI_STATUS 0x4a0a 3686 #define mmDIG1_HDMI_STATUS 0x4b0a 3687 #define mmDIG2_HDMI_STATUS 0x4c0a 3688 #define mmDIG3_HDMI_STATUS 0x4d0a 3689 #define mmDIG4_HDMI_STATUS 0x4e0a 3690 #define mmDIG5_HDMI_STATUS 0x4f0a 3691 #define mmDIG6_HDMI_STATUS 0x540a 3692 #define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b 3693 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b 3694 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b 3695 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b 3696 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b 3697 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b 3698 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b 3699 #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b 3700 #define mmHDMI_ACR_PACKET_CONTROL 0x4a0c 3701 #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c 3702 #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c 3703 #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c 3704 #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c 3705 #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c 3706 #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c 3707 #define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c 3708 #define mmHDMI_VBI_PACKET_CONTROL 0x4a0d 3709 #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d 3710 #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d 3711 #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d 3712 #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d 3713 #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d 3714 #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d 3715 #define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d 3716 #define mmHDMI_INFOFRAME_CONTROL0 0x4a0e 3717 #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e 3718 #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e 3719 #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e 3720 #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e 3721 #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e 3722 #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e 3723 #define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e 3724 #define mmHDMI_INFOFRAME_CONTROL1 0x4a0f 3725 #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f 3726 #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f 3727 #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f 3728 #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f 3729 #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f 3730 #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f 3731 #define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f 3732 #define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 3733 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 3734 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 3735 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 3736 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 3737 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 3738 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 3739 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 3740 #define mmAFMT_INTERRUPT_STATUS 0x4a11 3741 #define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 3742 #define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 3743 #define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 3744 #define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 3745 #define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 3746 #define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 3747 #define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 3748 #define mmHDMI_GC 0x4a13 3749 #define mmDIG0_HDMI_GC 0x4a13 3750 #define mmDIG1_HDMI_GC 0x4b13 3751 #define mmDIG2_HDMI_GC 0x4c13 3752 #define mmDIG3_HDMI_GC 0x4d13 3753 #define mmDIG4_HDMI_GC 0x4e13 3754 #define mmDIG5_HDMI_GC 0x4f13 3755 #define mmDIG6_HDMI_GC 0x5413 3756 #define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 3757 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 3758 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 3759 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 3760 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 3761 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 3762 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 3763 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 3764 #define mmAFMT_ISRC1_0 0x4a15 3765 #define mmDIG0_AFMT_ISRC1_0 0x4a15 3766 #define mmDIG1_AFMT_ISRC1_0 0x4b15 3767 #define mmDIG2_AFMT_ISRC1_0 0x4c15 3768 #define mmDIG3_AFMT_ISRC1_0 0x4d15 3769 #define mmDIG4_AFMT_ISRC1_0 0x4e15 3770 #define mmDIG5_AFMT_ISRC1_0 0x4f15 3771 #define mmDIG6_AFMT_ISRC1_0 0x5415 3772 #define mmAFMT_ISRC1_1 0x4a16 3773 #define mmDIG0_AFMT_ISRC1_1 0x4a16 3774 #define mmDIG1_AFMT_ISRC1_1 0x4b16 3775 #define mmDIG2_AFMT_ISRC1_1 0x4c16 3776 #define mmDIG3_AFMT_ISRC1_1 0x4d16 3777 #define mmDIG4_AFMT_ISRC1_1 0x4e16 3778 #define mmDIG5_AFMT_ISRC1_1 0x4f16 3779 #define mmDIG6_AFMT_ISRC1_1 0x5416 3780 #define mmAFMT_ISRC1_2 0x4a17 3781 #define mmDIG0_AFMT_ISRC1_2 0x4a17 3782 #define mmDIG1_AFMT_ISRC1_2 0x4b17 3783 #define mmDIG2_AFMT_ISRC1_2 0x4c17 3784 #define mmDIG3_AFMT_ISRC1_2 0x4d17 3785 #define mmDIG4_AFMT_ISRC1_2 0x4e17 3786 #define mmDIG5_AFMT_ISRC1_2 0x4f17 3787 #define mmDIG6_AFMT_ISRC1_2 0x5417 3788 #define mmAFMT_ISRC1_3 0x4a18 3789 #define mmDIG0_AFMT_ISRC1_3 0x4a18 3790 #define mmDIG1_AFMT_ISRC1_3 0x4b18 3791 #define mmDIG2_AFMT_ISRC1_3 0x4c18 3792 #define mmDIG3_AFMT_ISRC1_3 0x4d18 3793 #define mmDIG4_AFMT_ISRC1_3 0x4e18 3794 #define mmDIG5_AFMT_ISRC1_3 0x4f18 3795 #define mmDIG6_AFMT_ISRC1_3 0x5418 3796 #define mmAFMT_ISRC1_4 0x4a19 3797 #define mmDIG0_AFMT_ISRC1_4 0x4a19 3798 #define mmDIG1_AFMT_ISRC1_4 0x4b19 3799 #define mmDIG2_AFMT_ISRC1_4 0x4c19 3800 #define mmDIG3_AFMT_ISRC1_4 0x4d19 3801 #define mmDIG4_AFMT_ISRC1_4 0x4e19 3802 #define mmDIG5_AFMT_ISRC1_4 0x4f19 3803 #define mmDIG6_AFMT_ISRC1_4 0x5419 3804 #define mmAFMT_ISRC2_0 0x4a1a 3805 #define mmDIG0_AFMT_ISRC2_0 0x4a1a 3806 #define mmDIG1_AFMT_ISRC2_0 0x4b1a 3807 #define mmDIG2_AFMT_ISRC2_0 0x4c1a 3808 #define mmDIG3_AFMT_ISRC2_0 0x4d1a 3809 #define mmDIG4_AFMT_ISRC2_0 0x4e1a 3810 #define mmDIG5_AFMT_ISRC2_0 0x4f1a 3811 #define mmDIG6_AFMT_ISRC2_0 0x541a 3812 #define mmAFMT_ISRC2_1 0x4a1b 3813 #define mmDIG0_AFMT_ISRC2_1 0x4a1b 3814 #define mmDIG1_AFMT_ISRC2_1 0x4b1b 3815 #define mmDIG2_AFMT_ISRC2_1 0x4c1b 3816 #define mmDIG3_AFMT_ISRC2_1 0x4d1b 3817 #define mmDIG4_AFMT_ISRC2_1 0x4e1b 3818 #define mmDIG5_AFMT_ISRC2_1 0x4f1b 3819 #define mmDIG6_AFMT_ISRC2_1 0x541b 3820 #define mmAFMT_ISRC2_2 0x4a1c 3821 #define mmDIG0_AFMT_ISRC2_2 0x4a1c 3822 #define mmDIG1_AFMT_ISRC2_2 0x4b1c 3823 #define mmDIG2_AFMT_ISRC2_2 0x4c1c 3824 #define mmDIG3_AFMT_ISRC2_2 0x4d1c 3825 #define mmDIG4_AFMT_ISRC2_2 0x4e1c 3826 #define mmDIG5_AFMT_ISRC2_2 0x4f1c 3827 #define mmDIG6_AFMT_ISRC2_2 0x541c 3828 #define mmAFMT_ISRC2_3 0x4a1d 3829 #define mmDIG0_AFMT_ISRC2_3 0x4a1d 3830 #define mmDIG1_AFMT_ISRC2_3 0x4b1d 3831 #define mmDIG2_AFMT_ISRC2_3 0x4c1d 3832 #define mmDIG3_AFMT_ISRC2_3 0x4d1d 3833 #define mmDIG4_AFMT_ISRC2_3 0x4e1d 3834 #define mmDIG5_AFMT_ISRC2_3 0x4f1d 3835 #define mmDIG6_AFMT_ISRC2_3 0x541d 3836 #define mmAFMT_AVI_INFO0 0x4a1e 3837 #define mmDIG0_AFMT_AVI_INFO0 0x4a1e 3838 #define mmDIG1_AFMT_AVI_INFO0 0x4b1e 3839 #define mmDIG2_AFMT_AVI_INFO0 0x4c1e 3840 #define mmDIG3_AFMT_AVI_INFO0 0x4d1e 3841 #define mmDIG4_AFMT_AVI_INFO0 0x4e1e 3842 #define mmDIG5_AFMT_AVI_INFO0 0x4f1e 3843 #define mmDIG6_AFMT_AVI_INFO0 0x541e 3844 #define mmAFMT_AVI_INFO1 0x4a1f 3845 #define mmDIG0_AFMT_AVI_INFO1 0x4a1f 3846 #define mmDIG1_AFMT_AVI_INFO1 0x4b1f 3847 #define mmDIG2_AFMT_AVI_INFO1 0x4c1f 3848 #define mmDIG3_AFMT_AVI_INFO1 0x4d1f 3849 #define mmDIG4_AFMT_AVI_INFO1 0x4e1f 3850 #define mmDIG5_AFMT_AVI_INFO1 0x4f1f 3851 #define mmDIG6_AFMT_AVI_INFO1 0x541f 3852 #define mmAFMT_AVI_INFO2 0x4a20 3853 #define mmDIG0_AFMT_AVI_INFO2 0x4a20 3854 #define mmDIG1_AFMT_AVI_INFO2 0x4b20 3855 #define mmDIG2_AFMT_AVI_INFO2 0x4c20 3856 #define mmDIG3_AFMT_AVI_INFO2 0x4d20 3857 #define mmDIG4_AFMT_AVI_INFO2 0x4e20 3858 #define mmDIG5_AFMT_AVI_INFO2 0x4f20 3859 #define mmDIG6_AFMT_AVI_INFO2 0x5420 3860 #define mmAFMT_AVI_INFO3 0x4a21 3861 #define mmDIG0_AFMT_AVI_INFO3 0x4a21 3862 #define mmDIG1_AFMT_AVI_INFO3 0x4b21 3863 #define mmDIG2_AFMT_AVI_INFO3 0x4c21 3864 #define mmDIG3_AFMT_AVI_INFO3 0x4d21 3865 #define mmDIG4_AFMT_AVI_INFO3 0x4e21 3866 #define mmDIG5_AFMT_AVI_INFO3 0x4f21 3867 #define mmDIG6_AFMT_AVI_INFO3 0x5421 3868 #define mmAFMT_MPEG_INFO0 0x4a22 3869 #define mmDIG0_AFMT_MPEG_INFO0 0x4a22 3870 #define mmDIG1_AFMT_MPEG_INFO0 0x4b22 3871 #define mmDIG2_AFMT_MPEG_INFO0 0x4c22 3872 #define mmDIG3_AFMT_MPEG_INFO0 0x4d22 3873 #define mmDIG4_AFMT_MPEG_INFO0 0x4e22 3874 #define mmDIG5_AFMT_MPEG_INFO0 0x4f22 3875 #define mmDIG6_AFMT_MPEG_INFO0 0x5422 3876 #define mmAFMT_MPEG_INFO1 0x4a23 3877 #define mmDIG0_AFMT_MPEG_INFO1 0x4a23 3878 #define mmDIG1_AFMT_MPEG_INFO1 0x4b23 3879 #define mmDIG2_AFMT_MPEG_INFO1 0x4c23 3880 #define mmDIG3_AFMT_MPEG_INFO1 0x4d23 3881 #define mmDIG4_AFMT_MPEG_INFO1 0x4e23 3882 #define mmDIG5_AFMT_MPEG_INFO1 0x4f23 3883 #define mmDIG6_AFMT_MPEG_INFO1 0x5423 3884 #define mmAFMT_GENERIC_HDR 0x4a24 3885 #define mmDIG0_AFMT_GENERIC_HDR 0x4a24 3886 #define mmDIG1_AFMT_GENERIC_HDR 0x4b24 3887 #define mmDIG2_AFMT_GENERIC_HDR 0x4c24 3888 #define mmDIG3_AFMT_GENERIC_HDR 0x4d24 3889 #define mmDIG4_AFMT_GENERIC_HDR 0x4e24 3890 #define mmDIG5_AFMT_GENERIC_HDR 0x4f24 3891 #define mmDIG6_AFMT_GENERIC_HDR 0x5424 3892 #define mmAFMT_GENERIC_0 0x4a25 3893 #define mmDIG0_AFMT_GENERIC_0 0x4a25 3894 #define mmDIG1_AFMT_GENERIC_0 0x4b25 3895 #define mmDIG2_AFMT_GENERIC_0 0x4c25 3896 #define mmDIG3_AFMT_GENERIC_0 0x4d25 3897 #define mmDIG4_AFMT_GENERIC_0 0x4e25 3898 #define mmDIG5_AFMT_GENERIC_0 0x4f25 3899 #define mmDIG6_AFMT_GENERIC_0 0x5425 3900 #define mmAFMT_GENERIC_1 0x4a26 3901 #define mmDIG0_AFMT_GENERIC_1 0x4a26 3902 #define mmDIG1_AFMT_GENERIC_1 0x4b26 3903 #define mmDIG2_AFMT_GENERIC_1 0x4c26 3904 #define mmDIG3_AFMT_GENERIC_1 0x4d26 3905 #define mmDIG4_AFMT_GENERIC_1 0x4e26 3906 #define mmDIG5_AFMT_GENERIC_1 0x4f26 3907 #define mmDIG6_AFMT_GENERIC_1 0x5426 3908 #define mmAFMT_GENERIC_2 0x4a27 3909 #define mmDIG0_AFMT_GENERIC_2 0x4a27 3910 #define mmDIG1_AFMT_GENERIC_2 0x4b27 3911 #define mmDIG2_AFMT_GENERIC_2 0x4c27 3912 #define mmDIG3_AFMT_GENERIC_2 0x4d27 3913 #define mmDIG4_AFMT_GENERIC_2 0x4e27 3914 #define mmDIG5_AFMT_GENERIC_2 0x4f27 3915 #define mmDIG6_AFMT_GENERIC_2 0x5427 3916 #define mmAFMT_GENERIC_3 0x4a28 3917 #define mmDIG0_AFMT_GENERIC_3 0x4a28 3918 #define mmDIG1_AFMT_GENERIC_3 0x4b28 3919 #define mmDIG2_AFMT_GENERIC_3 0x4c28 3920 #define mmDIG3_AFMT_GENERIC_3 0x4d28 3921 #define mmDIG4_AFMT_GENERIC_3 0x4e28 3922 #define mmDIG5_AFMT_GENERIC_3 0x4f28 3923 #define mmDIG6_AFMT_GENERIC_3 0x5428 3924 #define mmAFMT_GENERIC_4 0x4a29 3925 #define mmDIG0_AFMT_GENERIC_4 0x4a29 3926 #define mmDIG1_AFMT_GENERIC_4 0x4b29 3927 #define mmDIG2_AFMT_GENERIC_4 0x4c29 3928 #define mmDIG3_AFMT_GENERIC_4 0x4d29 3929 #define mmDIG4_AFMT_GENERIC_4 0x4e29 3930 #define mmDIG5_AFMT_GENERIC_4 0x4f29 3931 #define mmDIG6_AFMT_GENERIC_4 0x5429 3932 #define mmAFMT_GENERIC_5 0x4a2a 3933 #define mmDIG0_AFMT_GENERIC_5 0x4a2a 3934 #define mmDIG1_AFMT_GENERIC_5 0x4b2a 3935 #define mmDIG2_AFMT_GENERIC_5 0x4c2a 3936 #define mmDIG3_AFMT_GENERIC_5 0x4d2a 3937 #define mmDIG4_AFMT_GENERIC_5 0x4e2a 3938 #define mmDIG5_AFMT_GENERIC_5 0x4f2a 3939 #define mmDIG6_AFMT_GENERIC_5 0x542a 3940 #define mmAFMT_GENERIC_6 0x4a2b 3941 #define mmDIG0_AFMT_GENERIC_6 0x4a2b 3942 #define mmDIG1_AFMT_GENERIC_6 0x4b2b 3943 #define mmDIG2_AFMT_GENERIC_6 0x4c2b 3944 #define mmDIG3_AFMT_GENERIC_6 0x4d2b 3945 #define mmDIG4_AFMT_GENERIC_6 0x4e2b 3946 #define mmDIG5_AFMT_GENERIC_6 0x4f2b 3947 #define mmDIG6_AFMT_GENERIC_6 0x542b 3948 #define mmAFMT_GENERIC_7 0x4a2c 3949 #define mmDIG0_AFMT_GENERIC_7 0x4a2c 3950 #define mmDIG1_AFMT_GENERIC_7 0x4b2c 3951 #define mmDIG2_AFMT_GENERIC_7 0x4c2c 3952 #define mmDIG3_AFMT_GENERIC_7 0x4d2c 3953 #define mmDIG4_AFMT_GENERIC_7 0x4e2c 3954 #define mmDIG5_AFMT_GENERIC_7 0x4f2c 3955 #define mmDIG6_AFMT_GENERIC_7 0x542c 3956 #define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d 3957 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d 3958 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d 3959 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d 3960 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d 3961 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d 3962 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d 3963 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d 3964 #define mmHDMI_ACR_32_0 0x4a2e 3965 #define mmDIG0_HDMI_ACR_32_0 0x4a2e 3966 #define mmDIG1_HDMI_ACR_32_0 0x4b2e 3967 #define mmDIG2_HDMI_ACR_32_0 0x4c2e 3968 #define mmDIG3_HDMI_ACR_32_0 0x4d2e 3969 #define mmDIG4_HDMI_ACR_32_0 0x4e2e 3970 #define mmDIG5_HDMI_ACR_32_0 0x4f2e 3971 #define mmDIG6_HDMI_ACR_32_0 0x542e 3972 #define mmHDMI_ACR_32_1 0x4a2f 3973 #define mmDIG0_HDMI_ACR_32_1 0x4a2f 3974 #define mmDIG1_HDMI_ACR_32_1 0x4b2f 3975 #define mmDIG2_HDMI_ACR_32_1 0x4c2f 3976 #define mmDIG3_HDMI_ACR_32_1 0x4d2f 3977 #define mmDIG4_HDMI_ACR_32_1 0x4e2f 3978 #define mmDIG5_HDMI_ACR_32_1 0x4f2f 3979 #define mmDIG6_HDMI_ACR_32_1 0x542f 3980 #define mmHDMI_ACR_44_0 0x4a30 3981 #define mmDIG0_HDMI_ACR_44_0 0x4a30 3982 #define mmDIG1_HDMI_ACR_44_0 0x4b30 3983 #define mmDIG2_HDMI_ACR_44_0 0x4c30 3984 #define mmDIG3_HDMI_ACR_44_0 0x4d30 3985 #define mmDIG4_HDMI_ACR_44_0 0x4e30 3986 #define mmDIG5_HDMI_ACR_44_0 0x4f30 3987 #define mmDIG6_HDMI_ACR_44_0 0x5430 3988 #define mmHDMI_ACR_44_1 0x4a31 3989 #define mmDIG0_HDMI_ACR_44_1 0x4a31 3990 #define mmDIG1_HDMI_ACR_44_1 0x4b31 3991 #define mmDIG2_HDMI_ACR_44_1 0x4c31 3992 #define mmDIG3_HDMI_ACR_44_1 0x4d31 3993 #define mmDIG4_HDMI_ACR_44_1 0x4e31 3994 #define mmDIG5_HDMI_ACR_44_1 0x4f31 3995 #define mmDIG6_HDMI_ACR_44_1 0x5431 3996 #define mmHDMI_ACR_48_0 0x4a32 3997 #define mmDIG0_HDMI_ACR_48_0 0x4a32 3998 #define mmDIG1_HDMI_ACR_48_0 0x4b32 3999 #define mmDIG2_HDMI_ACR_48_0 0x4c32 4000 #define mmDIG3_HDMI_ACR_48_0 0x4d32 4001 #define mmDIG4_HDMI_ACR_48_0 0x4e32 4002 #define mmDIG5_HDMI_ACR_48_0 0x4f32 4003 #define mmDIG6_HDMI_ACR_48_0 0x5432 4004 #define mmHDMI_ACR_48_1 0x4a33 4005 #define mmDIG0_HDMI_ACR_48_1 0x4a33 4006 #define mmDIG1_HDMI_ACR_48_1 0x4b33 4007 #define mmDIG2_HDMI_ACR_48_1 0x4c33 4008 #define mmDIG3_HDMI_ACR_48_1 0x4d33 4009 #define mmDIG4_HDMI_ACR_48_1 0x4e33 4010 #define mmDIG5_HDMI_ACR_48_1 0x4f33 4011 #define mmDIG6_HDMI_ACR_48_1 0x5433 4012 #define mmHDMI_ACR_STATUS_0 0x4a34 4013 #define mmDIG0_HDMI_ACR_STATUS_0 0x4a34 4014 #define mmDIG1_HDMI_ACR_STATUS_0 0x4b34 4015 #define mmDIG2_HDMI_ACR_STATUS_0 0x4c34 4016 #define mmDIG3_HDMI_ACR_STATUS_0 0x4d34 4017 #define mmDIG4_HDMI_ACR_STATUS_0 0x4e34 4018 #define mmDIG5_HDMI_ACR_STATUS_0 0x4f34 4019 #define mmDIG6_HDMI_ACR_STATUS_0 0x5434 4020 #define mmHDMI_ACR_STATUS_1 0x4a35 4021 #define mmDIG0_HDMI_ACR_STATUS_1 0x4a35 4022 #define mmDIG1_HDMI_ACR_STATUS_1 0x4b35 4023 #define mmDIG2_HDMI_ACR_STATUS_1 0x4c35 4024 #define mmDIG3_HDMI_ACR_STATUS_1 0x4d35 4025 #define mmDIG4_HDMI_ACR_STATUS_1 0x4e35 4026 #define mmDIG5_HDMI_ACR_STATUS_1 0x4f35 4027 #define mmDIG6_HDMI_ACR_STATUS_1 0x5435 4028 #define mmAFMT_AUDIO_INFO0 0x4a36 4029 #define mmDIG0_AFMT_AUDIO_INFO0 0x4a36 4030 #define mmDIG1_AFMT_AUDIO_INFO0 0x4b36 4031 #define mmDIG2_AFMT_AUDIO_INFO0 0x4c36 4032 #define mmDIG3_AFMT_AUDIO_INFO0 0x4d36 4033 #define mmDIG4_AFMT_AUDIO_INFO0 0x4e36 4034 #define mmDIG5_AFMT_AUDIO_INFO0 0x4f36 4035 #define mmDIG6_AFMT_AUDIO_INFO0 0x5436 4036 #define mmAFMT_AUDIO_INFO1 0x4a37 4037 #define mmDIG0_AFMT_AUDIO_INFO1 0x4a37 4038 #define mmDIG1_AFMT_AUDIO_INFO1 0x4b37 4039 #define mmDIG2_AFMT_AUDIO_INFO1 0x4c37 4040 #define mmDIG3_AFMT_AUDIO_INFO1 0x4d37 4041 #define mmDIG4_AFMT_AUDIO_INFO1 0x4e37 4042 #define mmDIG5_AFMT_AUDIO_INFO1 0x4f37 4043 #define mmDIG6_AFMT_AUDIO_INFO1 0x5437 4044 #define mmAFMT_60958_0 0x4a38 4045 #define mmDIG0_AFMT_60958_0 0x4a38 4046 #define mmDIG1_AFMT_60958_0 0x4b38 4047 #define mmDIG2_AFMT_60958_0 0x4c38 4048 #define mmDIG3_AFMT_60958_0 0x4d38 4049 #define mmDIG4_AFMT_60958_0 0x4e38 4050 #define mmDIG5_AFMT_60958_0 0x4f38 4051 #define mmDIG6_AFMT_60958_0 0x5438 4052 #define mmAFMT_60958_1 0x4a39 4053 #define mmDIG0_AFMT_60958_1 0x4a39 4054 #define mmDIG1_AFMT_60958_1 0x4b39 4055 #define mmDIG2_AFMT_60958_1 0x4c39 4056 #define mmDIG3_AFMT_60958_1 0x4d39 4057 #define mmDIG4_AFMT_60958_1 0x4e39 4058 #define mmDIG5_AFMT_60958_1 0x4f39 4059 #define mmDIG6_AFMT_60958_1 0x5439 4060 #define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a 4061 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a 4062 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a 4063 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a 4064 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a 4065 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a 4066 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a 4067 #define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a 4068 #define mmAFMT_RAMP_CONTROL0 0x4a3b 4069 #define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b 4070 #define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b 4071 #define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b 4072 #define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b 4073 #define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b 4074 #define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b 4075 #define mmDIG6_AFMT_RAMP_CONTROL0 0x543b 4076 #define mmAFMT_RAMP_CONTROL1 0x4a3c 4077 #define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c 4078 #define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c 4079 #define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c 4080 #define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c 4081 #define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c 4082 #define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c 4083 #define mmDIG6_AFMT_RAMP_CONTROL1 0x543c 4084 #define mmAFMT_RAMP_CONTROL2 0x4a3d 4085 #define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d 4086 #define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d 4087 #define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d 4088 #define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d 4089 #define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d 4090 #define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d 4091 #define mmDIG6_AFMT_RAMP_CONTROL2 0x543d 4092 #define mmAFMT_RAMP_CONTROL3 0x4a3e 4093 #define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e 4094 #define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e 4095 #define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e 4096 #define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e 4097 #define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e 4098 #define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e 4099 #define mmDIG6_AFMT_RAMP_CONTROL3 0x543e 4100 #define mmAFMT_60958_2 0x4a3f 4101 #define mmDIG0_AFMT_60958_2 0x4a3f 4102 #define mmDIG1_AFMT_60958_2 0x4b3f 4103 #define mmDIG2_AFMT_60958_2 0x4c3f 4104 #define mmDIG3_AFMT_60958_2 0x4d3f 4105 #define mmDIG4_AFMT_60958_2 0x4e3f 4106 #define mmDIG5_AFMT_60958_2 0x4f3f 4107 #define mmDIG6_AFMT_60958_2 0x543f 4108 #define mmAFMT_AUDIO_CRC_RESULT 0x4a40 4109 #define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 4110 #define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 4111 #define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 4112 #define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 4113 #define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 4114 #define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 4115 #define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 4116 #define mmAFMT_STATUS 0x4a41 4117 #define mmDIG0_AFMT_STATUS 0x4a41 4118 #define mmDIG1_AFMT_STATUS 0x4b41 4119 #define mmDIG2_AFMT_STATUS 0x4c41 4120 #define mmDIG3_AFMT_STATUS 0x4d41 4121 #define mmDIG4_AFMT_STATUS 0x4e41 4122 #define mmDIG5_AFMT_STATUS 0x4f41 4123 #define mmDIG6_AFMT_STATUS 0x5441 4124 #define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 4125 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 4126 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 4127 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 4128 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 4129 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 4130 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 4131 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 4132 #define mmAFMT_VBI_PACKET_CONTROL 0x4a43 4133 #define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 4134 #define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 4135 #define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 4136 #define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 4137 #define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 4138 #define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 4139 #define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 4140 #define mmAFMT_INFOFRAME_CONTROL0 0x4a44 4141 #define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 4142 #define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 4143 #define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 4144 #define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 4145 #define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 4146 #define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 4147 #define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 4148 #define mmAFMT_AUDIO_SRC_CONTROL 0x4a45 4149 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 4150 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 4151 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 4152 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 4153 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 4154 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 4155 #define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 4156 #define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 4157 #define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 4158 #define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 4159 #define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 4160 #define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 4161 #define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 4162 #define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 4163 #define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 4164 #define mmDIG_BE_CNTL 0x4a47 4165 #define mmDIG0_DIG_BE_CNTL 0x4a47 4166 #define mmDIG1_DIG_BE_CNTL 0x4b47 4167 #define mmDIG2_DIG_BE_CNTL 0x4c47 4168 #define mmDIG3_DIG_BE_CNTL 0x4d47 4169 #define mmDIG4_DIG_BE_CNTL 0x4e47 4170 #define mmDIG5_DIG_BE_CNTL 0x4f47 4171 #define mmDIG6_DIG_BE_CNTL 0x5447 4172 #define mmDIG_BE_EN_CNTL 0x4a48 4173 #define mmDIG0_DIG_BE_EN_CNTL 0x4a48 4174 #define mmDIG1_DIG_BE_EN_CNTL 0x4b48 4175 #define mmDIG2_DIG_BE_EN_CNTL 0x4c48 4176 #define mmDIG3_DIG_BE_EN_CNTL 0x4d48 4177 #define mmDIG4_DIG_BE_EN_CNTL 0x4e48 4178 #define mmDIG5_DIG_BE_EN_CNTL 0x4f48 4179 #define mmDIG6_DIG_BE_EN_CNTL 0x5448 4180 #define mmTMDS_CNTL 0x4a6b 4181 #define mmDIG0_TMDS_CNTL 0x4a6b 4182 #define mmDIG1_TMDS_CNTL 0x4b6b 4183 #define mmDIG2_TMDS_CNTL 0x4c6b 4184 #define mmDIG3_TMDS_CNTL 0x4d6b 4185 #define mmDIG4_TMDS_CNTL 0x4e6b 4186 #define mmDIG5_TMDS_CNTL 0x4f6b 4187 #define mmDIG6_TMDS_CNTL 0x546b 4188 #define mmTMDS_CONTROL_CHAR 0x4a6c 4189 #define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c 4190 #define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c 4191 #define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c 4192 #define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c 4193 #define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c 4194 #define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c 4195 #define mmDIG6_TMDS_CONTROL_CHAR 0x546c 4196 #define mmTMDS_CONTROL0_FEEDBACK 0x4a6d 4197 #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d 4198 #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d 4199 #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d 4200 #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d 4201 #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d 4202 #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d 4203 #define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d 4204 #define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e 4205 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e 4206 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e 4207 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e 4208 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e 4209 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e 4210 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e 4211 #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e 4212 #define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f 4213 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f 4214 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f 4215 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f 4216 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f 4217 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f 4218 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f 4219 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f 4220 #define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 4221 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 4222 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 4223 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 4224 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 4225 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 4226 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 4227 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 4228 #define mmTMDS_DEBUG 0x4a71 4229 #define mmDIG0_TMDS_DEBUG 0x4a71 4230 #define mmDIG1_TMDS_DEBUG 0x4b71 4231 #define mmDIG2_TMDS_DEBUG 0x4c71 4232 #define mmDIG3_TMDS_DEBUG 0x4d71 4233 #define mmDIG4_TMDS_DEBUG 0x4e71 4234 #define mmDIG5_TMDS_DEBUG 0x4f71 4235 #define mmDIG6_TMDS_DEBUG 0x5471 4236 #define mmTMDS_CTL_BITS 0x4a72 4237 #define mmDIG0_TMDS_CTL_BITS 0x4a72 4238 #define mmDIG1_TMDS_CTL_BITS 0x4b72 4239 #define mmDIG2_TMDS_CTL_BITS 0x4c72 4240 #define mmDIG3_TMDS_CTL_BITS 0x4d72 4241 #define mmDIG4_TMDS_CTL_BITS 0x4e72 4242 #define mmDIG5_TMDS_CTL_BITS 0x4f72 4243 #define mmDIG6_TMDS_CTL_BITS 0x5472 4244 #define mmTMDS_DCBALANCER_CONTROL 0x4a73 4245 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 4246 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 4247 #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 4248 #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 4249 #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 4250 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 4251 #define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 4252 #define mmTMDS_CTL0_1_GEN_CNTL 0x4a75 4253 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 4254 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 4255 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 4256 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 4257 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 4258 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 4259 #define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 4260 #define mmTMDS_CTL2_3_GEN_CNTL 0x4a76 4261 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 4262 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 4263 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 4264 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 4265 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 4266 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 4267 #define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 4268 #define ixTMDS_DEBUG1 0x1 4269 #define ixTMDS_DEBUG2 0x2 4270 #define ixTMDS_DEBUG3 0x3 4271 #define ixTMDS_DEBUG7 0x4 4272 #define ixTMDS_DEBUG8 0x5 4273 #define ixTMDS_DEBUG9 0x6 4274 #define ixTMDS_DEBUG10 0x7 4275 #define ixTMDS_DEBUG11 0x8 4276 #define ixTMDS_DEBUG12 0x9 4277 #define ixTMDS_DEBUG13 0xa 4278 #define mmLVDS_DATA_CNTL 0x4a78 4279 #define mmDIG0_LVDS_DATA_CNTL 0x4a78 4280 #define mmDIG1_LVDS_DATA_CNTL 0x4b78 4281 #define mmDIG2_LVDS_DATA_CNTL 0x4c78 4282 #define mmDIG3_LVDS_DATA_CNTL 0x4d78 4283 #define mmDIG4_LVDS_DATA_CNTL 0x4e78 4284 #define mmDIG5_LVDS_DATA_CNTL 0x4f78 4285 #define mmDIG6_LVDS_DATA_CNTL 0x5478 4286 #define mmDIG_LANE_ENABLE 0x4a79 4287 #define mmDIG0_DIG_LANE_ENABLE 0x4a79 4288 #define mmDIG1_DIG_LANE_ENABLE 0x4b79 4289 #define mmDIG2_DIG_LANE_ENABLE 0x4c79 4290 #define mmDIG3_DIG_LANE_ENABLE 0x4d79 4291 #define mmDIG4_DIG_LANE_ENABLE 0x4e79 4292 #define mmDIG5_DIG_LANE_ENABLE 0x4f79 4293 #define mmDIG6_DIG_LANE_ENABLE 0x5479 4294 #define mmDIG_TEST_DEBUG_INDEX 0x4a7a 4295 #define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a 4296 #define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a 4297 #define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a 4298 #define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a 4299 #define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a 4300 #define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a 4301 #define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a 4302 #define mmDIG_TEST_DEBUG_DATA 0x4a7b 4303 #define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b 4304 #define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b 4305 #define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b 4306 #define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b 4307 #define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b 4308 #define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b 4309 #define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b 4310 #define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c 4311 #define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c 4312 #define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c 4313 #define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c 4314 #define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c 4315 #define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c 4316 #define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c 4317 #define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c 4318 #define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d 4319 #define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d 4320 #define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d 4321 #define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d 4322 #define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d 4323 #define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d 4324 #define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d 4325 #define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d 4326 #define mmDMCU_CTRL 0x1600 4327 #define mmDMCU_STATUS 0x1601 4328 #define mmDMCU_PC_START_ADDR 0x1602 4329 #define mmDMCU_FW_START_ADDR 0x1603 4330 #define mmDMCU_FW_END_ADDR 0x1604 4331 #define mmDMCU_FW_ISR_START_ADDR 0x1605 4332 #define mmDMCU_FW_CS_HI 0x1606 4333 #define mmDMCU_FW_CS_LO 0x1607 4334 #define mmDMCU_RAM_ACCESS_CTRL 0x1608 4335 #define mmDMCU_ERAM_WR_CTRL 0x1609 4336 #define mmDMCU_ERAM_WR_DATA 0x160a 4337 #define mmDMCU_ERAM_RD_CTRL 0x160b 4338 #define mmDMCU_ERAM_RD_DATA 0x160c 4339 #define mmDMCU_IRAM_WR_CTRL 0x160d 4340 #define mmDMCU_IRAM_WR_DATA 0x160e 4341 #define mmDMCU_IRAM_RD_CTRL 0x160f 4342 #define mmDMCU_IRAM_RD_DATA 0x1610 4343 #define mmDMCU_EVENT_TRIGGER 0x1611 4344 #define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 4345 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 4346 #define mmDMCU_INTERRUPT_STATUS 0x1614 4347 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 4348 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 4349 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 4350 #define mmDC_DMCU_SCRATCH 0x1618 4351 #define mmDMCU_INT_CNT 0x1619 4352 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a 4353 #define mmDMCU_UC_CLK_GATING_CNTL 0x161b 4354 #define mmMASTER_COMM_DATA_REG1 0x161c 4355 #define mmMASTER_COMM_DATA_REG2 0x161d 4356 #define mmMASTER_COMM_DATA_REG3 0x161e 4357 #define mmMASTER_COMM_CMD_REG 0x161f 4358 #define mmMASTER_COMM_CNTL_REG 0x1620 4359 #define mmSLAVE_COMM_DATA_REG1 0x1621 4360 #define mmSLAVE_COMM_DATA_REG2 0x1622 4361 #define mmSLAVE_COMM_DATA_REG3 0x1623 4362 #define mmSLAVE_COMM_CMD_REG 0x1624 4363 #define mmSLAVE_COMM_CNTL_REG 0x1625 4364 #define mmDMCU_TEST_DEBUG_INDEX 0x1626 4365 #define mmDMCU_TEST_DEBUG_DATA 0x1627 4366 #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 4367 #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 4368 #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 4369 #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 4370 #define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 4371 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 4372 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 4373 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 4374 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 4375 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 4376 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 4377 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 4378 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a 4379 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b 4380 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 4381 #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1 0x167c 4382 #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2 0x167d 4383 #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3 0x167e 4384 #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4 0x167f 4385 #define mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5 0x1633 4386 #define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 4387 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 4388 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 4389 #define mmDP_LINK_CNTL 0x4aa0 4390 #define mmDP0_DP_LINK_CNTL 0x4aa0 4391 #define mmDP1_DP_LINK_CNTL 0x4ba0 4392 #define mmDP2_DP_LINK_CNTL 0x4ca0 4393 #define mmDP3_DP_LINK_CNTL 0x4da0 4394 #define mmDP4_DP_LINK_CNTL 0x4ea0 4395 #define mmDP5_DP_LINK_CNTL 0x4fa0 4396 #define mmDP6_DP_LINK_CNTL 0x54a0 4397 #define mmDP_PIXEL_FORMAT 0x4aa1 4398 #define mmDP0_DP_PIXEL_FORMAT 0x4aa1 4399 #define mmDP1_DP_PIXEL_FORMAT 0x4ba1 4400 #define mmDP2_DP_PIXEL_FORMAT 0x4ca1 4401 #define mmDP3_DP_PIXEL_FORMAT 0x4da1 4402 #define mmDP4_DP_PIXEL_FORMAT 0x4ea1 4403 #define mmDP5_DP_PIXEL_FORMAT 0x4fa1 4404 #define mmDP6_DP_PIXEL_FORMAT 0x54a1 4405 #define mmDP_MSA_COLORIMETRY 0x4aa2 4406 #define mmDP0_DP_MSA_COLORIMETRY 0x4aa2 4407 #define mmDP1_DP_MSA_COLORIMETRY 0x4ba2 4408 #define mmDP2_DP_MSA_COLORIMETRY 0x4ca2 4409 #define mmDP3_DP_MSA_COLORIMETRY 0x4da2 4410 #define mmDP4_DP_MSA_COLORIMETRY 0x4ea2 4411 #define mmDP5_DP_MSA_COLORIMETRY 0x4fa2 4412 #define mmDP6_DP_MSA_COLORIMETRY 0x54a2 4413 #define mmDP_CONFIG 0x4aa3 4414 #define mmDP0_DP_CONFIG 0x4aa3 4415 #define mmDP1_DP_CONFIG 0x4ba3 4416 #define mmDP2_DP_CONFIG 0x4ca3 4417 #define mmDP3_DP_CONFIG 0x4da3 4418 #define mmDP4_DP_CONFIG 0x4ea3 4419 #define mmDP5_DP_CONFIG 0x4fa3 4420 #define mmDP6_DP_CONFIG 0x54a3 4421 #define mmDP_VID_STREAM_CNTL 0x4aa4 4422 #define mmDP0_DP_VID_STREAM_CNTL 0x4aa4 4423 #define mmDP1_DP_VID_STREAM_CNTL 0x4ba4 4424 #define mmDP2_DP_VID_STREAM_CNTL 0x4ca4 4425 #define mmDP3_DP_VID_STREAM_CNTL 0x4da4 4426 #define mmDP4_DP_VID_STREAM_CNTL 0x4ea4 4427 #define mmDP5_DP_VID_STREAM_CNTL 0x4fa4 4428 #define mmDP6_DP_VID_STREAM_CNTL 0x54a4 4429 #define mmDP_STEER_FIFO 0x4aa5 4430 #define mmDP0_DP_STEER_FIFO 0x4aa5 4431 #define mmDP1_DP_STEER_FIFO 0x4ba5 4432 #define mmDP2_DP_STEER_FIFO 0x4ca5 4433 #define mmDP3_DP_STEER_FIFO 0x4da5 4434 #define mmDP4_DP_STEER_FIFO 0x4ea5 4435 #define mmDP5_DP_STEER_FIFO 0x4fa5 4436 #define mmDP6_DP_STEER_FIFO 0x54a5 4437 #define mmDP_MSA_MISC 0x4aa6 4438 #define mmDP0_DP_MSA_MISC 0x4aa6 4439 #define mmDP1_DP_MSA_MISC 0x4ba6 4440 #define mmDP2_DP_MSA_MISC 0x4ca6 4441 #define mmDP3_DP_MSA_MISC 0x4da6 4442 #define mmDP4_DP_MSA_MISC 0x4ea6 4443 #define mmDP5_DP_MSA_MISC 0x4fa6 4444 #define mmDP6_DP_MSA_MISC 0x54a6 4445 #define mmDP_VID_TIMING 0x4aa8 4446 #define mmDP0_DP_VID_TIMING 0x4aa8 4447 #define mmDP1_DP_VID_TIMING 0x4ba8 4448 #define mmDP2_DP_VID_TIMING 0x4ca8 4449 #define mmDP3_DP_VID_TIMING 0x4da8 4450 #define mmDP4_DP_VID_TIMING 0x4ea8 4451 #define mmDP5_DP_VID_TIMING 0x4fa8 4452 #define mmDP6_DP_VID_TIMING 0x54a8 4453 #define mmDP_VID_N 0x4aa9 4454 #define mmDP0_DP_VID_N 0x4aa9 4455 #define mmDP1_DP_VID_N 0x4ba9 4456 #define mmDP2_DP_VID_N 0x4ca9 4457 #define mmDP3_DP_VID_N 0x4da9 4458 #define mmDP4_DP_VID_N 0x4ea9 4459 #define mmDP5_DP_VID_N 0x4fa9 4460 #define mmDP6_DP_VID_N 0x54a9 4461 #define mmDP_VID_M 0x4aaa 4462 #define mmDP0_DP_VID_M 0x4aaa 4463 #define mmDP1_DP_VID_M 0x4baa 4464 #define mmDP2_DP_VID_M 0x4caa 4465 #define mmDP3_DP_VID_M 0x4daa 4466 #define mmDP4_DP_VID_M 0x4eaa 4467 #define mmDP5_DP_VID_M 0x4faa 4468 #define mmDP6_DP_VID_M 0x54aa 4469 #define mmDP_LINK_FRAMING_CNTL 0x4aab 4470 #define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab 4471 #define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab 4472 #define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab 4473 #define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab 4474 #define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab 4475 #define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab 4476 #define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab 4477 #define mmDP_HBR2_EYE_PATTERN 0x4aac 4478 #define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac 4479 #define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac 4480 #define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac 4481 #define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac 4482 #define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac 4483 #define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac 4484 #define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac 4485 #define mmDP_VID_MSA_VBID 0x4aad 4486 #define mmDP0_DP_VID_MSA_VBID 0x4aad 4487 #define mmDP1_DP_VID_MSA_VBID 0x4bad 4488 #define mmDP2_DP_VID_MSA_VBID 0x4cad 4489 #define mmDP3_DP_VID_MSA_VBID 0x4dad 4490 #define mmDP4_DP_VID_MSA_VBID 0x4ead 4491 #define mmDP5_DP_VID_MSA_VBID 0x4fad 4492 #define mmDP6_DP_VID_MSA_VBID 0x54ad 4493 #define mmDP_VID_INTERRUPT_CNTL 0x4aae 4494 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae 4495 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae 4496 #define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae 4497 #define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae 4498 #define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae 4499 #define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae 4500 #define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae 4501 #define mmDP_DPHY_CNTL 0x4aaf 4502 #define mmDP0_DP_DPHY_CNTL 0x4aaf 4503 #define mmDP1_DP_DPHY_CNTL 0x4baf 4504 #define mmDP2_DP_DPHY_CNTL 0x4caf 4505 #define mmDP3_DP_DPHY_CNTL 0x4daf 4506 #define mmDP4_DP_DPHY_CNTL 0x4eaf 4507 #define mmDP5_DP_DPHY_CNTL 0x4faf 4508 #define mmDP6_DP_DPHY_CNTL 0x54af 4509 #define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 4510 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 4511 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 4512 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 4513 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 4514 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 4515 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 4516 #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 4517 #define mmDP_DPHY_SYM0 0x4ab1 4518 #define mmDP0_DP_DPHY_SYM0 0x4ab1 4519 #define mmDP1_DP_DPHY_SYM0 0x4bb1 4520 #define mmDP2_DP_DPHY_SYM0 0x4cb1 4521 #define mmDP3_DP_DPHY_SYM0 0x4db1 4522 #define mmDP4_DP_DPHY_SYM0 0x4eb1 4523 #define mmDP5_DP_DPHY_SYM0 0x4fb1 4524 #define mmDP6_DP_DPHY_SYM0 0x54b1 4525 #define mmDP_DPHY_SYM1 0x4ab2 4526 #define mmDP0_DP_DPHY_SYM1 0x4ab2 4527 #define mmDP1_DP_DPHY_SYM1 0x4bb2 4528 #define mmDP2_DP_DPHY_SYM1 0x4cb2 4529 #define mmDP3_DP_DPHY_SYM1 0x4db2 4530 #define mmDP4_DP_DPHY_SYM1 0x4eb2 4531 #define mmDP5_DP_DPHY_SYM1 0x4fb2 4532 #define mmDP6_DP_DPHY_SYM1 0x54b2 4533 #define mmDP_DPHY_SYM2 0x4ab3 4534 #define mmDP0_DP_DPHY_SYM2 0x4ab3 4535 #define mmDP1_DP_DPHY_SYM2 0x4bb3 4536 #define mmDP2_DP_DPHY_SYM2 0x4cb3 4537 #define mmDP3_DP_DPHY_SYM2 0x4db3 4538 #define mmDP4_DP_DPHY_SYM2 0x4eb3 4539 #define mmDP5_DP_DPHY_SYM2 0x4fb3 4540 #define mmDP6_DP_DPHY_SYM2 0x54b3 4541 #define mmDP_DPHY_8B10B_CNTL 0x4ab4 4542 #define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 4543 #define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 4544 #define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 4545 #define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 4546 #define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 4547 #define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 4548 #define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 4549 #define mmDP_DPHY_PRBS_CNTL 0x4ab5 4550 #define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 4551 #define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 4552 #define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 4553 #define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 4554 #define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 4555 #define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 4556 #define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 4557 #define mmDP_DPHY_SCRAM_CNTL 0x4ab6 4558 #define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6 4559 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 4560 #define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6 4561 #define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6 4562 #define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6 4563 #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6 4564 #define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6 4565 #define mmDP_DPHY_CRC_EN 0x4ab7 4566 #define mmDP0_DP_DPHY_CRC_EN 0x4ab7 4567 #define mmDP1_DP_DPHY_CRC_EN 0x4bb7 4568 #define mmDP2_DP_DPHY_CRC_EN 0x4cb7 4569 #define mmDP3_DP_DPHY_CRC_EN 0x4db7 4570 #define mmDP4_DP_DPHY_CRC_EN 0x4eb7 4571 #define mmDP5_DP_DPHY_CRC_EN 0x4fb7 4572 #define mmDP6_DP_DPHY_CRC_EN 0x54b7 4573 #define mmDP_DPHY_CRC_CNTL 0x4ab8 4574 #define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 4575 #define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 4576 #define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 4577 #define mmDP3_DP_DPHY_CRC_CNTL 0x4db8 4578 #define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 4579 #define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 4580 #define mmDP6_DP_DPHY_CRC_CNTL 0x54b8 4581 #define mmDP_DPHY_CRC_RESULT 0x4ab9 4582 #define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 4583 #define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 4584 #define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 4585 #define mmDP3_DP_DPHY_CRC_RESULT 0x4db9 4586 #define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 4587 #define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 4588 #define mmDP6_DP_DPHY_CRC_RESULT 0x54b9 4589 #define mmDP_DPHY_CRC_MST_CNTL 0x4aba 4590 #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba 4591 #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba 4592 #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba 4593 #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba 4594 #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba 4595 #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba 4596 #define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba 4597 #define mmDP_DPHY_CRC_MST_STATUS 0x4abb 4598 #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb 4599 #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb 4600 #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb 4601 #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb 4602 #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb 4603 #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb 4604 #define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb 4605 #define mmDP_DPHY_FAST_TRAINING 0x4abc 4606 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc 4607 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc 4608 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc 4609 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc 4610 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc 4611 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc 4612 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc 4613 #define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd 4614 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd 4615 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd 4616 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd 4617 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd 4618 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd 4619 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd 4620 #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd 4621 #define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe 4622 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe 4623 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe 4624 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe 4625 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe 4626 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe 4627 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe 4628 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be 4629 #define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf 4630 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf 4631 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf 4632 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf 4633 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf 4634 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf 4635 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf 4636 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf 4637 #define mmDP_SEC_CNTL 0x4ac3 4638 #define mmDP0_DP_SEC_CNTL 0x4ac3 4639 #define mmDP1_DP_SEC_CNTL 0x4bc3 4640 #define mmDP2_DP_SEC_CNTL 0x4cc3 4641 #define mmDP3_DP_SEC_CNTL 0x4dc3 4642 #define mmDP4_DP_SEC_CNTL 0x4ec3 4643 #define mmDP5_DP_SEC_CNTL 0x4fc3 4644 #define mmDP6_DP_SEC_CNTL 0x54c3 4645 #define mmDP_SEC_CNTL1 0x4ac4 4646 #define mmDP0_DP_SEC_CNTL1 0x4ac4 4647 #define mmDP1_DP_SEC_CNTL1 0x4bc4 4648 #define mmDP2_DP_SEC_CNTL1 0x4cc4 4649 #define mmDP3_DP_SEC_CNTL1 0x4dc4 4650 #define mmDP4_DP_SEC_CNTL1 0x4ec4 4651 #define mmDP5_DP_SEC_CNTL1 0x4fc4 4652 #define mmDP6_DP_SEC_CNTL1 0x54c4 4653 #define mmDP_SEC_FRAMING1 0x4ac5 4654 #define mmDP0_DP_SEC_FRAMING1 0x4ac5 4655 #define mmDP1_DP_SEC_FRAMING1 0x4bc5 4656 #define mmDP2_DP_SEC_FRAMING1 0x4cc5 4657 #define mmDP3_DP_SEC_FRAMING1 0x4dc5 4658 #define mmDP4_DP_SEC_FRAMING1 0x4ec5 4659 #define mmDP5_DP_SEC_FRAMING1 0x4fc5 4660 #define mmDP6_DP_SEC_FRAMING1 0x54c5 4661 #define mmDP_SEC_FRAMING2 0x4ac6 4662 #define mmDP0_DP_SEC_FRAMING2 0x4ac6 4663 #define mmDP1_DP_SEC_FRAMING2 0x4bc6 4664 #define mmDP2_DP_SEC_FRAMING2 0x4cc6 4665 #define mmDP3_DP_SEC_FRAMING2 0x4dc6 4666 #define mmDP4_DP_SEC_FRAMING2 0x4ec6 4667 #define mmDP5_DP_SEC_FRAMING2 0x4fc6 4668 #define mmDP6_DP_SEC_FRAMING2 0x54c6 4669 #define mmDP_SEC_FRAMING3 0x4ac7 4670 #define mmDP0_DP_SEC_FRAMING3 0x4ac7 4671 #define mmDP1_DP_SEC_FRAMING3 0x4bc7 4672 #define mmDP2_DP_SEC_FRAMING3 0x4cc7 4673 #define mmDP3_DP_SEC_FRAMING3 0x4dc7 4674 #define mmDP4_DP_SEC_FRAMING3 0x4ec7 4675 #define mmDP5_DP_SEC_FRAMING3 0x4fc7 4676 #define mmDP6_DP_SEC_FRAMING3 0x54c7 4677 #define mmDP_SEC_FRAMING4 0x4ac8 4678 #define mmDP0_DP_SEC_FRAMING4 0x4ac8 4679 #define mmDP1_DP_SEC_FRAMING4 0x4bc8 4680 #define mmDP2_DP_SEC_FRAMING4 0x4cc8 4681 #define mmDP3_DP_SEC_FRAMING4 0x4dc8 4682 #define mmDP4_DP_SEC_FRAMING4 0x4ec8 4683 #define mmDP5_DP_SEC_FRAMING4 0x4fc8 4684 #define mmDP6_DP_SEC_FRAMING4 0x54c8 4685 #define mmDP_SEC_AUD_N 0x4ac9 4686 #define mmDP0_DP_SEC_AUD_N 0x4ac9 4687 #define mmDP1_DP_SEC_AUD_N 0x4bc9 4688 #define mmDP2_DP_SEC_AUD_N 0x4cc9 4689 #define mmDP3_DP_SEC_AUD_N 0x4dc9 4690 #define mmDP4_DP_SEC_AUD_N 0x4ec9 4691 #define mmDP5_DP_SEC_AUD_N 0x4fc9 4692 #define mmDP6_DP_SEC_AUD_N 0x54c9 4693 #define mmDP_SEC_AUD_N_READBACK 0x4aca 4694 #define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca 4695 #define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca 4696 #define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca 4697 #define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca 4698 #define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca 4699 #define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca 4700 #define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca 4701 #define mmDP_SEC_AUD_M 0x4acb 4702 #define mmDP0_DP_SEC_AUD_M 0x4acb 4703 #define mmDP1_DP_SEC_AUD_M 0x4bcb 4704 #define mmDP2_DP_SEC_AUD_M 0x4ccb 4705 #define mmDP3_DP_SEC_AUD_M 0x4dcb 4706 #define mmDP4_DP_SEC_AUD_M 0x4ecb 4707 #define mmDP5_DP_SEC_AUD_M 0x4fcb 4708 #define mmDP6_DP_SEC_AUD_M 0x54cb 4709 #define mmDP_SEC_AUD_M_READBACK 0x4acc 4710 #define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc 4711 #define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc 4712 #define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc 4713 #define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc 4714 #define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc 4715 #define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc 4716 #define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc 4717 #define mmDP_SEC_TIMESTAMP 0x4acd 4718 #define mmDP0_DP_SEC_TIMESTAMP 0x4acd 4719 #define mmDP1_DP_SEC_TIMESTAMP 0x4bcd 4720 #define mmDP2_DP_SEC_TIMESTAMP 0x4ccd 4721 #define mmDP3_DP_SEC_TIMESTAMP 0x4dcd 4722 #define mmDP4_DP_SEC_TIMESTAMP 0x4ecd 4723 #define mmDP5_DP_SEC_TIMESTAMP 0x4fcd 4724 #define mmDP6_DP_SEC_TIMESTAMP 0x54cd 4725 #define mmDP_SEC_PACKET_CNTL 0x4ace 4726 #define mmDP0_DP_SEC_PACKET_CNTL 0x4ace 4727 #define mmDP1_DP_SEC_PACKET_CNTL 0x4bce 4728 #define mmDP2_DP_SEC_PACKET_CNTL 0x4cce 4729 #define mmDP3_DP_SEC_PACKET_CNTL 0x4dce 4730 #define mmDP4_DP_SEC_PACKET_CNTL 0x4ece 4731 #define mmDP5_DP_SEC_PACKET_CNTL 0x4fce 4732 #define mmDP6_DP_SEC_PACKET_CNTL 0x54ce 4733 #define mmDP_MSE_RATE_CNTL 0x4acf 4734 #define mmDP0_DP_MSE_RATE_CNTL 0x4acf 4735 #define mmDP1_DP_MSE_RATE_CNTL 0x4bcf 4736 #define mmDP2_DP_MSE_RATE_CNTL 0x4ccf 4737 #define mmDP3_DP_MSE_RATE_CNTL 0x4dcf 4738 #define mmDP4_DP_MSE_RATE_CNTL 0x4ecf 4739 #define mmDP5_DP_MSE_RATE_CNTL 0x4fcf 4740 #define mmDP6_DP_MSE_RATE_CNTL 0x54cf 4741 #define mmDP_MSE_RATE_UPDATE 0x4ad1 4742 #define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 4743 #define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 4744 #define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 4745 #define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 4746 #define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 4747 #define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 4748 #define mmDP6_DP_MSE_RATE_UPDATE 0x54d1 4749 #define mmDP_MSE_SAT0 0x4ad2 4750 #define mmDP0_DP_MSE_SAT0 0x4ad2 4751 #define mmDP1_DP_MSE_SAT0 0x4bd2 4752 #define mmDP2_DP_MSE_SAT0 0x4cd2 4753 #define mmDP3_DP_MSE_SAT0 0x4dd2 4754 #define mmDP4_DP_MSE_SAT0 0x4ed2 4755 #define mmDP5_DP_MSE_SAT0 0x4fd2 4756 #define mmDP6_DP_MSE_SAT0 0x54d2 4757 #define mmDP_MSE_SAT1 0x4ad3 4758 #define mmDP0_DP_MSE_SAT1 0x4ad3 4759 #define mmDP1_DP_MSE_SAT1 0x4bd3 4760 #define mmDP2_DP_MSE_SAT1 0x4cd3 4761 #define mmDP3_DP_MSE_SAT1 0x4dd3 4762 #define mmDP4_DP_MSE_SAT1 0x4ed3 4763 #define mmDP5_DP_MSE_SAT1 0x4fd3 4764 #define mmDP6_DP_MSE_SAT1 0x54d3 4765 #define mmDP_MSE_SAT2 0x4ad4 4766 #define mmDP0_DP_MSE_SAT2 0x4ad4 4767 #define mmDP1_DP_MSE_SAT2 0x4bd4 4768 #define mmDP2_DP_MSE_SAT2 0x4cd4 4769 #define mmDP3_DP_MSE_SAT2 0x4dd4 4770 #define mmDP4_DP_MSE_SAT2 0x4ed4 4771 #define mmDP5_DP_MSE_SAT2 0x4fd4 4772 #define mmDP6_DP_MSE_SAT2 0x54d4 4773 #define mmDP_MSE_SAT_UPDATE 0x4ad5 4774 #define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 4775 #define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 4776 #define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 4777 #define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 4778 #define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 4779 #define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 4780 #define mmDP6_DP_MSE_SAT_UPDATE 0x54d5 4781 #define mmDP_MSE_LINK_TIMING 0x4ad6 4782 #define mmDP0_DP_MSE_LINK_TIMING 0x4ad6 4783 #define mmDP1_DP_MSE_LINK_TIMING 0x4bd6 4784 #define mmDP2_DP_MSE_LINK_TIMING 0x4cd6 4785 #define mmDP3_DP_MSE_LINK_TIMING 0x4dd6 4786 #define mmDP4_DP_MSE_LINK_TIMING 0x4ed6 4787 #define mmDP5_DP_MSE_LINK_TIMING 0x4fd6 4788 #define mmDP6_DP_MSE_LINK_TIMING 0x54d6 4789 #define mmDP_MSE_MISC_CNTL 0x4ad7 4790 #define mmDP0_DP_MSE_MISC_CNTL 0x4ad7 4791 #define mmDP1_DP_MSE_MISC_CNTL 0x4bd7 4792 #define mmDP2_DP_MSE_MISC_CNTL 0x4cd7 4793 #define mmDP3_DP_MSE_MISC_CNTL 0x4dd7 4794 #define mmDP4_DP_MSE_MISC_CNTL 0x4ed7 4795 #define mmDP5_DP_MSE_MISC_CNTL 0x4fd7 4796 #define mmDP6_DP_MSE_MISC_CNTL 0x54d7 4797 #define mmDP_TEST_DEBUG_INDEX 0x4ad8 4798 #define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 4799 #define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 4800 #define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 4801 #define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 4802 #define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 4803 #define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 4804 #define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 4805 #define mmDP_TEST_DEBUG_DATA 0x4ad9 4806 #define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 4807 #define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 4808 #define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 4809 #define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 4810 #define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 4811 #define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 4812 #define mmDP6_DP_TEST_DEBUG_DATA 0x54d9 4813 #define mmDP_FE_TEST_DEBUG_INDEX 0x4ada 4814 #define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada 4815 #define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda 4816 #define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda 4817 #define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda 4818 #define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda 4819 #define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda 4820 #define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da 4821 #define mmDP_FE_TEST_DEBUG_DATA 0x4adb 4822 #define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb 4823 #define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb 4824 #define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb 4825 #define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb 4826 #define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb 4827 #define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb 4828 #define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db 4829 #define mmAUX_CONTROL 0x5c00 4830 #define mmDP_AUX0_AUX_CONTROL 0x5c00 4831 #define mmDP_AUX1_AUX_CONTROL 0x5c1c 4832 #define mmDP_AUX2_AUX_CONTROL 0x5c38 4833 #define mmDP_AUX3_AUX_CONTROL 0x5c54 4834 #define mmDP_AUX4_AUX_CONTROL 0x5c70 4835 #define mmDP_AUX5_AUX_CONTROL 0x5c8c 4836 #define mmAUX_SW_CONTROL 0x5c01 4837 #define mmDP_AUX0_AUX_SW_CONTROL 0x5c01 4838 #define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d 4839 #define mmDP_AUX2_AUX_SW_CONTROL 0x5c39 4840 #define mmDP_AUX3_AUX_SW_CONTROL 0x5c55 4841 #define mmDP_AUX4_AUX_SW_CONTROL 0x5c71 4842 #define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d 4843 #define mmAUX_ARB_CONTROL 0x5c02 4844 #define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 4845 #define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e 4846 #define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a 4847 #define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 4848 #define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 4849 #define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e 4850 #define mmAUX_INTERRUPT_CONTROL 0x5c03 4851 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 4852 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f 4853 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b 4854 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 4855 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 4856 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f 4857 #define mmAUX_SW_STATUS 0x5c04 4858 #define mmDP_AUX0_AUX_SW_STATUS 0x5c04 4859 #define mmDP_AUX1_AUX_SW_STATUS 0x5c20 4860 #define mmDP_AUX2_AUX_SW_STATUS 0x5c3c 4861 #define mmDP_AUX3_AUX_SW_STATUS 0x5c58 4862 #define mmDP_AUX4_AUX_SW_STATUS 0x5c74 4863 #define mmDP_AUX5_AUX_SW_STATUS 0x5c90 4864 #define mmAUX_LS_STATUS 0x5c05 4865 #define mmDP_AUX0_AUX_LS_STATUS 0x5c05 4866 #define mmDP_AUX1_AUX_LS_STATUS 0x5c21 4867 #define mmDP_AUX2_AUX_LS_STATUS 0x5c3d 4868 #define mmDP_AUX3_AUX_LS_STATUS 0x5c59 4869 #define mmDP_AUX4_AUX_LS_STATUS 0x5c75 4870 #define mmDP_AUX5_AUX_LS_STATUS 0x5c91 4871 #define mmAUX_SW_DATA 0x5c06 4872 #define mmDP_AUX0_AUX_SW_DATA 0x5c06 4873 #define mmDP_AUX1_AUX_SW_DATA 0x5c22 4874 #define mmDP_AUX2_AUX_SW_DATA 0x5c3e 4875 #define mmDP_AUX3_AUX_SW_DATA 0x5c5a 4876 #define mmDP_AUX4_AUX_SW_DATA 0x5c76 4877 #define mmDP_AUX5_AUX_SW_DATA 0x5c92 4878 #define mmAUX_LS_DATA 0x5c07 4879 #define mmDP_AUX0_AUX_LS_DATA 0x5c07 4880 #define mmDP_AUX1_AUX_LS_DATA 0x5c23 4881 #define mmDP_AUX2_AUX_LS_DATA 0x5c3f 4882 #define mmDP_AUX3_AUX_LS_DATA 0x5c5b 4883 #define mmDP_AUX4_AUX_LS_DATA 0x5c77 4884 #define mmDP_AUX5_AUX_LS_DATA 0x5c93 4885 #define mmAUX_DPHY_TX_REF_CONTROL 0x5c08 4886 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 4887 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 4888 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 4889 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c 4890 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 4891 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 4892 #define mmAUX_DPHY_TX_CONTROL 0x5c09 4893 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 4894 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 4895 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 4896 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d 4897 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 4898 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 4899 #define mmAUX_DPHY_RX_CONTROL0 0x5c0a 4900 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a 4901 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 4902 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 4903 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e 4904 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a 4905 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 4906 #define mmAUX_DPHY_RX_CONTROL1 0x5c0b 4907 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b 4908 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 4909 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 4910 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f 4911 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b 4912 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 4913 #define mmAUX_DPHY_TX_STATUS 0x5c0c 4914 #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c 4915 #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 4916 #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 4917 #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 4918 #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c 4919 #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 4920 #define mmAUX_DPHY_RX_STATUS 0x5c0d 4921 #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d 4922 #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 4923 #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 4924 #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 4925 #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d 4926 #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 4927 #define mmAUX_GTC_SYNC_CONTROL 0x5c0e 4928 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e 4929 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a 4930 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46 4931 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62 4932 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e 4933 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a 4934 #define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f 4935 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f 4936 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b 4937 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 4938 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 4939 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f 4940 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b 4941 #define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 4942 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 4943 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c 4944 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 4945 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 4946 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 4947 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c 4948 #define mmAUX_GTC_SYNC_STATUS 0x5c11 4949 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 4950 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d 4951 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 4952 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 4953 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 4954 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d 4955 #define mmAUX_GTC_SYNC_DATA 0x5c12 4956 #define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12 4957 #define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e 4958 #define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a 4959 #define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66 4960 #define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82 4961 #define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e 4962 #define mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 4963 #define mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13 4964 #define mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f 4965 #define mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b 4966 #define mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67 4967 #define mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83 4968 #define mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f 4969 #define mmAUX_TEST_DEBUG_INDEX 0x5c14 4970 #define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 4971 #define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 4972 #define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c 4973 #define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 4974 #define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 4975 #define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 4976 #define mmAUX_TEST_DEBUG_DATA 0x5c15 4977 #define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 4978 #define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 4979 #define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d 4980 #define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 4981 #define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 4982 #define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 4983 #define ixDP_AUX_DEBUG_A 0x10 4984 #define ixDP_AUX_DEBUG_B 0x11 4985 #define ixDP_AUX_DEBUG_C 0x12 4986 #define ixDP_AUX_DEBUG_D 0x13 4987 #define ixDP_AUX_DEBUG_E 0x14 4988 #define ixDP_AUX_DEBUG_F 0x15 4989 #define ixDP_AUX_DEBUG_G 0x16 4990 #define ixDP_AUX_DEBUG_H 0x17 4991 #define ixDP_AUX_DEBUG_I 0x18 4992 #define ixDP_AUX_DEBUG_J 0x19 4993 #define ixDP_AUX_DEBUG_K 0x1a 4994 #define ixDP_AUX_DEBUG_L 0x1b 4995 #define ixDP_AUX_DEBUG_M 0x1c 4996 #define ixDP_AUX_DEBUG_N 0x1d 4997 #define ixDP_AUX_DEBUG_O 0x1e 4998 #define ixDP_AUX_DEBUG_P 0x1f 4999 #define ixDP_AUX_DEBUG_Q 0x20 5000 #define mmDVO_ENABLE 0x16a0 5001 #define mmDVO_SOURCE_SELECT 0x16a1 5002 #define mmDVO_OUTPUT 0x16a2 5003 #define mmDVO_CONTROL 0x16a3 5004 #define mmDVO_CRC_EN 0x16a4 5005 #define mmDVO_CRC2_SIG_MASK 0x16a5 5006 #define mmDVO_CRC2_SIG_RESULT 0x16a6 5007 #define mmDVO_FIFO_ERROR_STATUS 0x16a7 5008 #define mmDVO_TEST_DEBUG_INDEX 0x16a8 5009 #define mmDVO_TEST_DEBUG_DATA 0x16a9 5010 #define mmFBC_CNTL 0x280 5011 #define mmFBC_IDLE_MASK 0x281 5012 #define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 5013 #define mmFBC_START_STOP_DELAY 0x283 5014 #define mmFBC_COMP_CNTL 0x284 5015 #define mmFBC_COMP_MODE 0x285 5016 #define mmFBC_DEBUG0 0x286 5017 #define mmFBC_DEBUG1 0x287 5018 #define mmFBC_DEBUG2 0x288 5019 #define mmFBC_IND_LUT0 0x289 5020 #define mmFBC_IND_LUT1 0x28a 5021 #define mmFBC_IND_LUT2 0x28b 5022 #define mmFBC_IND_LUT3 0x28c 5023 #define mmFBC_IND_LUT4 0x28d 5024 #define mmFBC_IND_LUT5 0x28e 5025 #define mmFBC_IND_LUT6 0x28f 5026 #define mmFBC_IND_LUT7 0x290 5027 #define mmFBC_IND_LUT8 0x291 5028 #define mmFBC_IND_LUT9 0x292 5029 #define mmFBC_IND_LUT10 0x293 5030 #define mmFBC_IND_LUT11 0x294 5031 #define mmFBC_IND_LUT12 0x295 5032 #define mmFBC_IND_LUT13 0x296 5033 #define mmFBC_IND_LUT14 0x297 5034 #define mmFBC_IND_LUT15 0x298 5035 #define mmFBC_CSM_REGION_OFFSET_01 0x299 5036 #define mmFBC_CSM_REGION_OFFSET_23 0x29a 5037 #define mmFBC_CLIENT_REGION_MASK 0x29b 5038 #define mmFBC_DEBUG_COMP 0x29c 5039 #define mmFBC_DEBUG_CSR 0x29d 5040 #define mmFBC_DEBUG_CSR_RDATA 0x29e 5041 #define mmFBC_DEBUG_CSR_WDATA 0x29f 5042 #define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 5043 #define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 5044 #define mmFBC_MISC 0x2a2 5045 #define mmFBC_STATUS 0x2a3 5046 #define mmFBC_TEST_DEBUG_INDEX 0x2a4 5047 #define mmFBC_TEST_DEBUG_DATA 0x2a5 5048 #define mmFMT_CLAMP_COMPONENT_R 0x1be8 5049 #define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 5050 #define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 5051 #define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 5052 #define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 5053 #define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 5054 #define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 5055 #define mmFMT_CLAMP_COMPONENT_G 0x1be9 5056 #define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 5057 #define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 5058 #define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 5059 #define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 5060 #define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 5061 #define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 5062 #define mmFMT_CLAMP_COMPONENT_B 0x1bea 5063 #define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea 5064 #define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea 5065 #define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea 5066 #define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea 5067 #define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea 5068 #define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea 5069 #define mmFMT_DYNAMIC_EXP_CNTL 0x1bed 5070 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed 5071 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded 5072 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed 5073 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed 5074 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed 5075 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed 5076 #define mmFMT_CONTROL 0x1bee 5077 #define mmFMT0_FMT_CONTROL 0x1bee 5078 #define mmFMT1_FMT_CONTROL 0x1dee 5079 #define mmFMT2_FMT_CONTROL 0x1fee 5080 #define mmFMT3_FMT_CONTROL 0x41ee 5081 #define mmFMT4_FMT_CONTROL 0x43ee 5082 #define mmFMT5_FMT_CONTROL 0x45ee 5083 #define mmFMT_FORCE_OUTPUT_CNTL 0x1bef 5084 #define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1bef 5085 #define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1def 5086 #define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x1fef 5087 #define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x41ef 5088 #define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x43ef 5089 #define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x45ef 5090 #define mmFMT_FORCE_DATA_0_1 0x1bf0 5091 #define mmFMT0_FMT_FORCE_DATA_0_1 0x1bf0 5092 #define mmFMT1_FMT_FORCE_DATA_0_1 0x1df0 5093 #define mmFMT2_FMT_FORCE_DATA_0_1 0x1ff0 5094 #define mmFMT3_FMT_FORCE_DATA_0_1 0x41f0 5095 #define mmFMT4_FMT_FORCE_DATA_0_1 0x43f0 5096 #define mmFMT5_FMT_FORCE_DATA_0_1 0x45f0 5097 #define mmFMT_FORCE_DATA_2_3 0x1bf1 5098 #define mmFMT0_FMT_FORCE_DATA_2_3 0x1bf1 5099 #define mmFMT1_FMT_FORCE_DATA_2_3 0x1df1 5100 #define mmFMT2_FMT_FORCE_DATA_2_3 0x1ff1 5101 #define mmFMT3_FMT_FORCE_DATA_2_3 0x41f1 5102 #define mmFMT4_FMT_FORCE_DATA_2_3 0x43f1 5103 #define mmFMT5_FMT_FORCE_DATA_2_3 0x45f1 5104 #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 5105 #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 5106 #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 5107 #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 5108 #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 5109 #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 5110 #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 5111 #define mmFMT_DITHER_RAND_R_SEED 0x1bf3 5112 #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 5113 #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 5114 #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 5115 #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 5116 #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 5117 #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 5118 #define mmFMT_DITHER_RAND_G_SEED 0x1bf4 5119 #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 5120 #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 5121 #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 5122 #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 5123 #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 5124 #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 5125 #define mmFMT_DITHER_RAND_B_SEED 0x1bf5 5126 #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 5127 #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 5128 #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 5129 #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 5130 #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 5131 #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 5132 #define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 5133 #define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 5134 #define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 5135 #define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 5136 #define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 5137 #define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 5138 #define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 5139 #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 5140 #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 5141 #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 5142 #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 5143 #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 5144 #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 5145 #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 5146 #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 5147 #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 5148 #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 5149 #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 5150 #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 5151 #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 5152 #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 5153 #define mmFMT_CLAMP_CNTL 0x1bf9 5154 #define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 5155 #define mmFMT1_FMT_CLAMP_CNTL 0x1df9 5156 #define mmFMT2_FMT_CLAMP_CNTL 0x1ff9 5157 #define mmFMT3_FMT_CLAMP_CNTL 0x41f9 5158 #define mmFMT4_FMT_CLAMP_CNTL 0x43f9 5159 #define mmFMT5_FMT_CLAMP_CNTL 0x45f9 5160 #define mmFMT_CRC_CNTL 0x1bfa 5161 #define mmFMT0_FMT_CRC_CNTL 0x1bfa 5162 #define mmFMT1_FMT_CRC_CNTL 0x1dfa 5163 #define mmFMT2_FMT_CRC_CNTL 0x1ffa 5164 #define mmFMT3_FMT_CRC_CNTL 0x41fa 5165 #define mmFMT4_FMT_CRC_CNTL 0x43fa 5166 #define mmFMT5_FMT_CRC_CNTL 0x45fa 5167 #define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb 5168 #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb 5169 #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb 5170 #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb 5171 #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb 5172 #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb 5173 #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb 5174 #define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc 5175 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc 5176 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc 5177 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc 5178 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc 5179 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc 5180 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc 5181 #define mmFMT_CRC_SIG_RED_GREEN 0x1bfd 5182 #define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd 5183 #define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd 5184 #define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd 5185 #define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd 5186 #define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd 5187 #define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd 5188 #define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe 5189 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe 5190 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe 5191 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe 5192 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe 5193 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe 5194 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe 5195 #define mmFMT_DEBUG_CNTL 0x1bff 5196 #define mmFMT0_FMT_DEBUG_CNTL 0x1bff 5197 #define mmFMT1_FMT_DEBUG_CNTL 0x1dff 5198 #define mmFMT2_FMT_DEBUG_CNTL 0x1fff 5199 #define mmFMT3_FMT_DEBUG_CNTL 0x41ff 5200 #define mmFMT4_FMT_DEBUG_CNTL 0x43ff 5201 #define mmFMT5_FMT_DEBUG_CNTL 0x45ff 5202 #define mmFMT_TEST_DEBUG_INDEX 0x1beb 5203 #define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb 5204 #define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb 5205 #define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb 5206 #define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb 5207 #define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb 5208 #define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb 5209 #define mmFMT_TEST_DEBUG_DATA 0x1bec 5210 #define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec 5211 #define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec 5212 #define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec 5213 #define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec 5214 #define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec 5215 #define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec 5216 #define ixFMT_DEBUG0 0x1 5217 #define ixFMT_DEBUG1 0x2 5218 #define ixFMT_DEBUG2 0x3 5219 #define ixFMT_DEBUG_ID 0x0 5220 #define mmLB_DATA_FORMAT 0x1ac0 5221 #define mmLB0_LB_DATA_FORMAT 0x1ac0 5222 #define mmLB1_LB_DATA_FORMAT 0x1cc0 5223 #define mmLB2_LB_DATA_FORMAT 0x1ec0 5224 #define mmLB3_LB_DATA_FORMAT 0x40c0 5225 #define mmLB4_LB_DATA_FORMAT 0x42c0 5226 #define mmLB5_LB_DATA_FORMAT 0x44c0 5227 #define mmLB_MEMORY_CTRL 0x1ac1 5228 #define mmLB0_LB_MEMORY_CTRL 0x1ac1 5229 #define mmLB1_LB_MEMORY_CTRL 0x1cc1 5230 #define mmLB2_LB_MEMORY_CTRL 0x1ec1 5231 #define mmLB3_LB_MEMORY_CTRL 0x40c1 5232 #define mmLB4_LB_MEMORY_CTRL 0x42c1 5233 #define mmLB5_LB_MEMORY_CTRL 0x44c1 5234 #define mmLB_MEMORY_SIZE_STATUS 0x1ac2 5235 #define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 5236 #define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 5237 #define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 5238 #define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 5239 #define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 5240 #define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 5241 #define mmLB_DESKTOP_HEIGHT 0x1ac3 5242 #define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 5243 #define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 5244 #define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 5245 #define mmLB3_LB_DESKTOP_HEIGHT 0x40c3 5246 #define mmLB4_LB_DESKTOP_HEIGHT 0x42c3 5247 #define mmLB5_LB_DESKTOP_HEIGHT 0x44c3 5248 #define mmLB_VLINE_START_END 0x1ac4 5249 #define mmLB0_LB_VLINE_START_END 0x1ac4 5250 #define mmLB1_LB_VLINE_START_END 0x1cc4 5251 #define mmLB2_LB_VLINE_START_END 0x1ec4 5252 #define mmLB3_LB_VLINE_START_END 0x40c4 5253 #define mmLB4_LB_VLINE_START_END 0x42c4 5254 #define mmLB5_LB_VLINE_START_END 0x44c4 5255 #define mmLB_VLINE2_START_END 0x1ac5 5256 #define mmLB0_LB_VLINE2_START_END 0x1ac5 5257 #define mmLB1_LB_VLINE2_START_END 0x1cc5 5258 #define mmLB2_LB_VLINE2_START_END 0x1ec5 5259 #define mmLB3_LB_VLINE2_START_END 0x40c5 5260 #define mmLB4_LB_VLINE2_START_END 0x42c5 5261 #define mmLB5_LB_VLINE2_START_END 0x44c5 5262 #define mmLB_V_COUNTER 0x1ac6 5263 #define mmLB0_LB_V_COUNTER 0x1ac6 5264 #define mmLB1_LB_V_COUNTER 0x1cc6 5265 #define mmLB2_LB_V_COUNTER 0x1ec6 5266 #define mmLB3_LB_V_COUNTER 0x40c6 5267 #define mmLB4_LB_V_COUNTER 0x42c6 5268 #define mmLB5_LB_V_COUNTER 0x44c6 5269 #define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 5270 #define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 5271 #define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 5272 #define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 5273 #define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 5274 #define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 5275 #define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 5276 #define mmLB_INTERRUPT_MASK 0x1ac8 5277 #define mmLB0_LB_INTERRUPT_MASK 0x1ac8 5278 #define mmLB1_LB_INTERRUPT_MASK 0x1cc8 5279 #define mmLB2_LB_INTERRUPT_MASK 0x1ec8 5280 #define mmLB3_LB_INTERRUPT_MASK 0x40c8 5281 #define mmLB4_LB_INTERRUPT_MASK 0x42c8 5282 #define mmLB5_LB_INTERRUPT_MASK 0x44c8 5283 #define mmLB_VLINE_STATUS 0x1ac9 5284 #define mmLB0_LB_VLINE_STATUS 0x1ac9 5285 #define mmLB1_LB_VLINE_STATUS 0x1cc9 5286 #define mmLB2_LB_VLINE_STATUS 0x1ec9 5287 #define mmLB3_LB_VLINE_STATUS 0x40c9 5288 #define mmLB4_LB_VLINE_STATUS 0x42c9 5289 #define mmLB5_LB_VLINE_STATUS 0x44c9 5290 #define mmLB_VLINE2_STATUS 0x1aca 5291 #define mmLB0_LB_VLINE2_STATUS 0x1aca 5292 #define mmLB1_LB_VLINE2_STATUS 0x1cca 5293 #define mmLB2_LB_VLINE2_STATUS 0x1eca 5294 #define mmLB3_LB_VLINE2_STATUS 0x40ca 5295 #define mmLB4_LB_VLINE2_STATUS 0x42ca 5296 #define mmLB5_LB_VLINE2_STATUS 0x44ca 5297 #define mmLB_VBLANK_STATUS 0x1acb 5298 #define mmLB0_LB_VBLANK_STATUS 0x1acb 5299 #define mmLB1_LB_VBLANK_STATUS 0x1ccb 5300 #define mmLB2_LB_VBLANK_STATUS 0x1ecb 5301 #define mmLB3_LB_VBLANK_STATUS 0x40cb 5302 #define mmLB4_LB_VBLANK_STATUS 0x42cb 5303 #define mmLB5_LB_VBLANK_STATUS 0x44cb 5304 #define mmLB_SYNC_RESET_SEL 0x1acc 5305 #define mmLB0_LB_SYNC_RESET_SEL 0x1acc 5306 #define mmLB1_LB_SYNC_RESET_SEL 0x1ccc 5307 #define mmLB2_LB_SYNC_RESET_SEL 0x1ecc 5308 #define mmLB3_LB_SYNC_RESET_SEL 0x40cc 5309 #define mmLB4_LB_SYNC_RESET_SEL 0x42cc 5310 #define mmLB5_LB_SYNC_RESET_SEL 0x44cc 5311 #define mmLB_BLACK_KEYER_R_CR 0x1acd 5312 #define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd 5313 #define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd 5314 #define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd 5315 #define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd 5316 #define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd 5317 #define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd 5318 #define mmLB_BLACK_KEYER_G_Y 0x1ace 5319 #define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace 5320 #define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce 5321 #define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece 5322 #define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce 5323 #define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce 5324 #define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce 5325 #define mmLB_BLACK_KEYER_B_CB 0x1acf 5326 #define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf 5327 #define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf 5328 #define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf 5329 #define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf 5330 #define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf 5331 #define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf 5332 #define mmLB_KEYER_COLOR_CTRL 0x1ad0 5333 #define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 5334 #define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 5335 #define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 5336 #define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 5337 #define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 5338 #define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 5339 #define mmLB_KEYER_COLOR_R_CR 0x1ad1 5340 #define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 5341 #define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 5342 #define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 5343 #define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 5344 #define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 5345 #define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 5346 #define mmLB_KEYER_COLOR_G_Y 0x1ad2 5347 #define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 5348 #define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 5349 #define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 5350 #define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 5351 #define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 5352 #define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 5353 #define mmLB_KEYER_COLOR_B_CB 0x1ad3 5354 #define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 5355 #define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 5356 #define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 5357 #define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 5358 #define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 5359 #define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 5360 #define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 5361 #define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 5362 #define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 5363 #define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 5364 #define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 5365 #define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 5366 #define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 5367 #define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 5368 #define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 5369 #define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 5370 #define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 5371 #define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 5372 #define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 5373 #define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 5374 #define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 5375 #define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 5376 #define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 5377 #define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 5378 #define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 5379 #define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 5380 #define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 5381 #define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 5382 #define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 5383 #define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 5384 #define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 5385 #define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 5386 #define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 5387 #define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 5388 #define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 5389 #define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 5390 #define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 5391 #define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 5392 #define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 5393 #define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 5394 #define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 5395 #define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 5396 #define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 5397 #define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 5398 #define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 5399 #define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 5400 #define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 5401 #define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 5402 #define mmLB_BUFFER_STATUS 0x1ada 5403 #define mmLB0_LB_BUFFER_STATUS 0x1ada 5404 #define mmLB1_LB_BUFFER_STATUS 0x1cda 5405 #define mmLB2_LB_BUFFER_STATUS 0x1eda 5406 #define mmLB3_LB_BUFFER_STATUS 0x40da 5407 #define mmLB4_LB_BUFFER_STATUS 0x42da 5408 #define mmLB5_LB_BUFFER_STATUS 0x44da 5409 #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc 5410 #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc 5411 #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc 5412 #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc 5413 #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc 5414 #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc 5415 #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc 5416 #define mmMVP_AFR_FLIP_MODE 0x1ae0 5417 #define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 5418 #define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 5419 #define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 5420 #define mmLB3_MVP_AFR_FLIP_MODE 0x40e0 5421 #define mmLB4_MVP_AFR_FLIP_MODE 0x42e0 5422 #define mmLB5_MVP_AFR_FLIP_MODE 0x44e0 5423 #define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 5424 #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 5425 #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 5426 #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 5427 #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 5428 #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 5429 #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 5430 #define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 5431 #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 5432 #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 5433 #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 5434 #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 5435 #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 5436 #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 5437 #define mmDC_MVP_LB_CONTROL 0x1ae3 5438 #define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 5439 #define mmLB1_DC_MVP_LB_CONTROL 0x1ce3 5440 #define mmLB2_DC_MVP_LB_CONTROL 0x1ee3 5441 #define mmLB3_DC_MVP_LB_CONTROL 0x40e3 5442 #define mmLB4_DC_MVP_LB_CONTROL 0x42e3 5443 #define mmLB5_DC_MVP_LB_CONTROL 0x44e3 5444 #define mmLB_DEBUG 0x1ae4 5445 #define mmLB0_LB_DEBUG 0x1ae4 5446 #define mmLB1_LB_DEBUG 0x1ce4 5447 #define mmLB2_LB_DEBUG 0x1ee4 5448 #define mmLB3_LB_DEBUG 0x40e4 5449 #define mmLB4_LB_DEBUG 0x42e4 5450 #define mmLB5_LB_DEBUG 0x44e4 5451 #define mmLB_DEBUG2 0x1ae5 5452 #define mmLB0_LB_DEBUG2 0x1ae5 5453 #define mmLB1_LB_DEBUG2 0x1ce5 5454 #define mmLB2_LB_DEBUG2 0x1ee5 5455 #define mmLB3_LB_DEBUG2 0x40e5 5456 #define mmLB4_LB_DEBUG2 0x42e5 5457 #define mmLB5_LB_DEBUG2 0x44e5 5458 #define mmLB_DEBUG3 0x1ae6 5459 #define mmLB0_LB_DEBUG3 0x1ae6 5460 #define mmLB1_LB_DEBUG3 0x1ce6 5461 #define mmLB2_LB_DEBUG3 0x1ee6 5462 #define mmLB3_LB_DEBUG3 0x40e6 5463 #define mmLB4_LB_DEBUG3 0x42e6 5464 #define mmLB5_LB_DEBUG3 0x44e6 5465 #define mmLB_TEST_DEBUG_INDEX 0x1afe 5466 #define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe 5467 #define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe 5468 #define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe 5469 #define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe 5470 #define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe 5471 #define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe 5472 #define mmLB_TEST_DEBUG_DATA 0x1aff 5473 #define mmLB0_LB_TEST_DEBUG_DATA 0x1aff 5474 #define mmLB1_LB_TEST_DEBUG_DATA 0x1cff 5475 #define mmLB2_LB_TEST_DEBUG_DATA 0x1eff 5476 #define mmLB3_LB_TEST_DEBUG_DATA 0x40ff 5477 #define mmLB4_LB_TEST_DEBUG_DATA 0x42ff 5478 #define mmLB5_LB_TEST_DEBUG_DATA 0x44ff 5479 #define mmLBV_DATA_FORMAT 0x463c 5480 #define mmLBV_MEMORY_CTRL 0x463d 5481 #define mmLBV_MEMORY_SIZE_STATUS 0x463e 5482 #define mmLBV_DESKTOP_HEIGHT 0x463f 5483 #define mmLBV_VLINE_START_END 0x4640 5484 #define mmLBV_VLINE2_START_END 0x4641 5485 #define mmLBV_V_COUNTER 0x4642 5486 #define mmLBV_SNAPSHOT_V_COUNTER 0x4643 5487 #define mmLBV_V_COUNTER_CHROMA 0x4644 5488 #define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 5489 #define mmLBV_INTERRUPT_MASK 0x4646 5490 #define mmLBV_VLINE_STATUS 0x4647 5491 #define mmLBV_VLINE2_STATUS 0x4648 5492 #define mmLBV_VBLANK_STATUS 0x4649 5493 #define mmLBV_SYNC_RESET_SEL 0x464a 5494 #define mmLBV_BLACK_KEYER_R_CR 0x464b 5495 #define mmLBV_BLACK_KEYER_G_Y 0x464c 5496 #define mmLBV_BLACK_KEYER_B_CB 0x464d 5497 #define mmLBV_KEYER_COLOR_CTRL 0x464e 5498 #define mmLBV_KEYER_COLOR_R_CR 0x464f 5499 #define mmLBV_KEYER_COLOR_G_Y 0x4650 5500 #define mmLBV_KEYER_COLOR_B_CB 0x4651 5501 #define mmLBV_KEYER_COLOR_REP_R_CR 0x4652 5502 #define mmLBV_KEYER_COLOR_REP_G_Y 0x4653 5503 #define mmLBV_KEYER_COLOR_REP_B_CB 0x4654 5504 #define mmLBV_BUFFER_LEVEL_STATUS 0x4655 5505 #define mmLBV_BUFFER_URGENCY_CTRL 0x4656 5506 #define mmLBV_BUFFER_URGENCY_STATUS 0x4657 5507 #define mmLBV_BUFFER_STATUS 0x4658 5508 #define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 5509 #define mmLBV_DEBUG 0x465a 5510 #define mmLBV_DEBUG2 0x465b 5511 #define mmLBV_DEBUG3 0x465c 5512 #define mmLBV_TEST_DEBUG_INDEX 0x4666 5513 #define mmLBV_TEST_DEBUG_DATA 0x4667 5514 #define mmMVP_CONTROL1 0x2ac 5515 #define mmMVP_CONTROL2 0x2ad 5516 #define mmMVP_FIFO_CONTROL 0x2ae 5517 #define mmMVP_FIFO_STATUS 0x2af 5518 #define mmMVP_SLAVE_STATUS 0x2b0 5519 #define mmMVP_INBAND_CNTL_CAP 0x2b1 5520 #define mmMVP_BLACK_KEYER 0x2b2 5521 #define mmMVP_CRC_CNTL 0x2b3 5522 #define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 5523 #define mmMVP_CRC_RESULT_RED 0x2b5 5524 #define mmMVP_CONTROL3 0x2b6 5525 #define mmMVP_RECEIVE_CNT_CNTL1 0x2b7 5526 #define mmMVP_RECEIVE_CNT_CNTL2 0x2b8 5527 #define mmMVP_DEBUG 0x2bb 5528 #define mmMVP_TEST_DEBUG_INDEX 0x2b9 5529 #define mmMVP_TEST_DEBUG_DATA 0x2ba 5530 #define ixMVP_DEBUG_12 0xc 5531 #define ixMVP_DEBUG_13 0xd 5532 #define ixMVP_DEBUG_14 0xe 5533 #define ixMVP_DEBUG_15 0xf 5534 #define ixMVP_DEBUG_16 0x10 5535 #define ixMVP_DEBUG_17 0x11 5536 #define mmSCL_COEF_RAM_SELECT 0x1b40 5537 #define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 5538 #define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 5539 #define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 5540 #define mmSCL3_SCL_COEF_RAM_SELECT 0x4140 5541 #define mmSCL4_SCL_COEF_RAM_SELECT 0x4340 5542 #define mmSCL5_SCL_COEF_RAM_SELECT 0x4540 5543 #define mmSCL_COEF_RAM_TAP_DATA 0x1b41 5544 #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 5545 #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 5546 #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 5547 #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 5548 #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 5549 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 5550 #define mmSCL_MODE 0x1b42 5551 #define mmSCL0_SCL_MODE 0x1b42 5552 #define mmSCL1_SCL_MODE 0x1d42 5553 #define mmSCL2_SCL_MODE 0x1f42 5554 #define mmSCL3_SCL_MODE 0x4142 5555 #define mmSCL4_SCL_MODE 0x4342 5556 #define mmSCL5_SCL_MODE 0x4542 5557 #define mmSCL_TAP_CONTROL 0x1b43 5558 #define mmSCL0_SCL_TAP_CONTROL 0x1b43 5559 #define mmSCL1_SCL_TAP_CONTROL 0x1d43 5560 #define mmSCL2_SCL_TAP_CONTROL 0x1f43 5561 #define mmSCL3_SCL_TAP_CONTROL 0x4143 5562 #define mmSCL4_SCL_TAP_CONTROL 0x4343 5563 #define mmSCL5_SCL_TAP_CONTROL 0x4543 5564 #define mmSCL_CONTROL 0x1b44 5565 #define mmSCL0_SCL_CONTROL 0x1b44 5566 #define mmSCL1_SCL_CONTROL 0x1d44 5567 #define mmSCL2_SCL_CONTROL 0x1f44 5568 #define mmSCL3_SCL_CONTROL 0x4144 5569 #define mmSCL4_SCL_CONTROL 0x4344 5570 #define mmSCL5_SCL_CONTROL 0x4544 5571 #define mmSCL_BYPASS_CONTROL 0x1b45 5572 #define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 5573 #define mmSCL1_SCL_BYPASS_CONTROL 0x1d45 5574 #define mmSCL2_SCL_BYPASS_CONTROL 0x1f45 5575 #define mmSCL3_SCL_BYPASS_CONTROL 0x4145 5576 #define mmSCL4_SCL_BYPASS_CONTROL 0x4345 5577 #define mmSCL5_SCL_BYPASS_CONTROL 0x4545 5578 #define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 5579 #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 5580 #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 5581 #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 5582 #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 5583 #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 5584 #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 5585 #define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 5586 #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 5587 #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 5588 #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 5589 #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 5590 #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 5591 #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 5592 #define mmSCL_HORZ_FILTER_CONTROL 0x1b48 5593 #define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 5594 #define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 5595 #define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 5596 #define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 5597 #define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 5598 #define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 5599 #define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 5600 #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 5601 #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 5602 #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 5603 #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 5604 #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 5605 #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 5606 #define mmSCL_HORZ_FILTER_INIT 0x1b4a 5607 #define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a 5608 #define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a 5609 #define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a 5610 #define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a 5611 #define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a 5612 #define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a 5613 #define mmSCL_VERT_FILTER_CONTROL 0x1b4b 5614 #define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b 5615 #define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b 5616 #define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b 5617 #define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b 5618 #define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b 5619 #define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b 5620 #define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c 5621 #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c 5622 #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c 5623 #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c 5624 #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c 5625 #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c 5626 #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c 5627 #define mmSCL_VERT_FILTER_INIT 0x1b4d 5628 #define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d 5629 #define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d 5630 #define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d 5631 #define mmSCL3_SCL_VERT_FILTER_INIT 0x414d 5632 #define mmSCL4_SCL_VERT_FILTER_INIT 0x434d 5633 #define mmSCL5_SCL_VERT_FILTER_INIT 0x454d 5634 #define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e 5635 #define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e 5636 #define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e 5637 #define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e 5638 #define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e 5639 #define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e 5640 #define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e 5641 #define mmSCL_ROUND_OFFSET 0x1b4f 5642 #define mmSCL0_SCL_ROUND_OFFSET 0x1b4f 5643 #define mmSCL1_SCL_ROUND_OFFSET 0x1d4f 5644 #define mmSCL2_SCL_ROUND_OFFSET 0x1f4f 5645 #define mmSCL3_SCL_ROUND_OFFSET 0x414f 5646 #define mmSCL4_SCL_ROUND_OFFSET 0x434f 5647 #define mmSCL5_SCL_ROUND_OFFSET 0x454f 5648 #define mmSCL_UPDATE 0x1b51 5649 #define mmSCL0_SCL_UPDATE 0x1b51 5650 #define mmSCL1_SCL_UPDATE 0x1d51 5651 #define mmSCL2_SCL_UPDATE 0x1f51 5652 #define mmSCL3_SCL_UPDATE 0x4151 5653 #define mmSCL4_SCL_UPDATE 0x4351 5654 #define mmSCL5_SCL_UPDATE 0x4551 5655 #define mmSCL_F_SHARP_CONTROL 0x1b53 5656 #define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 5657 #define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 5658 #define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 5659 #define mmSCL3_SCL_F_SHARP_CONTROL 0x4153 5660 #define mmSCL4_SCL_F_SHARP_CONTROL 0x4353 5661 #define mmSCL5_SCL_F_SHARP_CONTROL 0x4553 5662 #define mmSCL_ALU_CONTROL 0x1b54 5663 #define mmSCL0_SCL_ALU_CONTROL 0x1b54 5664 #define mmSCL1_SCL_ALU_CONTROL 0x1d54 5665 #define mmSCL2_SCL_ALU_CONTROL 0x1f54 5666 #define mmSCL3_SCL_ALU_CONTROL 0x4154 5667 #define mmSCL4_SCL_ALU_CONTROL 0x4354 5668 #define mmSCL5_SCL_ALU_CONTROL 0x4554 5669 #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 5670 #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 5671 #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 5672 #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 5673 #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 5674 #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 5675 #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 5676 #define mmVIEWPORT_START_SECONDARY 0x1b5b 5677 #define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b 5678 #define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b 5679 #define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b 5680 #define mmSCL3_VIEWPORT_START_SECONDARY 0x415b 5681 #define mmSCL4_VIEWPORT_START_SECONDARY 0x435b 5682 #define mmSCL5_VIEWPORT_START_SECONDARY 0x455b 5683 #define mmVIEWPORT_START 0x1b5c 5684 #define mmSCL0_VIEWPORT_START 0x1b5c 5685 #define mmSCL1_VIEWPORT_START 0x1d5c 5686 #define mmSCL2_VIEWPORT_START 0x1f5c 5687 #define mmSCL3_VIEWPORT_START 0x415c 5688 #define mmSCL4_VIEWPORT_START 0x435c 5689 #define mmSCL5_VIEWPORT_START 0x455c 5690 #define mmVIEWPORT_SIZE 0x1b5d 5691 #define mmSCL0_VIEWPORT_SIZE 0x1b5d 5692 #define mmSCL1_VIEWPORT_SIZE 0x1d5d 5693 #define mmSCL2_VIEWPORT_SIZE 0x1f5d 5694 #define mmSCL3_VIEWPORT_SIZE 0x415d 5695 #define mmSCL4_VIEWPORT_SIZE 0x435d 5696 #define mmSCL5_VIEWPORT_SIZE 0x455d 5697 #define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e 5698 #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e 5699 #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e 5700 #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e 5701 #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e 5702 #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e 5703 #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e 5704 #define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f 5705 #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f 5706 #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f 5707 #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f 5708 #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f 5709 #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f 5710 #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f 5711 #define mmSCL_MODE_CHANGE_DET1 0x1b60 5712 #define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 5713 #define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 5714 #define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 5715 #define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 5716 #define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 5717 #define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 5718 #define mmSCL_MODE_CHANGE_DET2 0x1b61 5719 #define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 5720 #define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 5721 #define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 5722 #define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 5723 #define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 5724 #define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 5725 #define mmSCL_MODE_CHANGE_DET3 0x1b62 5726 #define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 5727 #define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 5728 #define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 5729 #define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 5730 #define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 5731 #define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 5732 #define mmSCL_MODE_CHANGE_MASK 0x1b63 5733 #define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 5734 #define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 5735 #define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 5736 #define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 5737 #define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 5738 #define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 5739 #define mmSCL_DEBUG2 0x1b69 5740 #define mmSCL0_SCL_DEBUG2 0x1b69 5741 #define mmSCL1_SCL_DEBUG2 0x1d69 5742 #define mmSCL2_SCL_DEBUG2 0x1f69 5743 #define mmSCL3_SCL_DEBUG2 0x4169 5744 #define mmSCL4_SCL_DEBUG2 0x4369 5745 #define mmSCL5_SCL_DEBUG2 0x4569 5746 #define mmSCL_DEBUG 0x1b6a 5747 #define mmSCL0_SCL_DEBUG 0x1b6a 5748 #define mmSCL1_SCL_DEBUG 0x1d6a 5749 #define mmSCL2_SCL_DEBUG 0x1f6a 5750 #define mmSCL3_SCL_DEBUG 0x416a 5751 #define mmSCL4_SCL_DEBUG 0x436a 5752 #define mmSCL5_SCL_DEBUG 0x456a 5753 #define mmSCL_TEST_DEBUG_INDEX 0x1b6b 5754 #define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b 5755 #define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b 5756 #define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b 5757 #define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b 5758 #define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b 5759 #define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b 5760 #define mmSCL_TEST_DEBUG_DATA 0x1b6c 5761 #define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c 5762 #define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c 5763 #define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c 5764 #define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c 5765 #define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c 5766 #define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c 5767 #define mmSCLV_COEF_RAM_SELECT 0x4670 5768 #define mmSCLV_COEF_RAM_TAP_DATA 0x4671 5769 #define mmSCLV_MODE 0x4672 5770 #define mmSCLV_TAP_CONTROL 0x4673 5771 #define mmSCLV_CONTROL 0x4674 5772 #define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 5773 #define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 5774 #define mmSCLV_HORZ_FILTER_CONTROL 0x4677 5775 #define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 5776 #define mmSCLV_HORZ_FILTER_INIT 0x4679 5777 #define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a 5778 #define mmSCLV_HORZ_FILTER_INIT_C 0x467b 5779 #define mmSCLV_VERT_FILTER_CONTROL 0x467c 5780 #define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d 5781 #define mmSCLV_VERT_FILTER_INIT 0x467e 5782 #define mmSCLV_VERT_FILTER_INIT_BOT 0x467f 5783 #define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 5784 #define mmSCLV_VERT_FILTER_INIT_C 0x4681 5785 #define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 5786 #define mmSCLV_ROUND_OFFSET 0x4683 5787 #define mmSCLV_UPDATE 0x4684 5788 #define mmSCLV_ALU_CONTROL 0x4685 5789 #define mmSCLV_VIEWPORT_START 0x4686 5790 #define mmSCLV_VIEWPORT_START_SECONDARY 0x4687 5791 #define mmSCLV_VIEWPORT_SIZE 0x4688 5792 #define mmSCLV_VIEWPORT_START_C 0x4689 5793 #define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a 5794 #define mmSCLV_VIEWPORT_SIZE_C 0x468b 5795 #define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c 5796 #define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d 5797 #define mmSCLV_MODE_CHANGE_DET1 0x468e 5798 #define mmSCLV_MODE_CHANGE_DET2 0x468f 5799 #define mmSCLV_MODE_CHANGE_DET3 0x4690 5800 #define mmSCLV_MODE_CHANGE_MASK 0x4691 5801 #define mmSCLV_DEBUG2 0x4692 5802 #define mmSCLV_DEBUG 0x4693 5803 #define mmSCLV_TEST_DEBUG_INDEX 0x4694 5804 #define mmSCLV_TEST_DEBUG_DATA 0x4695 5805 #define mmCOL_MAN_UPDATE 0x46a4 5806 #define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 5807 #define mmINPUT_CSC_C11_C12_A 0x46a6 5808 #define mmINPUT_CSC_C13_C14_A 0x46a7 5809 #define mmINPUT_CSC_C21_C22_A 0x46a8 5810 #define mmINPUT_CSC_C23_C24_A 0x46a9 5811 #define mmINPUT_CSC_C31_C32_A 0x46aa 5812 #define mmINPUT_CSC_C33_C34_A 0x46ab 5813 #define mmINPUT_CSC_C11_C12_B 0x46ac 5814 #define mmINPUT_CSC_C13_C14_B 0x46ad 5815 #define mmINPUT_CSC_C21_C22_B 0x46ae 5816 #define mmINPUT_CSC_C23_C24_B 0x46af 5817 #define mmINPUT_CSC_C31_C32_B 0x46b0 5818 #define mmINPUT_CSC_C33_C34_B 0x46b1 5819 #define mmPRESCALE_CONTROL 0x46b2 5820 #define mmPRESCALE_VALUES_R 0x46b3 5821 #define mmPRESCALE_VALUES_G 0x46b4 5822 #define mmPRESCALE_VALUES_B 0x46b5 5823 #define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 5824 #define mmOUTPUT_CSC_C11_C12_A 0x46b7 5825 #define mmOUTPUT_CSC_C13_C14_A 0x46b8 5826 #define mmOUTPUT_CSC_C21_C22_A 0x46b9 5827 #define mmOUTPUT_CSC_C23_C24_A 0x46ba 5828 #define mmOUTPUT_CSC_C31_C32_A 0x46bb 5829 #define mmOUTPUT_CSC_C33_C34_A 0x46bc 5830 #define mmOUTPUT_CSC_C11_C12_B 0x46bd 5831 #define mmOUTPUT_CSC_C13_C14_B 0x46be 5832 #define mmOUTPUT_CSC_C21_C22_B 0x46bf 5833 #define mmOUTPUT_CSC_C23_C24_B 0x46c0 5834 #define mmOUTPUT_CSC_C31_C32_B 0x46c1 5835 #define mmOUTPUT_CSC_C33_C34_B 0x46c2 5836 #define mmDENORM_CLAMP_CONTROL 0x46c3 5837 #define mmDENORM_CLAMP_RANGE_R_CR 0x46c4 5838 #define mmDENORM_CLAMP_RANGE_G_Y 0x46c5 5839 #define mmDENORM_CLAMP_RANGE_B_CB 0x46c6 5840 #define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 5841 #define mmGAMMA_CORR_CONTROL 0x46c8 5842 #define mmGAMMA_CORR_LUT_INDEX 0x46c9 5843 #define mmGAMMA_CORR_LUT_DATA 0x46ca 5844 #define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb 5845 #define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc 5846 #define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd 5847 #define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce 5848 #define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf 5849 #define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 5850 #define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 5851 #define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 5852 #define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 5853 #define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 5854 #define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 5855 #define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 5856 #define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 5857 #define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 5858 #define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 5859 #define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da 5860 #define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db 5861 #define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc 5862 #define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd 5863 #define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de 5864 #define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df 5865 #define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 5866 #define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 5867 #define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 5868 #define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 5869 #define mmCOL_MAN_TEST_DEBUG_INDEX 0x46e4 5870 #define mmCOL_MAN_TEST_DEBUG_DATA 0x46e5 5871 #define mmCOL_MAN_DEBUG_CONTROL 0x46e6 5872 #define mmUNP_GRPH_ENABLE 0x4600 5873 #define mmUNP_GRPH_CONTROL 0x4601 5874 #define mmUNP_GRPH_CONTROL_EXP 0x4603 5875 #define mmUNP_GRPH_SWAP_CNTL 0x4605 5876 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 5877 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 5878 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 5879 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 5880 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a 5881 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b 5882 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c 5883 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d 5884 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e 5885 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f 5886 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 5887 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 5888 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 5889 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 5890 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 5891 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 5892 #define mmUNP_GRPH_PITCH_L 0x4616 5893 #define mmUNP_GRPH_PITCH_C 0x4617 5894 #define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 5895 #define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 5896 #define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a 5897 #define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b 5898 #define mmUNP_GRPH_X_START_L 0x461c 5899 #define mmUNP_GRPH_X_START_C 0x461d 5900 #define mmUNP_GRPH_Y_START_L 0x461e 5901 #define mmUNP_GRPH_Y_START_C 0x461f 5902 #define mmUNP_GRPH_X_END_L 0x4620 5903 #define mmUNP_GRPH_X_END_C 0x4621 5904 #define mmUNP_GRPH_Y_END_L 0x4622 5905 #define mmUNP_GRPH_Y_END_C 0x4623 5906 #define mmUNP_GRPH_UPDATE 0x4624 5907 #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 5908 #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 5909 #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 5910 #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 5911 #define mmUNP_GRPH_DFQ_CONTROL 0x4629 5912 #define mmUNP_GRPH_DFQ_STATUS 0x462a 5913 #define mmUNP_GRPH_INTERRUPT_STATUS 0x462b 5914 #define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c 5915 #define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e 5916 #define mmUNP_GRPH_FLIP_RATE_CNTL 0x462f 5917 #define mmUNP_CRC_CONTROL 0x4630 5918 #define mmUNP_CRC_MASK 0x4631 5919 #define mmUNP_CRC_CURRENT 0x4632 5920 #define mmUNP_CRC_LAST 0x4633 5921 #define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 5922 #define mmUNP_HW_ROTATION 0x4635 5923 #define mmUNP_DEBUG 0x4636 5924 #define mmUNP_DEBUG2 0x4637 5925 #define mmUNP_TEST_DEBUG_INDEX 0x4638 5926 #define mmUNP_TEST_DEBUG_DATA 0x4639 5927 #define mmGENMO_WT 0xf0 5928 #define mmGENMO_RD 0xf3 5929 #define mmGENENB 0xf0 5930 #define mmGENFC_WT 0xee 5931 #define mmVGA0_GENFC_WT 0xee 5932 #define mmVGA1_GENFC_WT 0xf6 5933 #define mmGENFC_RD 0xf2 5934 #define mmGENS0 0xf0 5935 #define mmGENS1 0xee 5936 #define mmVGA0_GENS1 0xee 5937 #define mmVGA1_GENS1 0xf6 5938 #define mmDAC_DATA 0xf2 5939 #define mmDAC_MASK 0xf1 5940 #define mmDAC_R_INDEX 0xf1 5941 #define mmDAC_W_INDEX 0xf2 5942 #define mmSEQ8_IDX 0xf1 5943 #define mmSEQ8_DATA 0xf1 5944 #define ixSEQ00 0x0 5945 #define ixSEQ01 0x1 5946 #define ixSEQ02 0x2 5947 #define ixSEQ03 0x3 5948 #define ixSEQ04 0x4 5949 #define mmCRTC8_IDX 0xed 5950 #define mmVGA0_CRTC8_IDX 0xed 5951 #define mmVGA1_CRTC8_IDX 0xf5 5952 #define mmCRTC8_DATA 0xed 5953 #define mmVGA0_CRTC8_DATA 0xed 5954 #define mmVGA1_CRTC8_DATA 0xf5 5955 #define ixCRT00 0x0 5956 #define ixCRT01 0x1 5957 #define ixCRT02 0x2 5958 #define ixCRT03 0x3 5959 #define ixCRT04 0x4 5960 #define ixCRT05 0x5 5961 #define ixCRT06 0x6 5962 #define ixCRT07 0x7 5963 #define ixCRT08 0x8 5964 #define ixCRT09 0x9 5965 #define ixCRT0A 0xa 5966 #define ixCRT0B 0xb 5967 #define ixCRT0C 0xc 5968 #define ixCRT0D 0xd 5969 #define ixCRT0E 0xe 5970 #define ixCRT0F 0xf 5971 #define ixCRT10 0x10 5972 #define ixCRT11 0x11 5973 #define ixCRT12 0x12 5974 #define ixCRT13 0x13 5975 #define ixCRT14 0x14 5976 #define ixCRT15 0x15 5977 #define ixCRT16 0x16 5978 #define ixCRT17 0x17 5979 #define ixCRT18 0x18 5980 #define ixCRT1E 0x1e 5981 #define ixCRT1F 0x1f 5982 #define ixCRT22 0x22 5983 #define mmGRPH8_IDX 0xf3 5984 #define mmGRPH8_DATA 0xf3 5985 #define ixGRA00 0x0 5986 #define ixGRA01 0x1 5987 #define ixGRA02 0x2 5988 #define ixGRA03 0x3 5989 #define ixGRA04 0x4 5990 #define ixGRA05 0x5 5991 #define ixGRA06 0x6 5992 #define ixGRA07 0x7 5993 #define ixGRA08 0x8 5994 #define mmATTRX 0xf0 5995 #define mmATTRDW 0xf0 5996 #define mmATTRDR 0xf0 5997 #define ixATTR00 0x0 5998 #define ixATTR01 0x1 5999 #define ixATTR02 0x2 6000 #define ixATTR03 0x3 6001 #define ixATTR04 0x4 6002 #define ixATTR05 0x5 6003 #define ixATTR06 0x6 6004 #define ixATTR07 0x7 6005 #define ixATTR08 0x8 6006 #define ixATTR09 0x9 6007 #define ixATTR0A 0xa 6008 #define ixATTR0B 0xb 6009 #define ixATTR0C 0xc 6010 #define ixATTR0D 0xd 6011 #define ixATTR0E 0xe 6012 #define ixATTR0F 0xf 6013 #define ixATTR10 0x10 6014 #define ixATTR11 0x11 6015 #define ixATTR12 0x12 6016 #define ixATTR13 0x13 6017 #define ixATTR14 0x14 6018 #define mmVGA_RENDER_CONTROL 0xc0 6019 #define mmVGA_SOURCE_SELECT 0xfc 6020 #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 6021 #define mmVGA_MODE_CONTROL 0xc2 6022 #define mmVGA_SURFACE_PITCH_SELECT 0xc3 6023 #define mmVGA_MEMORY_BASE_ADDRESS 0xc4 6024 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 6025 #define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 6026 #define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 6027 #define mmVGA_HDP_CONTROL 0xca 6028 #define mmVGA_CACHE_CONTROL 0xcb 6029 #define mmD1VGA_CONTROL 0xcc 6030 #define mmD2VGA_CONTROL 0xce 6031 #define mmD3VGA_CONTROL 0xf8 6032 #define mmD4VGA_CONTROL 0xf9 6033 #define mmD5VGA_CONTROL 0xfa 6034 #define mmD6VGA_CONTROL 0xfb 6035 #define mmVGA_HW_DEBUG 0xcf 6036 #define mmVGA_STATUS 0xd0 6037 #define mmVGA_INTERRUPT_CONTROL 0xd1 6038 #define mmVGA_STATUS_CLEAR 0xd2 6039 #define mmVGA_INTERRUPT_STATUS 0xd3 6040 #define mmVGA_MAIN_CONTROL 0xd4 6041 #define mmVGA_TEST_CONTROL 0xd5 6042 #define mmVGA_DEBUG_READBACK_INDEX 0xd6 6043 #define mmVGA_DEBUG_READBACK_DATA 0xd7 6044 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 6045 #define mmVGA_MEM_READ_PAGE_ADDR 0x13 6046 #define mmVGA_TEST_DEBUG_INDEX 0xc5 6047 #define mmVGA_TEST_DEBUG_DATA 0xc7 6048 #define ixVGADCC_DBG_DCCIF_C 0x7e 6049 #define mmBPHYC_DAC_MACRO_CNTL 0x48b9 6050 #define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba 6051 #define mmPLL_REF_DIV 0x1700 6052 #define mmBPHYC_PLL0_PLL_REF_DIV 0x1700 6053 #define mmBPHYC_PLL1_PLL_REF_DIV 0x172a 6054 #define mmBPHYC_PLL2_PLL_REF_DIV 0x1754 6055 #define mmPLL_FB_DIV 0x1701 6056 #define mmBPHYC_PLL0_PLL_FB_DIV 0x1701 6057 #define mmBPHYC_PLL1_PLL_FB_DIV 0x172b 6058 #define mmBPHYC_PLL2_PLL_FB_DIV 0x1755 6059 #define mmPLL_POST_DIV 0x1702 6060 #define mmBPHYC_PLL0_PLL_POST_DIV 0x1702 6061 #define mmBPHYC_PLL1_PLL_POST_DIV 0x172c 6062 #define mmBPHYC_PLL2_PLL_POST_DIV 0x1756 6063 #define mmPLL_SS_AMOUNT_DSFRAC 0x1703 6064 #define mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 6065 #define mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d 6066 #define mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757 6067 #define mmPLL_SS_CNTL 0x1704 6068 #define mmBPHYC_PLL0_PLL_SS_CNTL 0x1704 6069 #define mmBPHYC_PLL1_PLL_SS_CNTL 0x172e 6070 #define mmBPHYC_PLL2_PLL_SS_CNTL 0x1758 6071 #define mmPLL_DS_CNTL 0x1705 6072 #define mmBPHYC_PLL0_PLL_DS_CNTL 0x1705 6073 #define mmBPHYC_PLL1_PLL_DS_CNTL 0x172f 6074 #define mmBPHYC_PLL2_PLL_DS_CNTL 0x1759 6075 #define mmPLL_IDCLK_CNTL 0x1706 6076 #define mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706 6077 #define mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730 6078 #define mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a 6079 #define mmPLL_CNTL 0x1707 6080 #define mmBPHYC_PLL0_PLL_CNTL 0x1707 6081 #define mmBPHYC_PLL1_PLL_CNTL 0x1731 6082 #define mmBPHYC_PLL2_PLL_CNTL 0x175b 6083 #define mmPLL_ANALOG 0x1708 6084 #define mmBPHYC_PLL0_PLL_ANALOG 0x1708 6085 #define mmBPHYC_PLL1_PLL_ANALOG 0x1732 6086 #define mmBPHYC_PLL2_PLL_ANALOG 0x175c 6087 #define mmPLL_VREG_CNTL 0x1709 6088 #define mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709 6089 #define mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733 6090 #define mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d 6091 #define mmPLL_UNLOCK_DETECT_CNTL 0x170a 6092 #define mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a 6093 #define mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734 6094 #define mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e 6095 #define mmPLL_DEBUG_CNTL 0x170b 6096 #define mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b 6097 #define mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735 6098 #define mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f 6099 #define mmPLL_UPDATE_LOCK 0x170c 6100 #define mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c 6101 #define mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736 6102 #define mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760 6103 #define mmPLL_UPDATE_CNTL 0x170d 6104 #define mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d 6105 #define mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737 6106 #define mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761 6107 #define mmPLL_XOR_LOCK 0x1710 6108 #define mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710 6109 #define mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a 6110 #define mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764 6111 #define mmPLL_ANALOG_CNTL 0x1711 6112 #define mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711 6113 #define mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b 6114 #define mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765 6115 #define mmVGA25_PPLL_REF_DIV 0x1712 6116 #define mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712 6117 #define mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c 6118 #define mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766 6119 #define mmVGA28_PPLL_REF_DIV 0x1713 6120 #define mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713 6121 #define mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d 6122 #define mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767 6123 #define mmVGA41_PPLL_REF_DIV 0x1714 6124 #define mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714 6125 #define mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e 6126 #define mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768 6127 #define mmVGA25_PPLL_FB_DIV 0x1715 6128 #define mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715 6129 #define mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f 6130 #define mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769 6131 #define mmVGA28_PPLL_FB_DIV 0x1716 6132 #define mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716 6133 #define mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740 6134 #define mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a 6135 #define mmVGA41_PPLL_FB_DIV 0x1717 6136 #define mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717 6137 #define mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741 6138 #define mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b 6139 #define mmVGA25_PPLL_POST_DIV 0x1718 6140 #define mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718 6141 #define mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742 6142 #define mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c 6143 #define mmVGA28_PPLL_POST_DIV 0x1719 6144 #define mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719 6145 #define mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743 6146 #define mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d 6147 #define mmVGA41_PPLL_POST_DIV 0x171a 6148 #define mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a 6149 #define mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744 6150 #define mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e 6151 #define mmVGA25_PPLL_ANALOG 0x171b 6152 #define mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b 6153 #define mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745 6154 #define mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f 6155 #define mmVGA28_PPLL_ANALOG 0x171c 6156 #define mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c 6157 #define mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746 6158 #define mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770 6159 #define mmVGA41_PPLL_ANALOG 0x171d 6160 #define mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d 6161 #define mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747 6162 #define mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771 6163 #define mmDISPPLL_BG_CNTL 0x171e 6164 #define mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e 6165 #define mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748 6166 #define mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772 6167 #define mmPPLL_DIV_UPDATE_DEBUG 0x171f 6168 #define mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f 6169 #define mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749 6170 #define mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773 6171 #define mmPPLL_STATUS_DEBUG 0x1720 6172 #define mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720 6173 #define mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a 6174 #define mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774 6175 #define mmPPLL_DEBUG_MUX_CNTL 0x1721 6176 #define mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721 6177 #define mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b 6178 #define mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775 6179 #define mmPPLL_SPARE0 0x1722 6180 #define mmBPHYC_PLL0_PPLL_SPARE0 0x1722 6181 #define mmBPHYC_PLL1_PPLL_SPARE0 0x174c 6182 #define mmBPHYC_PLL2_PPLL_SPARE0 0x1776 6183 #define mmPPLL_SPARE1 0x1723 6184 #define mmBPHYC_PLL0_PPLL_SPARE1 0x1723 6185 #define mmBPHYC_PLL1_PPLL_SPARE1 0x174d 6186 #define mmBPHYC_PLL2_PPLL_SPARE1 0x1777 6187 #define mmUNIPHY_TX_CONTROL1 0x48c0 6188 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0 6189 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0 6190 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900 6191 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920 6192 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940 6193 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960 6194 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980 6195 #define mmUNIPHY_TX_CONTROL2 0x48c1 6196 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1 6197 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1 6198 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901 6199 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921 6200 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941 6201 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961 6202 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981 6203 #define mmUNIPHY_TX_CONTROL3 0x48c2 6204 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2 6205 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2 6206 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902 6207 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922 6208 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942 6209 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962 6210 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982 6211 #define mmUNIPHY_TX_CONTROL4 0x48c3 6212 #define mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3 6213 #define mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3 6214 #define mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903 6215 #define mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923 6216 #define mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943 6217 #define mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963 6218 #define mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983 6219 #define mmUNIPHY_POWER_CONTROL 0x48c4 6220 #define mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4 6221 #define mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4 6222 #define mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904 6223 #define mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924 6224 #define mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944 6225 #define mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964 6226 #define mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984 6227 #define mmUNIPHY_PLL_FBDIV 0x48c5 6228 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5 6229 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5 6230 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905 6231 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925 6232 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945 6233 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965 6234 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985 6235 #define mmUNIPHY_PLL_CONTROL1 0x48c6 6236 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6 6237 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6 6238 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906 6239 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926 6240 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946 6241 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966 6242 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986 6243 #define mmUNIPHY_PLL_CONTROL2 0x48c7 6244 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7 6245 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7 6246 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907 6247 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927 6248 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947 6249 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967 6250 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987 6251 #define mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8 6252 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8 6253 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8 6254 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908 6255 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928 6256 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948 6257 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968 6258 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988 6259 #define mmUNIPHY_PLL_SS_CNTL 0x48c9 6260 #define mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9 6261 #define mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9 6262 #define mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909 6263 #define mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929 6264 #define mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949 6265 #define mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969 6266 #define mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989 6267 #define mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca 6268 #define mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca 6269 #define mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea 6270 #define mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a 6271 #define mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a 6272 #define mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a 6273 #define mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a 6274 #define mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a 6275 #define mmUNIPHY_REG_TEST_OUTPUT 0x48cb 6276 #define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb 6277 #define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb 6278 #define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b 6279 #define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b 6280 #define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b 6281 #define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b 6282 #define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b 6283 #define mmUNIPHY_ANG_BIST_CNTL 0x48cc 6284 #define mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc 6285 #define mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec 6286 #define mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c 6287 #define mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c 6288 #define mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c 6289 #define mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c 6290 #define mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c 6291 #define mmUNIPHY_REG_TEST_OUTPUT2 0x48cd 6292 #define mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd 6293 #define mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed 6294 #define mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d 6295 #define mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d 6296 #define mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d 6297 #define mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d 6298 #define mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d 6299 #define mmUNIPHY_TMDP_REG0 0x48ce 6300 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce 6301 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee 6302 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e 6303 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e 6304 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e 6305 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e 6306 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e 6307 #define mmUNIPHY_TMDP_REG1 0x48cf 6308 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf 6309 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef 6310 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f 6311 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f 6312 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f 6313 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f 6314 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f 6315 #define mmUNIPHY_TMDP_REG2 0x48d0 6316 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0 6317 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0 6318 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910 6319 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930 6320 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950 6321 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970 6322 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990 6323 #define mmUNIPHY_TMDP_REG3 0x48d1 6324 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1 6325 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1 6326 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911 6327 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931 6328 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951 6329 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971 6330 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991 6331 #define mmUNIPHY_TMDP_REG4 0x48d2 6332 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2 6333 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2 6334 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912 6335 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932 6336 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952 6337 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972 6338 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992 6339 #define mmUNIPHY_TMDP_REG5 0x48d3 6340 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3 6341 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3 6342 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913 6343 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933 6344 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953 6345 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973 6346 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993 6347 #define mmUNIPHY_TMDP_REG6 0x48d4 6348 #define mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4 6349 #define mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4 6350 #define mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914 6351 #define mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934 6352 #define mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954 6353 #define mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974 6354 #define mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994 6355 #define mmUNIPHY_TPG_CONTROL 0x48d5 6356 #define mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5 6357 #define mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5 6358 #define mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915 6359 #define mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935 6360 #define mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955 6361 #define mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975 6362 #define mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995 6363 #define mmUNIPHY_TPG_SEED 0x48d6 6364 #define mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6 6365 #define mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6 6366 #define mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916 6367 #define mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936 6368 #define mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956 6369 #define mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976 6370 #define mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996 6371 #define mmUNIPHY_DEBUG 0x48d7 6372 #define mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7 6373 #define mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7 6374 #define mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917 6375 #define mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937 6376 #define mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957 6377 #define mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977 6378 #define mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997 6379 #define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 6380 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 6381 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 6382 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 6383 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 6384 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 6385 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 6386 #define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 6387 #define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 6388 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 6389 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 6390 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 6391 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 6392 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 6393 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 6394 #define mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 6395 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 6396 #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 6397 #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 6398 #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 6399 #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 6400 #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 6401 #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 6402 #define mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL 0x4732 6403 #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 6404 #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 6405 #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 6406 #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 6407 #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 6408 #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 6409 #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 6410 #define mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL 0x4733 6411 #define mmDPG_PIPE_DPM_CONTROL 0x1b34 6412 #define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 6413 #define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 6414 #define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 6415 #define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 6416 #define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 6417 #define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 6418 #define mmDMIF_PG6_DPG_PIPE_DPM_CONTROL 0x4734 6419 #define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 6420 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 6421 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 6422 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 6423 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 6424 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 6425 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 6426 #define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL 0x4735 6427 #define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 6428 #define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 6429 #define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 6430 #define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 6431 #define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 6432 #define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 6433 #define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 6434 #define mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 6435 #define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 6436 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 6437 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 6438 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 6439 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 6440 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 6441 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 6442 #define mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 6443 #define mmDPG_REPEATER_PROGRAM 0x1b3a 6444 #define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a 6445 #define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a 6446 #define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a 6447 #define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a 6448 #define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a 6449 #define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a 6450 #define mmDMIF_PG6_DPG_REPEATER_PROGRAM 0x473a 6451 #define mmDPG_HW_DEBUG_A 0x1b3b 6452 #define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b 6453 #define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b 6454 #define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b 6455 #define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b 6456 #define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b 6457 #define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b 6458 #define mmDMIF_PG6_DPG_HW_DEBUG_A 0x473b 6459 #define mmDPG_HW_DEBUG_B 0x1b3c 6460 #define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c 6461 #define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c 6462 #define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c 6463 #define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c 6464 #define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c 6465 #define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c 6466 #define mmDMIF_PG6_DPG_HW_DEBUG_B 0x473c 6467 #define mmDPG_HW_DEBUG_11 0x1b3d 6468 #define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d 6469 #define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d 6470 #define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d 6471 #define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d 6472 #define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d 6473 #define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d 6474 #define mmDMIF_PG6_DPG_HW_DEBUG_11 0x473d 6475 #define mmDPG_TEST_DEBUG_INDEX 0x1b38 6476 #define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 6477 #define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 6478 #define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 6479 #define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 6480 #define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 6481 #define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 6482 #define mmDMIF_PG6_DPG_TEST_DEBUG_INDEX 0x4738 6483 #define mmDPG_TEST_DEBUG_DATA 0x1b39 6484 #define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 6485 #define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 6486 #define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 6487 #define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 6488 #define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 6489 #define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 6490 #define mmDMIF_PG6_DPG_TEST_DEBUG_DATA 0x4739 6491 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 6492 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 6493 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 6494 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 6495 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 6496 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 6497 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 6498 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 6499 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 6500 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 6501 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 6502 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 6503 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 6504 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 6505 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 6506 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 6507 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 6508 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 6509 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 6510 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a 6511 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b 6512 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c 6513 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d 6514 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e 6515 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f 6516 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 6517 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 6518 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 6519 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 6520 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 6521 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 6522 #define mmAZALIA_F0_CODEC_DEBUG 0x1836 6523 #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 6524 #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 6525 #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 6526 #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a 6527 #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b 6528 #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c 6529 #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d 6530 #define mmGLOBAL_CAPABILITIES 0x0 6531 #define mmMINOR_VERSION 0x0 6532 #define mmMAJOR_VERSION 0x0 6533 #define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 6534 #define mmINPUT_PAYLOAD_CAPABILITY 0x1 6535 #define mmGLOBAL_CONTROL 0x2 6536 #define mmWAKE_ENABLE 0x3 6537 #define mmSTATE_CHANGE_STATUS 0x3 6538 #define mmGLOBAL_STATUS 0x4 6539 #define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 6540 #define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 6541 #define mmINTERRUPT_CONTROL 0x8 6542 #define mmINTERRUPT_STATUS 0x9 6543 #define mmWALL_CLOCK_COUNTER 0xc 6544 #define mmSTREAM_SYNCHRONIZATION 0xe 6545 #define mmCORB_LOWER_BASE_ADDRESS 0x10 6546 #define mmCORB_UPPER_BASE_ADDRESS 0x11 6547 #define mmCORB_WRITE_POINTER 0x12 6548 #define mmCORB_READ_POINTER 0x12 6549 #define mmCORB_CONTROL 0x13 6550 #define mmCORB_STATUS 0x13 6551 #define mmCORB_SIZE 0x13 6552 #define mmRIRB_LOWER_BASE_ADDRESS 0x14 6553 #define mmRIRB_UPPER_BASE_ADDRESS 0x15 6554 #define mmRIRB_WRITE_POINTER 0x16 6555 #define mmRESPONSE_INTERRUPT_COUNT 0x16 6556 #define mmRIRB_CONTROL 0x17 6557 #define mmRIRB_STATUS 0x17 6558 #define mmRIRB_SIZE 0x17 6559 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 6560 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 6561 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 6562 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 6563 #define mmIMMEDIATE_COMMAND_STATUS 0x1a 6564 #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c 6565 #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d 6566 #define mmWALL_CLOCK_COUNTER_ALIAS 0x80c 6567 #define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 6568 #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 6569 #define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 6570 #define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 6571 #define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 6572 #define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 6573 #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 6574 #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 6575 #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 6576 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 6577 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 6578 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 6579 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 6580 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 6581 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 6582 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 6583 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 6584 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 6585 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 6586 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 6587 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 6588 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 6589 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 6590 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 6591 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 6592 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 6593 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 6594 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 6595 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 6596 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 6597 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 6598 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 6599 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 6600 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 6601 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 6602 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 6603 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 6604 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 6605 #define ixAUDIO_DESCRIPTOR0 0x1 6606 #define ixAUDIO_DESCRIPTOR1 0x2 6607 #define ixAUDIO_DESCRIPTOR2 0x3 6608 #define ixAUDIO_DESCRIPTOR3 0x4 6609 #define ixAUDIO_DESCRIPTOR4 0x5 6610 #define ixAUDIO_DESCRIPTOR5 0x6 6611 #define ixAUDIO_DESCRIPTOR6 0x7 6612 #define ixAUDIO_DESCRIPTOR7 0x8 6613 #define ixAUDIO_DESCRIPTOR8 0x9 6614 #define ixAUDIO_DESCRIPTOR9 0xa 6615 #define ixAUDIO_DESCRIPTOR10 0xb 6616 #define ixAUDIO_DESCRIPTOR11 0xc 6617 #define ixAUDIO_DESCRIPTOR12 0xd 6618 #define ixAUDIO_DESCRIPTOR13 0xe 6619 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 6620 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 6621 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 6622 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 6623 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 6624 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 6625 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 6626 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 6627 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 6628 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 6629 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 6630 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 6631 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 6632 #define ixSINK_DESCRIPTION0 0x5 6633 #define ixSINK_DESCRIPTION1 0x6 6634 #define ixSINK_DESCRIPTION2 0x7 6635 #define ixSINK_DESCRIPTION3 0x8 6636 #define ixSINK_DESCRIPTION4 0x9 6637 #define ixSINK_DESCRIPTION5 0xa 6638 #define ixSINK_DESCRIPTION6 0xb 6639 #define ixSINK_DESCRIPTION7 0xc 6640 #define ixSINK_DESCRIPTION8 0xd 6641 #define ixSINK_DESCRIPTION9 0xe 6642 #define ixSINK_DESCRIPTION10 0xf 6643 #define ixSINK_DESCRIPTION11 0x10 6644 #define ixSINK_DESCRIPTION12 0x11 6645 #define ixSINK_DESCRIPTION13 0x12 6646 #define ixSINK_DESCRIPTION14 0x13 6647 #define ixSINK_DESCRIPTION15 0x14 6648 #define ixSINK_DESCRIPTION16 0x15 6649 #define ixSINK_DESCRIPTION17 0x16 6650 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 6651 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 6652 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 6653 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 6654 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 6655 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 6656 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 6657 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 6658 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 6659 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 6660 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 6661 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 6662 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 6663 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 6664 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 6665 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 6666 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 6667 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 6668 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 6669 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 6670 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 6671 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 6672 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 6673 #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 6674 #define mmAZALIA_AUDIO_DTO 0x17e5 6675 #define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 6676 #define mmAZALIA_SCLK_CONTROL 0x17e7 6677 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 6678 #define mmAZALIA_DATA_DMA_CONTROL 0x17e9 6679 #define mmAZALIA_BDL_DMA_CONTROL 0x17ea 6680 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb 6681 #define mmAZALIA_CORB_DMA_CONTROL 0x17ec 6682 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 6683 #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 6684 #define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 6685 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 6686 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 6687 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 6688 #define mmAZALIA_CONTROLLER_DEBUG 0x17f9 6689 #define mmAZALIA_MEM_PWR_CTRL 0x1810 6690 #define mmAZALIA_MEM_PWR_STATUS 0x1811 6691 #define mmDCI_PG_DEBUG_CONFIG 0x1812 6692 #define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb 6693 #define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc 6694 #define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd 6695 #define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe 6696 #define mmAZALIA_INPUT_CRC0_RESULT 0x17ff 6697 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 6698 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 6699 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 6700 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 6701 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 6702 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 6703 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 6704 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 6705 #define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 6706 #define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 6707 #define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 6708 #define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 6709 #define mmAZALIA_INPUT_CRC1_RESULT 0x1804 6710 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 6711 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 6712 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 6713 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 6714 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 6715 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 6716 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 6717 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 6718 #define mmAZALIA_CRC0_CONTROL0 0x1805 6719 #define mmAZALIA_CRC0_CONTROL1 0x1806 6720 #define mmAZALIA_CRC0_CONTROL2 0x1807 6721 #define mmAZALIA_CRC0_CONTROL3 0x1808 6722 #define mmAZALIA_CRC0_RESULT 0x1809 6723 #define ixAZALIA_CRC0_CHANNEL0 0x0 6724 #define ixAZALIA_CRC0_CHANNEL1 0x1 6725 #define ixAZALIA_CRC0_CHANNEL2 0x2 6726 #define ixAZALIA_CRC0_CHANNEL3 0x3 6727 #define ixAZALIA_CRC0_CHANNEL4 0x4 6728 #define ixAZALIA_CRC0_CHANNEL5 0x5 6729 #define ixAZALIA_CRC0_CHANNEL6 0x6 6730 #define ixAZALIA_CRC0_CHANNEL7 0x7 6731 #define mmAZALIA_CRC1_CONTROL0 0x180a 6732 #define mmAZALIA_CRC1_CONTROL1 0x180b 6733 #define mmAZALIA_CRC1_CONTROL2 0x180c 6734 #define mmAZALIA_CRC1_CONTROL3 0x180d 6735 #define mmAZALIA_CRC1_RESULT 0x180e 6736 #define ixAZALIA_CRC1_CHANNEL0 0x0 6737 #define ixAZALIA_CRC1_CHANNEL1 0x1 6738 #define ixAZALIA_CRC1_CHANNEL2 0x2 6739 #define ixAZALIA_CRC1_CHANNEL3 0x3 6740 #define ixAZALIA_CRC1_CHANNEL4 0x4 6741 #define ixAZALIA_CRC1_CHANNEL5 0x5 6742 #define ixAZALIA_CRC1_CHANNEL6 0x6 6743 #define ixAZALIA_CRC1_CHANNEL7 0x7 6744 #define mmAZ_TEST_DEBUG_INDEX 0x181f 6745 #define mmAZ_TEST_DEBUG_DATA 0x1820 6746 #define mmAZALIA_STREAM_INDEX 0x1780 6747 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 6748 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 6749 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 6750 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 6751 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 6752 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a 6753 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c 6754 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e 6755 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 6756 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 6757 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 6758 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 6759 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 6760 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca 6761 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc 6762 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce 6763 #define mmAZALIA_STREAM_DATA 0x1781 6764 #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 6765 #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 6766 #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 6767 #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 6768 #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 6769 #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b 6770 #define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d 6771 #define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f 6772 #define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 6773 #define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 6774 #define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 6775 #define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 6776 #define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 6777 #define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb 6778 #define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd 6779 #define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf 6780 #define ixAZALIA_FIFO_SIZE_CONTROL 0x0 6781 #define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 6782 #define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 6783 #define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 6784 #define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 6785 #define ixAZALIA_STREAM_DEBUG 0x5 6786 #define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 6787 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 6788 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac 6789 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 6790 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 6791 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 6792 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc 6793 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 6794 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 6795 #define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 6796 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 6797 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad 6798 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 6799 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 6800 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 6801 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd 6802 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 6803 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 6804 #define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 6805 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 6806 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 6807 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 6808 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 6809 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 6810 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 6811 #define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 6812 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 6813 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 6814 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa 6815 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc 6816 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd 6817 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe 6818 #define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 6819 #define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 6820 #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 6821 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 6822 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 6823 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 6824 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 6825 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 6826 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a 6827 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b 6828 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c 6829 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d 6830 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e 6831 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f 6832 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 6833 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 6834 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 6835 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 6836 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 6837 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 6838 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 6839 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 6840 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 6841 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 6842 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 6843 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a 6844 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b 6845 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c 6846 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d 6847 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e 6848 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f 6849 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 6850 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 6851 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 6852 #define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 6853 #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 6854 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 6855 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 6856 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a 6857 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b 6858 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c 6859 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d 6860 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e 6861 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f 6862 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 6863 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 6864 #define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 6865 #define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 6866 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 6867 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 6868 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 6869 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 6870 #define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 6871 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 6872 #define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a 6873 #define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b 6874 #define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c 6875 #define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d 6876 #define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e 6877 #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 6878 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 6879 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 6880 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc 6881 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 6882 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 6883 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 6884 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec 6885 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 6886 #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 6887 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 6888 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 6889 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd 6890 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 6891 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 6892 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 6893 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed 6894 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 6895 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 6896 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 6897 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 6898 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 6899 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 6900 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 6901 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 6902 #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 6903 #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 6904 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 6905 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 6906 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 6907 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 6908 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 6909 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 6910 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 6911 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 6912 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 6913 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 6914 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 6915 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 6916 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 6917 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 6918 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 6919 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 6920 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 6921 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 6922 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 6923 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 6924 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 6925 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 6926 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 6927 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 6928 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 6929 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 6930 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 6931 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 6932 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 6933 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 6934 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 6935 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 6936 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 6937 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 6938 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 6939 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 6940 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 6941 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 6942 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 6943 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 6944 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 6945 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 6946 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 6947 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 6948 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 6949 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 6950 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 6951 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 6952 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 6953 #define mmBLND_CONTROL 0x1b6d 6954 #define mmBLND0_BLND_CONTROL 0x1b6d 6955 #define mmBLND1_BLND_CONTROL 0x1d6d 6956 #define mmBLND2_BLND_CONTROL 0x1f6d 6957 #define mmBLND3_BLND_CONTROL 0x416d 6958 #define mmBLND4_BLND_CONTROL 0x436d 6959 #define mmBLND5_BLND_CONTROL 0x456d 6960 #define mmBLND6_BLND_CONTROL 0x476d 6961 #define mmSM_CONTROL2 0x1b6e 6962 #define mmBLND0_SM_CONTROL2 0x1b6e 6963 #define mmBLND1_SM_CONTROL2 0x1d6e 6964 #define mmBLND2_SM_CONTROL2 0x1f6e 6965 #define mmBLND3_SM_CONTROL2 0x416e 6966 #define mmBLND4_SM_CONTROL2 0x436e 6967 #define mmBLND5_SM_CONTROL2 0x456e 6968 #define mmBLND6_SM_CONTROL2 0x476e 6969 #define mmBLND_CONTROL2 0x1b6f 6970 #define mmBLND0_BLND_CONTROL2 0x1b6f 6971 #define mmBLND1_BLND_CONTROL2 0x1d6f 6972 #define mmBLND2_BLND_CONTROL2 0x1f6f 6973 #define mmBLND3_BLND_CONTROL2 0x416f 6974 #define mmBLND4_BLND_CONTROL2 0x436f 6975 #define mmBLND5_BLND_CONTROL2 0x456f 6976 #define mmBLND6_BLND_CONTROL2 0x476f 6977 #define mmBLND_UPDATE 0x1b70 6978 #define mmBLND0_BLND_UPDATE 0x1b70 6979 #define mmBLND1_BLND_UPDATE 0x1d70 6980 #define mmBLND2_BLND_UPDATE 0x1f70 6981 #define mmBLND3_BLND_UPDATE 0x4170 6982 #define mmBLND4_BLND_UPDATE 0x4370 6983 #define mmBLND5_BLND_UPDATE 0x4570 6984 #define mmBLND6_BLND_UPDATE 0x4770 6985 #define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 6986 #define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 6987 #define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 6988 #define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 6989 #define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 6990 #define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 6991 #define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 6992 #define mmBLND6_BLND_UNDERFLOW_INTERRUPT 0x4771 6993 #define mmBLND_V_UPDATE_LOCK 0x1b73 6994 #define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 6995 #define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 6996 #define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 6997 #define mmBLND3_BLND_V_UPDATE_LOCK 0x4173 6998 #define mmBLND4_BLND_V_UPDATE_LOCK 0x4373 6999 #define mmBLND5_BLND_V_UPDATE_LOCK 0x4573 7000 #define mmBLND6_BLND_V_UPDATE_LOCK 0x4773 7001 #define mmBLND_REG_UPDATE_STATUS 0x1b77 7002 #define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 7003 #define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 7004 #define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 7005 #define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 7006 #define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 7007 #define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 7008 #define mmBLND6_BLND_REG_UPDATE_STATUS 0x4777 7009 #define mmBLND_DEBUG 0x1b74 7010 #define mmBLND0_BLND_DEBUG 0x1b74 7011 #define mmBLND1_BLND_DEBUG 0x1d74 7012 #define mmBLND2_BLND_DEBUG 0x1f74 7013 #define mmBLND3_BLND_DEBUG 0x4174 7014 #define mmBLND4_BLND_DEBUG 0x4374 7015 #define mmBLND5_BLND_DEBUG 0x4574 7016 #define mmBLND6_BLND_DEBUG 0x4774 7017 #define mmBLND_TEST_DEBUG_INDEX 0x1b75 7018 #define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 7019 #define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 7020 #define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 7021 #define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 7022 #define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 7023 #define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 7024 #define mmBLND6_BLND_TEST_DEBUG_INDEX 0x4775 7025 #define mmBLND_TEST_DEBUG_DATA 0x1b76 7026 #define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 7027 #define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 7028 #define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 7029 #define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 7030 #define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 7031 #define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 7032 #define mmBLND6_BLND_TEST_DEBUG_DATA 0x4776 7033 #define mmWB_ENABLE 0x5e18 7034 #define mmWB_EC_CONFIG 0x5e19 7035 #define mmCNV_MODE 0x5e1a 7036 #define mmCNV_WINDOW_START 0x5e1b 7037 #define mmCNV_WINDOW_SIZE 0x5e1c 7038 #define mmCNV_UPDATE 0x5e1d 7039 #define mmCNV_SOURCE_SIZE 0x5e1e 7040 #define mmCNV_CSC_CONTROL 0x5e1f 7041 #define mmCNV_CSC_C11_C12 0x5e20 7042 #define mmCNV_CSC_C13_C14 0x5e21 7043 #define mmCNV_CSC_C21_C22 0x5e22 7044 #define mmCNV_CSC_C23_C24 0x5e23 7045 #define mmCNV_CSC_C31_C32 0x5e24 7046 #define mmCNV_CSC_C33_C34 0x5e25 7047 #define mmCNV_CSC_ROUND_OFFSET_R 0x5e26 7048 #define mmCNV_CSC_ROUND_OFFSET_G 0x5e27 7049 #define mmCNV_CSC_ROUND_OFFSET_B 0x5e28 7050 #define mmCNV_CSC_CLAMP_R 0x5e29 7051 #define mmCNV_CSC_CLAMP_G 0x5e2a 7052 #define mmCNV_CSC_CLAMP_B 0x5e2b 7053 #define mmCNV_TEST_CNTL 0x5e2c 7054 #define mmCNV_TEST_CRC_RED 0x5e2d 7055 #define mmCNV_TEST_CRC_GREEN 0x5e2e 7056 #define mmCNV_TEST_CRC_BLUE 0x5e2f 7057 #define mmWB_DEBUG_CTRL 0x5e30 7058 #define mmWB_DBG_MODE 0x5e31 7059 #define mmWB_HW_DEBUG 0x5e32 7060 #define mmCNV_INPUT_SELECT 0x5e33 7061 #define mmWB_SOFT_RESET 0x5e36 7062 #define mmCNV_TEST_DEBUG_INDEX 0x5e34 7063 #define mmCNV_TEST_DEBUG_DATA 0x5e35 7064 #define mmDCFE_CLOCK_CONTROL 0x1b00 7065 #define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 7066 #define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 7067 #define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 7068 #define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 7069 #define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 7070 #define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 7071 #define mmDCFE_SOFT_RESET 0x1b01 7072 #define mmDCFE0_DCFE_SOFT_RESET 0x1b01 7073 #define mmDCFE1_DCFE_SOFT_RESET 0x1d01 7074 #define mmDCFE2_DCFE_SOFT_RESET 0x1f01 7075 #define mmDCFE3_DCFE_SOFT_RESET 0x4101 7076 #define mmDCFE4_DCFE_SOFT_RESET 0x4301 7077 #define mmDCFE5_DCFE_SOFT_RESET 0x4501 7078 #define mmDCFE_DBG_CONFIG 0x1b02 7079 #define mmDCFE0_DCFE_DBG_CONFIG 0x1b02 7080 #define mmDCFE1_DCFE_DBG_CONFIG 0x1d02 7081 #define mmDCFE2_DCFE_DBG_CONFIG 0x1f02 7082 #define mmDCFE3_DCFE_DBG_CONFIG 0x4102 7083 #define mmDCFE4_DCFE_DBG_CONFIG 0x4302 7084 #define mmDCFE5_DCFE_DBG_CONFIG 0x4502 7085 #define mmDCFEV_CLOCK_CONTROL 0x46f4 7086 #define mmDCFEV_SOFT_RESET 0x46f5 7087 #define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 7088 #define mmDCFEV_DBG_CONFIG 0x46f7 7089 #define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 7090 #define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 7091 #define mmDC_HPD_INT_STATUS 0x1898 7092 #define mmHPD0_DC_HPD_INT_STATUS 0x1898 7093 #define mmHPD1_DC_HPD_INT_STATUS 0x18a0 7094 #define mmHPD2_DC_HPD_INT_STATUS 0x18a8 7095 #define mmHPD3_DC_HPD_INT_STATUS 0x18b0 7096 #define mmHPD4_DC_HPD_INT_STATUS 0x18b8 7097 #define mmHPD5_DC_HPD_INT_STATUS 0x18c0 7098 #define mmDC_HPD_INT_CONTROL 0x1899 7099 #define mmHPD0_DC_HPD_INT_CONTROL 0x1899 7100 #define mmHPD1_DC_HPD_INT_CONTROL 0x18a1 7101 #define mmHPD2_DC_HPD_INT_CONTROL 0x18a9 7102 #define mmHPD3_DC_HPD_INT_CONTROL 0x18b1 7103 #define mmHPD4_DC_HPD_INT_CONTROL 0x18b9 7104 #define mmHPD5_DC_HPD_INT_CONTROL 0x18c1 7105 #define mmDC_HPD_CONTROL 0x189a 7106 #define mmHPD0_DC_HPD_CONTROL 0x189a 7107 #define mmHPD1_DC_HPD_CONTROL 0x18a2 7108 #define mmHPD2_DC_HPD_CONTROL 0x18aa 7109 #define mmHPD3_DC_HPD_CONTROL 0x18b2 7110 #define mmHPD4_DC_HPD_CONTROL 0x18ba 7111 #define mmHPD5_DC_HPD_CONTROL 0x18c2 7112 #define mmDC_HPD_FAST_TRAIN_CNTL 0x189b 7113 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b 7114 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 7115 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab 7116 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 7117 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb 7118 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 7119 #define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c 7120 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c 7121 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 7122 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac 7123 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 7124 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc 7125 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 7126 #define mmDCO_SCRATCH0 0x184e 7127 #define mmDCO_SCRATCH1 0x184f 7128 #define mmDCO_SCRATCH2 0x1850 7129 #define mmDCO_SCRATCH3 0x1851 7130 #define mmDCO_SCRATCH4 0x1852 7131 #define mmDCO_SCRATCH5 0x1853 7132 #define mmDCO_SCRATCH6 0x1854 7133 #define mmDCO_SCRATCH7 0x1855 7134 #define mmDCE_VCE_CONTROL 0x1856 7135 #define mmDISP_INTERRUPT_STATUS 0x1857 7136 #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 7137 #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 7138 #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a 7139 #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b 7140 #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c 7141 #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d 7142 #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e 7143 #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f 7144 #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 7145 #define mmDCO_MEM_PWR_STATUS 0x1861 7146 #define mmDCO_MEM_PWR_CTRL 0x1862 7147 #define mmDCO_MEM_PWR_CTRL2 0x1863 7148 #define mmDCO_CLK_CNTL 0x1864 7149 #define mmDCO_CLK_RAMP_CNTL 0x1865 7150 #define mmDPDBG_CNTL 0x1866 7151 #define mmDPDBG_INTERRUPT 0x1867 7152 #define mmDCO_POWER_MANAGEMENT_CNTL 0x1868 7153 #define mmDCO_SOFT_RESET 0x1871 7154 #define mmDIG_SOFT_RESET 0x1872 7155 #define mmDCO_STEREOSYNC_SEL 0x186e 7156 #define mmDCO_TEST_DEBUG_INDEX 0x186f 7157 #define mmDCO_TEST_DEBUG_DATA 0x1870 7158 #define mmDC_I2C_CONTROL 0x16d4 7159 #define mmDC_I2C_ARBITRATION 0x16d5 7160 #define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 7161 #define mmDC_I2C_SW_STATUS 0x16d7 7162 #define mmDC_I2C_DDC1_HW_STATUS 0x16d8 7163 #define mmDC_I2C_DDC2_HW_STATUS 0x16d9 7164 #define mmDC_I2C_DDC3_HW_STATUS 0x16da 7165 #define mmDC_I2C_DDC4_HW_STATUS 0x16db 7166 #define mmDC_I2C_DDC5_HW_STATUS 0x16dc 7167 #define mmDC_I2C_DDC6_HW_STATUS 0x16dd 7168 #define mmDC_I2C_DDC1_SPEED 0x16de 7169 #define mmDC_I2C_DDC1_SETUP 0x16df 7170 #define mmDC_I2C_DDC2_SPEED 0x16e0 7171 #define mmDC_I2C_DDC2_SETUP 0x16e1 7172 #define mmDC_I2C_DDC3_SPEED 0x16e2 7173 #define mmDC_I2C_DDC3_SETUP 0x16e3 7174 #define mmDC_I2C_DDC4_SPEED 0x16e4 7175 #define mmDC_I2C_DDC4_SETUP 0x16e5 7176 #define mmDC_I2C_DDC5_SPEED 0x16e6 7177 #define mmDC_I2C_DDC5_SETUP 0x16e7 7178 #define mmDC_I2C_DDC6_SPEED 0x16e8 7179 #define mmDC_I2C_DDC6_SETUP 0x16e9 7180 #define mmDC_I2C_TRANSACTION0 0x16ea 7181 #define mmDC_I2C_TRANSACTION1 0x16eb 7182 #define mmDC_I2C_TRANSACTION2 0x16ec 7183 #define mmDC_I2C_TRANSACTION3 0x16ed 7184 #define mmDC_I2C_DATA 0x16ee 7185 #define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef 7186 #define mmDC_I2C_DDCVGA_SPEED 0x16f0 7187 #define mmDC_I2C_DDCVGA_SETUP 0x16f1 7188 #define mmDC_I2C_EDID_DETECT_CTRL 0x16f2 7189 #define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 7190 #define mmGENERIC_I2C_CONTROL 0x16f4 7191 #define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 7192 #define mmGENERIC_I2C_STATUS 0x16f6 7193 #define mmGENERIC_I2C_SPEED 0x16f7 7194 #define mmGENERIC_I2C_SETUP 0x16f8 7195 #define mmGENERIC_I2C_TRANSACTION 0x16f9 7196 #define mmGENERIC_I2C_DATA 0x16fa 7197 #define mmGENERIC_I2C_PIN_SELECTION 0x16fb 7198 #define mmGENERIC_I2C_PIN_DEBUG 0x16fc 7199 #define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 7200 #define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 7201 #define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 7202 #define mmXDMA_INTERRUPT 0x3e3 7203 #define mmXDMA_CLOCK_GATING_CNTL 0x3e4 7204 #define mmXDMA_MEM_POWER_CNTL 0x3e6 7205 #define mmXDMA_IF_BIF_STATUS 0x3e7 7206 #define mmXDMA_PERF_MEAS_STATUS 0x3e8 7207 #define mmXDMA_IF_STATUS 0x3e9 7208 #define mmXDMA_TEST_DEBUG_INDEX 0x3ea 7209 #define mmXDMA_TEST_DEBUG_DATA 0x3eb 7210 #define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 7211 #define mmXDMA_PG_CONTROL 0x3f9 7212 #define mmXDMA_PG_WDATA 0x3fa 7213 #define mmXDMA_PG_STATUS 0x3fb 7214 #define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc 7215 #define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd 7216 #define mmXDMA_MSTR_CNTL 0x3ec 7217 #define mmXDMA_MSTR_STATUS 0x3ed 7218 #define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee 7219 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef 7220 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 7221 #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 7222 #define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 7223 #define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 7224 #define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 7225 #define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 7226 #define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 7227 #define mmXDMA_MSTR_PIPE_CNTL 0x400 7228 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 7229 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 7230 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 7231 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 7232 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 7233 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 7234 #define mmXDMA_MSTR_READ_COMMAND 0x401 7235 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 7236 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 7237 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 7238 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 7239 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 7240 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 7241 #define mmXDMA_MSTR_CHANNEL_DIM 0x402 7242 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 7243 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 7244 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 7245 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 7246 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 7247 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 7248 #define mmXDMA_MSTR_HEIGHT 0x403 7249 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 7250 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 7251 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 7252 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 7253 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 7254 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 7255 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 7256 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 7257 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 7258 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 7259 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 7260 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 7261 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 7262 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 7263 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 7264 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 7265 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 7266 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 7267 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 7268 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 7269 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 7270 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 7271 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 7272 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 7273 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 7274 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 7275 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 7276 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 7277 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 7278 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 7279 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 7280 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 7281 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 7282 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 7283 #define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 7284 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 7285 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 7286 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 7287 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 7288 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 7289 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 7290 #define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 7291 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 7292 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 7293 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 7294 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 7295 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 7296 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 7297 #define mmXDMA_MSTR_CACHE 0x40a 7298 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a 7299 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a 7300 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a 7301 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a 7302 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a 7303 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a 7304 #define mmXDMA_MSTR_CHANNEL_START 0x40b 7305 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b 7306 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b 7307 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b 7308 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b 7309 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b 7310 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b 7311 #define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e 7312 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e 7313 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e 7314 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e 7315 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e 7316 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e 7317 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e 7318 #define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f 7319 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f 7320 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f 7321 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f 7322 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f 7323 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f 7324 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f 7325 #define mmXDMA_SLV_CNTL 0x460 7326 #define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 7327 #define mmXDMA_SLV_SLS_PITCH 0x462 7328 #define mmXDMA_SLV_READ_URGENT_CNTL 0x463 7329 #define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 7330 #define mmXDMA_SLV_WB_RATE_CNTL 0x465 7331 #define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 7332 #define mmXDMA_SLV_READ_LATENCY_AVE 0x467 7333 #define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 7334 #define mmXDMA_SLV_MEM_NACK_STATUS 0x469 7335 #define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a 7336 #define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b 7337 #define mmXDMA_SLV_FLIP_PENDING 0x46c 7338 #define mmXDMA_SLV_CHANNEL_CNTL 0x470 7339 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 7340 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 7341 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 7342 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 7343 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 7344 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 7345 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 7346 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 7347 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 7348 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 7349 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 7350 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 7351 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 7352 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 7353 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 7354 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a 7355 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 7356 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a 7357 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 7358 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a 7359 7360 #endif /* DCE_10_0_D_H */ 7361