1 /* $NetBSD: dce_11_2_d.h,v 1.2 2021/12/18 23:45:10 riastradh Exp $ */ 2 3 /* 4 * DCE_11_2 Register documentation 5 * 6 * Copyright (C) 2016 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef DCE_11_2_D_H 27 #define DCE_11_2_D_H 28 29 #define mmPIPE0_PG_CONFIG 0x2c0 30 #define mmPIPE0_PG_ENABLE 0x2c1 31 #define mmPIPE0_PG_STATUS 0x2c2 32 #define mmPIPE1_PG_CONFIG 0x2c3 33 #define mmPIPE1_PG_ENABLE 0x2c4 34 #define mmPIPE1_PG_STATUS 0x2c5 35 #define mmPIPE2_PG_CONFIG 0x2c6 36 #define mmPIPE2_PG_ENABLE 0x2c7 37 #define mmPIPE2_PG_STATUS 0x2c8 38 #define mmPIPE3_PG_CONFIG 0x2c9 39 #define mmPIPE3_PG_ENABLE 0x2ca 40 #define mmPIPE3_PG_STATUS 0x2cb 41 #define mmPIPE4_PG_CONFIG 0x2cc 42 #define mmPIPE4_PG_ENABLE 0x2cd 43 #define mmPIPE4_PG_STATUS 0x2ce 44 #define mmPIPE5_PG_CONFIG 0x2cf 45 #define mmPIPE5_PG_ENABLE 0x2d0 46 #define mmPIPE5_PG_STATUS 0x2d1 47 #define mmDCPG_INTERRUPT_STATUS 0x2de 48 #define mmDCPG_INTERRUPT_CONTROL 0x2df 49 #define mmDCPG_INTERRUPT_CONTROL2 0x2e0 50 #define mmDC_IP_REQUEST_CNTL 0x2d2 51 #define mmDC_PGFSM_CONFIG_REG 0x2d3 52 #define mmDC_PGFSM_WRITE_REG 0x2d4 53 #define mmDC_PGCNTL_STATUS_REG 0x2d5 54 #define mmDCPG_TEST_DEBUG_INDEX 0x2d6 55 #define mmDCPG_TEST_DEBUG_DATA 0x2d7 56 #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 57 #define mmBL1_PWM_USER_LEVEL 0x1629 58 #define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a 59 #define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b 60 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c 61 #define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d 62 #define mmBL1_PWM_ABM_CNTL 0x162e 63 #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f 64 #define mmBL1_PWM_GRP2_REG_LOCK 0x1630 65 #define mmDC_ABM1_CNTL 0x1638 66 #define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 67 #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a 68 #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b 69 #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c 70 #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d 71 #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e 72 #define mmDC_ABM1_ACE_THRES_12 0x163f 73 #define mmDC_ABM1_ACE_THRES_34 0x1640 74 #define mmDC_ABM1_ACE_CNTL_MISC 0x1641 75 #define mmDC_ABM1_DEBUG_MISC 0x1649 76 #define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a 77 #define mmDC_ABM1_HG_MISC_CTRL 0x164b 78 #define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c 79 #define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d 80 #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e 81 #define mmDC_ABM1_LS_PIXEL_COUNT 0x164f 82 #define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 83 #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 84 #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 85 #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 86 #define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 87 #define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 88 #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 89 #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 90 #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 91 #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 92 #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a 93 #define mmDC_ABM1_HG_RESULT_1 0x165b 94 #define mmDC_ABM1_HG_RESULT_2 0x165c 95 #define mmDC_ABM1_HG_RESULT_3 0x165d 96 #define mmDC_ABM1_HG_RESULT_4 0x165e 97 #define mmDC_ABM1_HG_RESULT_5 0x165f 98 #define mmDC_ABM1_HG_RESULT_6 0x1660 99 #define mmDC_ABM1_HG_RESULT_7 0x1661 100 #define mmDC_ABM1_HG_RESULT_8 0x1662 101 #define mmDC_ABM1_HG_RESULT_9 0x1663 102 #define mmDC_ABM1_HG_RESULT_10 0x1664 103 #define mmDC_ABM1_HG_RESULT_11 0x1665 104 #define mmDC_ABM1_HG_RESULT_12 0x1666 105 #define mmDC_ABM1_HG_RESULT_13 0x1667 106 #define mmDC_ABM1_HG_RESULT_14 0x1668 107 #define mmDC_ABM1_HG_RESULT_15 0x1669 108 #define mmDC_ABM1_HG_RESULT_16 0x166a 109 #define mmDC_ABM1_HG_RESULT_17 0x166b 110 #define mmDC_ABM1_HG_RESULT_18 0x166c 111 #define mmDC_ABM1_HG_RESULT_19 0x166d 112 #define mmDC_ABM1_HG_RESULT_20 0x166e 113 #define mmDC_ABM1_HG_RESULT_21 0x166f 114 #define mmDC_ABM1_HG_RESULT_22 0x1670 115 #define mmDC_ABM1_HG_RESULT_23 0x1671 116 #define mmDC_ABM1_HG_RESULT_24 0x1672 117 #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b 118 #define mmDC_ABM1_BL_MASTER_LOCK 0x169c 119 #define mmABM_TEST_DEBUG_INDEX 0x169e 120 #define mmABM_TEST_DEBUG_DATA 0x169f 121 #define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d 122 #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d 123 #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d 124 #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d 125 #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d 126 #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d 127 #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d 128 #define mmCRTC_H_TOTAL 0x1b80 129 #define mmCRTC0_CRTC_H_TOTAL 0x1b80 130 #define mmCRTC1_CRTC_H_TOTAL 0x1d80 131 #define mmCRTC2_CRTC_H_TOTAL 0x1f80 132 #define mmCRTC3_CRTC_H_TOTAL 0x4180 133 #define mmCRTC4_CRTC_H_TOTAL 0x4380 134 #define mmCRTC5_CRTC_H_TOTAL 0x4580 135 #define mmCRTC_H_BLANK_START_END 0x1b81 136 #define mmCRTC0_CRTC_H_BLANK_START_END 0x1b81 137 #define mmCRTC1_CRTC_H_BLANK_START_END 0x1d81 138 #define mmCRTC2_CRTC_H_BLANK_START_END 0x1f81 139 #define mmCRTC3_CRTC_H_BLANK_START_END 0x4181 140 #define mmCRTC4_CRTC_H_BLANK_START_END 0x4381 141 #define mmCRTC5_CRTC_H_BLANK_START_END 0x4581 142 #define mmCRTC_H_SYNC_A 0x1b82 143 #define mmCRTC0_CRTC_H_SYNC_A 0x1b82 144 #define mmCRTC1_CRTC_H_SYNC_A 0x1d82 145 #define mmCRTC2_CRTC_H_SYNC_A 0x1f82 146 #define mmCRTC3_CRTC_H_SYNC_A 0x4182 147 #define mmCRTC4_CRTC_H_SYNC_A 0x4382 148 #define mmCRTC5_CRTC_H_SYNC_A 0x4582 149 #define mmCRTC_H_SYNC_A_CNTL 0x1b83 150 #define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83 151 #define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83 152 #define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83 153 #define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183 154 #define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383 155 #define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583 156 #define mmCRTC_H_SYNC_B 0x1b84 157 #define mmCRTC0_CRTC_H_SYNC_B 0x1b84 158 #define mmCRTC1_CRTC_H_SYNC_B 0x1d84 159 #define mmCRTC2_CRTC_H_SYNC_B 0x1f84 160 #define mmCRTC3_CRTC_H_SYNC_B 0x4184 161 #define mmCRTC4_CRTC_H_SYNC_B 0x4384 162 #define mmCRTC5_CRTC_H_SYNC_B 0x4584 163 #define mmCRTC_H_SYNC_B_CNTL 0x1b85 164 #define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85 165 #define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85 166 #define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85 167 #define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185 168 #define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385 169 #define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585 170 #define mmCRTC_VBI_END 0x1b86 171 #define mmCRTC0_CRTC_VBI_END 0x1b86 172 #define mmCRTC1_CRTC_VBI_END 0x1d86 173 #define mmCRTC2_CRTC_VBI_END 0x1f86 174 #define mmCRTC3_CRTC_VBI_END 0x4186 175 #define mmCRTC4_CRTC_VBI_END 0x4386 176 #define mmCRTC5_CRTC_VBI_END 0x4586 177 #define mmCRTC_V_TOTAL 0x1b87 178 #define mmCRTC0_CRTC_V_TOTAL 0x1b87 179 #define mmCRTC1_CRTC_V_TOTAL 0x1d87 180 #define mmCRTC2_CRTC_V_TOTAL 0x1f87 181 #define mmCRTC3_CRTC_V_TOTAL 0x4187 182 #define mmCRTC4_CRTC_V_TOTAL 0x4387 183 #define mmCRTC5_CRTC_V_TOTAL 0x4587 184 #define mmCRTC_V_TOTAL_MIN 0x1b88 185 #define mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88 186 #define mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88 187 #define mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88 188 #define mmCRTC3_CRTC_V_TOTAL_MIN 0x4188 189 #define mmCRTC4_CRTC_V_TOTAL_MIN 0x4388 190 #define mmCRTC5_CRTC_V_TOTAL_MIN 0x4588 191 #define mmCRTC_V_TOTAL_MAX 0x1b89 192 #define mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89 193 #define mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89 194 #define mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89 195 #define mmCRTC3_CRTC_V_TOTAL_MAX 0x4189 196 #define mmCRTC4_CRTC_V_TOTAL_MAX 0x4389 197 #define mmCRTC5_CRTC_V_TOTAL_MAX 0x4589 198 #define mmCRTC_V_TOTAL_CONTROL 0x1b8a 199 #define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a 200 #define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a 201 #define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a 202 #define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a 203 #define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a 204 #define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a 205 #define mmCRTC_V_TOTAL_INT_STATUS 0x1b8b 206 #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b 207 #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b 208 #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b 209 #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b 210 #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b 211 #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b 212 #define mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c 213 #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c 214 #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c 215 #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c 216 #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c 217 #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c 218 #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c 219 #define mmCRTC_V_BLANK_START_END 0x1b8d 220 #define mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d 221 #define mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d 222 #define mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d 223 #define mmCRTC3_CRTC_V_BLANK_START_END 0x418d 224 #define mmCRTC4_CRTC_V_BLANK_START_END 0x438d 225 #define mmCRTC5_CRTC_V_BLANK_START_END 0x458d 226 #define mmCRTC_V_SYNC_A 0x1b8e 227 #define mmCRTC0_CRTC_V_SYNC_A 0x1b8e 228 #define mmCRTC1_CRTC_V_SYNC_A 0x1d8e 229 #define mmCRTC2_CRTC_V_SYNC_A 0x1f8e 230 #define mmCRTC3_CRTC_V_SYNC_A 0x418e 231 #define mmCRTC4_CRTC_V_SYNC_A 0x438e 232 #define mmCRTC5_CRTC_V_SYNC_A 0x458e 233 #define mmCRTC_V_SYNC_A_CNTL 0x1b8f 234 #define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f 235 #define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f 236 #define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f 237 #define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f 238 #define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f 239 #define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f 240 #define mmCRTC_V_SYNC_B 0x1b90 241 #define mmCRTC0_CRTC_V_SYNC_B 0x1b90 242 #define mmCRTC1_CRTC_V_SYNC_B 0x1d90 243 #define mmCRTC2_CRTC_V_SYNC_B 0x1f90 244 #define mmCRTC3_CRTC_V_SYNC_B 0x4190 245 #define mmCRTC4_CRTC_V_SYNC_B 0x4390 246 #define mmCRTC5_CRTC_V_SYNC_B 0x4590 247 #define mmCRTC_V_SYNC_B_CNTL 0x1b91 248 #define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91 249 #define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91 250 #define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91 251 #define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191 252 #define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391 253 #define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591 254 #define mmCRTC_DTMTEST_CNTL 0x1b92 255 #define mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92 256 #define mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92 257 #define mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92 258 #define mmCRTC3_CRTC_DTMTEST_CNTL 0x4192 259 #define mmCRTC4_CRTC_DTMTEST_CNTL 0x4392 260 #define mmCRTC5_CRTC_DTMTEST_CNTL 0x4592 261 #define mmCRTC_DTMTEST_STATUS_POSITION 0x1b93 262 #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93 263 #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93 264 #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93 265 #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193 266 #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393 267 #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593 268 #define mmCRTC_TRIGA_CNTL 0x1b94 269 #define mmCRTC0_CRTC_TRIGA_CNTL 0x1b94 270 #define mmCRTC1_CRTC_TRIGA_CNTL 0x1d94 271 #define mmCRTC2_CRTC_TRIGA_CNTL 0x1f94 272 #define mmCRTC3_CRTC_TRIGA_CNTL 0x4194 273 #define mmCRTC4_CRTC_TRIGA_CNTL 0x4394 274 #define mmCRTC5_CRTC_TRIGA_CNTL 0x4594 275 #define mmCRTC_TRIGA_MANUAL_TRIG 0x1b95 276 #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95 277 #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95 278 #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95 279 #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195 280 #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395 281 #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595 282 #define mmCRTC_TRIGB_CNTL 0x1b96 283 #define mmCRTC0_CRTC_TRIGB_CNTL 0x1b96 284 #define mmCRTC1_CRTC_TRIGB_CNTL 0x1d96 285 #define mmCRTC2_CRTC_TRIGB_CNTL 0x1f96 286 #define mmCRTC3_CRTC_TRIGB_CNTL 0x4196 287 #define mmCRTC4_CRTC_TRIGB_CNTL 0x4396 288 #define mmCRTC5_CRTC_TRIGB_CNTL 0x4596 289 #define mmCRTC_TRIGB_MANUAL_TRIG 0x1b97 290 #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97 291 #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97 292 #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97 293 #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197 294 #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397 295 #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597 296 #define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98 297 #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98 298 #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98 299 #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98 300 #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 301 #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398 302 #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598 303 #define mmCRTC_FLOW_CONTROL 0x1b99 304 #define mmCRTC0_CRTC_FLOW_CONTROL 0x1b99 305 #define mmCRTC1_CRTC_FLOW_CONTROL 0x1d99 306 #define mmCRTC2_CRTC_FLOW_CONTROL 0x1f99 307 #define mmCRTC3_CRTC_FLOW_CONTROL 0x4199 308 #define mmCRTC4_CRTC_FLOW_CONTROL 0x4399 309 #define mmCRTC5_CRTC_FLOW_CONTROL 0x4599 310 #define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a 311 #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a 312 #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a 313 #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a 314 #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a 315 #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a 316 #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a 317 #define mmCRTC_AVSYNC_COUNTER 0x1b9b 318 #define mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b 319 #define mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b 320 #define mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b 321 #define mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b 322 #define mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b 323 #define mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b 324 #define mmCRTC_CONTROL 0x1b9c 325 #define mmCRTC0_CRTC_CONTROL 0x1b9c 326 #define mmCRTC1_CRTC_CONTROL 0x1d9c 327 #define mmCRTC2_CRTC_CONTROL 0x1f9c 328 #define mmCRTC3_CRTC_CONTROL 0x419c 329 #define mmCRTC4_CRTC_CONTROL 0x439c 330 #define mmCRTC5_CRTC_CONTROL 0x459c 331 #define mmCRTC_BLANK_CONTROL 0x1b9d 332 #define mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d 333 #define mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d 334 #define mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d 335 #define mmCRTC3_CRTC_BLANK_CONTROL 0x419d 336 #define mmCRTC4_CRTC_BLANK_CONTROL 0x439d 337 #define mmCRTC5_CRTC_BLANK_CONTROL 0x459d 338 #define mmCRTC_INTERLACE_CONTROL 0x1b9e 339 #define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e 340 #define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e 341 #define mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e 342 #define mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e 343 #define mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e 344 #define mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e 345 #define mmCRTC_INTERLACE_STATUS 0x1b9f 346 #define mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f 347 #define mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f 348 #define mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f 349 #define mmCRTC3_CRTC_INTERLACE_STATUS 0x419f 350 #define mmCRTC4_CRTC_INTERLACE_STATUS 0x439f 351 #define mmCRTC5_CRTC_INTERLACE_STATUS 0x459f 352 #define mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0 353 #define mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0 354 #define mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0 355 #define mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0 356 #define mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0 357 #define mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0 358 #define mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0 359 #define mmCRTC_PIXEL_DATA_READBACK0 0x1ba1 360 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1 361 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1 362 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1 363 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1 364 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1 365 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1 366 #define mmCRTC_PIXEL_DATA_READBACK1 0x1ba2 367 #define mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2 368 #define mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2 369 #define mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2 370 #define mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2 371 #define mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2 372 #define mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2 373 #define mmCRTC_STATUS 0x1ba3 374 #define mmCRTC0_CRTC_STATUS 0x1ba3 375 #define mmCRTC1_CRTC_STATUS 0x1da3 376 #define mmCRTC2_CRTC_STATUS 0x1fa3 377 #define mmCRTC3_CRTC_STATUS 0x41a3 378 #define mmCRTC4_CRTC_STATUS 0x43a3 379 #define mmCRTC5_CRTC_STATUS 0x45a3 380 #define mmCRTC_STATUS_POSITION 0x1ba4 381 #define mmCRTC0_CRTC_STATUS_POSITION 0x1ba4 382 #define mmCRTC1_CRTC_STATUS_POSITION 0x1da4 383 #define mmCRTC2_CRTC_STATUS_POSITION 0x1fa4 384 #define mmCRTC3_CRTC_STATUS_POSITION 0x41a4 385 #define mmCRTC4_CRTC_STATUS_POSITION 0x43a4 386 #define mmCRTC5_CRTC_STATUS_POSITION 0x45a4 387 #define mmCRTC_NOM_VERT_POSITION 0x1ba5 388 #define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5 389 #define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5 390 #define mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5 391 #define mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5 392 #define mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5 393 #define mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5 394 #define mmCRTC_STATUS_FRAME_COUNT 0x1ba6 395 #define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6 396 #define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6 397 #define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6 398 #define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6 399 #define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6 400 #define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6 401 #define mmCRTC_STATUS_VF_COUNT 0x1ba7 402 #define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7 403 #define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7 404 #define mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7 405 #define mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7 406 #define mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7 407 #define mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7 408 #define mmCRTC_STATUS_HV_COUNT 0x1ba8 409 #define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8 410 #define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8 411 #define mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8 412 #define mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8 413 #define mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8 414 #define mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8 415 #define mmCRTC_COUNT_CONTROL 0x1ba9 416 #define mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9 417 #define mmCRTC1_CRTC_COUNT_CONTROL 0x1da9 418 #define mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9 419 #define mmCRTC3_CRTC_COUNT_CONTROL 0x41a9 420 #define mmCRTC4_CRTC_COUNT_CONTROL 0x43a9 421 #define mmCRTC5_CRTC_COUNT_CONTROL 0x45a9 422 #define mmCRTC_COUNT_RESET 0x1baa 423 #define mmCRTC0_CRTC_COUNT_RESET 0x1baa 424 #define mmCRTC1_CRTC_COUNT_RESET 0x1daa 425 #define mmCRTC2_CRTC_COUNT_RESET 0x1faa 426 #define mmCRTC3_CRTC_COUNT_RESET 0x41aa 427 #define mmCRTC4_CRTC_COUNT_RESET 0x43aa 428 #define mmCRTC5_CRTC_COUNT_RESET 0x45aa 429 #define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab 430 #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab 431 #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab 432 #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab 433 #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab 434 #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab 435 #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab 436 #define mmCRTC_VERT_SYNC_CONTROL 0x1bac 437 #define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac 438 #define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac 439 #define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac 440 #define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac 441 #define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac 442 #define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac 443 #define mmCRTC_STEREO_STATUS 0x1bad 444 #define mmCRTC0_CRTC_STEREO_STATUS 0x1bad 445 #define mmCRTC1_CRTC_STEREO_STATUS 0x1dad 446 #define mmCRTC2_CRTC_STEREO_STATUS 0x1fad 447 #define mmCRTC3_CRTC_STEREO_STATUS 0x41ad 448 #define mmCRTC4_CRTC_STEREO_STATUS 0x43ad 449 #define mmCRTC5_CRTC_STEREO_STATUS 0x45ad 450 #define mmCRTC_STEREO_CONTROL 0x1bae 451 #define mmCRTC0_CRTC_STEREO_CONTROL 0x1bae 452 #define mmCRTC1_CRTC_STEREO_CONTROL 0x1dae 453 #define mmCRTC2_CRTC_STEREO_CONTROL 0x1fae 454 #define mmCRTC3_CRTC_STEREO_CONTROL 0x41ae 455 #define mmCRTC4_CRTC_STEREO_CONTROL 0x43ae 456 #define mmCRTC5_CRTC_STEREO_CONTROL 0x45ae 457 #define mmCRTC_SNAPSHOT_STATUS 0x1baf 458 #define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf 459 #define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf 460 #define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf 461 #define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af 462 #define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af 463 #define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af 464 #define mmCRTC_SNAPSHOT_CONTROL 0x1bb0 465 #define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0 466 #define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0 467 #define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0 468 #define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0 469 #define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0 470 #define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0 471 #define mmCRTC_SNAPSHOT_POSITION 0x1bb1 472 #define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1 473 #define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1 474 #define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1 475 #define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1 476 #define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1 477 #define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1 478 #define mmCRTC_SNAPSHOT_FRAME 0x1bb2 479 #define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2 480 #define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2 481 #define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2 482 #define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2 483 #define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2 484 #define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2 485 #define mmCRTC_START_LINE_CONTROL 0x1bb3 486 #define mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3 487 #define mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3 488 #define mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3 489 #define mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3 490 #define mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3 491 #define mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3 492 #define mmCRTC_INTERRUPT_CONTROL 0x1bb4 493 #define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4 494 #define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4 495 #define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4 496 #define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4 497 #define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4 498 #define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4 499 #define mmCRTC_UPDATE_LOCK 0x1bb5 500 #define mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5 501 #define mmCRTC1_CRTC_UPDATE_LOCK 0x1db5 502 #define mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5 503 #define mmCRTC3_CRTC_UPDATE_LOCK 0x41b5 504 #define mmCRTC4_CRTC_UPDATE_LOCK 0x43b5 505 #define mmCRTC5_CRTC_UPDATE_LOCK 0x45b5 506 #define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 507 #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6 508 #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6 509 #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6 510 #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6 511 #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6 512 #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6 513 #define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 514 #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7 515 #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7 516 #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7 517 #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7 518 #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7 519 #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7 520 #define mmCRTC_TEST_PATTERN_CONTROL 0x1bba 521 #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba 522 #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba 523 #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba 524 #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba 525 #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba 526 #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba 527 #define mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb 528 #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb 529 #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb 530 #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb 531 #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb 532 #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb 533 #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb 534 #define mmCRTC_TEST_PATTERN_COLOR 0x1bbc 535 #define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc 536 #define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc 537 #define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc 538 #define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc 539 #define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc 540 #define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc 541 #define mmCRTC_MASTER_UPDATE_LOCK 0x1bbd 542 #define mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd 543 #define mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd 544 #define mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd 545 #define mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd 546 #define mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd 547 #define mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd 548 #define mmCRTC_MASTER_UPDATE_MODE 0x1bbe 549 #define mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe 550 #define mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe 551 #define mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe 552 #define mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be 553 #define mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be 554 #define mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be 555 #define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf 556 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf 557 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf 558 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf 559 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf 560 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf 561 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf 562 #define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 563 #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0 564 #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0 565 #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0 566 #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0 567 #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0 568 #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0 569 #define mmCRTC_MVP_STATUS 0x1bc1 570 #define mmCRTC0_CRTC_MVP_STATUS 0x1bc1 571 #define mmCRTC1_CRTC_MVP_STATUS 0x1dc1 572 #define mmCRTC2_CRTC_MVP_STATUS 0x1fc1 573 #define mmCRTC3_CRTC_MVP_STATUS 0x41c1 574 #define mmCRTC4_CRTC_MVP_STATUS 0x43c1 575 #define mmCRTC5_CRTC_MVP_STATUS 0x45c1 576 #define mmCRTC_MASTER_EN 0x1bc2 577 #define mmCRTC0_CRTC_MASTER_EN 0x1bc2 578 #define mmCRTC1_CRTC_MASTER_EN 0x1dc2 579 #define mmCRTC2_CRTC_MASTER_EN 0x1fc2 580 #define mmCRTC3_CRTC_MASTER_EN 0x41c2 581 #define mmCRTC4_CRTC_MASTER_EN 0x43c2 582 #define mmCRTC5_CRTC_MASTER_EN 0x45c2 583 #define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 584 #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3 585 #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3 586 #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3 587 #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3 588 #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3 589 #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3 590 #define mmCRTC_V_UPDATE_INT_STATUS 0x1bc4 591 #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4 592 #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4 593 #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4 594 #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4 595 #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4 596 #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4 597 #define mmCRTC_OVERSCAN_COLOR 0x1bc8 598 #define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8 599 #define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8 600 #define mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8 601 #define mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8 602 #define mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8 603 #define mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8 604 #define mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9 605 #define mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9 606 #define mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9 607 #define mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9 608 #define mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9 609 #define mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9 610 #define mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9 611 #define mmCRTC_BLANK_DATA_COLOR 0x1bca 612 #define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca 613 #define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca 614 #define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca 615 #define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca 616 #define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca 617 #define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca 618 #define mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb 619 #define mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb 620 #define mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb 621 #define mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb 622 #define mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb 623 #define mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb 624 #define mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb 625 #define mmCRTC_BLACK_COLOR 0x1bcc 626 #define mmCRTC0_CRTC_BLACK_COLOR 0x1bcc 627 #define mmCRTC1_CRTC_BLACK_COLOR 0x1dcc 628 #define mmCRTC2_CRTC_BLACK_COLOR 0x1fcc 629 #define mmCRTC3_CRTC_BLACK_COLOR 0x41cc 630 #define mmCRTC4_CRTC_BLACK_COLOR 0x43cc 631 #define mmCRTC5_CRTC_BLACK_COLOR 0x45cc 632 #define mmCRTC_BLACK_COLOR_EXT 0x1bcd 633 #define mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd 634 #define mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd 635 #define mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd 636 #define mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd 637 #define mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd 638 #define mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd 639 #define mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce 640 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce 641 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce 642 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce 643 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce 644 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce 645 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce 646 #define mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf 647 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf 648 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf 649 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf 650 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf 651 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf 652 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf 653 #define mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 654 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0 655 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0 656 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0 657 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0 658 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0 659 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0 660 #define mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 661 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1 662 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1 663 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1 664 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1 665 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1 666 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1 667 #define mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 668 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2 669 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2 670 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2 671 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2 672 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2 673 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2 674 #define mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 675 #define mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3 676 #define mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3 677 #define mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3 678 #define mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3 679 #define mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3 680 #define mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3 681 #define mmCRTC_CRC_CNTL 0x1bd4 682 #define mmCRTC0_CRTC_CRC_CNTL 0x1bd4 683 #define mmCRTC1_CRTC_CRC_CNTL 0x1dd4 684 #define mmCRTC2_CRTC_CRC_CNTL 0x1fd4 685 #define mmCRTC3_CRTC_CRC_CNTL 0x41d4 686 #define mmCRTC4_CRTC_CRC_CNTL 0x43d4 687 #define mmCRTC5_CRTC_CRC_CNTL 0x45d4 688 #define mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 689 #define mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5 690 #define mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5 691 #define mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5 692 #define mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5 693 #define mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5 694 #define mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5 695 #define mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 696 #define mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6 697 #define mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6 698 #define mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6 699 #define mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6 700 #define mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6 701 #define mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6 702 #define mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 703 #define mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7 704 #define mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7 705 #define mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7 706 #define mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7 707 #define mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7 708 #define mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7 709 #define mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 710 #define mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8 711 #define mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8 712 #define mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8 713 #define mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8 714 #define mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8 715 #define mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8 716 #define mmCRTC_CRC0_DATA_RG 0x1bd9 717 #define mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9 718 #define mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9 719 #define mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9 720 #define mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9 721 #define mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9 722 #define mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9 723 #define mmCRTC_CRC0_DATA_B 0x1bda 724 #define mmCRTC0_CRTC_CRC0_DATA_B 0x1bda 725 #define mmCRTC1_CRTC_CRC0_DATA_B 0x1dda 726 #define mmCRTC2_CRTC_CRC0_DATA_B 0x1fda 727 #define mmCRTC3_CRTC_CRC0_DATA_B 0x41da 728 #define mmCRTC4_CRTC_CRC0_DATA_B 0x43da 729 #define mmCRTC5_CRTC_CRC0_DATA_B 0x45da 730 #define mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb 731 #define mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb 732 #define mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb 733 #define mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb 734 #define mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db 735 #define mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db 736 #define mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db 737 #define mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc 738 #define mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc 739 #define mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc 740 #define mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc 741 #define mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc 742 #define mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc 743 #define mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc 744 #define mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd 745 #define mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd 746 #define mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd 747 #define mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd 748 #define mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd 749 #define mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd 750 #define mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd 751 #define mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde 752 #define mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde 753 #define mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde 754 #define mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde 755 #define mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de 756 #define mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de 757 #define mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de 758 #define mmCRTC_CRC1_DATA_RG 0x1bdf 759 #define mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf 760 #define mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf 761 #define mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf 762 #define mmCRTC3_CRTC_CRC1_DATA_RG 0x41df 763 #define mmCRTC4_CRTC_CRC1_DATA_RG 0x43df 764 #define mmCRTC5_CRTC_CRC1_DATA_RG 0x45df 765 #define mmCRTC_CRC1_DATA_B 0x1be0 766 #define mmCRTC0_CRTC_CRC1_DATA_B 0x1be0 767 #define mmCRTC1_CRTC_CRC1_DATA_B 0x1de0 768 #define mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0 769 #define mmCRTC3_CRTC_CRC1_DATA_B 0x41e0 770 #define mmCRTC4_CRTC_CRC1_DATA_B 0x43e0 771 #define mmCRTC5_CRTC_CRC1_DATA_B 0x45e0 772 #define mmCRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 773 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL 0x1be1 774 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL 0x1de1 775 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL 0x1fe1 776 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL 0x41e1 777 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL 0x43e1 778 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL 0x45e1 779 #define mmCRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 780 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1be2 781 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1de2 782 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x1fe2 783 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x41e2 784 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x43e2 785 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START 0x45e2 786 #define mmCRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 787 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1be3 788 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1de3 789 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x1fe3 790 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x41e3 791 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x43e3 792 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END 0x45e3 793 #define mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 794 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1be4 795 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1de4 796 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1fe4 797 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x41e4 798 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x43e4 799 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x45e4 800 #define mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 801 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1be5 802 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1de5 803 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1fe5 804 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x41e5 805 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x43e5 806 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x45e5 807 #define mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 808 #define mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1be6 809 #define mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1de6 810 #define mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1fe6 811 #define mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x41e6 812 #define mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x43e6 813 #define mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x45e6 814 #define mmCRTC_STATIC_SCREEN_CONTROL 0x1be7 815 #define mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7 816 #define mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7 817 #define mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7 818 #define mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7 819 #define mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7 820 #define mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7 821 #define mmCRTC_3D_STRUCTURE_CONTROL 0x1b78 822 #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78 823 #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78 824 #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78 825 #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178 826 #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378 827 #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578 828 #define mmCRTC_GSL_VSYNC_GAP 0x1b79 829 #define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79 830 #define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79 831 #define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79 832 #define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179 833 #define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379 834 #define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579 835 #define mmCRTC_GSL_WINDOW 0x1b7a 836 #define mmCRTC0_CRTC_GSL_WINDOW 0x1b7a 837 #define mmCRTC1_CRTC_GSL_WINDOW 0x1d7a 838 #define mmCRTC2_CRTC_GSL_WINDOW 0x1f7a 839 #define mmCRTC3_CRTC_GSL_WINDOW 0x417a 840 #define mmCRTC4_CRTC_GSL_WINDOW 0x437a 841 #define mmCRTC5_CRTC_GSL_WINDOW 0x457a 842 #define mmCRTC_GSL_CONTROL 0x1b7b 843 #define mmCRTC0_CRTC_GSL_CONTROL 0x1b7b 844 #define mmCRTC1_CRTC_GSL_CONTROL 0x1d7b 845 #define mmCRTC2_CRTC_GSL_CONTROL 0x1f7b 846 #define mmCRTC3_CRTC_GSL_CONTROL 0x417b 847 #define mmCRTC4_CRTC_GSL_CONTROL 0x437b 848 #define mmCRTC5_CRTC_GSL_CONTROL 0x457b 849 #define mmCRTC_TEST_DEBUG_INDEX 0x1bc6 850 #define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6 851 #define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6 852 #define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6 853 #define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6 854 #define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6 855 #define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6 856 #define mmCRTC_TEST_DEBUG_DATA 0x1bc7 857 #define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7 858 #define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7 859 #define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7 860 #define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7 861 #define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7 862 #define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7 863 #define mmDAC_ENABLE 0x16aa 864 #define mmDAC_SOURCE_SELECT 0x16ab 865 #define mmDAC_CRC_EN 0x16ac 866 #define mmDAC_CRC_CONTROL 0x16ad 867 #define mmDAC_CRC_SIG_RGB_MASK 0x16ae 868 #define mmDAC_CRC_SIG_CONTROL_MASK 0x16af 869 #define mmDAC_CRC_SIG_RGB 0x16b0 870 #define mmDAC_CRC_SIG_CONTROL 0x16b1 871 #define mmDAC_SYNC_TRISTATE_CONTROL 0x16b2 872 #define mmDAC_STEREOSYNC_SELECT 0x16b3 873 #define mmDAC_AUTODETECT_CONTROL 0x16b4 874 #define mmDAC_AUTODETECT_CONTROL2 0x16b5 875 #define mmDAC_AUTODETECT_CONTROL3 0x16b6 876 #define mmDAC_AUTODETECT_STATUS 0x16b7 877 #define mmDAC_AUTODETECT_INT_CONTROL 0x16b8 878 #define mmDAC_FORCE_OUTPUT_CNTL 0x16b9 879 #define mmDAC_FORCE_DATA 0x16ba 880 #define mmDAC_POWERDOWN 0x16bb 881 #define mmDAC_CONTROL 0x16bc 882 #define mmDAC_COMPARATOR_ENABLE 0x16bd 883 #define mmDAC_COMPARATOR_OUTPUT 0x16be 884 #define mmDAC_PWR_CNTL 0x16bf 885 #define mmDAC_DFT_CONFIG 0x16c0 886 #define mmDAC_FIFO_STATUS 0x16c1 887 #define mmDAC_TEST_DEBUG_INDEX 0x16c2 888 #define mmDAC_TEST_DEBUG_DATA 0x16c3 889 #define mmPERFCOUNTER_CNTL 0x170 890 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170 891 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x358 892 #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x364 893 #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x18c8 894 #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1b24 895 #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1d24 896 #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x1f24 897 #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4124 898 #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4324 899 #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4524 900 #define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x4724 901 #define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x59a0 902 #define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x5f68 903 #define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x9924 904 #define mmPERFCOUNTER_STATE 0x171 905 #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x171 906 #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x359 907 #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x365 908 #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x18c9 909 #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x1b25 910 #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x1d25 911 #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x1f25 912 #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x4125 913 #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x4325 914 #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x4525 915 #define mmDC_PERFMON10_PERFCOUNTER_STATE 0x4725 916 #define mmDC_PERFMON11_PERFCOUNTER_STATE 0x59a1 917 #define mmDC_PERFMON12_PERFCOUNTER_STATE 0x5f69 918 #define mmDC_PERFMON13_PERFCOUNTER_STATE 0x9925 919 #define mmPERFMON_CNTL 0x173 920 #define mmDC_PERFMON0_PERFMON_CNTL 0x173 921 #define mmDC_PERFMON1_PERFMON_CNTL 0x35b 922 #define mmDC_PERFMON2_PERFMON_CNTL 0x367 923 #define mmDC_PERFMON3_PERFMON_CNTL 0x18cb 924 #define mmDC_PERFMON4_PERFMON_CNTL 0x1b27 925 #define mmDC_PERFMON5_PERFMON_CNTL 0x1d27 926 #define mmDC_PERFMON6_PERFMON_CNTL 0x1f27 927 #define mmDC_PERFMON7_PERFMON_CNTL 0x4127 928 #define mmDC_PERFMON8_PERFMON_CNTL 0x4327 929 #define mmDC_PERFMON9_PERFMON_CNTL 0x4527 930 #define mmDC_PERFMON10_PERFMON_CNTL 0x4727 931 #define mmDC_PERFMON11_PERFMON_CNTL 0x59a3 932 #define mmDC_PERFMON12_PERFMON_CNTL 0x5f6b 933 #define mmDC_PERFMON13_PERFMON_CNTL 0x9927 934 #define mmPERFMON_CNTL2 0x17a 935 #define mmDC_PERFMON0_PERFMON_CNTL2 0x17a 936 #define mmDC_PERFMON1_PERFMON_CNTL2 0x362 937 #define mmDC_PERFMON2_PERFMON_CNTL2 0x36e 938 #define mmDC_PERFMON3_PERFMON_CNTL2 0x18d2 939 #define mmDC_PERFMON4_PERFMON_CNTL2 0x1b2e 940 #define mmDC_PERFMON5_PERFMON_CNTL2 0x1d2e 941 #define mmDC_PERFMON6_PERFMON_CNTL2 0x1f2e 942 #define mmDC_PERFMON7_PERFMON_CNTL2 0x412e 943 #define mmDC_PERFMON8_PERFMON_CNTL2 0x432e 944 #define mmDC_PERFMON9_PERFMON_CNTL2 0x452e 945 #define mmDC_PERFMON10_PERFMON_CNTL2 0x472e 946 #define mmDC_PERFMON11_PERFMON_CNTL2 0x59aa 947 #define mmDC_PERFMON12_PERFMON_CNTL2 0x5f72 948 #define mmDC_PERFMON13_PERFMON_CNTL2 0x992e 949 #define mmPERFMON_CVALUE_INT_MISC 0x172 950 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172 951 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x35a 952 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x366 953 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x18ca 954 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1b26 955 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1d26 956 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x1f26 957 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4126 958 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4326 959 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4526 960 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x4726 961 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x59a2 962 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x5f6a 963 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x9926 964 #define mmPERFMON_CVALUE_LOW 0x174 965 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174 966 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x35c 967 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x368 968 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x18cc 969 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1b28 970 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1d28 971 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x1f28 972 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4128 973 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4328 974 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4528 975 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x4728 976 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x59a4 977 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x5f6c 978 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x9928 979 #define mmPERFMON_HI 0x175 980 #define mmDC_PERFMON0_PERFMON_HI 0x175 981 #define mmDC_PERFMON1_PERFMON_HI 0x35d 982 #define mmDC_PERFMON2_PERFMON_HI 0x369 983 #define mmDC_PERFMON3_PERFMON_HI 0x18cd 984 #define mmDC_PERFMON4_PERFMON_HI 0x1b29 985 #define mmDC_PERFMON5_PERFMON_HI 0x1d29 986 #define mmDC_PERFMON6_PERFMON_HI 0x1f29 987 #define mmDC_PERFMON7_PERFMON_HI 0x4129 988 #define mmDC_PERFMON8_PERFMON_HI 0x4329 989 #define mmDC_PERFMON9_PERFMON_HI 0x4529 990 #define mmDC_PERFMON10_PERFMON_HI 0x4729 991 #define mmDC_PERFMON11_PERFMON_HI 0x59a5 992 #define mmDC_PERFMON12_PERFMON_HI 0x5f6d 993 #define mmDC_PERFMON13_PERFMON_HI 0x9929 994 #define mmPERFMON_LOW 0x176 995 #define mmDC_PERFMON0_PERFMON_LOW 0x176 996 #define mmDC_PERFMON1_PERFMON_LOW 0x35e 997 #define mmDC_PERFMON2_PERFMON_LOW 0x36a 998 #define mmDC_PERFMON3_PERFMON_LOW 0x18ce 999 #define mmDC_PERFMON4_PERFMON_LOW 0x1b2a 1000 #define mmDC_PERFMON5_PERFMON_LOW 0x1d2a 1001 #define mmDC_PERFMON6_PERFMON_LOW 0x1f2a 1002 #define mmDC_PERFMON7_PERFMON_LOW 0x412a 1003 #define mmDC_PERFMON8_PERFMON_LOW 0x432a 1004 #define mmDC_PERFMON9_PERFMON_LOW 0x452a 1005 #define mmDC_PERFMON10_PERFMON_LOW 0x472a 1006 #define mmDC_PERFMON11_PERFMON_LOW 0x59a6 1007 #define mmDC_PERFMON12_PERFMON_LOW 0x5f6e 1008 #define mmDC_PERFMON13_PERFMON_LOW 0x992a 1009 #define mmPERFMON_TEST_DEBUG_INDEX 0x177 1010 #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177 1011 #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x35f 1012 #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x36b 1013 #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x18cf 1014 #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1b2b 1015 #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1d2b 1016 #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x1f2b 1017 #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x412b 1018 #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x432b 1019 #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x452b 1020 #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x472b 1021 #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x59a7 1022 #define mmDC_PERFMON12_PERFMON_TEST_DEBUG_INDEX 0x5f6f 1023 #define mmDC_PERFMON13_PERFMON_TEST_DEBUG_INDEX 0x992b 1024 #define mmPERFMON_TEST_DEBUG_DATA 0x178 1025 #define mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178 1026 #define mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x360 1027 #define mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x36c 1028 #define mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x18d0 1029 #define mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1b2c 1030 #define mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1d2c 1031 #define mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x1f2c 1032 #define mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x412c 1033 #define mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x432c 1034 #define mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x452c 1035 #define mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x472c 1036 #define mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x59a8 1037 #define mmDC_PERFMON12_PERFMON_TEST_DEBUG_DATA 0x5f70 1038 #define mmDC_PERFMON13_PERFMON_TEST_DEBUG_DATA 0x992c 1039 #define mmREFCLK_CNTL 0x109 1040 #define mmDCCG_CBUS_ANTIGLITCH_RESETB 0x15c 1041 #define mmDCCG_CBUS_SPARE 0x15d 1042 #define mmDCCG_CBUS_WRCMD_DELAY 0x110 1043 #define mmDPREFCLK_CNTL 0x118 1044 #define mmDCE_VERSION 0x11e 1045 #define mmAVSYNC_COUNTER_WRITE 0x12a 1046 #define mmAVSYNC_COUNTER_CONTROL 0x12b 1047 #define mmAVSYNC_COUNTER_READ 0x12f 1048 #define mmDCCG_GTC_CNTL 0x120 1049 #define mmDCCG_GTC_DTO_INCR 0x121 1050 #define mmDCCG_GTC_DTO_MODULO 0x122 1051 #define mmDCCG_GTC_CURRENT 0x123 1052 #define mmDCCG_DS_DTO_INCR 0x113 1053 #define mmDCCG_DS_DTO_MODULO 0x114 1054 #define mmDCCG_DS_CNTL 0x115 1055 #define mmDCCG_DS_HW_CAL_INTERVAL 0x116 1056 #define mmDCCG_DS_DEBUG_CNTL 0x112 1057 #define mmDMCU_SMU_INTERRUPT_CNTL 0x12c 1058 #define mmSMU_CONTROL 0x12d 1059 #define mmSMU_INTERRUPT_CONTROL 0x12e 1060 #define mmDAC_CLK_ENABLE 0x128 1061 #define mmDVO_CLK_ENABLE 0x129 1062 #define mmDCCG_GATE_DISABLE_CNTL 0x134 1063 #define mmDCCG_GATE_DISABLE_CNTL2 0x13c 1064 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x135 1065 #define mmSCLK_CGTT_BLK_CTRL_REG 0x136 1066 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108 1067 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x10b 1068 #define mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d 1069 #define mmDCCG_CAC_STATUS 0x137 1070 #define mmPIXCLK0_RESYNC_CNTL 0x13a 1071 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x100 1072 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x101 1073 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x102 1074 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x103 1075 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x10c 1076 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x13e 1077 #define mmMICROSECOND_TIME_BASE_DIV 0x13b 1078 #define mmDCCG_DISP_CNTL_REG 0x13f 1079 #define mmMILLISECOND_TIME_BASE_DIV 0x130 1080 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x131 1081 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132 1082 #define mmDCCG_PERFMON_CNTL 0x133 1083 #define mmDCCG_PERFMON_CNTL2 0x10e 1084 #define mmCRTC0_PIXEL_RATE_CNTL 0x140 1085 #define mmDP_DTO0_PHASE 0x141 1086 #define mmDP_DTO0_MODULO 0x142 1087 #define mmCRTC0_PHYPLL_PIXEL_RATE_CNTL 0x143 1088 #define mmCRTC1_PIXEL_RATE_CNTL 0x144 1089 #define mmDP_DTO1_PHASE 0x145 1090 #define mmDP_DTO1_MODULO 0x146 1091 #define mmCRTC1_PHYPLL_PIXEL_RATE_CNTL 0x147 1092 #define mmCRTC2_PIXEL_RATE_CNTL 0x148 1093 #define mmDP_DTO2_PHASE 0x149 1094 #define mmDP_DTO2_MODULO 0x14a 1095 #define mmCRTC2_PHYPLL_PIXEL_RATE_CNTL 0x14b 1096 #define mmCRTC3_PIXEL_RATE_CNTL 0x14c 1097 #define mmDP_DTO3_PHASE 0x14d 1098 #define mmDP_DTO3_MODULO 0x14e 1099 #define mmCRTC3_PHYPLL_PIXEL_RATE_CNTL 0x14f 1100 #define mmCRTC4_PIXEL_RATE_CNTL 0x150 1101 #define mmDP_DTO4_PHASE 0x151 1102 #define mmDP_DTO4_MODULO 0x152 1103 #define mmCRTC4_PHYPLL_PIXEL_RATE_CNTL 0x153 1104 #define mmCRTC5_PIXEL_RATE_CNTL 0x154 1105 #define mmDP_DTO5_PHASE 0x155 1106 #define mmDP_DTO5_MODULO 0x156 1107 #define mmCRTC5_PHYPLL_PIXEL_RATE_CNTL 0x157 1108 #define mmDCCG_SOFT_RESET 0x15f 1109 #define mmSYMCLKA_CLOCK_ENABLE 0x160 1110 #define mmSYMCLKB_CLOCK_ENABLE 0x161 1111 #define mmSYMCLKC_CLOCK_ENABLE 0x162 1112 #define mmSYMCLKD_CLOCK_ENABLE 0x163 1113 #define mmSYMCLKE_CLOCK_ENABLE 0x164 1114 #define mmSYMCLKF_CLOCK_ENABLE 0x165 1115 #define mmDPDBG_CLK_FORCE_CONTROL 0x10d 1116 #define mmDCCG_AUDIO_DTO_SOURCE 0x16b 1117 #define mmDCCG_AUDIO_DTO0_PHASE 0x16c 1118 #define mmDCCG_AUDIO_DTO0_MODULE 0x16d 1119 #define mmDCCG_AUDIO_DTO1_PHASE 0x16e 1120 #define mmDCCG_AUDIO_DTO1_MODULE 0x16f 1121 #define mmDCCG_TEST_DEBUG_INDEX 0x17c 1122 #define mmDCCG_TEST_DEBUG_DATA 0x17d 1123 #define mmDCCG_TEST_CLK_SEL 0x17e 1124 #define mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0 1125 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0 1126 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc 1127 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8 1128 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4 1129 #define mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1 1130 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1 1131 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd 1132 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9 1133 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5 1134 #define mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2 1135 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2 1136 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde 1137 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea 1138 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6 1139 #define mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3 1140 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3 1141 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf 1142 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb 1143 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7 1144 #define mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4 1145 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4 1146 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0 1147 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec 1148 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8 1149 #define mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5 1150 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5 1151 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1 1152 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed 1153 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9 1154 #define mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6 1155 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6 1156 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2 1157 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee 1158 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa 1159 #define mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7 1160 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7 1161 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3 1162 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef 1163 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb 1164 #define mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8 1165 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8 1166 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4 1167 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0 1168 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc 1169 #define mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9 1170 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9 1171 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5 1172 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1 1173 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd 1174 #define mmCPLL_MACRO_CNTL_RESERVED10 0x5fda 1175 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda 1176 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6 1177 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2 1178 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe 1179 #define mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb 1180 #define mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb 1181 #define mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7 1182 #define mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3 1183 #define mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff 1184 #define mmPLL_MACRO_CNTL_RESERVED0 0x1700 1185 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700 1186 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a 1187 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754 1188 #define mmPLL_MACRO_CNTL_RESERVED1 0x1701 1189 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701 1190 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b 1191 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755 1192 #define mmPLL_MACRO_CNTL_RESERVED2 0x1702 1193 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702 1194 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c 1195 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756 1196 #define mmPLL_MACRO_CNTL_RESERVED3 0x1703 1197 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703 1198 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d 1199 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757 1200 #define mmPLL_MACRO_CNTL_RESERVED4 0x1704 1201 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704 1202 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e 1203 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758 1204 #define mmPLL_MACRO_CNTL_RESERVED5 0x1705 1205 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705 1206 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f 1207 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759 1208 #define mmPLL_MACRO_CNTL_RESERVED6 0x1706 1209 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706 1210 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730 1211 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a 1212 #define mmPLL_MACRO_CNTL_RESERVED7 0x1707 1213 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707 1214 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731 1215 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b 1216 #define mmPLL_MACRO_CNTL_RESERVED8 0x1708 1217 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708 1218 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732 1219 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c 1220 #define mmPLL_MACRO_CNTL_RESERVED9 0x1709 1221 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709 1222 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733 1223 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d 1224 #define mmPLL_MACRO_CNTL_RESERVED10 0x170a 1225 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a 1226 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734 1227 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e 1228 #define mmPLL_MACRO_CNTL_RESERVED11 0x170b 1229 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b 1230 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735 1231 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f 1232 #define mmPLL_MACRO_CNTL_RESERVED12 0x170c 1233 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c 1234 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736 1235 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760 1236 #define mmPLL_MACRO_CNTL_RESERVED13 0x170d 1237 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d 1238 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737 1239 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761 1240 #define mmPLL_MACRO_CNTL_RESERVED14 0x170e 1241 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e 1242 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738 1243 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762 1244 #define mmPLL_MACRO_CNTL_RESERVED15 0x170f 1245 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f 1246 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739 1247 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763 1248 #define mmPLL_MACRO_CNTL_RESERVED16 0x1710 1249 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710 1250 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a 1251 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764 1252 #define mmPLL_MACRO_CNTL_RESERVED17 0x1711 1253 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711 1254 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b 1255 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765 1256 #define mmPLL_MACRO_CNTL_RESERVED18 0x1712 1257 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712 1258 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c 1259 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766 1260 #define mmPLL_MACRO_CNTL_RESERVED19 0x1713 1261 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713 1262 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d 1263 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767 1264 #define mmPLL_MACRO_CNTL_RESERVED20 0x1714 1265 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714 1266 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e 1267 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768 1268 #define mmPLL_MACRO_CNTL_RESERVED21 0x1715 1269 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715 1270 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f 1271 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769 1272 #define mmPLL_MACRO_CNTL_RESERVED22 0x1716 1273 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716 1274 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740 1275 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a 1276 #define mmPLL_MACRO_CNTL_RESERVED23 0x1717 1277 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717 1278 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741 1279 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b 1280 #define mmPLL_MACRO_CNTL_RESERVED24 0x1718 1281 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718 1282 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742 1283 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c 1284 #define mmPLL_MACRO_CNTL_RESERVED25 0x1719 1285 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719 1286 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743 1287 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d 1288 #define mmPLL_MACRO_CNTL_RESERVED26 0x171a 1289 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a 1290 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744 1291 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e 1292 #define mmPLL_MACRO_CNTL_RESERVED27 0x171b 1293 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b 1294 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745 1295 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f 1296 #define mmPLL_MACRO_CNTL_RESERVED28 0x171c 1297 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c 1298 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746 1299 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770 1300 #define mmPLL_MACRO_CNTL_RESERVED29 0x171d 1301 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d 1302 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747 1303 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771 1304 #define mmPLL_MACRO_CNTL_RESERVED30 0x171e 1305 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e 1306 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748 1307 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772 1308 #define mmPLL_MACRO_CNTL_RESERVED31 0x171f 1309 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f 1310 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749 1311 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773 1312 #define mmPLL_MACRO_CNTL_RESERVED32 0x1720 1313 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720 1314 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a 1315 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774 1316 #define mmPLL_MACRO_CNTL_RESERVED33 0x1721 1317 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721 1318 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b 1319 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775 1320 #define mmPLL_MACRO_CNTL_RESERVED34 0x1722 1321 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722 1322 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c 1323 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776 1324 #define mmPLL_MACRO_CNTL_RESERVED35 0x1723 1325 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723 1326 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d 1327 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777 1328 #define mmPLL_MACRO_CNTL_RESERVED36 0x1724 1329 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724 1330 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e 1331 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778 1332 #define mmPLL_MACRO_CNTL_RESERVED37 0x1725 1333 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725 1334 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f 1335 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779 1336 #define mmPLL_MACRO_CNTL_RESERVED38 0x1726 1337 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726 1338 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750 1339 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a 1340 #define mmPLL_MACRO_CNTL_RESERVED39 0x1727 1341 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727 1342 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751 1343 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b 1344 #define mmPLL_MACRO_CNTL_RESERVED40 0x1728 1345 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728 1346 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752 1347 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c 1348 #define mmPLL_MACRO_CNTL_RESERVED41 0x1729 1349 #define mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729 1350 #define mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753 1351 #define mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d 1352 #define mmDENTIST_DISPCLK_CNTL 0x124 1353 #define mmDCDEBUG_BUS_CLK1_SEL 0x16c4 1354 #define mmDCDEBUG_BUS_CLK2_SEL 0x16c5 1355 #define mmDCDEBUG_BUS_CLK3_SEL 0x16c6 1356 #define mmDCDEBUG_BUS_CLK4_SEL 0x16c7 1357 #define mmDCDEBUG_BUS_CLK5_SEL 0x16c8 1358 #define mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9 1359 #define mmDCDEBUG_OUT_CNTL 0x16ca 1360 #define mmDCDEBUG_OUT_DATA 0x16cb 1361 #define mmDMIF_CONTROL 0x2f6 1362 #define mmDMIF_STATUS 0x2f7 1363 #define mmDMIFV_STATUS 0x2f5 1364 #define mmDMIF_HW_DEBUG 0x2f8 1365 #define mmDMIF_ARBITRATION_CONTROL 0x2f9 1366 #define mmPIPE0_ARBITRATION_CONTROL3 0x2fa 1367 #define mmPIPE1_ARBITRATION_CONTROL3 0x2fb 1368 #define mmPIPE2_ARBITRATION_CONTROL3 0x2fc 1369 #define mmPIPE3_ARBITRATION_CONTROL3 0x2fd 1370 #define mmPIPE4_ARBITRATION_CONTROL3 0x2fe 1371 #define mmPIPE5_ARBITRATION_CONTROL3 0x2ff 1372 #define mmPIPE6_ARBITRATION_CONTROL3 0x32a 1373 #define mmPIPE7_ARBITRATION_CONTROL3 0x32b 1374 #define mmDMIF_P_VMID 0x300 1375 #define mmDMIF_URG_OVERRIDE 0x329 1376 #define mmDMIF_TEST_DEBUG_INDEX 0x301 1377 #define mmDMIF_TEST_DEBUG_DATA 0x302 1378 #define ixDMIF_DEBUG02_CORE0 0x2 1379 #define ixDMIF_DEBUG02_CORE1 0xa 1380 #define mmDMIF_ADDR_CALC 0x303 1381 #define mmDMIF_STATUS2 0x304 1382 #define mmPIPE0_MAX_REQUESTS 0x305 1383 #define mmPIPE1_MAX_REQUESTS 0x306 1384 #define mmPIPE2_MAX_REQUESTS 0x307 1385 #define mmPIPE3_MAX_REQUESTS 0x308 1386 #define mmPIPE4_MAX_REQUESTS 0x309 1387 #define mmPIPE5_MAX_REQUESTS 0x30a 1388 #define mmPIPE6_MAX_REQUESTS 0x32c 1389 #define mmPIPE7_MAX_REQUESTS 0x32d 1390 #define mmDVMM_REG_RD_STATUS 0x32e 1391 #define mmDVMM_REG_RD_DATA 0x32f 1392 #define mmDVMM_PTE_REQ 0x330 1393 #define mmDVMM_CNTL 0x331 1394 #define mmDVMM_FAULT_STATUS 0x332 1395 #define mmDVMM_FAULT_ADDR 0x333 1396 #define mmLOW_POWER_TILING_CONTROL 0x30b 1397 #define mmMCIF_CONTROL 0x30c 1398 #define mmMCIF_WRITE_COMBINE_CONTROL 0x30d 1399 #define mmMCIF_TEST_DEBUG_INDEX 0x30e 1400 #define mmMCIF_TEST_DEBUG_DATA 0x30f 1401 #define ixIDDCCIF02_DBG_DCCIF_C 0x9 1402 #define ixIDDCCIF04_DBG_DCCIF_E 0xb 1403 #define ixIDDCCIF05_DBG_DCCIF_F 0xc 1404 #define mmMCIF_VMID 0x310 1405 #define mmMCIF_MEM_CONTROL 0x311 1406 #define mmCC_DC_PIPE_DIS 0x312 1407 #define mmMC_DC_INTERFACE_NACK_STATUS 0x313 1408 #define mmRBBMIF_TIMEOUT 0x314 1409 #define mmRBBMIF_STATUS 0x315 1410 #define mmRBBMIF_TIMEOUT_DIS 0x316 1411 #define mmRBBMIF_STATUS_FLAG 0x327 1412 #define mmDCI_MEM_PWR_STATUS 0x317 1413 #define mmDCI_MEM_PWR_STATUS2 0x318 1414 #define mmDCI_MEM_PWR_STATUS3 0x33d 1415 #define mmDCI_CLK_CNTL 0x319 1416 #define mmDCI_CLK_RAMP_CNTL 0x31a 1417 #define mmDCI_MEM_PWR_CNTL 0x31b 1418 #define mmDCI_MEM_PWR_CNTL2 0x31c 1419 #define mmDCI_MEM_PWR_CNTL3 0x31d 1420 #define mmDCI_MEM_PWR_CNTL4 0x33b 1421 #define mmDVMM_PTE_PGMEM_CONTROL 0x335 1422 #define mmDVMM_PTE_PGMEM_STATE 0x336 1423 #define mmDCI_SOFT_RESET 0x328 1424 #define mmDCI_MISC 0x33c 1425 #define mmDCI_TEST_DEBUG_INDEX 0x31e 1426 #define mmDCI_TEST_DEBUG_DATA 0x31f 1427 #define mmDCI_DEBUG_CONFIG 0x320 1428 #define mmPIPE0_DMIF_BUFFER_CONTROL 0x321 1429 #define mmPIPE1_DMIF_BUFFER_CONTROL 0x322 1430 #define mmPIPE2_DMIF_BUFFER_CONTROL 0x323 1431 #define mmPIPE3_DMIF_BUFFER_CONTROL 0x324 1432 #define mmPIPE4_DMIF_BUFFER_CONTROL 0x325 1433 #define mmPIPE5_DMIF_BUFFER_CONTROL 0x326 1434 #define mmDC_GENERICA 0x4800 1435 #define mmDC_GENERICB 0x4801 1436 #define mmDC_PAD_EXTERN_SIG 0x4802 1437 #define mmDC_REF_CLK_CNTL 0x4803 1438 #define mmDC_GPIO_DEBUG 0x4804 1439 #define mmUNIPHYA_LINK_CNTL 0x4805 1440 #define mmUNIPHYB_LINK_CNTL 0x4807 1441 #define mmUNIPHYC_LINK_CNTL 0x4809 1442 #define mmUNIPHYD_LINK_CNTL 0x480b 1443 #define mmUNIPHYE_LINK_CNTL 0x480d 1444 #define mmUNIPHYF_LINK_CNTL 0x480f 1445 #define mmUNIPHYG_LINK_CNTL 0x4811 1446 #define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806 1447 #define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808 1448 #define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a 1449 #define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c 1450 #define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e 1451 #define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810 1452 #define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812 1453 #define mmUNIPHYLPA_LINK_CNTL 0x4847 1454 #define mmUNIPHYLPB_LINK_CNTL 0x4848 1455 #define mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849 1456 #define mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a 1457 #define mmUNIPHY_IMPCAL_LINKA 0x4838 1458 #define mmUNIPHY_IMPCAL_LINKB 0x4839 1459 #define mmUNIPHY_IMPCAL_LINKC 0x483f 1460 #define mmUNIPHY_IMPCAL_LINKD 0x4840 1461 #define mmUNIPHY_IMPCAL_LINKE 0x4843 1462 #define mmUNIPHY_IMPCAL_LINKF 0x4844 1463 #define mmUNIPHY_IMPCAL_PERIOD 0x483a 1464 #define mmAUXP_IMPCAL 0x483b 1465 #define mmAUXN_IMPCAL 0x483c 1466 #define mmDCIO_IMPCAL_CNTL 0x483d 1467 #define mmUNIPHY_IMPCAL_PSW_AB 0x483e 1468 #define mmDCIO_IMPCAL_CNTL_CD 0x4841 1469 #define mmUNIPHY_IMPCAL_PSW_CD 0x4842 1470 #define mmDCIO_IMPCAL_CNTL_EF 0x4845 1471 #define mmUNIPHY_IMPCAL_PSW_EF 0x4846 1472 #define mmDCIO_WRCMD_DELAY 0x4816 1473 #define mmDC_PINSTRAPS 0x4818 1474 #define mmDC_DVODATA_CONFIG 0x481a 1475 #define mmLVTMA_PWRSEQ_CNTL 0x481b 1476 #define mmLVTMA_PWRSEQ_STATE 0x481c 1477 #define mmLVTMA_PWRSEQ_REF_DIV 0x481d 1478 #define mmLVTMA_PWRSEQ_DELAY1 0x481e 1479 #define mmLVTMA_PWRSEQ_DELAY2 0x481f 1480 #define mmBL_PWM_CNTL 0x4820 1481 #define mmBL_PWM_CNTL2 0x4821 1482 #define mmBL_PWM_PERIOD_CNTL 0x4822 1483 #define mmBL_PWM_GRP1_REG_LOCK 0x4823 1484 #define mmDCIO_GSL_GENLK_PAD_CNTL 0x4824 1485 #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825 1486 #define mmDCIO_GSL0_CNTL 0x4826 1487 #define mmDCIO_GSL1_CNTL 0x4827 1488 #define mmDCIO_GSL2_CNTL 0x4828 1489 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829 1490 #define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a 1491 #define mmDC_GPU_TIMER_READ 0x482b 1492 #define mmDC_GPU_TIMER_READ_CNTL 0x482c 1493 #define mmDCIO_CLOCK_CNTL 0x482d 1494 #define mmDCIO_DEBUG 0x482f 1495 #define mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830 1496 #define mmDBG_OUT_CNTL 0x4834 1497 #define mmDCIO_DEBUG_CONFIG 0x4835 1498 #define mmDCIO_SOFT_RESET 0x4836 1499 #define mmDCIO_DPHY_SEL 0x4837 1500 #define mmDCIO_DPCS_TX_INTERRUPT 0x484b 1501 #define mmDCIO_DPCS_RX_INTERRUPT 0x484c 1502 #define mmDCIO_SEMAPHORE0 0x484d 1503 #define mmDCIO_SEMAPHORE1 0x484e 1504 #define mmDCIO_SEMAPHORE2 0x484f 1505 #define mmDCIO_SEMAPHORE3 0x4850 1506 #define mmDCIO_SEMAPHORE4 0x4851 1507 #define mmDCIO_SEMAPHORE5 0x4852 1508 #define mmDCIO_SEMAPHORE6 0x4853 1509 #define mmDCIO_SEMAPHORE7 0x4854 1510 #define mmDCIO_TEST_DEBUG_INDEX 0x4831 1511 #define mmDCIO_TEST_DEBUG_DATA 0x4832 1512 #define ixDCIO_DEBUG1 0x1 1513 #define ixDCIO_DEBUG2 0x2 1514 #define ixDCIO_DEBUG3 0x3 1515 #define ixDCIO_DEBUG4 0x4 1516 #define ixDCIO_DEBUG5 0x5 1517 #define ixDCIO_DEBUG6 0x6 1518 #define ixDCIO_DEBUG7 0x7 1519 #define ixDCIO_DEBUG8 0x8 1520 #define ixDCIO_DEBUG9 0x9 1521 #define ixDCIO_DEBUGA 0xa 1522 #define ixDCIO_DEBUGB 0xb 1523 #define ixDCIO_DEBUGC 0xc 1524 #define ixDCIO_DEBUGD 0xd 1525 #define ixDCIO_DEBUGE 0xe 1526 #define ixDCIO_DEBUGF 0xf 1527 #define ixDCIO_DEBUG10 0x10 1528 #define ixDCIO_DEBUG11 0x11 1529 #define ixDCIO_DEBUG12 0x12 1530 #define ixDCIO_DEBUG13 0x13 1531 #define ixDCIO_DEBUG14 0x14 1532 #define ixDCIO_DEBUG15 0x15 1533 #define ixDCIO_DEBUG16 0x16 1534 #define ixDCIO_DEBUG17 0x17 1535 #define ixDCIO_DEBUG18 0x18 1536 #define ixDCIO_DEBUG19 0x19 1537 #define ixDCIO_DEBUG1A 0x1a 1538 #define ixDCIO_DEBUG1B 0x1b 1539 #define ixDCIO_DEBUG1C 0x1c 1540 #define ixDCIO_DEBUG1D 0x1d 1541 #define ixDCIO_DEBUG1E 0x1e 1542 #define ixDCIO_DEBUG1F 0x1f 1543 #define ixDCIO_DEBUG20 0x20 1544 #define ixDCIO_DEBUG21 0x21 1545 #define ixDCIO_DEBUG22 0x22 1546 #define ixDCIO_DEBUG23 0x23 1547 #define ixDCIO_DEBUG24 0x24 1548 #define ixDCIO_DEBUG25 0x25 1549 #define ixDCIO_DEBUG26 0x26 1550 #define ixDCIO_DEBUG27 0x27 1551 #define ixDCIO_DEBUG28 0x28 1552 #define ixDCIO_DEBUG_ID 0x0 1553 #define mmDC_GPIO_GENERIC_MASK 0x4860 1554 #define mmDC_GPIO_GENERIC_A 0x4861 1555 #define mmDC_GPIO_GENERIC_EN 0x4862 1556 #define mmDC_GPIO_GENERIC_Y 0x4863 1557 #define mmDC_GPIO_DDC1_MASK 0x4868 1558 #define mmDC_GPIO_DDC1_A 0x4869 1559 #define mmDC_GPIO_DDC1_EN 0x486a 1560 #define mmDC_GPIO_DDC1_Y 0x486b 1561 #define mmDC_GPIO_DDC2_MASK 0x486c 1562 #define mmDC_GPIO_DDC2_A 0x486d 1563 #define mmDC_GPIO_DDC2_EN 0x486e 1564 #define mmDC_GPIO_DDC2_Y 0x486f 1565 #define mmDC_GPIO_DDC3_MASK 0x4870 1566 #define mmDC_GPIO_DDC3_A 0x4871 1567 #define mmDC_GPIO_DDC3_EN 0x4872 1568 #define mmDC_GPIO_DDC3_Y 0x4873 1569 #define mmDC_GPIO_DDC4_MASK 0x4874 1570 #define mmDC_GPIO_DDC4_A 0x4875 1571 #define mmDC_GPIO_DDC4_EN 0x4876 1572 #define mmDC_GPIO_DDC4_Y 0x4877 1573 #define mmDC_GPIO_DDC5_MASK 0x4878 1574 #define mmDC_GPIO_DDC5_A 0x4879 1575 #define mmDC_GPIO_DDC5_EN 0x487a 1576 #define mmDC_GPIO_DDC5_Y 0x487b 1577 #define mmDC_GPIO_DDC6_MASK 0x487c 1578 #define mmDC_GPIO_DDC6_A 0x487d 1579 #define mmDC_GPIO_DDC6_EN 0x487e 1580 #define mmDC_GPIO_DDC6_Y 0x487f 1581 #define mmDC_GPIO_DDCVGA_MASK 0x4880 1582 #define mmDC_GPIO_DDCVGA_A 0x4881 1583 #define mmDC_GPIO_DDCVGA_EN 0x4882 1584 #define mmDC_GPIO_DDCVGA_Y 0x4883 1585 #define mmDC_GPIO_SYNCA_MASK 0x4884 1586 #define mmDC_GPIO_SYNCA_A 0x4885 1587 #define mmDC_GPIO_SYNCA_EN 0x4886 1588 #define mmDC_GPIO_SYNCA_Y 0x4887 1589 #define mmDC_GPIO_GENLK_MASK 0x4888 1590 #define mmDC_GPIO_GENLK_A 0x4889 1591 #define mmDC_GPIO_GENLK_EN 0x488a 1592 #define mmDC_GPIO_GENLK_Y 0x488b 1593 #define mmDC_GPIO_HPD_MASK 0x488c 1594 #define mmDC_GPIO_HPD_A 0x488d 1595 #define mmDC_GPIO_HPD_EN 0x488e 1596 #define mmDC_GPIO_HPD_Y 0x488f 1597 #define mmDC_GPIO_PWRSEQ_MASK 0x4890 1598 #define mmDC_GPIO_PWRSEQ_A 0x4891 1599 #define mmDC_GPIO_PWRSEQ_EN 0x4892 1600 #define mmDC_GPIO_PWRSEQ_Y 0x4893 1601 #define mmDC_GPIO_PAD_STRENGTH_1 0x4894 1602 #define mmDC_GPIO_PAD_STRENGTH_2 0x4895 1603 #define mmPHY_AUX_CNTL 0x4897 1604 #define mmDC_GPIO_I2CPAD_A 0x4899 1605 #define mmDC_GPIO_I2CPAD_EN 0x489a 1606 #define mmDC_GPIO_I2CPAD_Y 0x489b 1607 #define mmDC_GPIO_I2CPAD_STRENGTH 0x489c 1608 #define mmDVO_VREF_CONTROL 0x489e 1609 #define mmDVO_SKEW_ADJUST 0x489f 1610 #define mmDC_GPIO_RECEIVER_EN0 0x48a0 1611 #define mmDC_GPIO_RECEIVER_EN1 0x48a1 1612 #define mmDC_GPIO_I2S_SPDIF_MASK 0x48a8 1613 #define mmDC_GPIO_I2S_SPDIF_A 0x48a9 1614 #define mmDC_GPIO_I2S_SPDIF_EN 0x48aa 1615 #define mmDC_GPIO_I2S_SPDIF_Y 0x48ab 1616 #define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x48ac 1617 #define mmDC_GPIO_TX12_EN 0x48ad 1618 #define mmDC_GPIO_AUX_CTRL_0 0x48ae 1619 #define mmDC_GPIO_AUX_CTRL_1 0x48af 1620 #define mmDC_GPIO_AUX_CTRL_2 0x48b0 1621 #define mmDC_GPIO_HPD_CTRL_0 0x48b1 1622 #define mmDC_GPIO_HPD_CTRL_1 0x48b2 1623 #define mmDAC_MACRO_CNTL_RESERVED0 0x48b8 1624 #define mmDAC_MACRO_CNTL_RESERVED1 0x48b9 1625 #define mmDAC_MACRO_CNTL_RESERVED2 0x48ba 1626 #define mmDAC_MACRO_CNTL_RESERVED3 0x48bb 1627 #define mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0 1628 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0 1629 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x4960 1630 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x9a00 1631 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x9aa0 1632 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x9b40 1633 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x9be0 1634 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x9c80 1635 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x9d20 1636 #define mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1 1637 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1 1638 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x4961 1639 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x9a01 1640 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x9aa1 1641 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x9b41 1642 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x9be1 1643 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x9c81 1644 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x9d21 1645 #define mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2 1646 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2 1647 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x4962 1648 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x9a02 1649 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x9aa2 1650 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x9b42 1651 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x9be2 1652 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x9c82 1653 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x9d22 1654 #define mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3 1655 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3 1656 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x4963 1657 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x9a03 1658 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x9aa3 1659 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x9b43 1660 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x9be3 1661 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x9c83 1662 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x9d23 1663 #define mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4 1664 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4 1665 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x4964 1666 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x9a04 1667 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x9aa4 1668 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x9b44 1669 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x9be4 1670 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x9c84 1671 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x9d24 1672 #define mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5 1673 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5 1674 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x4965 1675 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x9a05 1676 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x9aa5 1677 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x9b45 1678 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x9be5 1679 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x9c85 1680 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x9d25 1681 #define mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6 1682 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6 1683 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x4966 1684 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x9a06 1685 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x9aa6 1686 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x9b46 1687 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x9be6 1688 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x9c86 1689 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x9d26 1690 #define mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7 1691 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7 1692 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x4967 1693 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x9a07 1694 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x9aa7 1695 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x9b47 1696 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x9be7 1697 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x9c87 1698 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x9d27 1699 #define mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8 1700 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8 1701 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x4968 1702 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x9a08 1703 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x9aa8 1704 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x9b48 1705 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x9be8 1706 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x9c88 1707 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x9d28 1708 #define mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9 1709 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9 1710 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x4969 1711 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x9a09 1712 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x9aa9 1713 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x9b49 1714 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x9be9 1715 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x9c89 1716 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x9d29 1717 #define mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca 1718 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca 1719 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x496a 1720 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x9a0a 1721 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x9aaa 1722 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x9b4a 1723 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x9bea 1724 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x9c8a 1725 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x9d2a 1726 #define mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb 1727 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb 1728 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x496b 1729 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x9a0b 1730 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x9aab 1731 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x9b4b 1732 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x9beb 1733 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x9c8b 1734 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x9d2b 1735 #define mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc 1736 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc 1737 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x496c 1738 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x9a0c 1739 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x9aac 1740 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x9b4c 1741 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x9bec 1742 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x9c8c 1743 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x9d2c 1744 #define mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd 1745 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd 1746 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x496d 1747 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x9a0d 1748 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x9aad 1749 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x9b4d 1750 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x9bed 1751 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x9c8d 1752 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x9d2d 1753 #define mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce 1754 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce 1755 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x496e 1756 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x9a0e 1757 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x9aae 1758 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x9b4e 1759 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x9bee 1760 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x9c8e 1761 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x9d2e 1762 #define mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf 1763 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf 1764 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x496f 1765 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x9a0f 1766 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x9aaf 1767 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x9b4f 1768 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x9bef 1769 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x9c8f 1770 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x9d2f 1771 #define mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0 1772 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0 1773 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x4970 1774 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x9a10 1775 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x9ab0 1776 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x9b50 1777 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x9bf0 1778 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x9c90 1779 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x9d30 1780 #define mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1 1781 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1 1782 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x4971 1783 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x9a11 1784 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x9ab1 1785 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x9b51 1786 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x9bf1 1787 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x9c91 1788 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x9d31 1789 #define mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2 1790 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2 1791 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x4972 1792 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x9a12 1793 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x9ab2 1794 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x9b52 1795 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x9bf2 1796 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x9c92 1797 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x9d32 1798 #define mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3 1799 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3 1800 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x4973 1801 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x9a13 1802 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x9ab3 1803 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x9b53 1804 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x9bf3 1805 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x9c93 1806 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x9d33 1807 #define mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4 1808 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4 1809 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x4974 1810 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x9a14 1811 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x9ab4 1812 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x9b54 1813 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x9bf4 1814 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x9c94 1815 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x9d34 1816 #define mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5 1817 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5 1818 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x4975 1819 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x9a15 1820 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x9ab5 1821 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x9b55 1822 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x9bf5 1823 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x9c95 1824 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x9d35 1825 #define mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6 1826 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6 1827 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x4976 1828 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x9a16 1829 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x9ab6 1830 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x9b56 1831 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x9bf6 1832 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x9c96 1833 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x9d36 1834 #define mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7 1835 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7 1836 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x4977 1837 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x9a17 1838 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x9ab7 1839 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x9b57 1840 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x9bf7 1841 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x9c97 1842 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x9d37 1843 #define mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8 1844 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8 1845 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x4978 1846 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x9a18 1847 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x9ab8 1848 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x9b58 1849 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x9bf8 1850 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x9c98 1851 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x9d38 1852 #define mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9 1853 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9 1854 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x4979 1855 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x9a19 1856 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x9ab9 1857 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x9b59 1858 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x9bf9 1859 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x9c99 1860 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x9d39 1861 #define mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da 1862 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da 1863 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x497a 1864 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x9a1a 1865 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x9aba 1866 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x9b5a 1867 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x9bfa 1868 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x9c9a 1869 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x9d3a 1870 #define mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db 1871 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db 1872 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x497b 1873 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x9a1b 1874 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x9abb 1875 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x9b5b 1876 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x9bfb 1877 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x9c9b 1878 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x9d3b 1879 #define mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc 1880 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc 1881 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x497c 1882 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x9a1c 1883 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x9abc 1884 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x9b5c 1885 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x9bfc 1886 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x9c9c 1887 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x9d3c 1888 #define mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd 1889 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd 1890 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x497d 1891 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x9a1d 1892 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x9abd 1893 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x9b5d 1894 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x9bfd 1895 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x9c9d 1896 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x9d3d 1897 #define mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de 1898 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de 1899 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x497e 1900 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x9a1e 1901 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x9abe 1902 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x9b5e 1903 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x9bfe 1904 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x9c9e 1905 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x9d3e 1906 #define mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df 1907 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df 1908 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x497f 1909 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x9a1f 1910 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x9abf 1911 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x9b5f 1912 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x9bff 1913 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x9c9f 1914 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x9d3f 1915 #define mmUNIPHY_MACRO_CNTL_RESERVED32 0x48e0 1916 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x48e0 1917 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x4980 1918 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x9a20 1919 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x9ac0 1920 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x9b60 1921 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x9c00 1922 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x9ca0 1923 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED32 0x9d40 1924 #define mmUNIPHY_MACRO_CNTL_RESERVED33 0x48e1 1925 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x48e1 1926 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x4981 1927 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x9a21 1928 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x9ac1 1929 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x9b61 1930 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x9c01 1931 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x9ca1 1932 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED33 0x9d41 1933 #define mmUNIPHY_MACRO_CNTL_RESERVED34 0x48e2 1934 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x48e2 1935 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x4982 1936 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x9a22 1937 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x9ac2 1938 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x9b62 1939 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x9c02 1940 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x9ca2 1941 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED34 0x9d42 1942 #define mmUNIPHY_MACRO_CNTL_RESERVED35 0x48e3 1943 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x48e3 1944 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x4983 1945 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x9a23 1946 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x9ac3 1947 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x9b63 1948 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x9c03 1949 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x9ca3 1950 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED35 0x9d43 1951 #define mmUNIPHY_MACRO_CNTL_RESERVED36 0x48e4 1952 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x48e4 1953 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x4984 1954 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x9a24 1955 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x9ac4 1956 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x9b64 1957 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x9c04 1958 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x9ca4 1959 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED36 0x9d44 1960 #define mmUNIPHY_MACRO_CNTL_RESERVED37 0x48e5 1961 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x48e5 1962 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x4985 1963 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x9a25 1964 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x9ac5 1965 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x9b65 1966 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x9c05 1967 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x9ca5 1968 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED37 0x9d45 1969 #define mmUNIPHY_MACRO_CNTL_RESERVED38 0x48e6 1970 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x48e6 1971 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x4986 1972 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x9a26 1973 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x9ac6 1974 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x9b66 1975 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x9c06 1976 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x9ca6 1977 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED38 0x9d46 1978 #define mmUNIPHY_MACRO_CNTL_RESERVED39 0x48e7 1979 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x48e7 1980 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x4987 1981 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x9a27 1982 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x9ac7 1983 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x9b67 1984 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x9c07 1985 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x9ca7 1986 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED39 0x9d47 1987 #define mmUNIPHY_MACRO_CNTL_RESERVED40 0x48e8 1988 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x48e8 1989 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x4988 1990 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x9a28 1991 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x9ac8 1992 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x9b68 1993 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x9c08 1994 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x9ca8 1995 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED40 0x9d48 1996 #define mmUNIPHY_MACRO_CNTL_RESERVED41 0x48e9 1997 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x48e9 1998 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x4989 1999 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x9a29 2000 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x9ac9 2001 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x9b69 2002 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x9c09 2003 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x9ca9 2004 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED41 0x9d49 2005 #define mmUNIPHY_MACRO_CNTL_RESERVED42 0x48ea 2006 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x48ea 2007 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x498a 2008 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x9a2a 2009 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x9aca 2010 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x9b6a 2011 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x9c0a 2012 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x9caa 2013 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED42 0x9d4a 2014 #define mmUNIPHY_MACRO_CNTL_RESERVED43 0x48eb 2015 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x48eb 2016 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x498b 2017 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x9a2b 2018 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x9acb 2019 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x9b6b 2020 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x9c0b 2021 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x9cab 2022 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED43 0x9d4b 2023 #define mmUNIPHY_MACRO_CNTL_RESERVED44 0x48ec 2024 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x48ec 2025 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x498c 2026 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x9a2c 2027 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x9acc 2028 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x9b6c 2029 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x9c0c 2030 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x9cac 2031 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED44 0x9d4c 2032 #define mmUNIPHY_MACRO_CNTL_RESERVED45 0x48ed 2033 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x48ed 2034 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x498d 2035 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x9a2d 2036 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x9acd 2037 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x9b6d 2038 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x9c0d 2039 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x9cad 2040 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED45 0x9d4d 2041 #define mmUNIPHY_MACRO_CNTL_RESERVED46 0x48ee 2042 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x48ee 2043 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x498e 2044 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x9a2e 2045 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x9ace 2046 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x9b6e 2047 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x9c0e 2048 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x9cae 2049 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED46 0x9d4e 2050 #define mmUNIPHY_MACRO_CNTL_RESERVED47 0x48ef 2051 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x48ef 2052 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x498f 2053 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x9a2f 2054 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x9acf 2055 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x9b6f 2056 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x9c0f 2057 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x9caf 2058 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED47 0x9d4f 2059 #define mmUNIPHY_MACRO_CNTL_RESERVED48 0x48f0 2060 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x48f0 2061 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x4990 2062 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x9a30 2063 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x9ad0 2064 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x9b70 2065 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48 0x9c10 2066 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48 0x9cb0 2067 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED48 0x9d50 2068 #define mmUNIPHY_MACRO_CNTL_RESERVED49 0x48f1 2069 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x48f1 2070 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x4991 2071 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x9a31 2072 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x9ad1 2073 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x9b71 2074 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49 0x9c11 2075 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49 0x9cb1 2076 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED49 0x9d51 2077 #define mmUNIPHY_MACRO_CNTL_RESERVED50 0x48f2 2078 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x48f2 2079 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x4992 2080 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x9a32 2081 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x9ad2 2082 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x9b72 2083 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50 0x9c12 2084 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50 0x9cb2 2085 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED50 0x9d52 2086 #define mmUNIPHY_MACRO_CNTL_RESERVED51 0x48f3 2087 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x48f3 2088 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x4993 2089 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x9a33 2090 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x9ad3 2091 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x9b73 2092 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51 0x9c13 2093 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51 0x9cb3 2094 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED51 0x9d53 2095 #define mmUNIPHY_MACRO_CNTL_RESERVED52 0x48f4 2096 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x48f4 2097 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x4994 2098 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x9a34 2099 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x9ad4 2100 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x9b74 2101 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52 0x9c14 2102 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52 0x9cb4 2103 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED52 0x9d54 2104 #define mmUNIPHY_MACRO_CNTL_RESERVED53 0x48f5 2105 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x48f5 2106 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x4995 2107 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x9a35 2108 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x9ad5 2109 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x9b75 2110 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53 0x9c15 2111 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53 0x9cb5 2112 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED53 0x9d55 2113 #define mmUNIPHY_MACRO_CNTL_RESERVED54 0x48f6 2114 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x48f6 2115 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x4996 2116 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x9a36 2117 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x9ad6 2118 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x9b76 2119 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54 0x9c16 2120 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54 0x9cb6 2121 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED54 0x9d56 2122 #define mmUNIPHY_MACRO_CNTL_RESERVED55 0x48f7 2123 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x48f7 2124 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x4997 2125 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x9a37 2126 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x9ad7 2127 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x9b77 2128 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55 0x9c17 2129 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55 0x9cb7 2130 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED55 0x9d57 2131 #define mmUNIPHY_MACRO_CNTL_RESERVED56 0x48f8 2132 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x48f8 2133 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x4998 2134 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x9a38 2135 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x9ad8 2136 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x9b78 2137 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56 0x9c18 2138 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56 0x9cb8 2139 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED56 0x9d58 2140 #define mmUNIPHY_MACRO_CNTL_RESERVED57 0x48f9 2141 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x48f9 2142 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x4999 2143 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x9a39 2144 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x9ad9 2145 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x9b79 2146 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57 0x9c19 2147 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57 0x9cb9 2148 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED57 0x9d59 2149 #define mmUNIPHY_MACRO_CNTL_RESERVED58 0x48fa 2150 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x48fa 2151 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x499a 2152 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x9a3a 2153 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x9ada 2154 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58 0x9b7a 2155 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58 0x9c1a 2156 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58 0x9cba 2157 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED58 0x9d5a 2158 #define mmUNIPHY_MACRO_CNTL_RESERVED59 0x48fb 2159 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x48fb 2160 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x499b 2161 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x9a3b 2162 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x9adb 2163 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59 0x9b7b 2164 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59 0x9c1b 2165 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59 0x9cbb 2166 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED59 0x9d5b 2167 #define mmUNIPHY_MACRO_CNTL_RESERVED60 0x48fc 2168 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x48fc 2169 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x499c 2170 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x9a3c 2171 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x9adc 2172 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60 0x9b7c 2173 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60 0x9c1c 2174 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60 0x9cbc 2175 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED60 0x9d5c 2176 #define mmUNIPHY_MACRO_CNTL_RESERVED61 0x48fd 2177 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x48fd 2178 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x499d 2179 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x9a3d 2180 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x9add 2181 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61 0x9b7d 2182 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61 0x9c1d 2183 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61 0x9cbd 2184 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED61 0x9d5d 2185 #define mmUNIPHY_MACRO_CNTL_RESERVED62 0x48fe 2186 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x48fe 2187 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x499e 2188 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x9a3e 2189 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x9ade 2190 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62 0x9b7e 2191 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62 0x9c1e 2192 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62 0x9cbe 2193 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED62 0x9d5e 2194 #define mmUNIPHY_MACRO_CNTL_RESERVED63 0x48ff 2195 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x48ff 2196 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x499f 2197 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x9a3f 2198 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x9adf 2199 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63 0x9b7f 2200 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63 0x9c1f 2201 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63 0x9cbf 2202 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED63 0x9d5f 2203 #define mmUNIPHY_MACRO_CNTL_RESERVED64 0x4900 2204 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x4900 2205 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x49a0 2206 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x9a40 2207 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x9ae0 2208 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64 0x9b80 2209 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64 0x9c20 2210 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64 0x9cc0 2211 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED64 0x9d60 2212 #define mmUNIPHY_MACRO_CNTL_RESERVED65 0x4901 2213 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x4901 2214 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x49a1 2215 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x9a41 2216 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x9ae1 2217 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65 0x9b81 2218 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65 0x9c21 2219 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65 0x9cc1 2220 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED65 0x9d61 2221 #define mmUNIPHY_MACRO_CNTL_RESERVED66 0x4902 2222 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x4902 2223 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x49a2 2224 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x9a42 2225 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x9ae2 2226 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66 0x9b82 2227 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66 0x9c22 2228 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66 0x9cc2 2229 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED66 0x9d62 2230 #define mmUNIPHY_MACRO_CNTL_RESERVED67 0x4903 2231 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x4903 2232 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x49a3 2233 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x9a43 2234 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x9ae3 2235 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67 0x9b83 2236 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67 0x9c23 2237 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67 0x9cc3 2238 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED67 0x9d63 2239 #define mmUNIPHY_MACRO_CNTL_RESERVED68 0x4904 2240 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x4904 2241 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x49a4 2242 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x9a44 2243 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x9ae4 2244 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68 0x9b84 2245 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68 0x9c24 2246 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68 0x9cc4 2247 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED68 0x9d64 2248 #define mmUNIPHY_MACRO_CNTL_RESERVED69 0x4905 2249 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x4905 2250 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x49a5 2251 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x9a45 2252 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x9ae5 2253 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69 0x9b85 2254 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69 0x9c25 2255 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69 0x9cc5 2256 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED69 0x9d65 2257 #define mmUNIPHY_MACRO_CNTL_RESERVED70 0x4906 2258 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x4906 2259 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x49a6 2260 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x9a46 2261 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x9ae6 2262 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70 0x9b86 2263 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70 0x9c26 2264 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70 0x9cc6 2265 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED70 0x9d66 2266 #define mmUNIPHY_MACRO_CNTL_RESERVED71 0x4907 2267 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x4907 2268 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x49a7 2269 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x9a47 2270 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x9ae7 2271 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71 0x9b87 2272 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71 0x9c27 2273 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71 0x9cc7 2274 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED71 0x9d67 2275 #define mmUNIPHY_MACRO_CNTL_RESERVED72 0x4908 2276 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x4908 2277 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x49a8 2278 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x9a48 2279 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x9ae8 2280 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72 0x9b88 2281 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72 0x9c28 2282 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72 0x9cc8 2283 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED72 0x9d68 2284 #define mmUNIPHY_MACRO_CNTL_RESERVED73 0x4909 2285 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x4909 2286 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x49a9 2287 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x9a49 2288 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x9ae9 2289 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73 0x9b89 2290 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73 0x9c29 2291 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73 0x9cc9 2292 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED73 0x9d69 2293 #define mmUNIPHY_MACRO_CNTL_RESERVED74 0x490a 2294 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x490a 2295 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x49aa 2296 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x9a4a 2297 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x9aea 2298 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74 0x9b8a 2299 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74 0x9c2a 2300 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74 0x9cca 2301 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED74 0x9d6a 2302 #define mmUNIPHY_MACRO_CNTL_RESERVED75 0x490b 2303 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x490b 2304 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x49ab 2305 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x9a4b 2306 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x9aeb 2307 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75 0x9b8b 2308 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75 0x9c2b 2309 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75 0x9ccb 2310 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED75 0x9d6b 2311 #define mmUNIPHY_MACRO_CNTL_RESERVED76 0x490c 2312 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x490c 2313 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x49ac 2314 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x9a4c 2315 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x9aec 2316 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76 0x9b8c 2317 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76 0x9c2c 2318 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76 0x9ccc 2319 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED76 0x9d6c 2320 #define mmUNIPHY_MACRO_CNTL_RESERVED77 0x490d 2321 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x490d 2322 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x49ad 2323 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x9a4d 2324 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x9aed 2325 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77 0x9b8d 2326 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77 0x9c2d 2327 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77 0x9ccd 2328 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED77 0x9d6d 2329 #define mmUNIPHY_MACRO_CNTL_RESERVED78 0x490e 2330 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x490e 2331 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x49ae 2332 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x9a4e 2333 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x9aee 2334 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78 0x9b8e 2335 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78 0x9c2e 2336 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78 0x9cce 2337 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED78 0x9d6e 2338 #define mmUNIPHY_MACRO_CNTL_RESERVED79 0x490f 2339 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x490f 2340 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x49af 2341 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x9a4f 2342 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x9aef 2343 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79 0x9b8f 2344 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79 0x9c2f 2345 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79 0x9ccf 2346 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED79 0x9d6f 2347 #define mmUNIPHY_MACRO_CNTL_RESERVED80 0x4910 2348 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x4910 2349 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x49b0 2350 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x9a50 2351 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x9af0 2352 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80 0x9b90 2353 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80 0x9c30 2354 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80 0x9cd0 2355 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED80 0x9d70 2356 #define mmUNIPHY_MACRO_CNTL_RESERVED81 0x4911 2357 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x4911 2358 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x49b1 2359 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x9a51 2360 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x9af1 2361 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81 0x9b91 2362 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81 0x9c31 2363 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81 0x9cd1 2364 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED81 0x9d71 2365 #define mmUNIPHY_MACRO_CNTL_RESERVED82 0x4912 2366 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x4912 2367 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x49b2 2368 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x9a52 2369 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x9af2 2370 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82 0x9b92 2371 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82 0x9c32 2372 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82 0x9cd2 2373 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED82 0x9d72 2374 #define mmUNIPHY_MACRO_CNTL_RESERVED83 0x4913 2375 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x4913 2376 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x49b3 2377 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x9a53 2378 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x9af3 2379 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83 0x9b93 2380 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83 0x9c33 2381 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83 0x9cd3 2382 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED83 0x9d73 2383 #define mmUNIPHY_MACRO_CNTL_RESERVED84 0x4914 2384 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x4914 2385 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x49b4 2386 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x9a54 2387 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x9af4 2388 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84 0x9b94 2389 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84 0x9c34 2390 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84 0x9cd4 2391 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED84 0x9d74 2392 #define mmUNIPHY_MACRO_CNTL_RESERVED85 0x4915 2393 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x4915 2394 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x49b5 2395 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x9a55 2396 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x9af5 2397 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85 0x9b95 2398 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85 0x9c35 2399 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85 0x9cd5 2400 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED85 0x9d75 2401 #define mmUNIPHY_MACRO_CNTL_RESERVED86 0x4916 2402 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x4916 2403 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x49b6 2404 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x9a56 2405 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x9af6 2406 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86 0x9b96 2407 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86 0x9c36 2408 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86 0x9cd6 2409 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED86 0x9d76 2410 #define mmUNIPHY_MACRO_CNTL_RESERVED87 0x4917 2411 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x4917 2412 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x49b7 2413 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x9a57 2414 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x9af7 2415 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87 0x9b97 2416 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87 0x9c37 2417 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87 0x9cd7 2418 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED87 0x9d77 2419 #define mmUNIPHY_MACRO_CNTL_RESERVED88 0x4918 2420 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x4918 2421 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x49b8 2422 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x9a58 2423 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x9af8 2424 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88 0x9b98 2425 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88 0x9c38 2426 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88 0x9cd8 2427 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED88 0x9d78 2428 #define mmUNIPHY_MACRO_CNTL_RESERVED89 0x4919 2429 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x4919 2430 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x49b9 2431 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x9a59 2432 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x9af9 2433 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89 0x9b99 2434 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89 0x9c39 2435 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89 0x9cd9 2436 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED89 0x9d79 2437 #define mmUNIPHY_MACRO_CNTL_RESERVED90 0x491a 2438 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x491a 2439 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x49ba 2440 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x9a5a 2441 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x9afa 2442 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90 0x9b9a 2443 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90 0x9c3a 2444 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90 0x9cda 2445 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED90 0x9d7a 2446 #define mmUNIPHY_MACRO_CNTL_RESERVED91 0x491b 2447 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x491b 2448 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x49bb 2449 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x9a5b 2450 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x9afb 2451 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91 0x9b9b 2452 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91 0x9c3b 2453 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91 0x9cdb 2454 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED91 0x9d7b 2455 #define mmUNIPHY_MACRO_CNTL_RESERVED92 0x491c 2456 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x491c 2457 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x49bc 2458 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x9a5c 2459 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x9afc 2460 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92 0x9b9c 2461 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92 0x9c3c 2462 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92 0x9cdc 2463 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED92 0x9d7c 2464 #define mmUNIPHY_MACRO_CNTL_RESERVED93 0x491d 2465 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x491d 2466 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x49bd 2467 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x9a5d 2468 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x9afd 2469 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93 0x9b9d 2470 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93 0x9c3d 2471 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93 0x9cdd 2472 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED93 0x9d7d 2473 #define mmUNIPHY_MACRO_CNTL_RESERVED94 0x491e 2474 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x491e 2475 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x49be 2476 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x9a5e 2477 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x9afe 2478 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94 0x9b9e 2479 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94 0x9c3e 2480 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94 0x9cde 2481 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED94 0x9d7e 2482 #define mmUNIPHY_MACRO_CNTL_RESERVED95 0x491f 2483 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x491f 2484 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x49bf 2485 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x9a5f 2486 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x9aff 2487 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95 0x9b9f 2488 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95 0x9c3f 2489 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95 0x9cdf 2490 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED95 0x9d7f 2491 #define mmUNIPHY_MACRO_CNTL_RESERVED96 0x4920 2492 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x4920 2493 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x49c0 2494 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x9a60 2495 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x9b00 2496 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96 0x9ba0 2497 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96 0x9c40 2498 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96 0x9ce0 2499 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED96 0x9d80 2500 #define mmUNIPHY_MACRO_CNTL_RESERVED97 0x4921 2501 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x4921 2502 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x49c1 2503 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x9a61 2504 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x9b01 2505 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97 0x9ba1 2506 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97 0x9c41 2507 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97 0x9ce1 2508 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED97 0x9d81 2509 #define mmUNIPHY_MACRO_CNTL_RESERVED98 0x4922 2510 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x4922 2511 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x49c2 2512 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x9a62 2513 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x9b02 2514 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98 0x9ba2 2515 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98 0x9c42 2516 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98 0x9ce2 2517 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED98 0x9d82 2518 #define mmUNIPHY_MACRO_CNTL_RESERVED99 0x4923 2519 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x4923 2520 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x49c3 2521 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x9a63 2522 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x9b03 2523 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99 0x9ba3 2524 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99 0x9c43 2525 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99 0x9ce3 2526 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED99 0x9d83 2527 #define mmUNIPHY_MACRO_CNTL_RESERVED100 0x4924 2528 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x4924 2529 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x49c4 2530 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x9a64 2531 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x9b04 2532 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100 0x9ba4 2533 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100 0x9c44 2534 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100 0x9ce4 2535 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED100 0x9d84 2536 #define mmUNIPHY_MACRO_CNTL_RESERVED101 0x4925 2537 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x4925 2538 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x49c5 2539 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x9a65 2540 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x9b05 2541 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101 0x9ba5 2542 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101 0x9c45 2543 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101 0x9ce5 2544 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED101 0x9d85 2545 #define mmUNIPHY_MACRO_CNTL_RESERVED102 0x4926 2546 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x4926 2547 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x49c6 2548 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x9a66 2549 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x9b06 2550 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102 0x9ba6 2551 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102 0x9c46 2552 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102 0x9ce6 2553 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED102 0x9d86 2554 #define mmUNIPHY_MACRO_CNTL_RESERVED103 0x4927 2555 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x4927 2556 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x49c7 2557 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x9a67 2558 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x9b07 2559 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103 0x9ba7 2560 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103 0x9c47 2561 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103 0x9ce7 2562 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED103 0x9d87 2563 #define mmUNIPHY_MACRO_CNTL_RESERVED104 0x4928 2564 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x4928 2565 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x49c8 2566 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x9a68 2567 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x9b08 2568 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104 0x9ba8 2569 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104 0x9c48 2570 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104 0x9ce8 2571 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED104 0x9d88 2572 #define mmUNIPHY_MACRO_CNTL_RESERVED105 0x4929 2573 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x4929 2574 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x49c9 2575 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x9a69 2576 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x9b09 2577 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105 0x9ba9 2578 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105 0x9c49 2579 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105 0x9ce9 2580 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED105 0x9d89 2581 #define mmUNIPHY_MACRO_CNTL_RESERVED106 0x492a 2582 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x492a 2583 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x49ca 2584 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x9a6a 2585 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x9b0a 2586 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106 0x9baa 2587 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106 0x9c4a 2588 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106 0x9cea 2589 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED106 0x9d8a 2590 #define mmUNIPHY_MACRO_CNTL_RESERVED107 0x492b 2591 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x492b 2592 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x49cb 2593 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x9a6b 2594 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x9b0b 2595 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107 0x9bab 2596 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107 0x9c4b 2597 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107 0x9ceb 2598 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED107 0x9d8b 2599 #define mmUNIPHY_MACRO_CNTL_RESERVED108 0x492c 2600 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x492c 2601 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x49cc 2602 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x9a6c 2603 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x9b0c 2604 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108 0x9bac 2605 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108 0x9c4c 2606 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108 0x9cec 2607 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED108 0x9d8c 2608 #define mmUNIPHY_MACRO_CNTL_RESERVED109 0x492d 2609 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x492d 2610 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x49cd 2611 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x9a6d 2612 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x9b0d 2613 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109 0x9bad 2614 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109 0x9c4d 2615 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109 0x9ced 2616 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED109 0x9d8d 2617 #define mmUNIPHY_MACRO_CNTL_RESERVED110 0x492e 2618 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x492e 2619 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x49ce 2620 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x9a6e 2621 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x9b0e 2622 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110 0x9bae 2623 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110 0x9c4e 2624 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110 0x9cee 2625 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED110 0x9d8e 2626 #define mmUNIPHY_MACRO_CNTL_RESERVED111 0x492f 2627 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x492f 2628 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x49cf 2629 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x9a6f 2630 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x9b0f 2631 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111 0x9baf 2632 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111 0x9c4f 2633 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111 0x9cef 2634 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED111 0x9d8f 2635 #define mmUNIPHY_MACRO_CNTL_RESERVED112 0x4930 2636 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x4930 2637 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x49d0 2638 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x9a70 2639 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x9b10 2640 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112 0x9bb0 2641 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112 0x9c50 2642 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112 0x9cf0 2643 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED112 0x9d90 2644 #define mmUNIPHY_MACRO_CNTL_RESERVED113 0x4931 2645 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x4931 2646 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x49d1 2647 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x9a71 2648 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x9b11 2649 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113 0x9bb1 2650 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113 0x9c51 2651 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113 0x9cf1 2652 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED113 0x9d91 2653 #define mmUNIPHY_MACRO_CNTL_RESERVED114 0x4932 2654 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x4932 2655 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x49d2 2656 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x9a72 2657 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x9b12 2658 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114 0x9bb2 2659 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114 0x9c52 2660 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114 0x9cf2 2661 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED114 0x9d92 2662 #define mmUNIPHY_MACRO_CNTL_RESERVED115 0x4933 2663 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x4933 2664 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x49d3 2665 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x9a73 2666 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x9b13 2667 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115 0x9bb3 2668 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115 0x9c53 2669 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115 0x9cf3 2670 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED115 0x9d93 2671 #define mmUNIPHY_MACRO_CNTL_RESERVED116 0x4934 2672 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x4934 2673 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x49d4 2674 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x9a74 2675 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x9b14 2676 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116 0x9bb4 2677 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116 0x9c54 2678 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116 0x9cf4 2679 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED116 0x9d94 2680 #define mmUNIPHY_MACRO_CNTL_RESERVED117 0x4935 2681 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x4935 2682 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x49d5 2683 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x9a75 2684 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x9b15 2685 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117 0x9bb5 2686 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117 0x9c55 2687 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117 0x9cf5 2688 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED117 0x9d95 2689 #define mmUNIPHY_MACRO_CNTL_RESERVED118 0x4936 2690 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x4936 2691 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x49d6 2692 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x9a76 2693 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x9b16 2694 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118 0x9bb6 2695 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118 0x9c56 2696 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118 0x9cf6 2697 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED118 0x9d96 2698 #define mmUNIPHY_MACRO_CNTL_RESERVED119 0x4937 2699 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x4937 2700 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x49d7 2701 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x9a77 2702 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x9b17 2703 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119 0x9bb7 2704 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119 0x9c57 2705 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119 0x9cf7 2706 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED119 0x9d97 2707 #define mmUNIPHY_MACRO_CNTL_RESERVED120 0x4938 2708 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x4938 2709 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x49d8 2710 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x9a78 2711 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x9b18 2712 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120 0x9bb8 2713 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120 0x9c58 2714 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120 0x9cf8 2715 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED120 0x9d98 2716 #define mmUNIPHY_MACRO_CNTL_RESERVED121 0x4939 2717 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x4939 2718 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x49d9 2719 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x9a79 2720 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x9b19 2721 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121 0x9bb9 2722 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121 0x9c59 2723 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121 0x9cf9 2724 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED121 0x9d99 2725 #define mmUNIPHY_MACRO_CNTL_RESERVED122 0x493a 2726 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x493a 2727 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x49da 2728 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x9a7a 2729 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x9b1a 2730 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122 0x9bba 2731 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122 0x9c5a 2732 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122 0x9cfa 2733 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED122 0x9d9a 2734 #define mmUNIPHY_MACRO_CNTL_RESERVED123 0x493b 2735 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x493b 2736 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x49db 2737 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x9a7b 2738 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x9b1b 2739 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123 0x9bbb 2740 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123 0x9c5b 2741 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123 0x9cfb 2742 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED123 0x9d9b 2743 #define mmUNIPHY_MACRO_CNTL_RESERVED124 0x493c 2744 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x493c 2745 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x49dc 2746 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x9a7c 2747 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x9b1c 2748 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124 0x9bbc 2749 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124 0x9c5c 2750 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124 0x9cfc 2751 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED124 0x9d9c 2752 #define mmUNIPHY_MACRO_CNTL_RESERVED125 0x493d 2753 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x493d 2754 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x49dd 2755 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x9a7d 2756 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x9b1d 2757 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125 0x9bbd 2758 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125 0x9c5d 2759 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125 0x9cfd 2760 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED125 0x9d9d 2761 #define mmUNIPHY_MACRO_CNTL_RESERVED126 0x493e 2762 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x493e 2763 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x49de 2764 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x9a7e 2765 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x9b1e 2766 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126 0x9bbe 2767 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126 0x9c5e 2768 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126 0x9cfe 2769 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED126 0x9d9e 2770 #define mmUNIPHY_MACRO_CNTL_RESERVED127 0x493f 2771 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x493f 2772 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x49df 2773 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x9a7f 2774 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x9b1f 2775 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127 0x9bbf 2776 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127 0x9c5f 2777 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127 0x9cff 2778 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED127 0x9d9f 2779 #define mmUNIPHY_MACRO_CNTL_RESERVED128 0x4940 2780 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x4940 2781 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x49e0 2782 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x9a80 2783 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x9b20 2784 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128 0x9bc0 2785 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128 0x9c60 2786 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128 0x9d00 2787 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED128 0x9da0 2788 #define mmUNIPHY_MACRO_CNTL_RESERVED129 0x4941 2789 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x4941 2790 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x49e1 2791 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x9a81 2792 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x9b21 2793 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129 0x9bc1 2794 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129 0x9c61 2795 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129 0x9d01 2796 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED129 0x9da1 2797 #define mmUNIPHY_MACRO_CNTL_RESERVED130 0x4942 2798 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x4942 2799 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x49e2 2800 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x9a82 2801 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x9b22 2802 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130 0x9bc2 2803 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130 0x9c62 2804 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130 0x9d02 2805 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED130 0x9da2 2806 #define mmUNIPHY_MACRO_CNTL_RESERVED131 0x4943 2807 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x4943 2808 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x49e3 2809 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x9a83 2810 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x9b23 2811 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131 0x9bc3 2812 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131 0x9c63 2813 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131 0x9d03 2814 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED131 0x9da3 2815 #define mmUNIPHY_MACRO_CNTL_RESERVED132 0x4944 2816 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x4944 2817 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x49e4 2818 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x9a84 2819 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x9b24 2820 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132 0x9bc4 2821 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132 0x9c64 2822 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132 0x9d04 2823 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED132 0x9da4 2824 #define mmUNIPHY_MACRO_CNTL_RESERVED133 0x4945 2825 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x4945 2826 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x49e5 2827 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x9a85 2828 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x9b25 2829 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133 0x9bc5 2830 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133 0x9c65 2831 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133 0x9d05 2832 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED133 0x9da5 2833 #define mmUNIPHY_MACRO_CNTL_RESERVED134 0x4946 2834 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x4946 2835 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x49e6 2836 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x9a86 2837 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x9b26 2838 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134 0x9bc6 2839 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134 0x9c66 2840 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134 0x9d06 2841 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED134 0x9da6 2842 #define mmUNIPHY_MACRO_CNTL_RESERVED135 0x4947 2843 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x4947 2844 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x49e7 2845 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x9a87 2846 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x9b27 2847 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135 0x9bc7 2848 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135 0x9c67 2849 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135 0x9d07 2850 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED135 0x9da7 2851 #define mmUNIPHY_MACRO_CNTL_RESERVED136 0x4948 2852 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x4948 2853 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x49e8 2854 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x9a88 2855 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x9b28 2856 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136 0x9bc8 2857 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136 0x9c68 2858 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136 0x9d08 2859 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED136 0x9da8 2860 #define mmUNIPHY_MACRO_CNTL_RESERVED137 0x4949 2861 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x4949 2862 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x49e9 2863 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x9a89 2864 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x9b29 2865 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137 0x9bc9 2866 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137 0x9c69 2867 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137 0x9d09 2868 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED137 0x9da9 2869 #define mmUNIPHY_MACRO_CNTL_RESERVED138 0x494a 2870 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x494a 2871 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x49ea 2872 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x9a8a 2873 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x9b2a 2874 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138 0x9bca 2875 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138 0x9c6a 2876 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138 0x9d0a 2877 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED138 0x9daa 2878 #define mmUNIPHY_MACRO_CNTL_RESERVED139 0x494b 2879 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x494b 2880 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x49eb 2881 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x9a8b 2882 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x9b2b 2883 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139 0x9bcb 2884 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139 0x9c6b 2885 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139 0x9d0b 2886 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED139 0x9dab 2887 #define mmUNIPHY_MACRO_CNTL_RESERVED140 0x494c 2888 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x494c 2889 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x49ec 2890 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x9a8c 2891 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x9b2c 2892 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140 0x9bcc 2893 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140 0x9c6c 2894 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140 0x9d0c 2895 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED140 0x9dac 2896 #define mmUNIPHY_MACRO_CNTL_RESERVED141 0x494d 2897 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x494d 2898 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x49ed 2899 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x9a8d 2900 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x9b2d 2901 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141 0x9bcd 2902 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141 0x9c6d 2903 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141 0x9d0d 2904 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED141 0x9dad 2905 #define mmUNIPHY_MACRO_CNTL_RESERVED142 0x494e 2906 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x494e 2907 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x49ee 2908 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x9a8e 2909 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x9b2e 2910 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142 0x9bce 2911 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142 0x9c6e 2912 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142 0x9d0e 2913 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED142 0x9dae 2914 #define mmUNIPHY_MACRO_CNTL_RESERVED143 0x494f 2915 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x494f 2916 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x49ef 2917 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x9a8f 2918 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x9b2f 2919 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143 0x9bcf 2920 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143 0x9c6f 2921 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143 0x9d0f 2922 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED143 0x9daf 2923 #define mmUNIPHY_MACRO_CNTL_RESERVED144 0x4950 2924 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x4950 2925 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x49f0 2926 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x9a90 2927 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x9b30 2928 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144 0x9bd0 2929 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144 0x9c70 2930 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144 0x9d10 2931 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED144 0x9db0 2932 #define mmUNIPHY_MACRO_CNTL_RESERVED145 0x4951 2933 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x4951 2934 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x49f1 2935 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x9a91 2936 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x9b31 2937 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145 0x9bd1 2938 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145 0x9c71 2939 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145 0x9d11 2940 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED145 0x9db1 2941 #define mmUNIPHY_MACRO_CNTL_RESERVED146 0x4952 2942 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x4952 2943 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x49f2 2944 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x9a92 2945 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x9b32 2946 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146 0x9bd2 2947 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146 0x9c72 2948 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146 0x9d12 2949 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED146 0x9db2 2950 #define mmUNIPHY_MACRO_CNTL_RESERVED147 0x4953 2951 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x4953 2952 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x49f3 2953 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x9a93 2954 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x9b33 2955 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147 0x9bd3 2956 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147 0x9c73 2957 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147 0x9d13 2958 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED147 0x9db3 2959 #define mmUNIPHY_MACRO_CNTL_RESERVED148 0x4954 2960 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x4954 2961 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x49f4 2962 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x9a94 2963 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x9b34 2964 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148 0x9bd4 2965 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148 0x9c74 2966 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148 0x9d14 2967 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED148 0x9db4 2968 #define mmUNIPHY_MACRO_CNTL_RESERVED149 0x4955 2969 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x4955 2970 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x49f5 2971 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x9a95 2972 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x9b35 2973 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149 0x9bd5 2974 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149 0x9c75 2975 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149 0x9d15 2976 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED149 0x9db5 2977 #define mmUNIPHY_MACRO_CNTL_RESERVED150 0x4956 2978 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x4956 2979 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x49f6 2980 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x9a96 2981 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x9b36 2982 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150 0x9bd6 2983 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150 0x9c76 2984 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150 0x9d16 2985 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED150 0x9db6 2986 #define mmUNIPHY_MACRO_CNTL_RESERVED151 0x4957 2987 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x4957 2988 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x49f7 2989 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x9a97 2990 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x9b37 2991 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151 0x9bd7 2992 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151 0x9c77 2993 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151 0x9d17 2994 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED151 0x9db7 2995 #define mmUNIPHY_MACRO_CNTL_RESERVED152 0x4958 2996 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x4958 2997 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x49f8 2998 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x9a98 2999 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x9b38 3000 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152 0x9bd8 3001 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152 0x9c78 3002 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152 0x9d18 3003 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED152 0x9db8 3004 #define mmUNIPHY_MACRO_CNTL_RESERVED153 0x4959 3005 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x4959 3006 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x49f9 3007 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x9a99 3008 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x9b39 3009 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153 0x9bd9 3010 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153 0x9c79 3011 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153 0x9d19 3012 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED153 0x9db9 3013 #define mmUNIPHY_MACRO_CNTL_RESERVED154 0x495a 3014 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x495a 3015 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x49fa 3016 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x9a9a 3017 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x9b3a 3018 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154 0x9bda 3019 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154 0x9c7a 3020 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154 0x9d1a 3021 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED154 0x9dba 3022 #define mmUNIPHY_MACRO_CNTL_RESERVED155 0x495b 3023 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x495b 3024 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x49fb 3025 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x9a9b 3026 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x9b3b 3027 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155 0x9bdb 3028 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155 0x9c7b 3029 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155 0x9d1b 3030 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED155 0x9dbb 3031 #define mmUNIPHY_MACRO_CNTL_RESERVED156 0x495c 3032 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x495c 3033 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x49fc 3034 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x9a9c 3035 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x9b3c 3036 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156 0x9bdc 3037 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156 0x9c7c 3038 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156 0x9d1c 3039 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED156 0x9dbc 3040 #define mmUNIPHY_MACRO_CNTL_RESERVED157 0x495d 3041 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x495d 3042 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x49fd 3043 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x9a9d 3044 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x9b3d 3045 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157 0x9bdd 3046 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157 0x9c7d 3047 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157 0x9d1d 3048 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED157 0x9dbd 3049 #define mmUNIPHY_MACRO_CNTL_RESERVED158 0x495e 3050 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x495e 3051 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x49fe 3052 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x9a9e 3053 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x9b3e 3054 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158 0x9bde 3055 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158 0x9c7e 3056 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158 0x9d1e 3057 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED158 0x9dbe 3058 #define mmUNIPHY_MACRO_CNTL_RESERVED159 0x495f 3059 #define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x495f 3060 #define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x49ff 3061 #define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x9a9f 3062 #define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x9b3f 3063 #define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159 0x9bdf 3064 #define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159 0x9c7f 3065 #define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159 0x9d1f 3066 #define mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED159 0x9dbf 3067 #define mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84 3068 #define mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85 3069 #define mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86 3070 #define mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87 3071 #define mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88 3072 #define mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89 3073 #define mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a 3074 #define mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b 3075 #define mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c 3076 #define mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d 3077 #define mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e 3078 #define mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f 3079 #define mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90 3080 #define mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91 3081 #define mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92 3082 #define mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93 3083 #define mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94 3084 #define mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95 3085 #define mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96 3086 #define mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97 3087 #define mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98 3088 #define mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99 3089 #define mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a 3090 #define mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b 3091 #define mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c 3092 #define mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d 3093 #define mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e 3094 #define mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f 3095 #define mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0 3096 #define mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1 3097 #define mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2 3098 #define mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3 3099 #define mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4 3100 #define mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5 3101 #define mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6 3102 #define mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7 3103 #define mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8 3104 #define mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9 3105 #define mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa 3106 #define mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab 3107 #define mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac 3108 #define mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad 3109 #define mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae 3110 #define mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf 3111 #define mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0 3112 #define mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1 3113 #define mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2 3114 #define mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3 3115 #define mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4 3116 #define mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5 3117 #define mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6 3118 #define mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7 3119 #define mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8 3120 #define mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9 3121 #define mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba 3122 #define mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb 3123 #define mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc 3124 #define mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd 3125 #define mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe 3126 #define mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf 3127 #define mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0 3128 #define mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1 3129 #define mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2 3130 #define mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3 3131 #define mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4 3132 #define mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5 3133 #define mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6 3134 #define mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7 3135 #define mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8 3136 #define mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9 3137 #define mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca 3138 #define mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb 3139 #define mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc 3140 #define mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd 3141 #define mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace 3142 #define mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf 3143 #define mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0 3144 #define mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1 3145 #define mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2 3146 #define mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3 3147 #define mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4 3148 #define mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5 3149 #define mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6 3150 #define mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7 3151 #define mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8 3152 #define mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9 3153 #define mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada 3154 #define mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb 3155 #define mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc 3156 #define mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add 3157 #define mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade 3158 #define mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf 3159 #define mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0 3160 #define mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1 3161 #define mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2 3162 #define mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3 3163 #define mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4 3164 #define mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5 3165 #define mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6 3166 #define mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7 3167 #define mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8 3168 #define mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9 3169 #define mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea 3170 #define mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb 3171 #define mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec 3172 #define mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed 3173 #define mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee 3174 #define mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef 3175 #define mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0 3176 #define mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1 3177 #define mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2 3178 #define mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3 3179 #define mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4 3180 #define mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5 3181 #define mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6 3182 #define mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7 3183 #define mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8 3184 #define mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9 3185 #define mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa 3186 #define mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb 3187 #define mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc 3188 #define mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd 3189 #define mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe 3190 #define mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff 3191 #define mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00 3192 #define mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01 3193 #define mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02 3194 #define mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03 3195 #define mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04 3196 #define mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05 3197 #define mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06 3198 #define mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07 3199 #define mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08 3200 #define mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09 3201 #define mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a 3202 #define mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b 3203 #define mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c 3204 #define mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d 3205 #define mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e 3206 #define mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f 3207 #define mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10 3208 #define mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11 3209 #define mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12 3210 #define mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13 3211 #define mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14 3212 #define mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15 3213 #define mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16 3214 #define mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17 3215 #define mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18 3216 #define mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19 3217 #define mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a 3218 #define mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b 3219 #define mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c 3220 #define mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d 3221 #define mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e 3222 #define mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f 3223 #define mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20 3224 #define mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21 3225 #define mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22 3226 #define mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23 3227 #define mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24 3228 #define mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25 3229 #define mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26 3230 #define mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27 3231 #define mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28 3232 #define mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29 3233 #define mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a 3234 #define mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b 3235 #define mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c 3236 #define mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d 3237 #define mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e 3238 #define mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f 3239 #define mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30 3240 #define mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31 3241 #define mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32 3242 #define mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33 3243 #define mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34 3244 #define mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35 3245 #define mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36 3246 #define mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37 3247 #define mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38 3248 #define mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39 3249 #define mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a 3250 #define mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b 3251 #define mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c 3252 #define mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d 3253 #define mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e 3254 #define mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f 3255 #define mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40 3256 #define mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41 3257 #define mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42 3258 #define mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43 3259 #define mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44 3260 #define mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45 3261 #define mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46 3262 #define mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47 3263 #define mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48 3264 #define mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49 3265 #define mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a 3266 #define mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b 3267 #define mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c 3268 #define mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d 3269 #define mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e 3270 #define mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f 3271 #define mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50 3272 #define mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51 3273 #define mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52 3274 #define mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53 3275 #define mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54 3276 #define mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55 3277 #define mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56 3278 #define mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57 3279 #define mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58 3280 #define mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59 3281 #define mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a 3282 #define mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b 3283 #define mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c 3284 #define mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d 3285 #define mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e 3286 #define mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f 3287 #define mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60 3288 #define mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61 3289 #define mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62 3290 #define mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63 3291 #define mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64 3292 #define mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65 3293 #define mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66 3294 #define mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67 3295 #define mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68 3296 #define mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69 3297 #define mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a 3298 #define mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b 3299 #define mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c 3300 #define mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d 3301 #define mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e 3302 #define mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f 3303 #define mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70 3304 #define mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71 3305 #define mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72 3306 #define mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73 3307 #define mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74 3308 #define mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75 3309 #define mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76 3310 #define mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77 3311 #define mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78 3312 #define mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79 3313 #define mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a 3314 #define mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b 3315 #define mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c 3316 #define mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d 3317 #define mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e 3318 #define mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f 3319 #define mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80 3320 #define mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81 3321 #define mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82 3322 #define mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83 3323 #define mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84 3324 #define mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85 3325 #define mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86 3326 #define mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87 3327 #define mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88 3328 #define mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89 3329 #define mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a 3330 #define mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b 3331 #define mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c 3332 #define mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d 3333 #define mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e 3334 #define mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f 3335 #define mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90 3336 #define mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91 3337 #define mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92 3338 #define mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93 3339 #define mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94 3340 #define mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95 3341 #define mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96 3342 #define mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97 3343 #define mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98 3344 #define mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99 3345 #define mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a 3346 #define mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b 3347 #define mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c 3348 #define mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d 3349 #define mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e 3350 #define mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f 3351 #define mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0 3352 #define mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1 3353 #define mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2 3354 #define mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3 3355 #define mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4 3356 #define mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5 3357 #define mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6 3358 #define mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7 3359 #define mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8 3360 #define mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9 3361 #define mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa 3362 #define mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab 3363 #define mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac 3364 #define mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad 3365 #define mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae 3366 #define mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf 3367 #define mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0 3368 #define mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1 3369 #define mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2 3370 #define mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3 3371 #define mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4 3372 #define mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5 3373 #define mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6 3374 #define mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7 3375 #define mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8 3376 #define mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9 3377 #define mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba 3378 #define mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb 3379 #define mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc 3380 #define mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd 3381 #define mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe 3382 #define mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf 3383 #define mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0 3384 #define mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1 3385 #define mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2 3386 #define mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3 3387 #define mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4 3388 #define mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5 3389 #define mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6 3390 #define mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7 3391 #define mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8 3392 #define mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9 3393 #define mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca 3394 #define mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb 3395 #define mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc 3396 #define mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd 3397 #define mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce 3398 #define mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf 3399 #define mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0 3400 #define mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1 3401 #define mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2 3402 #define mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3 3403 #define mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4 3404 #define mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5 3405 #define mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6 3406 #define mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7 3407 #define mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8 3408 #define mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9 3409 #define mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda 3410 #define mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb 3411 #define mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc 3412 #define mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd 3413 #define mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde 3414 #define mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf 3415 #define mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0 3416 #define mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1 3417 #define mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2 3418 #define mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3 3419 #define mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4 3420 #define mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5 3421 #define mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6 3422 #define mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7 3423 #define mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8 3424 #define mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9 3425 #define mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea 3426 #define mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb 3427 #define mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec 3428 #define mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed 3429 #define mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee 3430 #define mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef 3431 #define mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0 3432 #define mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1 3433 #define mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2 3434 #define mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3 3435 #define mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4 3436 #define mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5 3437 #define mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6 3438 #define mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7 3439 #define mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8 3440 #define mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9 3441 #define mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa 3442 #define mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb 3443 #define mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc 3444 #define mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd 3445 #define mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe 3446 #define mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff 3447 #define mmDPHY_MACRO_CNTL_RESERVED0 0x5d98 3448 #define mmDPHY_MACRO_CNTL_RESERVED1 0x5d99 3449 #define mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a 3450 #define mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b 3451 #define mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c 3452 #define mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d 3453 #define mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e 3454 #define mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f 3455 #define mmDPHY_MACRO_CNTL_RESERVED8 0x5da0 3456 #define mmDPHY_MACRO_CNTL_RESERVED9 0x5da1 3457 #define mmDPHY_MACRO_CNTL_RESERVED10 0x5da2 3458 #define mmDPHY_MACRO_CNTL_RESERVED11 0x5da3 3459 #define mmDPHY_MACRO_CNTL_RESERVED12 0x5da4 3460 #define mmDPHY_MACRO_CNTL_RESERVED13 0x5da5 3461 #define mmDPHY_MACRO_CNTL_RESERVED14 0x5da6 3462 #define mmDPHY_MACRO_CNTL_RESERVED15 0x5da7 3463 #define mmDPHY_MACRO_CNTL_RESERVED16 0x5da8 3464 #define mmDPHY_MACRO_CNTL_RESERVED17 0x5da9 3465 #define mmDPHY_MACRO_CNTL_RESERVED18 0x5daa 3466 #define mmDPHY_MACRO_CNTL_RESERVED19 0x5dab 3467 #define mmDPHY_MACRO_CNTL_RESERVED20 0x5dac 3468 #define mmDPHY_MACRO_CNTL_RESERVED21 0x5dad 3469 #define mmDPHY_MACRO_CNTL_RESERVED22 0x5dae 3470 #define mmDPHY_MACRO_CNTL_RESERVED23 0x5daf 3471 #define mmDPHY_MACRO_CNTL_RESERVED24 0x5db0 3472 #define mmDPHY_MACRO_CNTL_RESERVED25 0x5db1 3473 #define mmDPHY_MACRO_CNTL_RESERVED26 0x5db2 3474 #define mmDPHY_MACRO_CNTL_RESERVED27 0x5db3 3475 #define mmDPHY_MACRO_CNTL_RESERVED28 0x5db4 3476 #define mmDPHY_MACRO_CNTL_RESERVED29 0x5db5 3477 #define mmDPHY_MACRO_CNTL_RESERVED30 0x5db6 3478 #define mmDPHY_MACRO_CNTL_RESERVED31 0x5db7 3479 #define mmDPHY_MACRO_CNTL_RESERVED32 0x5db8 3480 #define mmDPHY_MACRO_CNTL_RESERVED33 0x5db9 3481 #define mmDPHY_MACRO_CNTL_RESERVED34 0x5dba 3482 #define mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb 3483 #define mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc 3484 #define mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd 3485 #define mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe 3486 #define mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf 3487 #define mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0 3488 #define mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1 3489 #define mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2 3490 #define mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3 3491 #define mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4 3492 #define mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5 3493 #define mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6 3494 #define mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7 3495 #define mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8 3496 #define mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9 3497 #define mmDPHY_MACRO_CNTL_RESERVED50 0x5dca 3498 #define mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb 3499 #define mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc 3500 #define mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd 3501 #define mmDPHY_MACRO_CNTL_RESERVED54 0x5dce 3502 #define mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf 3503 #define mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0 3504 #define mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1 3505 #define mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2 3506 #define mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3 3507 #define mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4 3508 #define mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5 3509 #define mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6 3510 #define mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7 3511 #define mmGRPH_ENABLE 0x1a00 3512 #define mmDCP0_GRPH_ENABLE 0x1a00 3513 #define mmDCP1_GRPH_ENABLE 0x1c00 3514 #define mmDCP2_GRPH_ENABLE 0x1e00 3515 #define mmDCP3_GRPH_ENABLE 0x4000 3516 #define mmDCP4_GRPH_ENABLE 0x4200 3517 #define mmDCP5_GRPH_ENABLE 0x4400 3518 #define mmGRPH_CONTROL 0x1a01 3519 #define mmDCP0_GRPH_CONTROL 0x1a01 3520 #define mmDCP1_GRPH_CONTROL 0x1c01 3521 #define mmDCP2_GRPH_CONTROL 0x1e01 3522 #define mmDCP3_GRPH_CONTROL 0x4001 3523 #define mmDCP4_GRPH_CONTROL 0x4201 3524 #define mmDCP5_GRPH_CONTROL 0x4401 3525 #define mmGRPH_LUT_10BIT_BYPASS 0x1a02 3526 #define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02 3527 #define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02 3528 #define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02 3529 #define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002 3530 #define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202 3531 #define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402 3532 #define mmGRPH_SWAP_CNTL 0x1a03 3533 #define mmDCP0_GRPH_SWAP_CNTL 0x1a03 3534 #define mmDCP1_GRPH_SWAP_CNTL 0x1c03 3535 #define mmDCP2_GRPH_SWAP_CNTL 0x1e03 3536 #define mmDCP3_GRPH_SWAP_CNTL 0x4003 3537 #define mmDCP4_GRPH_SWAP_CNTL 0x4203 3538 #define mmDCP5_GRPH_SWAP_CNTL 0x4403 3539 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 3540 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 3541 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04 3542 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04 3543 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 3544 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204 3545 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404 3546 #define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 3547 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05 3548 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05 3549 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05 3550 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 3551 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205 3552 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405 3553 #define mmGRPH_PITCH 0x1a06 3554 #define mmDCP0_GRPH_PITCH 0x1a06 3555 #define mmDCP1_GRPH_PITCH 0x1c06 3556 #define mmDCP2_GRPH_PITCH 0x1e06 3557 #define mmDCP3_GRPH_PITCH 0x4006 3558 #define mmDCP4_GRPH_PITCH 0x4206 3559 #define mmDCP5_GRPH_PITCH 0x4406 3560 #define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 3561 #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07 3562 #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07 3563 #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07 3564 #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 3565 #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207 3566 #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407 3567 #define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 3568 #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08 3569 #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08 3570 #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08 3571 #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 3572 #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208 3573 #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408 3574 #define mmGRPH_SURFACE_OFFSET_X 0x1a09 3575 #define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09 3576 #define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09 3577 #define mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09 3578 #define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009 3579 #define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209 3580 #define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409 3581 #define mmGRPH_SURFACE_OFFSET_Y 0x1a0a 3582 #define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a 3583 #define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a 3584 #define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a 3585 #define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a 3586 #define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a 3587 #define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a 3588 #define mmGRPH_X_START 0x1a0b 3589 #define mmDCP0_GRPH_X_START 0x1a0b 3590 #define mmDCP1_GRPH_X_START 0x1c0b 3591 #define mmDCP2_GRPH_X_START 0x1e0b 3592 #define mmDCP3_GRPH_X_START 0x400b 3593 #define mmDCP4_GRPH_X_START 0x420b 3594 #define mmDCP5_GRPH_X_START 0x440b 3595 #define mmGRPH_Y_START 0x1a0c 3596 #define mmDCP0_GRPH_Y_START 0x1a0c 3597 #define mmDCP1_GRPH_Y_START 0x1c0c 3598 #define mmDCP2_GRPH_Y_START 0x1e0c 3599 #define mmDCP3_GRPH_Y_START 0x400c 3600 #define mmDCP4_GRPH_Y_START 0x420c 3601 #define mmDCP5_GRPH_Y_START 0x440c 3602 #define mmGRPH_X_END 0x1a0d 3603 #define mmDCP0_GRPH_X_END 0x1a0d 3604 #define mmDCP1_GRPH_X_END 0x1c0d 3605 #define mmDCP2_GRPH_X_END 0x1e0d 3606 #define mmDCP3_GRPH_X_END 0x400d 3607 #define mmDCP4_GRPH_X_END 0x420d 3608 #define mmDCP5_GRPH_X_END 0x440d 3609 #define mmGRPH_Y_END 0x1a0e 3610 #define mmDCP0_GRPH_Y_END 0x1a0e 3611 #define mmDCP1_GRPH_Y_END 0x1c0e 3612 #define mmDCP2_GRPH_Y_END 0x1e0e 3613 #define mmDCP3_GRPH_Y_END 0x400e 3614 #define mmDCP4_GRPH_Y_END 0x420e 3615 #define mmDCP5_GRPH_Y_END 0x440e 3616 #define mmINPUT_GAMMA_CONTROL 0x1a10 3617 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 3618 #define mmDCP1_INPUT_GAMMA_CONTROL 0x1c10 3619 #define mmDCP2_INPUT_GAMMA_CONTROL 0x1e10 3620 #define mmDCP3_INPUT_GAMMA_CONTROL 0x4010 3621 #define mmDCP4_INPUT_GAMMA_CONTROL 0x4210 3622 #define mmDCP5_INPUT_GAMMA_CONTROL 0x4410 3623 #define mmGRPH_UPDATE 0x1a11 3624 #define mmDCP0_GRPH_UPDATE 0x1a11 3625 #define mmDCP1_GRPH_UPDATE 0x1c11 3626 #define mmDCP2_GRPH_UPDATE 0x1e11 3627 #define mmDCP3_GRPH_UPDATE 0x4011 3628 #define mmDCP4_GRPH_UPDATE 0x4211 3629 #define mmDCP5_GRPH_UPDATE 0x4411 3630 #define mmGRPH_FLIP_CONTROL 0x1a12 3631 #define mmDCP0_GRPH_FLIP_CONTROL 0x1a12 3632 #define mmDCP1_GRPH_FLIP_CONTROL 0x1c12 3633 #define mmDCP2_GRPH_FLIP_CONTROL 0x1e12 3634 #define mmDCP3_GRPH_FLIP_CONTROL 0x4012 3635 #define mmDCP4_GRPH_FLIP_CONTROL 0x4212 3636 #define mmDCP5_GRPH_FLIP_CONTROL 0x4412 3637 #define mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13 3638 #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13 3639 #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13 3640 #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13 3641 #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013 3642 #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213 3643 #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413 3644 #define mmGRPH_DFQ_CONTROL 0x1a14 3645 #define mmDCP0_GRPH_DFQ_CONTROL 0x1a14 3646 #define mmDCP1_GRPH_DFQ_CONTROL 0x1c14 3647 #define mmDCP2_GRPH_DFQ_CONTROL 0x1e14 3648 #define mmDCP3_GRPH_DFQ_CONTROL 0x4014 3649 #define mmDCP4_GRPH_DFQ_CONTROL 0x4214 3650 #define mmDCP5_GRPH_DFQ_CONTROL 0x4414 3651 #define mmGRPH_DFQ_STATUS 0x1a15 3652 #define mmDCP0_GRPH_DFQ_STATUS 0x1a15 3653 #define mmDCP1_GRPH_DFQ_STATUS 0x1c15 3654 #define mmDCP2_GRPH_DFQ_STATUS 0x1e15 3655 #define mmDCP3_GRPH_DFQ_STATUS 0x4015 3656 #define mmDCP4_GRPH_DFQ_STATUS 0x4215 3657 #define mmDCP5_GRPH_DFQ_STATUS 0x4415 3658 #define mmGRPH_INTERRUPT_STATUS 0x1a16 3659 #define mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16 3660 #define mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16 3661 #define mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16 3662 #define mmDCP3_GRPH_INTERRUPT_STATUS 0x4016 3663 #define mmDCP4_GRPH_INTERRUPT_STATUS 0x4216 3664 #define mmDCP5_GRPH_INTERRUPT_STATUS 0x4416 3665 #define mmGRPH_INTERRUPT_CONTROL 0x1a17 3666 #define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17 3667 #define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17 3668 #define mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17 3669 #define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017 3670 #define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217 3671 #define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417 3672 #define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 3673 #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18 3674 #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18 3675 #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18 3676 #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 3677 #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218 3678 #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418 3679 #define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 3680 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19 3681 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19 3682 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19 3683 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 3684 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219 3685 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419 3686 #define mmGRPH_COMPRESS_PITCH 0x1a1a 3687 #define mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a 3688 #define mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a 3689 #define mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a 3690 #define mmDCP3_GRPH_COMPRESS_PITCH 0x401a 3691 #define mmDCP4_GRPH_COMPRESS_PITCH 0x421a 3692 #define mmDCP5_GRPH_COMPRESS_PITCH 0x441a 3693 #define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b 3694 #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b 3695 #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b 3696 #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b 3697 #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b 3698 #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b 3699 #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b 3700 #define mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c 3701 #define mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c 3702 #define mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c 3703 #define mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c 3704 #define mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c 3705 #define mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c 3706 #define mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c 3707 #define mmPRESCALE_GRPH_CONTROL 0x1a2d 3708 #define mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d 3709 #define mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d 3710 #define mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d 3711 #define mmDCP3_PRESCALE_GRPH_CONTROL 0x402d 3712 #define mmDCP4_PRESCALE_GRPH_CONTROL 0x422d 3713 #define mmDCP5_PRESCALE_GRPH_CONTROL 0x442d 3714 #define mmPRESCALE_VALUES_GRPH_R 0x1a2e 3715 #define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e 3716 #define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e 3717 #define mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e 3718 #define mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e 3719 #define mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e 3720 #define mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e 3721 #define mmPRESCALE_VALUES_GRPH_G 0x1a2f 3722 #define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f 3723 #define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f 3724 #define mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f 3725 #define mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f 3726 #define mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f 3727 #define mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f 3728 #define mmPRESCALE_VALUES_GRPH_B 0x1a30 3729 #define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30 3730 #define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30 3731 #define mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30 3732 #define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030 3733 #define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230 3734 #define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430 3735 #define mmINPUT_CSC_CONTROL 0x1a35 3736 #define mmDCP0_INPUT_CSC_CONTROL 0x1a35 3737 #define mmDCP1_INPUT_CSC_CONTROL 0x1c35 3738 #define mmDCP2_INPUT_CSC_CONTROL 0x1e35 3739 #define mmDCP3_INPUT_CSC_CONTROL 0x4035 3740 #define mmDCP4_INPUT_CSC_CONTROL 0x4235 3741 #define mmDCP5_INPUT_CSC_CONTROL 0x4435 3742 #define mmINPUT_CSC_C11_C12 0x1a36 3743 #define mmDCP0_INPUT_CSC_C11_C12 0x1a36 3744 #define mmDCP1_INPUT_CSC_C11_C12 0x1c36 3745 #define mmDCP2_INPUT_CSC_C11_C12 0x1e36 3746 #define mmDCP3_INPUT_CSC_C11_C12 0x4036 3747 #define mmDCP4_INPUT_CSC_C11_C12 0x4236 3748 #define mmDCP5_INPUT_CSC_C11_C12 0x4436 3749 #define mmINPUT_CSC_C13_C14 0x1a37 3750 #define mmDCP0_INPUT_CSC_C13_C14 0x1a37 3751 #define mmDCP1_INPUT_CSC_C13_C14 0x1c37 3752 #define mmDCP2_INPUT_CSC_C13_C14 0x1e37 3753 #define mmDCP3_INPUT_CSC_C13_C14 0x4037 3754 #define mmDCP4_INPUT_CSC_C13_C14 0x4237 3755 #define mmDCP5_INPUT_CSC_C13_C14 0x4437 3756 #define mmINPUT_CSC_C21_C22 0x1a38 3757 #define mmDCP0_INPUT_CSC_C21_C22 0x1a38 3758 #define mmDCP1_INPUT_CSC_C21_C22 0x1c38 3759 #define mmDCP2_INPUT_CSC_C21_C22 0x1e38 3760 #define mmDCP3_INPUT_CSC_C21_C22 0x4038 3761 #define mmDCP4_INPUT_CSC_C21_C22 0x4238 3762 #define mmDCP5_INPUT_CSC_C21_C22 0x4438 3763 #define mmINPUT_CSC_C23_C24 0x1a39 3764 #define mmDCP0_INPUT_CSC_C23_C24 0x1a39 3765 #define mmDCP1_INPUT_CSC_C23_C24 0x1c39 3766 #define mmDCP2_INPUT_CSC_C23_C24 0x1e39 3767 #define mmDCP3_INPUT_CSC_C23_C24 0x4039 3768 #define mmDCP4_INPUT_CSC_C23_C24 0x4239 3769 #define mmDCP5_INPUT_CSC_C23_C24 0x4439 3770 #define mmINPUT_CSC_C31_C32 0x1a3a 3771 #define mmDCP0_INPUT_CSC_C31_C32 0x1a3a 3772 #define mmDCP1_INPUT_CSC_C31_C32 0x1c3a 3773 #define mmDCP2_INPUT_CSC_C31_C32 0x1e3a 3774 #define mmDCP3_INPUT_CSC_C31_C32 0x403a 3775 #define mmDCP4_INPUT_CSC_C31_C32 0x423a 3776 #define mmDCP5_INPUT_CSC_C31_C32 0x443a 3777 #define mmINPUT_CSC_C33_C34 0x1a3b 3778 #define mmDCP0_INPUT_CSC_C33_C34 0x1a3b 3779 #define mmDCP1_INPUT_CSC_C33_C34 0x1c3b 3780 #define mmDCP2_INPUT_CSC_C33_C34 0x1e3b 3781 #define mmDCP3_INPUT_CSC_C33_C34 0x403b 3782 #define mmDCP4_INPUT_CSC_C33_C34 0x423b 3783 #define mmDCP5_INPUT_CSC_C33_C34 0x443b 3784 #define mmOUTPUT_CSC_CONTROL 0x1a3c 3785 #define mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c 3786 #define mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c 3787 #define mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c 3788 #define mmDCP3_OUTPUT_CSC_CONTROL 0x403c 3789 #define mmDCP4_OUTPUT_CSC_CONTROL 0x423c 3790 #define mmDCP5_OUTPUT_CSC_CONTROL 0x443c 3791 #define mmOUTPUT_CSC_C11_C12 0x1a3d 3792 #define mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d 3793 #define mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d 3794 #define mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d 3795 #define mmDCP3_OUTPUT_CSC_C11_C12 0x403d 3796 #define mmDCP4_OUTPUT_CSC_C11_C12 0x423d 3797 #define mmDCP5_OUTPUT_CSC_C11_C12 0x443d 3798 #define mmOUTPUT_CSC_C13_C14 0x1a3e 3799 #define mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e 3800 #define mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e 3801 #define mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e 3802 #define mmDCP3_OUTPUT_CSC_C13_C14 0x403e 3803 #define mmDCP4_OUTPUT_CSC_C13_C14 0x423e 3804 #define mmDCP5_OUTPUT_CSC_C13_C14 0x443e 3805 #define mmOUTPUT_CSC_C21_C22 0x1a3f 3806 #define mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f 3807 #define mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f 3808 #define mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f 3809 #define mmDCP3_OUTPUT_CSC_C21_C22 0x403f 3810 #define mmDCP4_OUTPUT_CSC_C21_C22 0x423f 3811 #define mmDCP5_OUTPUT_CSC_C21_C22 0x443f 3812 #define mmOUTPUT_CSC_C23_C24 0x1a40 3813 #define mmDCP0_OUTPUT_CSC_C23_C24 0x1a40 3814 #define mmDCP1_OUTPUT_CSC_C23_C24 0x1c40 3815 #define mmDCP2_OUTPUT_CSC_C23_C24 0x1e40 3816 #define mmDCP3_OUTPUT_CSC_C23_C24 0x4040 3817 #define mmDCP4_OUTPUT_CSC_C23_C24 0x4240 3818 #define mmDCP5_OUTPUT_CSC_C23_C24 0x4440 3819 #define mmOUTPUT_CSC_C31_C32 0x1a41 3820 #define mmDCP0_OUTPUT_CSC_C31_C32 0x1a41 3821 #define mmDCP1_OUTPUT_CSC_C31_C32 0x1c41 3822 #define mmDCP2_OUTPUT_CSC_C31_C32 0x1e41 3823 #define mmDCP3_OUTPUT_CSC_C31_C32 0x4041 3824 #define mmDCP4_OUTPUT_CSC_C31_C32 0x4241 3825 #define mmDCP5_OUTPUT_CSC_C31_C32 0x4441 3826 #define mmOUTPUT_CSC_C33_C34 0x1a42 3827 #define mmDCP0_OUTPUT_CSC_C33_C34 0x1a42 3828 #define mmDCP1_OUTPUT_CSC_C33_C34 0x1c42 3829 #define mmDCP2_OUTPUT_CSC_C33_C34 0x1e42 3830 #define mmDCP3_OUTPUT_CSC_C33_C34 0x4042 3831 #define mmDCP4_OUTPUT_CSC_C33_C34 0x4242 3832 #define mmDCP5_OUTPUT_CSC_C33_C34 0x4442 3833 #define mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43 3834 #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43 3835 #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43 3836 #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43 3837 #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043 3838 #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243 3839 #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443 3840 #define mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44 3841 #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44 3842 #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44 3843 #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44 3844 #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044 3845 #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244 3846 #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444 3847 #define mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45 3848 #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45 3849 #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45 3850 #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45 3851 #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045 3852 #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245 3853 #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445 3854 #define mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46 3855 #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46 3856 #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46 3857 #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46 3858 #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046 3859 #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246 3860 #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446 3861 #define mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47 3862 #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47 3863 #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47 3864 #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47 3865 #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047 3866 #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247 3867 #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447 3868 #define mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48 3869 #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48 3870 #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48 3871 #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48 3872 #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048 3873 #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248 3874 #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448 3875 #define mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49 3876 #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49 3877 #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49 3878 #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49 3879 #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049 3880 #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249 3881 #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449 3882 #define mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a 3883 #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a 3884 #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a 3885 #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a 3886 #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a 3887 #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a 3888 #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a 3889 #define mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b 3890 #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b 3891 #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b 3892 #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b 3893 #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b 3894 #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b 3895 #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b 3896 #define mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c 3897 #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c 3898 #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c 3899 #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c 3900 #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c 3901 #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c 3902 #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c 3903 #define mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d 3904 #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d 3905 #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d 3906 #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d 3907 #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d 3908 #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d 3909 #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d 3910 #define mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e 3911 #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e 3912 #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e 3913 #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e 3914 #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e 3915 #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e 3916 #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e 3917 #define mmDENORM_CONTROL 0x1a50 3918 #define mmDCP0_DENORM_CONTROL 0x1a50 3919 #define mmDCP1_DENORM_CONTROL 0x1c50 3920 #define mmDCP2_DENORM_CONTROL 0x1e50 3921 #define mmDCP3_DENORM_CONTROL 0x4050 3922 #define mmDCP4_DENORM_CONTROL 0x4250 3923 #define mmDCP5_DENORM_CONTROL 0x4450 3924 #define mmOUT_ROUND_CONTROL 0x1a51 3925 #define mmDCP0_OUT_ROUND_CONTROL 0x1a51 3926 #define mmDCP1_OUT_ROUND_CONTROL 0x1c51 3927 #define mmDCP2_OUT_ROUND_CONTROL 0x1e51 3928 #define mmDCP3_OUT_ROUND_CONTROL 0x4051 3929 #define mmDCP4_OUT_ROUND_CONTROL 0x4251 3930 #define mmDCP5_OUT_ROUND_CONTROL 0x4451 3931 #define mmOUT_CLAMP_CONTROL_R_CR 0x1a52 3932 #define mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52 3933 #define mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52 3934 #define mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52 3935 #define mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052 3936 #define mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252 3937 #define mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452 3938 #define mmOUT_CLAMP_CONTROL_G_Y 0x1a9c 3939 #define mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c 3940 #define mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c 3941 #define mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c 3942 #define mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c 3943 #define mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c 3944 #define mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c 3945 #define mmOUT_CLAMP_CONTROL_B_CB 0x1a9d 3946 #define mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d 3947 #define mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d 3948 #define mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d 3949 #define mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d 3950 #define mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d 3951 #define mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d 3952 #define mmKEY_CONTROL 0x1a53 3953 #define mmDCP0_KEY_CONTROL 0x1a53 3954 #define mmDCP1_KEY_CONTROL 0x1c53 3955 #define mmDCP2_KEY_CONTROL 0x1e53 3956 #define mmDCP3_KEY_CONTROL 0x4053 3957 #define mmDCP4_KEY_CONTROL 0x4253 3958 #define mmDCP5_KEY_CONTROL 0x4453 3959 #define mmKEY_RANGE_ALPHA 0x1a54 3960 #define mmDCP0_KEY_RANGE_ALPHA 0x1a54 3961 #define mmDCP1_KEY_RANGE_ALPHA 0x1c54 3962 #define mmDCP2_KEY_RANGE_ALPHA 0x1e54 3963 #define mmDCP3_KEY_RANGE_ALPHA 0x4054 3964 #define mmDCP4_KEY_RANGE_ALPHA 0x4254 3965 #define mmDCP5_KEY_RANGE_ALPHA 0x4454 3966 #define mmKEY_RANGE_RED 0x1a55 3967 #define mmDCP0_KEY_RANGE_RED 0x1a55 3968 #define mmDCP1_KEY_RANGE_RED 0x1c55 3969 #define mmDCP2_KEY_RANGE_RED 0x1e55 3970 #define mmDCP3_KEY_RANGE_RED 0x4055 3971 #define mmDCP4_KEY_RANGE_RED 0x4255 3972 #define mmDCP5_KEY_RANGE_RED 0x4455 3973 #define mmKEY_RANGE_GREEN 0x1a56 3974 #define mmDCP0_KEY_RANGE_GREEN 0x1a56 3975 #define mmDCP1_KEY_RANGE_GREEN 0x1c56 3976 #define mmDCP2_KEY_RANGE_GREEN 0x1e56 3977 #define mmDCP3_KEY_RANGE_GREEN 0x4056 3978 #define mmDCP4_KEY_RANGE_GREEN 0x4256 3979 #define mmDCP5_KEY_RANGE_GREEN 0x4456 3980 #define mmKEY_RANGE_BLUE 0x1a57 3981 #define mmDCP0_KEY_RANGE_BLUE 0x1a57 3982 #define mmDCP1_KEY_RANGE_BLUE 0x1c57 3983 #define mmDCP2_KEY_RANGE_BLUE 0x1e57 3984 #define mmDCP3_KEY_RANGE_BLUE 0x4057 3985 #define mmDCP4_KEY_RANGE_BLUE 0x4257 3986 #define mmDCP5_KEY_RANGE_BLUE 0x4457 3987 #define mmDEGAMMA_CONTROL 0x1a58 3988 #define mmDCP0_DEGAMMA_CONTROL 0x1a58 3989 #define mmDCP1_DEGAMMA_CONTROL 0x1c58 3990 #define mmDCP2_DEGAMMA_CONTROL 0x1e58 3991 #define mmDCP3_DEGAMMA_CONTROL 0x4058 3992 #define mmDCP4_DEGAMMA_CONTROL 0x4258 3993 #define mmDCP5_DEGAMMA_CONTROL 0x4458 3994 #define mmGAMUT_REMAP_CONTROL 0x1a59 3995 #define mmDCP0_GAMUT_REMAP_CONTROL 0x1a59 3996 #define mmDCP1_GAMUT_REMAP_CONTROL 0x1c59 3997 #define mmDCP2_GAMUT_REMAP_CONTROL 0x1e59 3998 #define mmDCP3_GAMUT_REMAP_CONTROL 0x4059 3999 #define mmDCP4_GAMUT_REMAP_CONTROL 0x4259 4000 #define mmDCP5_GAMUT_REMAP_CONTROL 0x4459 4001 #define mmGAMUT_REMAP_C11_C12 0x1a5a 4002 #define mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a 4003 #define mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a 4004 #define mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a 4005 #define mmDCP3_GAMUT_REMAP_C11_C12 0x405a 4006 #define mmDCP4_GAMUT_REMAP_C11_C12 0x425a 4007 #define mmDCP5_GAMUT_REMAP_C11_C12 0x445a 4008 #define mmGAMUT_REMAP_C13_C14 0x1a5b 4009 #define mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b 4010 #define mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b 4011 #define mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b 4012 #define mmDCP3_GAMUT_REMAP_C13_C14 0x405b 4013 #define mmDCP4_GAMUT_REMAP_C13_C14 0x425b 4014 #define mmDCP5_GAMUT_REMAP_C13_C14 0x445b 4015 #define mmGAMUT_REMAP_C21_C22 0x1a5c 4016 #define mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c 4017 #define mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c 4018 #define mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c 4019 #define mmDCP3_GAMUT_REMAP_C21_C22 0x405c 4020 #define mmDCP4_GAMUT_REMAP_C21_C22 0x425c 4021 #define mmDCP5_GAMUT_REMAP_C21_C22 0x445c 4022 #define mmGAMUT_REMAP_C23_C24 0x1a5d 4023 #define mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d 4024 #define mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d 4025 #define mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d 4026 #define mmDCP3_GAMUT_REMAP_C23_C24 0x405d 4027 #define mmDCP4_GAMUT_REMAP_C23_C24 0x425d 4028 #define mmDCP5_GAMUT_REMAP_C23_C24 0x445d 4029 #define mmGAMUT_REMAP_C31_C32 0x1a5e 4030 #define mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e 4031 #define mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e 4032 #define mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e 4033 #define mmDCP3_GAMUT_REMAP_C31_C32 0x405e 4034 #define mmDCP4_GAMUT_REMAP_C31_C32 0x425e 4035 #define mmDCP5_GAMUT_REMAP_C31_C32 0x445e 4036 #define mmGAMUT_REMAP_C33_C34 0x1a5f 4037 #define mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f 4038 #define mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f 4039 #define mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f 4040 #define mmDCP3_GAMUT_REMAP_C33_C34 0x405f 4041 #define mmDCP4_GAMUT_REMAP_C33_C34 0x425f 4042 #define mmDCP5_GAMUT_REMAP_C33_C34 0x445f 4043 #define mmDCP_SPATIAL_DITHER_CNTL 0x1a60 4044 #define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60 4045 #define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60 4046 #define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60 4047 #define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060 4048 #define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260 4049 #define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460 4050 #define mmDCP_RANDOM_SEEDS 0x1a61 4051 #define mmDCP0_DCP_RANDOM_SEEDS 0x1a61 4052 #define mmDCP1_DCP_RANDOM_SEEDS 0x1c61 4053 #define mmDCP2_DCP_RANDOM_SEEDS 0x1e61 4054 #define mmDCP3_DCP_RANDOM_SEEDS 0x4061 4055 #define mmDCP4_DCP_RANDOM_SEEDS 0x4261 4056 #define mmDCP5_DCP_RANDOM_SEEDS 0x4461 4057 #define mmDCP_FP_CONVERTED_FIELD 0x1a65 4058 #define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65 4059 #define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65 4060 #define mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65 4061 #define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065 4062 #define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265 4063 #define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465 4064 #define mmCUR_CONTROL 0x1a66 4065 #define mmDCP0_CUR_CONTROL 0x1a66 4066 #define mmDCP1_CUR_CONTROL 0x1c66 4067 #define mmDCP2_CUR_CONTROL 0x1e66 4068 #define mmDCP3_CUR_CONTROL 0x4066 4069 #define mmDCP4_CUR_CONTROL 0x4266 4070 #define mmDCP5_CUR_CONTROL 0x4466 4071 #define mmCUR_SURFACE_ADDRESS 0x1a67 4072 #define mmDCP0_CUR_SURFACE_ADDRESS 0x1a67 4073 #define mmDCP1_CUR_SURFACE_ADDRESS 0x1c67 4074 #define mmDCP2_CUR_SURFACE_ADDRESS 0x1e67 4075 #define mmDCP3_CUR_SURFACE_ADDRESS 0x4067 4076 #define mmDCP4_CUR_SURFACE_ADDRESS 0x4267 4077 #define mmDCP5_CUR_SURFACE_ADDRESS 0x4467 4078 #define mmCUR_SIZE 0x1a68 4079 #define mmDCP0_CUR_SIZE 0x1a68 4080 #define mmDCP1_CUR_SIZE 0x1c68 4081 #define mmDCP2_CUR_SIZE 0x1e68 4082 #define mmDCP3_CUR_SIZE 0x4068 4083 #define mmDCP4_CUR_SIZE 0x4268 4084 #define mmDCP5_CUR_SIZE 0x4468 4085 #define mmCUR_SURFACE_ADDRESS_HIGH 0x1a69 4086 #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69 4087 #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69 4088 #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69 4089 #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069 4090 #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269 4091 #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469 4092 #define mmCUR_POSITION 0x1a6a 4093 #define mmDCP0_CUR_POSITION 0x1a6a 4094 #define mmDCP1_CUR_POSITION 0x1c6a 4095 #define mmDCP2_CUR_POSITION 0x1e6a 4096 #define mmDCP3_CUR_POSITION 0x406a 4097 #define mmDCP4_CUR_POSITION 0x426a 4098 #define mmDCP5_CUR_POSITION 0x446a 4099 #define mmCUR_HOT_SPOT 0x1a6b 4100 #define mmDCP0_CUR_HOT_SPOT 0x1a6b 4101 #define mmDCP1_CUR_HOT_SPOT 0x1c6b 4102 #define mmDCP2_CUR_HOT_SPOT 0x1e6b 4103 #define mmDCP3_CUR_HOT_SPOT 0x406b 4104 #define mmDCP4_CUR_HOT_SPOT 0x426b 4105 #define mmDCP5_CUR_HOT_SPOT 0x446b 4106 #define mmCUR_COLOR1 0x1a6c 4107 #define mmDCP0_CUR_COLOR1 0x1a6c 4108 #define mmDCP1_CUR_COLOR1 0x1c6c 4109 #define mmDCP2_CUR_COLOR1 0x1e6c 4110 #define mmDCP3_CUR_COLOR1 0x406c 4111 #define mmDCP4_CUR_COLOR1 0x426c 4112 #define mmDCP5_CUR_COLOR1 0x446c 4113 #define mmCUR_COLOR2 0x1a6d 4114 #define mmDCP0_CUR_COLOR2 0x1a6d 4115 #define mmDCP1_CUR_COLOR2 0x1c6d 4116 #define mmDCP2_CUR_COLOR2 0x1e6d 4117 #define mmDCP3_CUR_COLOR2 0x406d 4118 #define mmDCP4_CUR_COLOR2 0x426d 4119 #define mmDCP5_CUR_COLOR2 0x446d 4120 #define mmCUR_UPDATE 0x1a6e 4121 #define mmDCP0_CUR_UPDATE 0x1a6e 4122 #define mmDCP1_CUR_UPDATE 0x1c6e 4123 #define mmDCP2_CUR_UPDATE 0x1e6e 4124 #define mmDCP3_CUR_UPDATE 0x406e 4125 #define mmDCP4_CUR_UPDATE 0x426e 4126 #define mmDCP5_CUR_UPDATE 0x446e 4127 #define mmCUR_REQUEST_FILTER_CNTL 0x1a99 4128 #define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99 4129 #define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99 4130 #define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99 4131 #define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099 4132 #define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299 4133 #define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499 4134 #define mmCUR_STEREO_CONTROL 0x1a9a 4135 #define mmDCP0_CUR_STEREO_CONTROL 0x1a9a 4136 #define mmDCP1_CUR_STEREO_CONTROL 0x1c9a 4137 #define mmDCP2_CUR_STEREO_CONTROL 0x1e9a 4138 #define mmDCP3_CUR_STEREO_CONTROL 0x409a 4139 #define mmDCP4_CUR_STEREO_CONTROL 0x429a 4140 #define mmDCP5_CUR_STEREO_CONTROL 0x449a 4141 #define mmDC_LUT_RW_MODE 0x1a78 4142 #define mmDCP0_DC_LUT_RW_MODE 0x1a78 4143 #define mmDCP1_DC_LUT_RW_MODE 0x1c78 4144 #define mmDCP2_DC_LUT_RW_MODE 0x1e78 4145 #define mmDCP3_DC_LUT_RW_MODE 0x4078 4146 #define mmDCP4_DC_LUT_RW_MODE 0x4278 4147 #define mmDCP5_DC_LUT_RW_MODE 0x4478 4148 #define mmDC_LUT_RW_INDEX 0x1a79 4149 #define mmDCP0_DC_LUT_RW_INDEX 0x1a79 4150 #define mmDCP1_DC_LUT_RW_INDEX 0x1c79 4151 #define mmDCP2_DC_LUT_RW_INDEX 0x1e79 4152 #define mmDCP3_DC_LUT_RW_INDEX 0x4079 4153 #define mmDCP4_DC_LUT_RW_INDEX 0x4279 4154 #define mmDCP5_DC_LUT_RW_INDEX 0x4479 4155 #define mmDC_LUT_SEQ_COLOR 0x1a7a 4156 #define mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a 4157 #define mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a 4158 #define mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a 4159 #define mmDCP3_DC_LUT_SEQ_COLOR 0x407a 4160 #define mmDCP4_DC_LUT_SEQ_COLOR 0x427a 4161 #define mmDCP5_DC_LUT_SEQ_COLOR 0x447a 4162 #define mmDC_LUT_PWL_DATA 0x1a7b 4163 #define mmDCP0_DC_LUT_PWL_DATA 0x1a7b 4164 #define mmDCP1_DC_LUT_PWL_DATA 0x1c7b 4165 #define mmDCP2_DC_LUT_PWL_DATA 0x1e7b 4166 #define mmDCP3_DC_LUT_PWL_DATA 0x407b 4167 #define mmDCP4_DC_LUT_PWL_DATA 0x427b 4168 #define mmDCP5_DC_LUT_PWL_DATA 0x447b 4169 #define mmDC_LUT_30_COLOR 0x1a7c 4170 #define mmDCP0_DC_LUT_30_COLOR 0x1a7c 4171 #define mmDCP1_DC_LUT_30_COLOR 0x1c7c 4172 #define mmDCP2_DC_LUT_30_COLOR 0x1e7c 4173 #define mmDCP3_DC_LUT_30_COLOR 0x407c 4174 #define mmDCP4_DC_LUT_30_COLOR 0x427c 4175 #define mmDCP5_DC_LUT_30_COLOR 0x447c 4176 #define mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d 4177 #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d 4178 #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d 4179 #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d 4180 #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d 4181 #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d 4182 #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d 4183 #define mmDC_LUT_WRITE_EN_MASK 0x1a7e 4184 #define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e 4185 #define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e 4186 #define mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e 4187 #define mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e 4188 #define mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e 4189 #define mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e 4190 #define mmDC_LUT_AUTOFILL 0x1a7f 4191 #define mmDCP0_DC_LUT_AUTOFILL 0x1a7f 4192 #define mmDCP1_DC_LUT_AUTOFILL 0x1c7f 4193 #define mmDCP2_DC_LUT_AUTOFILL 0x1e7f 4194 #define mmDCP3_DC_LUT_AUTOFILL 0x407f 4195 #define mmDCP4_DC_LUT_AUTOFILL 0x427f 4196 #define mmDCP5_DC_LUT_AUTOFILL 0x447f 4197 #define mmDC_LUT_CONTROL 0x1a80 4198 #define mmDCP0_DC_LUT_CONTROL 0x1a80 4199 #define mmDCP1_DC_LUT_CONTROL 0x1c80 4200 #define mmDCP2_DC_LUT_CONTROL 0x1e80 4201 #define mmDCP3_DC_LUT_CONTROL 0x4080 4202 #define mmDCP4_DC_LUT_CONTROL 0x4280 4203 #define mmDCP5_DC_LUT_CONTROL 0x4480 4204 #define mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81 4205 #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81 4206 #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81 4207 #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81 4208 #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081 4209 #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281 4210 #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481 4211 #define mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82 4212 #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82 4213 #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82 4214 #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82 4215 #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082 4216 #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282 4217 #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482 4218 #define mmDC_LUT_BLACK_OFFSET_RED 0x1a83 4219 #define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83 4220 #define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83 4221 #define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83 4222 #define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083 4223 #define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283 4224 #define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483 4225 #define mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84 4226 #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84 4227 #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84 4228 #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84 4229 #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084 4230 #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284 4231 #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484 4232 #define mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85 4233 #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85 4234 #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85 4235 #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85 4236 #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085 4237 #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285 4238 #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485 4239 #define mmDC_LUT_WHITE_OFFSET_RED 0x1a86 4240 #define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86 4241 #define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86 4242 #define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86 4243 #define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086 4244 #define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286 4245 #define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486 4246 #define mmDCP_CRC_CONTROL 0x1a87 4247 #define mmDCP0_DCP_CRC_CONTROL 0x1a87 4248 #define mmDCP1_DCP_CRC_CONTROL 0x1c87 4249 #define mmDCP2_DCP_CRC_CONTROL 0x1e87 4250 #define mmDCP3_DCP_CRC_CONTROL 0x4087 4251 #define mmDCP4_DCP_CRC_CONTROL 0x4287 4252 #define mmDCP5_DCP_CRC_CONTROL 0x4487 4253 #define mmDCP_CRC_MASK 0x1a88 4254 #define mmDCP0_DCP_CRC_MASK 0x1a88 4255 #define mmDCP1_DCP_CRC_MASK 0x1c88 4256 #define mmDCP2_DCP_CRC_MASK 0x1e88 4257 #define mmDCP3_DCP_CRC_MASK 0x4088 4258 #define mmDCP4_DCP_CRC_MASK 0x4288 4259 #define mmDCP5_DCP_CRC_MASK 0x4488 4260 #define mmDCP_CRC_CURRENT 0x1a89 4261 #define mmDCP0_DCP_CRC_CURRENT 0x1a89 4262 #define mmDCP1_DCP_CRC_CURRENT 0x1c89 4263 #define mmDCP2_DCP_CRC_CURRENT 0x1e89 4264 #define mmDCP3_DCP_CRC_CURRENT 0x4089 4265 #define mmDCP4_DCP_CRC_CURRENT 0x4289 4266 #define mmDCP5_DCP_CRC_CURRENT 0x4489 4267 #define mmDVMM_PTE_CONTROL 0x1a8a 4268 #define mmDCP0_DVMM_PTE_CONTROL 0x1a8a 4269 #define mmDCP1_DVMM_PTE_CONTROL 0x1c8a 4270 #define mmDCP2_DVMM_PTE_CONTROL 0x1e8a 4271 #define mmDCP3_DVMM_PTE_CONTROL 0x408a 4272 #define mmDCP4_DVMM_PTE_CONTROL 0x428a 4273 #define mmDCP5_DVMM_PTE_CONTROL 0x448a 4274 #define mmDCP_CRC_LAST 0x1a8b 4275 #define mmDCP0_DCP_CRC_LAST 0x1a8b 4276 #define mmDCP1_DCP_CRC_LAST 0x1c8b 4277 #define mmDCP2_DCP_CRC_LAST 0x1e8b 4278 #define mmDCP3_DCP_CRC_LAST 0x408b 4279 #define mmDCP4_DCP_CRC_LAST 0x428b 4280 #define mmDCP5_DCP_CRC_LAST 0x448b 4281 #define mmDCP_DEBUG 0x1a8d 4282 #define mmDCP0_DCP_DEBUG 0x1a8d 4283 #define mmDCP1_DCP_DEBUG 0x1c8d 4284 #define mmDCP2_DCP_DEBUG 0x1e8d 4285 #define mmDCP3_DCP_DEBUG 0x408d 4286 #define mmDCP4_DCP_DEBUG 0x428d 4287 #define mmDCP5_DCP_DEBUG 0x448d 4288 #define mmGRPH_FLIP_RATE_CNTL 0x1a8e 4289 #define mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e 4290 #define mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e 4291 #define mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e 4292 #define mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e 4293 #define mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e 4294 #define mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e 4295 #define mmDCP_GSL_CONTROL 0x1a90 4296 #define mmDCP0_DCP_GSL_CONTROL 0x1a90 4297 #define mmDCP1_DCP_GSL_CONTROL 0x1c90 4298 #define mmDCP2_DCP_GSL_CONTROL 0x1e90 4299 #define mmDCP3_DCP_GSL_CONTROL 0x4090 4300 #define mmDCP4_DCP_GSL_CONTROL 0x4290 4301 #define mmDCP5_DCP_GSL_CONTROL 0x4490 4302 #define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 4303 #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91 4304 #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91 4305 #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91 4306 #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 4307 #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291 4308 #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491 4309 #define mmDCP_DEBUG_SG 0x1a92 4310 #define mmDCP0_DCP_DEBUG_SG 0x1a92 4311 #define mmDCP1_DCP_DEBUG_SG 0x1c92 4312 #define mmDCP2_DCP_DEBUG_SG 0x1e92 4313 #define mmDCP3_DCP_DEBUG_SG 0x4092 4314 #define mmDCP4_DCP_DEBUG_SG 0x4292 4315 #define mmDCP5_DCP_DEBUG_SG 0x4492 4316 #define mmDCP_DEBUG_SG2 0x1a94 4317 #define mmDCP0_DCP_DEBUG_SG2 0x1a94 4318 #define mmDCP1_DCP_DEBUG_SG2 0x1c94 4319 #define mmDCP2_DCP_DEBUG_SG2 0x1e94 4320 #define mmDCP3_DCP_DEBUG_SG2 0x4094 4321 #define mmDCP4_DCP_DEBUG_SG2 0x4294 4322 #define mmDCP5_DCP_DEBUG_SG2 0x4494 4323 #define mmDCP_DVMM_DEBUG 0x1a93 4324 #define mmDCP0_DCP_DVMM_DEBUG 0x1a93 4325 #define mmDCP1_DCP_DVMM_DEBUG 0x1c93 4326 #define mmDCP2_DCP_DVMM_DEBUG 0x1e93 4327 #define mmDCP3_DCP_DVMM_DEBUG 0x4093 4328 #define mmDCP4_DCP_DVMM_DEBUG 0x4293 4329 #define mmDCP5_DCP_DVMM_DEBUG 0x4493 4330 #define mmDCP_TEST_DEBUG_INDEX 0x1a95 4331 #define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95 4332 #define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95 4333 #define mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95 4334 #define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095 4335 #define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295 4336 #define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495 4337 #define mmDCP_TEST_DEBUG_DATA 0x1a96 4338 #define mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96 4339 #define mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96 4340 #define mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96 4341 #define mmDCP3_DCP_TEST_DEBUG_DATA 0x4096 4342 #define mmDCP4_DCP_TEST_DEBUG_DATA 0x4296 4343 #define mmDCP5_DCP_TEST_DEBUG_DATA 0x4496 4344 #define mmGRPH_STEREOSYNC_FLIP 0x1a97 4345 #define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97 4346 #define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97 4347 #define mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97 4348 #define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097 4349 #define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297 4350 #define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497 4351 #define mmDCP_DEBUG2 0x1a98 4352 #define mmDCP0_DCP_DEBUG2 0x1a98 4353 #define mmDCP1_DCP_DEBUG2 0x1c98 4354 #define mmDCP2_DCP_DEBUG2 0x1e98 4355 #define mmDCP3_DCP_DEBUG2 0x4098 4356 #define mmDCP4_DCP_DEBUG2 0x4298 4357 #define mmDCP5_DCP_DEBUG2 0x4498 4358 #define mmHW_ROTATION 0x1a9e 4359 #define mmDCP0_HW_ROTATION 0x1a9e 4360 #define mmDCP1_HW_ROTATION 0x1c9e 4361 #define mmDCP2_HW_ROTATION 0x1e9e 4362 #define mmDCP3_HW_ROTATION 0x409e 4363 #define mmDCP4_HW_ROTATION 0x429e 4364 #define mmDCP5_HW_ROTATION 0x449e 4365 #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f 4366 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f 4367 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f 4368 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f 4369 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f 4370 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f 4371 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f 4372 #define mmREGAMMA_CONTROL 0x1aa0 4373 #define mmDCP0_REGAMMA_CONTROL 0x1aa0 4374 #define mmDCP1_REGAMMA_CONTROL 0x1ca0 4375 #define mmDCP2_REGAMMA_CONTROL 0x1ea0 4376 #define mmDCP3_REGAMMA_CONTROL 0x40a0 4377 #define mmDCP4_REGAMMA_CONTROL 0x42a0 4378 #define mmDCP5_REGAMMA_CONTROL 0x44a0 4379 #define mmREGAMMA_LUT_INDEX 0x1aa1 4380 #define mmDCP0_REGAMMA_LUT_INDEX 0x1aa1 4381 #define mmDCP1_REGAMMA_LUT_INDEX 0x1ca1 4382 #define mmDCP2_REGAMMA_LUT_INDEX 0x1ea1 4383 #define mmDCP3_REGAMMA_LUT_INDEX 0x40a1 4384 #define mmDCP4_REGAMMA_LUT_INDEX 0x42a1 4385 #define mmDCP5_REGAMMA_LUT_INDEX 0x44a1 4386 #define mmREGAMMA_LUT_DATA 0x1aa2 4387 #define mmDCP0_REGAMMA_LUT_DATA 0x1aa2 4388 #define mmDCP1_REGAMMA_LUT_DATA 0x1ca2 4389 #define mmDCP2_REGAMMA_LUT_DATA 0x1ea2 4390 #define mmDCP3_REGAMMA_LUT_DATA 0x40a2 4391 #define mmDCP4_REGAMMA_LUT_DATA 0x42a2 4392 #define mmDCP5_REGAMMA_LUT_DATA 0x44a2 4393 #define mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3 4394 #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3 4395 #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3 4396 #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3 4397 #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3 4398 #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3 4399 #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3 4400 #define mmREGAMMA_CNTLA_START_CNTL 0x1aa4 4401 #define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4 4402 #define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4 4403 #define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4 4404 #define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4 4405 #define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4 4406 #define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4 4407 #define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 4408 #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5 4409 #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5 4410 #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5 4411 #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5 4412 #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5 4413 #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5 4414 #define mmREGAMMA_CNTLA_END_CNTL1 0x1aa6 4415 #define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6 4416 #define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6 4417 #define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6 4418 #define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6 4419 #define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6 4420 #define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6 4421 #define mmREGAMMA_CNTLA_END_CNTL2 0x1aa7 4422 #define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7 4423 #define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7 4424 #define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7 4425 #define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7 4426 #define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7 4427 #define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7 4428 #define mmREGAMMA_CNTLA_REGION_0_1 0x1aa8 4429 #define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8 4430 #define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8 4431 #define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8 4432 #define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8 4433 #define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8 4434 #define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8 4435 #define mmREGAMMA_CNTLA_REGION_2_3 0x1aa9 4436 #define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9 4437 #define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9 4438 #define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9 4439 #define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9 4440 #define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9 4441 #define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9 4442 #define mmREGAMMA_CNTLA_REGION_4_5 0x1aaa 4443 #define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa 4444 #define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa 4445 #define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa 4446 #define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa 4447 #define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa 4448 #define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa 4449 #define mmREGAMMA_CNTLA_REGION_6_7 0x1aab 4450 #define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab 4451 #define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab 4452 #define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab 4453 #define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab 4454 #define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab 4455 #define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab 4456 #define mmREGAMMA_CNTLA_REGION_8_9 0x1aac 4457 #define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac 4458 #define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac 4459 #define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac 4460 #define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac 4461 #define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac 4462 #define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac 4463 #define mmREGAMMA_CNTLA_REGION_10_11 0x1aad 4464 #define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad 4465 #define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad 4466 #define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead 4467 #define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad 4468 #define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad 4469 #define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad 4470 #define mmREGAMMA_CNTLA_REGION_12_13 0x1aae 4471 #define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae 4472 #define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae 4473 #define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae 4474 #define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae 4475 #define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae 4476 #define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae 4477 #define mmREGAMMA_CNTLA_REGION_14_15 0x1aaf 4478 #define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf 4479 #define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf 4480 #define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf 4481 #define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af 4482 #define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af 4483 #define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af 4484 #define mmREGAMMA_CNTLB_START_CNTL 0x1ab0 4485 #define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0 4486 #define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0 4487 #define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0 4488 #define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0 4489 #define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0 4490 #define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0 4491 #define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 4492 #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1 4493 #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1 4494 #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1 4495 #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1 4496 #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1 4497 #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1 4498 #define mmREGAMMA_CNTLB_END_CNTL1 0x1ab2 4499 #define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2 4500 #define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2 4501 #define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2 4502 #define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2 4503 #define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2 4504 #define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2 4505 #define mmREGAMMA_CNTLB_END_CNTL2 0x1ab3 4506 #define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3 4507 #define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3 4508 #define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3 4509 #define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3 4510 #define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3 4511 #define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3 4512 #define mmREGAMMA_CNTLB_REGION_0_1 0x1ab4 4513 #define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4 4514 #define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4 4515 #define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4 4516 #define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4 4517 #define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4 4518 #define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4 4519 #define mmREGAMMA_CNTLB_REGION_2_3 0x1ab5 4520 #define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5 4521 #define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5 4522 #define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5 4523 #define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5 4524 #define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5 4525 #define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5 4526 #define mmREGAMMA_CNTLB_REGION_4_5 0x1ab6 4527 #define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6 4528 #define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6 4529 #define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6 4530 #define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6 4531 #define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6 4532 #define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6 4533 #define mmREGAMMA_CNTLB_REGION_6_7 0x1ab7 4534 #define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7 4535 #define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7 4536 #define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7 4537 #define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7 4538 #define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7 4539 #define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7 4540 #define mmREGAMMA_CNTLB_REGION_8_9 0x1ab8 4541 #define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8 4542 #define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8 4543 #define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8 4544 #define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8 4545 #define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8 4546 #define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8 4547 #define mmREGAMMA_CNTLB_REGION_10_11 0x1ab9 4548 #define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9 4549 #define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9 4550 #define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9 4551 #define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9 4552 #define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9 4553 #define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9 4554 #define mmREGAMMA_CNTLB_REGION_12_13 0x1aba 4555 #define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba 4556 #define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba 4557 #define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba 4558 #define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba 4559 #define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba 4560 #define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba 4561 #define mmREGAMMA_CNTLB_REGION_14_15 0x1abb 4562 #define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb 4563 #define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb 4564 #define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb 4565 #define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb 4566 #define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb 4567 #define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb 4568 #define mmALPHA_CONTROL 0x1abc 4569 #define mmDCP0_ALPHA_CONTROL 0x1abc 4570 #define mmDCP1_ALPHA_CONTROL 0x1cbc 4571 #define mmDCP2_ALPHA_CONTROL 0x1ebc 4572 #define mmDCP3_ALPHA_CONTROL 0x40bc 4573 #define mmDCP4_ALPHA_CONTROL 0x42bc 4574 #define mmDCP5_ALPHA_CONTROL 0x44bc 4575 #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd 4576 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd 4577 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd 4578 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd 4579 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd 4580 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd 4581 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd 4582 #define mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe 4583 #define mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe 4584 #define mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe 4585 #define mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe 4586 #define mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be 4587 #define mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be 4588 #define mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be 4589 #define mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf 4590 #define mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf 4591 #define mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf 4592 #define mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf 4593 #define mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf 4594 #define mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf 4595 #define mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf 4596 #define mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f 4597 #define mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f 4598 #define mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f 4599 #define mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f 4600 #define mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f 4601 #define mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f 4602 #define mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f 4603 #define mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d 4604 #define mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d 4605 #define mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d 4606 #define mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d 4607 #define mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d 4608 #define mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d 4609 #define mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d 4610 #define mmDIG_FE_CNTL 0x4a00 4611 #define mmDIG0_DIG_FE_CNTL 0x4a00 4612 #define mmDIG1_DIG_FE_CNTL 0x4b00 4613 #define mmDIG2_DIG_FE_CNTL 0x4c00 4614 #define mmDIG3_DIG_FE_CNTL 0x4d00 4615 #define mmDIG4_DIG_FE_CNTL 0x4e00 4616 #define mmDIG5_DIG_FE_CNTL 0x4f00 4617 #define mmDIG6_DIG_FE_CNTL 0x5400 4618 #define mmDIG7_DIG_FE_CNTL 0x5600 4619 #define mmDIG8_DIG_FE_CNTL 0x5700 4620 #define mmDIG_OUTPUT_CRC_CNTL 0x4a01 4621 #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01 4622 #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01 4623 #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01 4624 #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01 4625 #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01 4626 #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01 4627 #define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401 4628 #define mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601 4629 #define mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701 4630 #define mmDIG_OUTPUT_CRC_RESULT 0x4a02 4631 #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02 4632 #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02 4633 #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02 4634 #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02 4635 #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02 4636 #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02 4637 #define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402 4638 #define mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602 4639 #define mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702 4640 #define mmDIG_CLOCK_PATTERN 0x4a03 4641 #define mmDIG0_DIG_CLOCK_PATTERN 0x4a03 4642 #define mmDIG1_DIG_CLOCK_PATTERN 0x4b03 4643 #define mmDIG2_DIG_CLOCK_PATTERN 0x4c03 4644 #define mmDIG3_DIG_CLOCK_PATTERN 0x4d03 4645 #define mmDIG4_DIG_CLOCK_PATTERN 0x4e03 4646 #define mmDIG5_DIG_CLOCK_PATTERN 0x4f03 4647 #define mmDIG6_DIG_CLOCK_PATTERN 0x5403 4648 #define mmDIG7_DIG_CLOCK_PATTERN 0x5603 4649 #define mmDIG8_DIG_CLOCK_PATTERN 0x5703 4650 #define mmDIG_TEST_PATTERN 0x4a04 4651 #define mmDIG0_DIG_TEST_PATTERN 0x4a04 4652 #define mmDIG1_DIG_TEST_PATTERN 0x4b04 4653 #define mmDIG2_DIG_TEST_PATTERN 0x4c04 4654 #define mmDIG3_DIG_TEST_PATTERN 0x4d04 4655 #define mmDIG4_DIG_TEST_PATTERN 0x4e04 4656 #define mmDIG5_DIG_TEST_PATTERN 0x4f04 4657 #define mmDIG6_DIG_TEST_PATTERN 0x5404 4658 #define mmDIG7_DIG_TEST_PATTERN 0x5604 4659 #define mmDIG8_DIG_TEST_PATTERN 0x5704 4660 #define mmDIG_RANDOM_PATTERN_SEED 0x4a05 4661 #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05 4662 #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05 4663 #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05 4664 #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05 4665 #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05 4666 #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05 4667 #define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405 4668 #define mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605 4669 #define mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705 4670 #define mmDIG_FIFO_STATUS 0x4a06 4671 #define mmDIG0_DIG_FIFO_STATUS 0x4a06 4672 #define mmDIG1_DIG_FIFO_STATUS 0x4b06 4673 #define mmDIG2_DIG_FIFO_STATUS 0x4c06 4674 #define mmDIG3_DIG_FIFO_STATUS 0x4d06 4675 #define mmDIG4_DIG_FIFO_STATUS 0x4e06 4676 #define mmDIG5_DIG_FIFO_STATUS 0x4f06 4677 #define mmDIG6_DIG_FIFO_STATUS 0x5406 4678 #define mmDIG7_DIG_FIFO_STATUS 0x5606 4679 #define mmDIG8_DIG_FIFO_STATUS 0x5706 4680 #define mmDIG_DISPCLK_SWITCH_CNTL 0x4a07 4681 #define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07 4682 #define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07 4683 #define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07 4684 #define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07 4685 #define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07 4686 #define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07 4687 #define mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407 4688 #define mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607 4689 #define mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707 4690 #define mmDIG_DISPCLK_SWITCH_STATUS 0x4a08 4691 #define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08 4692 #define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08 4693 #define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08 4694 #define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08 4695 #define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08 4696 #define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08 4697 #define mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408 4698 #define mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608 4699 #define mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708 4700 #define mmHDMI_CONTROL 0x4a09 4701 #define mmDIG0_HDMI_CONTROL 0x4a09 4702 #define mmDIG1_HDMI_CONTROL 0x4b09 4703 #define mmDIG2_HDMI_CONTROL 0x4c09 4704 #define mmDIG3_HDMI_CONTROL 0x4d09 4705 #define mmDIG4_HDMI_CONTROL 0x4e09 4706 #define mmDIG5_HDMI_CONTROL 0x4f09 4707 #define mmDIG6_HDMI_CONTROL 0x5409 4708 #define mmDIG7_HDMI_CONTROL 0x5609 4709 #define mmDIG8_HDMI_CONTROL 0x5709 4710 #define mmHDMI_STATUS 0x4a0a 4711 #define mmDIG0_HDMI_STATUS 0x4a0a 4712 #define mmDIG1_HDMI_STATUS 0x4b0a 4713 #define mmDIG2_HDMI_STATUS 0x4c0a 4714 #define mmDIG3_HDMI_STATUS 0x4d0a 4715 #define mmDIG4_HDMI_STATUS 0x4e0a 4716 #define mmDIG5_HDMI_STATUS 0x4f0a 4717 #define mmDIG6_HDMI_STATUS 0x540a 4718 #define mmDIG7_HDMI_STATUS 0x560a 4719 #define mmDIG8_HDMI_STATUS 0x570a 4720 #define mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b 4721 #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b 4722 #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b 4723 #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b 4724 #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b 4725 #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b 4726 #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b 4727 #define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b 4728 #define mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b 4729 #define mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b 4730 #define mmHDMI_ACR_PACKET_CONTROL 0x4a0c 4731 #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c 4732 #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c 4733 #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c 4734 #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c 4735 #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c 4736 #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c 4737 #define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c 4738 #define mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c 4739 #define mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c 4740 #define mmHDMI_VBI_PACKET_CONTROL 0x4a0d 4741 #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d 4742 #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d 4743 #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d 4744 #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d 4745 #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d 4746 #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d 4747 #define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d 4748 #define mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d 4749 #define mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d 4750 #define mmHDMI_INFOFRAME_CONTROL0 0x4a0e 4751 #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e 4752 #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e 4753 #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e 4754 #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e 4755 #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e 4756 #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e 4757 #define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e 4758 #define mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e 4759 #define mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e 4760 #define mmHDMI_INFOFRAME_CONTROL1 0x4a0f 4761 #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f 4762 #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f 4763 #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f 4764 #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f 4765 #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f 4766 #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f 4767 #define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f 4768 #define mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f 4769 #define mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f 4770 #define mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10 4771 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10 4772 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10 4773 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10 4774 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10 4775 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10 4776 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10 4777 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410 4778 #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610 4779 #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710 4780 #define mmAFMT_INTERRUPT_STATUS 0x4a11 4781 #define mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11 4782 #define mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11 4783 #define mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11 4784 #define mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11 4785 #define mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11 4786 #define mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11 4787 #define mmDIG6_AFMT_INTERRUPT_STATUS 0x5411 4788 #define mmDIG7_AFMT_INTERRUPT_STATUS 0x5611 4789 #define mmDIG8_AFMT_INTERRUPT_STATUS 0x5711 4790 #define mmHDMI_GC 0x4a13 4791 #define mmDIG0_HDMI_GC 0x4a13 4792 #define mmDIG1_HDMI_GC 0x4b13 4793 #define mmDIG2_HDMI_GC 0x4c13 4794 #define mmDIG3_HDMI_GC 0x4d13 4795 #define mmDIG4_HDMI_GC 0x4e13 4796 #define mmDIG5_HDMI_GC 0x4f13 4797 #define mmDIG6_HDMI_GC 0x5413 4798 #define mmDIG7_HDMI_GC 0x5613 4799 #define mmDIG8_HDMI_GC 0x5713 4800 #define mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14 4801 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14 4802 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14 4803 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14 4804 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14 4805 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14 4806 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14 4807 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414 4808 #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614 4809 #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714 4810 #define mmAFMT_ISRC1_0 0x4a15 4811 #define mmDIG0_AFMT_ISRC1_0 0x4a15 4812 #define mmDIG1_AFMT_ISRC1_0 0x4b15 4813 #define mmDIG2_AFMT_ISRC1_0 0x4c15 4814 #define mmDIG3_AFMT_ISRC1_0 0x4d15 4815 #define mmDIG4_AFMT_ISRC1_0 0x4e15 4816 #define mmDIG5_AFMT_ISRC1_0 0x4f15 4817 #define mmDIG6_AFMT_ISRC1_0 0x5415 4818 #define mmDIG7_AFMT_ISRC1_0 0x5615 4819 #define mmDIG8_AFMT_ISRC1_0 0x5715 4820 #define mmAFMT_ISRC1_1 0x4a16 4821 #define mmDIG0_AFMT_ISRC1_1 0x4a16 4822 #define mmDIG1_AFMT_ISRC1_1 0x4b16 4823 #define mmDIG2_AFMT_ISRC1_1 0x4c16 4824 #define mmDIG3_AFMT_ISRC1_1 0x4d16 4825 #define mmDIG4_AFMT_ISRC1_1 0x4e16 4826 #define mmDIG5_AFMT_ISRC1_1 0x4f16 4827 #define mmDIG6_AFMT_ISRC1_1 0x5416 4828 #define mmDIG7_AFMT_ISRC1_1 0x5616 4829 #define mmDIG8_AFMT_ISRC1_1 0x5716 4830 #define mmAFMT_ISRC1_2 0x4a17 4831 #define mmDIG0_AFMT_ISRC1_2 0x4a17 4832 #define mmDIG1_AFMT_ISRC1_2 0x4b17 4833 #define mmDIG2_AFMT_ISRC1_2 0x4c17 4834 #define mmDIG3_AFMT_ISRC1_2 0x4d17 4835 #define mmDIG4_AFMT_ISRC1_2 0x4e17 4836 #define mmDIG5_AFMT_ISRC1_2 0x4f17 4837 #define mmDIG6_AFMT_ISRC1_2 0x5417 4838 #define mmDIG7_AFMT_ISRC1_2 0x5617 4839 #define mmDIG8_AFMT_ISRC1_2 0x5717 4840 #define mmAFMT_ISRC1_3 0x4a18 4841 #define mmDIG0_AFMT_ISRC1_3 0x4a18 4842 #define mmDIG1_AFMT_ISRC1_3 0x4b18 4843 #define mmDIG2_AFMT_ISRC1_3 0x4c18 4844 #define mmDIG3_AFMT_ISRC1_3 0x4d18 4845 #define mmDIG4_AFMT_ISRC1_3 0x4e18 4846 #define mmDIG5_AFMT_ISRC1_3 0x4f18 4847 #define mmDIG6_AFMT_ISRC1_3 0x5418 4848 #define mmDIG7_AFMT_ISRC1_3 0x5618 4849 #define mmDIG8_AFMT_ISRC1_3 0x5718 4850 #define mmAFMT_ISRC1_4 0x4a19 4851 #define mmDIG0_AFMT_ISRC1_4 0x4a19 4852 #define mmDIG1_AFMT_ISRC1_4 0x4b19 4853 #define mmDIG2_AFMT_ISRC1_4 0x4c19 4854 #define mmDIG3_AFMT_ISRC1_4 0x4d19 4855 #define mmDIG4_AFMT_ISRC1_4 0x4e19 4856 #define mmDIG5_AFMT_ISRC1_4 0x4f19 4857 #define mmDIG6_AFMT_ISRC1_4 0x5419 4858 #define mmDIG7_AFMT_ISRC1_4 0x5619 4859 #define mmDIG8_AFMT_ISRC1_4 0x5719 4860 #define mmAFMT_ISRC2_0 0x4a1a 4861 #define mmDIG0_AFMT_ISRC2_0 0x4a1a 4862 #define mmDIG1_AFMT_ISRC2_0 0x4b1a 4863 #define mmDIG2_AFMT_ISRC2_0 0x4c1a 4864 #define mmDIG3_AFMT_ISRC2_0 0x4d1a 4865 #define mmDIG4_AFMT_ISRC2_0 0x4e1a 4866 #define mmDIG5_AFMT_ISRC2_0 0x4f1a 4867 #define mmDIG6_AFMT_ISRC2_0 0x541a 4868 #define mmDIG7_AFMT_ISRC2_0 0x561a 4869 #define mmDIG8_AFMT_ISRC2_0 0x571a 4870 #define mmAFMT_ISRC2_1 0x4a1b 4871 #define mmDIG0_AFMT_ISRC2_1 0x4a1b 4872 #define mmDIG1_AFMT_ISRC2_1 0x4b1b 4873 #define mmDIG2_AFMT_ISRC2_1 0x4c1b 4874 #define mmDIG3_AFMT_ISRC2_1 0x4d1b 4875 #define mmDIG4_AFMT_ISRC2_1 0x4e1b 4876 #define mmDIG5_AFMT_ISRC2_1 0x4f1b 4877 #define mmDIG6_AFMT_ISRC2_1 0x541b 4878 #define mmDIG7_AFMT_ISRC2_1 0x561b 4879 #define mmDIG8_AFMT_ISRC2_1 0x571b 4880 #define mmAFMT_ISRC2_2 0x4a1c 4881 #define mmDIG0_AFMT_ISRC2_2 0x4a1c 4882 #define mmDIG1_AFMT_ISRC2_2 0x4b1c 4883 #define mmDIG2_AFMT_ISRC2_2 0x4c1c 4884 #define mmDIG3_AFMT_ISRC2_2 0x4d1c 4885 #define mmDIG4_AFMT_ISRC2_2 0x4e1c 4886 #define mmDIG5_AFMT_ISRC2_2 0x4f1c 4887 #define mmDIG6_AFMT_ISRC2_2 0x541c 4888 #define mmDIG7_AFMT_ISRC2_2 0x561c 4889 #define mmDIG8_AFMT_ISRC2_2 0x571c 4890 #define mmAFMT_ISRC2_3 0x4a1d 4891 #define mmDIG0_AFMT_ISRC2_3 0x4a1d 4892 #define mmDIG1_AFMT_ISRC2_3 0x4b1d 4893 #define mmDIG2_AFMT_ISRC2_3 0x4c1d 4894 #define mmDIG3_AFMT_ISRC2_3 0x4d1d 4895 #define mmDIG4_AFMT_ISRC2_3 0x4e1d 4896 #define mmDIG5_AFMT_ISRC2_3 0x4f1d 4897 #define mmDIG6_AFMT_ISRC2_3 0x541d 4898 #define mmDIG7_AFMT_ISRC2_3 0x561d 4899 #define mmDIG8_AFMT_ISRC2_3 0x571d 4900 #define mmAFMT_AVI_INFO0 0x4a1e 4901 #define mmDIG0_AFMT_AVI_INFO0 0x4a1e 4902 #define mmDIG1_AFMT_AVI_INFO0 0x4b1e 4903 #define mmDIG2_AFMT_AVI_INFO0 0x4c1e 4904 #define mmDIG3_AFMT_AVI_INFO0 0x4d1e 4905 #define mmDIG4_AFMT_AVI_INFO0 0x4e1e 4906 #define mmDIG5_AFMT_AVI_INFO0 0x4f1e 4907 #define mmDIG6_AFMT_AVI_INFO0 0x541e 4908 #define mmDIG7_AFMT_AVI_INFO0 0x561e 4909 #define mmDIG8_AFMT_AVI_INFO0 0x571e 4910 #define mmAFMT_AVI_INFO1 0x4a1f 4911 #define mmDIG0_AFMT_AVI_INFO1 0x4a1f 4912 #define mmDIG1_AFMT_AVI_INFO1 0x4b1f 4913 #define mmDIG2_AFMT_AVI_INFO1 0x4c1f 4914 #define mmDIG3_AFMT_AVI_INFO1 0x4d1f 4915 #define mmDIG4_AFMT_AVI_INFO1 0x4e1f 4916 #define mmDIG5_AFMT_AVI_INFO1 0x4f1f 4917 #define mmDIG6_AFMT_AVI_INFO1 0x541f 4918 #define mmDIG7_AFMT_AVI_INFO1 0x561f 4919 #define mmDIG8_AFMT_AVI_INFO1 0x571f 4920 #define mmAFMT_AVI_INFO2 0x4a20 4921 #define mmDIG0_AFMT_AVI_INFO2 0x4a20 4922 #define mmDIG1_AFMT_AVI_INFO2 0x4b20 4923 #define mmDIG2_AFMT_AVI_INFO2 0x4c20 4924 #define mmDIG3_AFMT_AVI_INFO2 0x4d20 4925 #define mmDIG4_AFMT_AVI_INFO2 0x4e20 4926 #define mmDIG5_AFMT_AVI_INFO2 0x4f20 4927 #define mmDIG6_AFMT_AVI_INFO2 0x5420 4928 #define mmDIG7_AFMT_AVI_INFO2 0x5620 4929 #define mmDIG8_AFMT_AVI_INFO2 0x5720 4930 #define mmAFMT_AVI_INFO3 0x4a21 4931 #define mmDIG0_AFMT_AVI_INFO3 0x4a21 4932 #define mmDIG1_AFMT_AVI_INFO3 0x4b21 4933 #define mmDIG2_AFMT_AVI_INFO3 0x4c21 4934 #define mmDIG3_AFMT_AVI_INFO3 0x4d21 4935 #define mmDIG4_AFMT_AVI_INFO3 0x4e21 4936 #define mmDIG5_AFMT_AVI_INFO3 0x4f21 4937 #define mmDIG6_AFMT_AVI_INFO3 0x5421 4938 #define mmDIG7_AFMT_AVI_INFO3 0x5621 4939 #define mmDIG8_AFMT_AVI_INFO3 0x5721 4940 #define mmAFMT_MPEG_INFO0 0x4a22 4941 #define mmDIG0_AFMT_MPEG_INFO0 0x4a22 4942 #define mmDIG1_AFMT_MPEG_INFO0 0x4b22 4943 #define mmDIG2_AFMT_MPEG_INFO0 0x4c22 4944 #define mmDIG3_AFMT_MPEG_INFO0 0x4d22 4945 #define mmDIG4_AFMT_MPEG_INFO0 0x4e22 4946 #define mmDIG5_AFMT_MPEG_INFO0 0x4f22 4947 #define mmDIG6_AFMT_MPEG_INFO0 0x5422 4948 #define mmDIG7_AFMT_MPEG_INFO0 0x5622 4949 #define mmDIG8_AFMT_MPEG_INFO0 0x5722 4950 #define mmAFMT_MPEG_INFO1 0x4a23 4951 #define mmDIG0_AFMT_MPEG_INFO1 0x4a23 4952 #define mmDIG1_AFMT_MPEG_INFO1 0x4b23 4953 #define mmDIG2_AFMT_MPEG_INFO1 0x4c23 4954 #define mmDIG3_AFMT_MPEG_INFO1 0x4d23 4955 #define mmDIG4_AFMT_MPEG_INFO1 0x4e23 4956 #define mmDIG5_AFMT_MPEG_INFO1 0x4f23 4957 #define mmDIG6_AFMT_MPEG_INFO1 0x5423 4958 #define mmDIG7_AFMT_MPEG_INFO1 0x5623 4959 #define mmDIG8_AFMT_MPEG_INFO1 0x5723 4960 #define mmAFMT_GENERIC_HDR 0x4a24 4961 #define mmDIG0_AFMT_GENERIC_HDR 0x4a24 4962 #define mmDIG1_AFMT_GENERIC_HDR 0x4b24 4963 #define mmDIG2_AFMT_GENERIC_HDR 0x4c24 4964 #define mmDIG3_AFMT_GENERIC_HDR 0x4d24 4965 #define mmDIG4_AFMT_GENERIC_HDR 0x4e24 4966 #define mmDIG5_AFMT_GENERIC_HDR 0x4f24 4967 #define mmDIG6_AFMT_GENERIC_HDR 0x5424 4968 #define mmDIG7_AFMT_GENERIC_HDR 0x5624 4969 #define mmDIG8_AFMT_GENERIC_HDR 0x5724 4970 #define mmAFMT_GENERIC_0 0x4a25 4971 #define mmDIG0_AFMT_GENERIC_0 0x4a25 4972 #define mmDIG1_AFMT_GENERIC_0 0x4b25 4973 #define mmDIG2_AFMT_GENERIC_0 0x4c25 4974 #define mmDIG3_AFMT_GENERIC_0 0x4d25 4975 #define mmDIG4_AFMT_GENERIC_0 0x4e25 4976 #define mmDIG5_AFMT_GENERIC_0 0x4f25 4977 #define mmDIG6_AFMT_GENERIC_0 0x5425 4978 #define mmDIG7_AFMT_GENERIC_0 0x5625 4979 #define mmDIG8_AFMT_GENERIC_0 0x5725 4980 #define mmAFMT_GENERIC_1 0x4a26 4981 #define mmDIG0_AFMT_GENERIC_1 0x4a26 4982 #define mmDIG1_AFMT_GENERIC_1 0x4b26 4983 #define mmDIG2_AFMT_GENERIC_1 0x4c26 4984 #define mmDIG3_AFMT_GENERIC_1 0x4d26 4985 #define mmDIG4_AFMT_GENERIC_1 0x4e26 4986 #define mmDIG5_AFMT_GENERIC_1 0x4f26 4987 #define mmDIG6_AFMT_GENERIC_1 0x5426 4988 #define mmDIG7_AFMT_GENERIC_1 0x5626 4989 #define mmDIG8_AFMT_GENERIC_1 0x5726 4990 #define mmAFMT_GENERIC_2 0x4a27 4991 #define mmDIG0_AFMT_GENERIC_2 0x4a27 4992 #define mmDIG1_AFMT_GENERIC_2 0x4b27 4993 #define mmDIG2_AFMT_GENERIC_2 0x4c27 4994 #define mmDIG3_AFMT_GENERIC_2 0x4d27 4995 #define mmDIG4_AFMT_GENERIC_2 0x4e27 4996 #define mmDIG5_AFMT_GENERIC_2 0x4f27 4997 #define mmDIG6_AFMT_GENERIC_2 0x5427 4998 #define mmDIG7_AFMT_GENERIC_2 0x5627 4999 #define mmDIG8_AFMT_GENERIC_2 0x5727 5000 #define mmAFMT_GENERIC_3 0x4a28 5001 #define mmDIG0_AFMT_GENERIC_3 0x4a28 5002 #define mmDIG1_AFMT_GENERIC_3 0x4b28 5003 #define mmDIG2_AFMT_GENERIC_3 0x4c28 5004 #define mmDIG3_AFMT_GENERIC_3 0x4d28 5005 #define mmDIG4_AFMT_GENERIC_3 0x4e28 5006 #define mmDIG5_AFMT_GENERIC_3 0x4f28 5007 #define mmDIG6_AFMT_GENERIC_3 0x5428 5008 #define mmDIG7_AFMT_GENERIC_3 0x5628 5009 #define mmDIG8_AFMT_GENERIC_3 0x5728 5010 #define mmAFMT_GENERIC_4 0x4a29 5011 #define mmDIG0_AFMT_GENERIC_4 0x4a29 5012 #define mmDIG1_AFMT_GENERIC_4 0x4b29 5013 #define mmDIG2_AFMT_GENERIC_4 0x4c29 5014 #define mmDIG3_AFMT_GENERIC_4 0x4d29 5015 #define mmDIG4_AFMT_GENERIC_4 0x4e29 5016 #define mmDIG5_AFMT_GENERIC_4 0x4f29 5017 #define mmDIG6_AFMT_GENERIC_4 0x5429 5018 #define mmDIG7_AFMT_GENERIC_4 0x5629 5019 #define mmDIG8_AFMT_GENERIC_4 0x5729 5020 #define mmAFMT_GENERIC_5 0x4a2a 5021 #define mmDIG0_AFMT_GENERIC_5 0x4a2a 5022 #define mmDIG1_AFMT_GENERIC_5 0x4b2a 5023 #define mmDIG2_AFMT_GENERIC_5 0x4c2a 5024 #define mmDIG3_AFMT_GENERIC_5 0x4d2a 5025 #define mmDIG4_AFMT_GENERIC_5 0x4e2a 5026 #define mmDIG5_AFMT_GENERIC_5 0x4f2a 5027 #define mmDIG6_AFMT_GENERIC_5 0x542a 5028 #define mmDIG7_AFMT_GENERIC_5 0x562a 5029 #define mmDIG8_AFMT_GENERIC_5 0x572a 5030 #define mmAFMT_GENERIC_6 0x4a2b 5031 #define mmDIG0_AFMT_GENERIC_6 0x4a2b 5032 #define mmDIG1_AFMT_GENERIC_6 0x4b2b 5033 #define mmDIG2_AFMT_GENERIC_6 0x4c2b 5034 #define mmDIG3_AFMT_GENERIC_6 0x4d2b 5035 #define mmDIG4_AFMT_GENERIC_6 0x4e2b 5036 #define mmDIG5_AFMT_GENERIC_6 0x4f2b 5037 #define mmDIG6_AFMT_GENERIC_6 0x542b 5038 #define mmDIG7_AFMT_GENERIC_6 0x562b 5039 #define mmDIG8_AFMT_GENERIC_6 0x572b 5040 #define mmAFMT_GENERIC_7 0x4a2c 5041 #define mmDIG0_AFMT_GENERIC_7 0x4a2c 5042 #define mmDIG1_AFMT_GENERIC_7 0x4b2c 5043 #define mmDIG2_AFMT_GENERIC_7 0x4c2c 5044 #define mmDIG3_AFMT_GENERIC_7 0x4d2c 5045 #define mmDIG4_AFMT_GENERIC_7 0x4e2c 5046 #define mmDIG5_AFMT_GENERIC_7 0x4f2c 5047 #define mmDIG6_AFMT_GENERIC_7 0x542c 5048 #define mmDIG7_AFMT_GENERIC_7 0x562c 5049 #define mmDIG8_AFMT_GENERIC_7 0x572c 5050 #define mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d 5051 #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d 5052 #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d 5053 #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d 5054 #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d 5055 #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d 5056 #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d 5057 #define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d 5058 #define mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d 5059 #define mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d 5060 #define mmHDMI_ACR_32_0 0x4a2e 5061 #define mmDIG0_HDMI_ACR_32_0 0x4a2e 5062 #define mmDIG1_HDMI_ACR_32_0 0x4b2e 5063 #define mmDIG2_HDMI_ACR_32_0 0x4c2e 5064 #define mmDIG3_HDMI_ACR_32_0 0x4d2e 5065 #define mmDIG4_HDMI_ACR_32_0 0x4e2e 5066 #define mmDIG5_HDMI_ACR_32_0 0x4f2e 5067 #define mmDIG6_HDMI_ACR_32_0 0x542e 5068 #define mmDIG7_HDMI_ACR_32_0 0x562e 5069 #define mmDIG8_HDMI_ACR_32_0 0x572e 5070 #define mmHDMI_ACR_32_1 0x4a2f 5071 #define mmDIG0_HDMI_ACR_32_1 0x4a2f 5072 #define mmDIG1_HDMI_ACR_32_1 0x4b2f 5073 #define mmDIG2_HDMI_ACR_32_1 0x4c2f 5074 #define mmDIG3_HDMI_ACR_32_1 0x4d2f 5075 #define mmDIG4_HDMI_ACR_32_1 0x4e2f 5076 #define mmDIG5_HDMI_ACR_32_1 0x4f2f 5077 #define mmDIG6_HDMI_ACR_32_1 0x542f 5078 #define mmDIG7_HDMI_ACR_32_1 0x562f 5079 #define mmDIG8_HDMI_ACR_32_1 0x572f 5080 #define mmHDMI_ACR_44_0 0x4a30 5081 #define mmDIG0_HDMI_ACR_44_0 0x4a30 5082 #define mmDIG1_HDMI_ACR_44_0 0x4b30 5083 #define mmDIG2_HDMI_ACR_44_0 0x4c30 5084 #define mmDIG3_HDMI_ACR_44_0 0x4d30 5085 #define mmDIG4_HDMI_ACR_44_0 0x4e30 5086 #define mmDIG5_HDMI_ACR_44_0 0x4f30 5087 #define mmDIG6_HDMI_ACR_44_0 0x5430 5088 #define mmDIG7_HDMI_ACR_44_0 0x5630 5089 #define mmDIG8_HDMI_ACR_44_0 0x5730 5090 #define mmHDMI_ACR_44_1 0x4a31 5091 #define mmDIG0_HDMI_ACR_44_1 0x4a31 5092 #define mmDIG1_HDMI_ACR_44_1 0x4b31 5093 #define mmDIG2_HDMI_ACR_44_1 0x4c31 5094 #define mmDIG3_HDMI_ACR_44_1 0x4d31 5095 #define mmDIG4_HDMI_ACR_44_1 0x4e31 5096 #define mmDIG5_HDMI_ACR_44_1 0x4f31 5097 #define mmDIG6_HDMI_ACR_44_1 0x5431 5098 #define mmDIG7_HDMI_ACR_44_1 0x5631 5099 #define mmDIG8_HDMI_ACR_44_1 0x5731 5100 #define mmHDMI_ACR_48_0 0x4a32 5101 #define mmDIG0_HDMI_ACR_48_0 0x4a32 5102 #define mmDIG1_HDMI_ACR_48_0 0x4b32 5103 #define mmDIG2_HDMI_ACR_48_0 0x4c32 5104 #define mmDIG3_HDMI_ACR_48_0 0x4d32 5105 #define mmDIG4_HDMI_ACR_48_0 0x4e32 5106 #define mmDIG5_HDMI_ACR_48_0 0x4f32 5107 #define mmDIG6_HDMI_ACR_48_0 0x5432 5108 #define mmDIG7_HDMI_ACR_48_0 0x5632 5109 #define mmDIG8_HDMI_ACR_48_0 0x5732 5110 #define mmHDMI_ACR_48_1 0x4a33 5111 #define mmDIG0_HDMI_ACR_48_1 0x4a33 5112 #define mmDIG1_HDMI_ACR_48_1 0x4b33 5113 #define mmDIG2_HDMI_ACR_48_1 0x4c33 5114 #define mmDIG3_HDMI_ACR_48_1 0x4d33 5115 #define mmDIG4_HDMI_ACR_48_1 0x4e33 5116 #define mmDIG5_HDMI_ACR_48_1 0x4f33 5117 #define mmDIG6_HDMI_ACR_48_1 0x5433 5118 #define mmDIG7_HDMI_ACR_48_1 0x5633 5119 #define mmDIG8_HDMI_ACR_48_1 0x5733 5120 #define mmHDMI_ACR_STATUS_0 0x4a34 5121 #define mmDIG0_HDMI_ACR_STATUS_0 0x4a34 5122 #define mmDIG1_HDMI_ACR_STATUS_0 0x4b34 5123 #define mmDIG2_HDMI_ACR_STATUS_0 0x4c34 5124 #define mmDIG3_HDMI_ACR_STATUS_0 0x4d34 5125 #define mmDIG4_HDMI_ACR_STATUS_0 0x4e34 5126 #define mmDIG5_HDMI_ACR_STATUS_0 0x4f34 5127 #define mmDIG6_HDMI_ACR_STATUS_0 0x5434 5128 #define mmDIG7_HDMI_ACR_STATUS_0 0x5634 5129 #define mmDIG8_HDMI_ACR_STATUS_0 0x5734 5130 #define mmHDMI_ACR_STATUS_1 0x4a35 5131 #define mmDIG0_HDMI_ACR_STATUS_1 0x4a35 5132 #define mmDIG1_HDMI_ACR_STATUS_1 0x4b35 5133 #define mmDIG2_HDMI_ACR_STATUS_1 0x4c35 5134 #define mmDIG3_HDMI_ACR_STATUS_1 0x4d35 5135 #define mmDIG4_HDMI_ACR_STATUS_1 0x4e35 5136 #define mmDIG5_HDMI_ACR_STATUS_1 0x4f35 5137 #define mmDIG6_HDMI_ACR_STATUS_1 0x5435 5138 #define mmDIG7_HDMI_ACR_STATUS_1 0x5635 5139 #define mmDIG8_HDMI_ACR_STATUS_1 0x5735 5140 #define mmAFMT_AUDIO_INFO0 0x4a36 5141 #define mmDIG0_AFMT_AUDIO_INFO0 0x4a36 5142 #define mmDIG1_AFMT_AUDIO_INFO0 0x4b36 5143 #define mmDIG2_AFMT_AUDIO_INFO0 0x4c36 5144 #define mmDIG3_AFMT_AUDIO_INFO0 0x4d36 5145 #define mmDIG4_AFMT_AUDIO_INFO0 0x4e36 5146 #define mmDIG5_AFMT_AUDIO_INFO0 0x4f36 5147 #define mmDIG6_AFMT_AUDIO_INFO0 0x5436 5148 #define mmDIG7_AFMT_AUDIO_INFO0 0x5636 5149 #define mmDIG8_AFMT_AUDIO_INFO0 0x5736 5150 #define mmAFMT_AUDIO_INFO1 0x4a37 5151 #define mmDIG0_AFMT_AUDIO_INFO1 0x4a37 5152 #define mmDIG1_AFMT_AUDIO_INFO1 0x4b37 5153 #define mmDIG2_AFMT_AUDIO_INFO1 0x4c37 5154 #define mmDIG3_AFMT_AUDIO_INFO1 0x4d37 5155 #define mmDIG4_AFMT_AUDIO_INFO1 0x4e37 5156 #define mmDIG5_AFMT_AUDIO_INFO1 0x4f37 5157 #define mmDIG6_AFMT_AUDIO_INFO1 0x5437 5158 #define mmDIG7_AFMT_AUDIO_INFO1 0x5637 5159 #define mmDIG8_AFMT_AUDIO_INFO1 0x5737 5160 #define mmAFMT_60958_0 0x4a38 5161 #define mmDIG0_AFMT_60958_0 0x4a38 5162 #define mmDIG1_AFMT_60958_0 0x4b38 5163 #define mmDIG2_AFMT_60958_0 0x4c38 5164 #define mmDIG3_AFMT_60958_0 0x4d38 5165 #define mmDIG4_AFMT_60958_0 0x4e38 5166 #define mmDIG5_AFMT_60958_0 0x4f38 5167 #define mmDIG6_AFMT_60958_0 0x5438 5168 #define mmDIG7_AFMT_60958_0 0x5638 5169 #define mmDIG8_AFMT_60958_0 0x5738 5170 #define mmAFMT_60958_1 0x4a39 5171 #define mmDIG0_AFMT_60958_1 0x4a39 5172 #define mmDIG1_AFMT_60958_1 0x4b39 5173 #define mmDIG2_AFMT_60958_1 0x4c39 5174 #define mmDIG3_AFMT_60958_1 0x4d39 5175 #define mmDIG4_AFMT_60958_1 0x4e39 5176 #define mmDIG5_AFMT_60958_1 0x4f39 5177 #define mmDIG6_AFMT_60958_1 0x5439 5178 #define mmDIG7_AFMT_60958_1 0x5639 5179 #define mmDIG8_AFMT_60958_1 0x5739 5180 #define mmAFMT_AUDIO_CRC_CONTROL 0x4a3a 5181 #define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a 5182 #define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a 5183 #define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a 5184 #define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a 5185 #define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a 5186 #define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a 5187 #define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a 5188 #define mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a 5189 #define mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a 5190 #define mmAFMT_RAMP_CONTROL0 0x4a3b 5191 #define mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b 5192 #define mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b 5193 #define mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b 5194 #define mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b 5195 #define mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b 5196 #define mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b 5197 #define mmDIG6_AFMT_RAMP_CONTROL0 0x543b 5198 #define mmDIG7_AFMT_RAMP_CONTROL0 0x563b 5199 #define mmDIG8_AFMT_RAMP_CONTROL0 0x573b 5200 #define mmAFMT_RAMP_CONTROL1 0x4a3c 5201 #define mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c 5202 #define mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c 5203 #define mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c 5204 #define mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c 5205 #define mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c 5206 #define mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c 5207 #define mmDIG6_AFMT_RAMP_CONTROL1 0x543c 5208 #define mmDIG7_AFMT_RAMP_CONTROL1 0x563c 5209 #define mmDIG8_AFMT_RAMP_CONTROL1 0x573c 5210 #define mmAFMT_RAMP_CONTROL2 0x4a3d 5211 #define mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d 5212 #define mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d 5213 #define mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d 5214 #define mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d 5215 #define mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d 5216 #define mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d 5217 #define mmDIG6_AFMT_RAMP_CONTROL2 0x543d 5218 #define mmDIG7_AFMT_RAMP_CONTROL2 0x563d 5219 #define mmDIG8_AFMT_RAMP_CONTROL2 0x573d 5220 #define mmAFMT_RAMP_CONTROL3 0x4a3e 5221 #define mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e 5222 #define mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e 5223 #define mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e 5224 #define mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e 5225 #define mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e 5226 #define mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e 5227 #define mmDIG6_AFMT_RAMP_CONTROL3 0x543e 5228 #define mmDIG7_AFMT_RAMP_CONTROL3 0x563e 5229 #define mmDIG8_AFMT_RAMP_CONTROL3 0x573e 5230 #define mmAFMT_60958_2 0x4a3f 5231 #define mmDIG0_AFMT_60958_2 0x4a3f 5232 #define mmDIG1_AFMT_60958_2 0x4b3f 5233 #define mmDIG2_AFMT_60958_2 0x4c3f 5234 #define mmDIG3_AFMT_60958_2 0x4d3f 5235 #define mmDIG4_AFMT_60958_2 0x4e3f 5236 #define mmDIG5_AFMT_60958_2 0x4f3f 5237 #define mmDIG6_AFMT_60958_2 0x543f 5238 #define mmDIG7_AFMT_60958_2 0x563f 5239 #define mmDIG8_AFMT_60958_2 0x573f 5240 #define mmAFMT_AUDIO_CRC_RESULT 0x4a40 5241 #define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40 5242 #define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40 5243 #define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40 5244 #define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40 5245 #define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40 5246 #define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40 5247 #define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440 5248 #define mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640 5249 #define mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740 5250 #define mmAFMT_STATUS 0x4a41 5251 #define mmDIG0_AFMT_STATUS 0x4a41 5252 #define mmDIG1_AFMT_STATUS 0x4b41 5253 #define mmDIG2_AFMT_STATUS 0x4c41 5254 #define mmDIG3_AFMT_STATUS 0x4d41 5255 #define mmDIG4_AFMT_STATUS 0x4e41 5256 #define mmDIG5_AFMT_STATUS 0x4f41 5257 #define mmDIG6_AFMT_STATUS 0x5441 5258 #define mmDIG7_AFMT_STATUS 0x5641 5259 #define mmDIG8_AFMT_STATUS 0x5741 5260 #define mmAFMT_AUDIO_PACKET_CONTROL 0x4a42 5261 #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42 5262 #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42 5263 #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42 5264 #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42 5265 #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42 5266 #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42 5267 #define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442 5268 #define mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642 5269 #define mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742 5270 #define mmAFMT_VBI_PACKET_CONTROL 0x4a43 5271 #define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43 5272 #define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43 5273 #define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43 5274 #define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43 5275 #define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43 5276 #define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43 5277 #define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443 5278 #define mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643 5279 #define mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743 5280 #define mmAFMT_INFOFRAME_CONTROL0 0x4a44 5281 #define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44 5282 #define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44 5283 #define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44 5284 #define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44 5285 #define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44 5286 #define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44 5287 #define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444 5288 #define mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644 5289 #define mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744 5290 #define mmAFMT_AUDIO_SRC_CONTROL 0x4a45 5291 #define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45 5292 #define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45 5293 #define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45 5294 #define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45 5295 #define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45 5296 #define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45 5297 #define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445 5298 #define mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645 5299 #define mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745 5300 #define mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46 5301 #define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46 5302 #define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46 5303 #define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46 5304 #define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46 5305 #define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46 5306 #define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46 5307 #define mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446 5308 #define mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646 5309 #define mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746 5310 #define mmAFMT_CNTL 0x4a7e 5311 #define mmDIG0_AFMT_CNTL 0x4a7e 5312 #define mmDIG1_AFMT_CNTL 0x4b7e 5313 #define mmDIG2_AFMT_CNTL 0x4c7e 5314 #define mmDIG3_AFMT_CNTL 0x4d7e 5315 #define mmDIG4_AFMT_CNTL 0x4e7e 5316 #define mmDIG5_AFMT_CNTL 0x4f7e 5317 #define mmDIG6_AFMT_CNTL 0x547e 5318 #define mmDIG7_AFMT_CNTL 0x567e 5319 #define mmDIG8_AFMT_CNTL 0x577e 5320 #define mmDIG_BE_CNTL 0x4a47 5321 #define mmDIG0_DIG_BE_CNTL 0x4a47 5322 #define mmDIG1_DIG_BE_CNTL 0x4b47 5323 #define mmDIG2_DIG_BE_CNTL 0x4c47 5324 #define mmDIG3_DIG_BE_CNTL 0x4d47 5325 #define mmDIG4_DIG_BE_CNTL 0x4e47 5326 #define mmDIG5_DIG_BE_CNTL 0x4f47 5327 #define mmDIG6_DIG_BE_CNTL 0x5447 5328 #define mmDIG7_DIG_BE_CNTL 0x5647 5329 #define mmDIG8_DIG_BE_CNTL 0x5747 5330 #define mmDIG_BE_EN_CNTL 0x4a48 5331 #define mmDIG0_DIG_BE_EN_CNTL 0x4a48 5332 #define mmDIG1_DIG_BE_EN_CNTL 0x4b48 5333 #define mmDIG2_DIG_BE_EN_CNTL 0x4c48 5334 #define mmDIG3_DIG_BE_EN_CNTL 0x4d48 5335 #define mmDIG4_DIG_BE_EN_CNTL 0x4e48 5336 #define mmDIG5_DIG_BE_EN_CNTL 0x4f48 5337 #define mmDIG6_DIG_BE_EN_CNTL 0x5448 5338 #define mmDIG7_DIG_BE_EN_CNTL 0x5648 5339 #define mmDIG8_DIG_BE_EN_CNTL 0x5748 5340 #define mmTMDS_CNTL 0x4a6b 5341 #define mmDIG0_TMDS_CNTL 0x4a6b 5342 #define mmDIG1_TMDS_CNTL 0x4b6b 5343 #define mmDIG2_TMDS_CNTL 0x4c6b 5344 #define mmDIG3_TMDS_CNTL 0x4d6b 5345 #define mmDIG4_TMDS_CNTL 0x4e6b 5346 #define mmDIG5_TMDS_CNTL 0x4f6b 5347 #define mmDIG6_TMDS_CNTL 0x546b 5348 #define mmDIG7_TMDS_CNTL 0x566b 5349 #define mmDIG8_TMDS_CNTL 0x576b 5350 #define mmTMDS_CONTROL_CHAR 0x4a6c 5351 #define mmDIG0_TMDS_CONTROL_CHAR 0x4a6c 5352 #define mmDIG1_TMDS_CONTROL_CHAR 0x4b6c 5353 #define mmDIG2_TMDS_CONTROL_CHAR 0x4c6c 5354 #define mmDIG3_TMDS_CONTROL_CHAR 0x4d6c 5355 #define mmDIG4_TMDS_CONTROL_CHAR 0x4e6c 5356 #define mmDIG5_TMDS_CONTROL_CHAR 0x4f6c 5357 #define mmDIG6_TMDS_CONTROL_CHAR 0x546c 5358 #define mmDIG7_TMDS_CONTROL_CHAR 0x566c 5359 #define mmDIG8_TMDS_CONTROL_CHAR 0x576c 5360 #define mmTMDS_CONTROL0_FEEDBACK 0x4a6d 5361 #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d 5362 #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d 5363 #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d 5364 #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d 5365 #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d 5366 #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d 5367 #define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d 5368 #define mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d 5369 #define mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d 5370 #define mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e 5371 #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e 5372 #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e 5373 #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e 5374 #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e 5375 #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e 5376 #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e 5377 #define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e 5378 #define mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e 5379 #define mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e 5380 #define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f 5381 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f 5382 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f 5383 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f 5384 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f 5385 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f 5386 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f 5387 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f 5388 #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f 5389 #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f 5390 #define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 5391 #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70 5392 #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70 5393 #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70 5394 #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70 5395 #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70 5396 #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70 5397 #define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470 5398 #define mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670 5399 #define mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770 5400 #define mmTMDS_DEBUG 0x4a71 5401 #define mmDIG0_TMDS_DEBUG 0x4a71 5402 #define mmDIG1_TMDS_DEBUG 0x4b71 5403 #define mmDIG2_TMDS_DEBUG 0x4c71 5404 #define mmDIG3_TMDS_DEBUG 0x4d71 5405 #define mmDIG4_TMDS_DEBUG 0x4e71 5406 #define mmDIG5_TMDS_DEBUG 0x4f71 5407 #define mmDIG6_TMDS_DEBUG 0x5471 5408 #define mmDIG7_TMDS_DEBUG 0x5671 5409 #define mmDIG8_TMDS_DEBUG 0x5771 5410 #define mmTMDS_CTL_BITS 0x4a72 5411 #define mmDIG0_TMDS_CTL_BITS 0x4a72 5412 #define mmDIG1_TMDS_CTL_BITS 0x4b72 5413 #define mmDIG2_TMDS_CTL_BITS 0x4c72 5414 #define mmDIG3_TMDS_CTL_BITS 0x4d72 5415 #define mmDIG4_TMDS_CTL_BITS 0x4e72 5416 #define mmDIG5_TMDS_CTL_BITS 0x4f72 5417 #define mmDIG6_TMDS_CTL_BITS 0x5472 5418 #define mmDIG7_TMDS_CTL_BITS 0x5672 5419 #define mmDIG8_TMDS_CTL_BITS 0x5772 5420 #define mmTMDS_DCBALANCER_CONTROL 0x4a73 5421 #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73 5422 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 5423 #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73 5424 #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73 5425 #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73 5426 #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73 5427 #define mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473 5428 #define mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673 5429 #define mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773 5430 #define mmTMDS_CTL0_1_GEN_CNTL 0x4a75 5431 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 5432 #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75 5433 #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75 5434 #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75 5435 #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75 5436 #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75 5437 #define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475 5438 #define mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675 5439 #define mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775 5440 #define mmTMDS_CTL2_3_GEN_CNTL 0x4a76 5441 #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76 5442 #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76 5443 #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76 5444 #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76 5445 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76 5446 #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76 5447 #define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476 5448 #define mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676 5449 #define mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776 5450 #define mmDIG_VERSION 0x4a78 5451 #define mmDIG0_DIG_VERSION 0x4a78 5452 #define mmDIG1_DIG_VERSION 0x4b78 5453 #define mmDIG2_DIG_VERSION 0x4c78 5454 #define mmDIG3_DIG_VERSION 0x4d78 5455 #define mmDIG4_DIG_VERSION 0x4e78 5456 #define mmDIG5_DIG_VERSION 0x4f78 5457 #define mmDIG6_DIG_VERSION 0x5478 5458 #define mmDIG7_DIG_VERSION 0x5678 5459 #define mmDIG8_DIG_VERSION 0x5778 5460 #define mmDIG_LANE_ENABLE 0x4a79 5461 #define mmDIG0_DIG_LANE_ENABLE 0x4a79 5462 #define mmDIG1_DIG_LANE_ENABLE 0x4b79 5463 #define mmDIG2_DIG_LANE_ENABLE 0x4c79 5464 #define mmDIG3_DIG_LANE_ENABLE 0x4d79 5465 #define mmDIG4_DIG_LANE_ENABLE 0x4e79 5466 #define mmDIG5_DIG_LANE_ENABLE 0x4f79 5467 #define mmDIG6_DIG_LANE_ENABLE 0x5479 5468 #define mmDIG7_DIG_LANE_ENABLE 0x5679 5469 #define mmDIG8_DIG_LANE_ENABLE 0x5779 5470 #define mmDIG_TEST_DEBUG_INDEX 0x4a7a 5471 #define mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a 5472 #define mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a 5473 #define mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a 5474 #define mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a 5475 #define mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a 5476 #define mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a 5477 #define mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a 5478 #define mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a 5479 #define mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a 5480 #define mmDIG_TEST_DEBUG_DATA 0x4a7b 5481 #define mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b 5482 #define mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b 5483 #define mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b 5484 #define mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b 5485 #define mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b 5486 #define mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b 5487 #define mmDIG6_DIG_TEST_DEBUG_DATA 0x547b 5488 #define mmDIG7_DIG_TEST_DEBUG_DATA 0x567b 5489 #define mmDIG8_DIG_TEST_DEBUG_DATA 0x577b 5490 #define mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c 5491 #define mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c 5492 #define mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c 5493 #define mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c 5494 #define mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c 5495 #define mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c 5496 #define mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c 5497 #define mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c 5498 #define mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c 5499 #define mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c 5500 #define mmDIG_FE_TEST_DEBUG_DATA 0x4a7d 5501 #define mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d 5502 #define mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d 5503 #define mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d 5504 #define mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d 5505 #define mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d 5506 #define mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d 5507 #define mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d 5508 #define mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d 5509 #define mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d 5510 #define mmDMCU_CTRL 0x1600 5511 #define mmDMCU_STATUS 0x1601 5512 #define mmDMCU_PC_START_ADDR 0x1602 5513 #define mmDMCU_FW_START_ADDR 0x1603 5514 #define mmDMCU_FW_END_ADDR 0x1604 5515 #define mmDMCU_FW_ISR_START_ADDR 0x1605 5516 #define mmDMCU_FW_CS_HI 0x1606 5517 #define mmDMCU_FW_CS_LO 0x1607 5518 #define mmDMCU_RAM_ACCESS_CTRL 0x1608 5519 #define mmDMCU_ERAM_WR_CTRL 0x1609 5520 #define mmDMCU_ERAM_WR_DATA 0x160a 5521 #define mmDMCU_ERAM_RD_CTRL 0x160b 5522 #define mmDMCU_ERAM_RD_DATA 0x160c 5523 #define mmDMCU_IRAM_WR_CTRL 0x160d 5524 #define mmDMCU_IRAM_WR_DATA 0x160e 5525 #define mmDMCU_IRAM_RD_CTRL 0x160f 5526 #define mmDMCU_IRAM_RD_DATA 0x1610 5527 #define mmDMCU_EVENT_TRIGGER 0x1611 5528 #define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 5529 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613 5530 #define mmDMCU_INTERRUPT_STATUS 0x1614 5531 #define mmDMCU_INTERRUPT_STATUS_1 0x1633 5532 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 5533 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 5534 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631 5535 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 5536 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632 5537 #define mmDC_DMCU_SCRATCH 0x1618 5538 #define mmDMCU_INT_CNT 0x1619 5539 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a 5540 #define mmDMCU_UC_CLK_GATING_CNTL 0x161b 5541 #define mmMASTER_COMM_DATA_REG1 0x161c 5542 #define mmMASTER_COMM_DATA_REG2 0x161d 5543 #define mmMASTER_COMM_DATA_REG3 0x161e 5544 #define mmMASTER_COMM_CMD_REG 0x161f 5545 #define mmMASTER_COMM_CNTL_REG 0x1620 5546 #define mmSLAVE_COMM_DATA_REG1 0x1621 5547 #define mmSLAVE_COMM_DATA_REG2 0x1622 5548 #define mmSLAVE_COMM_DATA_REG3 0x1623 5549 #define mmSLAVE_COMM_CMD_REG 0x1624 5550 #define mmSLAVE_COMM_CNTL_REG 0x1625 5551 #define mmDMCU_TEST_DEBUG_INDEX 0x1626 5552 #define mmDMCU_TEST_DEBUG_DATA 0x1627 5553 #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644 5554 #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645 5555 #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646 5556 #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647 5557 #define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642 5558 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674 5559 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675 5560 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676 5561 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677 5562 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643 5563 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678 5564 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679 5565 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a 5566 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b 5567 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673 5568 #define mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634 5569 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635 5570 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636 5571 #define mmDP_LINK_CNTL 0x4aa0 5572 #define mmDP0_DP_LINK_CNTL 0x4aa0 5573 #define mmDP1_DP_LINK_CNTL 0x4ba0 5574 #define mmDP2_DP_LINK_CNTL 0x4ca0 5575 #define mmDP3_DP_LINK_CNTL 0x4da0 5576 #define mmDP4_DP_LINK_CNTL 0x4ea0 5577 #define mmDP5_DP_LINK_CNTL 0x4fa0 5578 #define mmDP6_DP_LINK_CNTL 0x54a0 5579 #define mmDP7_DP_LINK_CNTL 0x56a0 5580 #define mmDP8_DP_LINK_CNTL 0x57a0 5581 #define mmDP_PIXEL_FORMAT 0x4aa1 5582 #define mmDP0_DP_PIXEL_FORMAT 0x4aa1 5583 #define mmDP1_DP_PIXEL_FORMAT 0x4ba1 5584 #define mmDP2_DP_PIXEL_FORMAT 0x4ca1 5585 #define mmDP3_DP_PIXEL_FORMAT 0x4da1 5586 #define mmDP4_DP_PIXEL_FORMAT 0x4ea1 5587 #define mmDP5_DP_PIXEL_FORMAT 0x4fa1 5588 #define mmDP6_DP_PIXEL_FORMAT 0x54a1 5589 #define mmDP7_DP_PIXEL_FORMAT 0x56a1 5590 #define mmDP8_DP_PIXEL_FORMAT 0x57a1 5591 #define mmDP_MSA_COLORIMETRY 0x4aa2 5592 #define mmDP0_DP_MSA_COLORIMETRY 0x4aa2 5593 #define mmDP1_DP_MSA_COLORIMETRY 0x4ba2 5594 #define mmDP2_DP_MSA_COLORIMETRY 0x4ca2 5595 #define mmDP3_DP_MSA_COLORIMETRY 0x4da2 5596 #define mmDP4_DP_MSA_COLORIMETRY 0x4ea2 5597 #define mmDP5_DP_MSA_COLORIMETRY 0x4fa2 5598 #define mmDP6_DP_MSA_COLORIMETRY 0x54a2 5599 #define mmDP7_DP_MSA_COLORIMETRY 0x56a2 5600 #define mmDP8_DP_MSA_COLORIMETRY 0x57a2 5601 #define mmDP_CONFIG 0x4aa3 5602 #define mmDP0_DP_CONFIG 0x4aa3 5603 #define mmDP1_DP_CONFIG 0x4ba3 5604 #define mmDP2_DP_CONFIG 0x4ca3 5605 #define mmDP3_DP_CONFIG 0x4da3 5606 #define mmDP4_DP_CONFIG 0x4ea3 5607 #define mmDP5_DP_CONFIG 0x4fa3 5608 #define mmDP6_DP_CONFIG 0x54a3 5609 #define mmDP7_DP_CONFIG 0x56a3 5610 #define mmDP8_DP_CONFIG 0x57a3 5611 #define mmDP_VID_STREAM_CNTL 0x4aa4 5612 #define mmDP0_DP_VID_STREAM_CNTL 0x4aa4 5613 #define mmDP1_DP_VID_STREAM_CNTL 0x4ba4 5614 #define mmDP2_DP_VID_STREAM_CNTL 0x4ca4 5615 #define mmDP3_DP_VID_STREAM_CNTL 0x4da4 5616 #define mmDP4_DP_VID_STREAM_CNTL 0x4ea4 5617 #define mmDP5_DP_VID_STREAM_CNTL 0x4fa4 5618 #define mmDP6_DP_VID_STREAM_CNTL 0x54a4 5619 #define mmDP7_DP_VID_STREAM_CNTL 0x56a4 5620 #define mmDP8_DP_VID_STREAM_CNTL 0x57a4 5621 #define mmDP_STEER_FIFO 0x4aa5 5622 #define mmDP0_DP_STEER_FIFO 0x4aa5 5623 #define mmDP1_DP_STEER_FIFO 0x4ba5 5624 #define mmDP2_DP_STEER_FIFO 0x4ca5 5625 #define mmDP3_DP_STEER_FIFO 0x4da5 5626 #define mmDP4_DP_STEER_FIFO 0x4ea5 5627 #define mmDP5_DP_STEER_FIFO 0x4fa5 5628 #define mmDP6_DP_STEER_FIFO 0x54a5 5629 #define mmDP7_DP_STEER_FIFO 0x56a5 5630 #define mmDP8_DP_STEER_FIFO 0x57a5 5631 #define mmDP_MSA_MISC 0x4aa6 5632 #define mmDP0_DP_MSA_MISC 0x4aa6 5633 #define mmDP1_DP_MSA_MISC 0x4ba6 5634 #define mmDP2_DP_MSA_MISC 0x4ca6 5635 #define mmDP3_DP_MSA_MISC 0x4da6 5636 #define mmDP4_DP_MSA_MISC 0x4ea6 5637 #define mmDP5_DP_MSA_MISC 0x4fa6 5638 #define mmDP6_DP_MSA_MISC 0x54a6 5639 #define mmDP7_DP_MSA_MISC 0x56a6 5640 #define mmDP8_DP_MSA_MISC 0x57a6 5641 #define mmDP_VID_TIMING 0x4aa8 5642 #define mmDP0_DP_VID_TIMING 0x4aa8 5643 #define mmDP1_DP_VID_TIMING 0x4ba8 5644 #define mmDP2_DP_VID_TIMING 0x4ca8 5645 #define mmDP3_DP_VID_TIMING 0x4da8 5646 #define mmDP4_DP_VID_TIMING 0x4ea8 5647 #define mmDP5_DP_VID_TIMING 0x4fa8 5648 #define mmDP6_DP_VID_TIMING 0x54a8 5649 #define mmDP7_DP_VID_TIMING 0x56a8 5650 #define mmDP8_DP_VID_TIMING 0x57a8 5651 #define mmDP_VID_N 0x4aa9 5652 #define mmDP0_DP_VID_N 0x4aa9 5653 #define mmDP1_DP_VID_N 0x4ba9 5654 #define mmDP2_DP_VID_N 0x4ca9 5655 #define mmDP3_DP_VID_N 0x4da9 5656 #define mmDP4_DP_VID_N 0x4ea9 5657 #define mmDP5_DP_VID_N 0x4fa9 5658 #define mmDP6_DP_VID_N 0x54a9 5659 #define mmDP7_DP_VID_N 0x56a9 5660 #define mmDP8_DP_VID_N 0x57a9 5661 #define mmDP_VID_M 0x4aaa 5662 #define mmDP0_DP_VID_M 0x4aaa 5663 #define mmDP1_DP_VID_M 0x4baa 5664 #define mmDP2_DP_VID_M 0x4caa 5665 #define mmDP3_DP_VID_M 0x4daa 5666 #define mmDP4_DP_VID_M 0x4eaa 5667 #define mmDP5_DP_VID_M 0x4faa 5668 #define mmDP6_DP_VID_M 0x54aa 5669 #define mmDP7_DP_VID_M 0x56aa 5670 #define mmDP8_DP_VID_M 0x57aa 5671 #define mmDP_LINK_FRAMING_CNTL 0x4aab 5672 #define mmDP0_DP_LINK_FRAMING_CNTL 0x4aab 5673 #define mmDP1_DP_LINK_FRAMING_CNTL 0x4bab 5674 #define mmDP2_DP_LINK_FRAMING_CNTL 0x4cab 5675 #define mmDP3_DP_LINK_FRAMING_CNTL 0x4dab 5676 #define mmDP4_DP_LINK_FRAMING_CNTL 0x4eab 5677 #define mmDP5_DP_LINK_FRAMING_CNTL 0x4fab 5678 #define mmDP6_DP_LINK_FRAMING_CNTL 0x54ab 5679 #define mmDP7_DP_LINK_FRAMING_CNTL 0x56ab 5680 #define mmDP8_DP_LINK_FRAMING_CNTL 0x57ab 5681 #define mmDP_HBR2_EYE_PATTERN 0x4aac 5682 #define mmDP0_DP_HBR2_EYE_PATTERN 0x4aac 5683 #define mmDP1_DP_HBR2_EYE_PATTERN 0x4bac 5684 #define mmDP2_DP_HBR2_EYE_PATTERN 0x4cac 5685 #define mmDP3_DP_HBR2_EYE_PATTERN 0x4dac 5686 #define mmDP4_DP_HBR2_EYE_PATTERN 0x4eac 5687 #define mmDP5_DP_HBR2_EYE_PATTERN 0x4fac 5688 #define mmDP6_DP_HBR2_EYE_PATTERN 0x54ac 5689 #define mmDP7_DP_HBR2_EYE_PATTERN 0x56ac 5690 #define mmDP8_DP_HBR2_EYE_PATTERN 0x57ac 5691 #define mmDP_VID_MSA_VBID 0x4aad 5692 #define mmDP0_DP_VID_MSA_VBID 0x4aad 5693 #define mmDP1_DP_VID_MSA_VBID 0x4bad 5694 #define mmDP2_DP_VID_MSA_VBID 0x4cad 5695 #define mmDP3_DP_VID_MSA_VBID 0x4dad 5696 #define mmDP4_DP_VID_MSA_VBID 0x4ead 5697 #define mmDP5_DP_VID_MSA_VBID 0x4fad 5698 #define mmDP6_DP_VID_MSA_VBID 0x54ad 5699 #define mmDP7_DP_VID_MSA_VBID 0x56ad 5700 #define mmDP8_DP_VID_MSA_VBID 0x57ad 5701 #define mmDP_VID_INTERRUPT_CNTL 0x4aae 5702 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae 5703 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae 5704 #define mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae 5705 #define mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae 5706 #define mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae 5707 #define mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae 5708 #define mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae 5709 #define mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae 5710 #define mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae 5711 #define mmDP_DPHY_CNTL 0x4aaf 5712 #define mmDP0_DP_DPHY_CNTL 0x4aaf 5713 #define mmDP1_DP_DPHY_CNTL 0x4baf 5714 #define mmDP2_DP_DPHY_CNTL 0x4caf 5715 #define mmDP3_DP_DPHY_CNTL 0x4daf 5716 #define mmDP4_DP_DPHY_CNTL 0x4eaf 5717 #define mmDP5_DP_DPHY_CNTL 0x4faf 5718 #define mmDP6_DP_DPHY_CNTL 0x54af 5719 #define mmDP7_DP_DPHY_CNTL 0x56af 5720 #define mmDP8_DP_DPHY_CNTL 0x57af 5721 #define mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 5722 #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0 5723 #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0 5724 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 5725 #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0 5726 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 5727 #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0 5728 #define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0 5729 #define mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0 5730 #define mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0 5731 #define mmDP_DPHY_SYM0 0x4ab1 5732 #define mmDP0_DP_DPHY_SYM0 0x4ab1 5733 #define mmDP1_DP_DPHY_SYM0 0x4bb1 5734 #define mmDP2_DP_DPHY_SYM0 0x4cb1 5735 #define mmDP3_DP_DPHY_SYM0 0x4db1 5736 #define mmDP4_DP_DPHY_SYM0 0x4eb1 5737 #define mmDP5_DP_DPHY_SYM0 0x4fb1 5738 #define mmDP6_DP_DPHY_SYM0 0x54b1 5739 #define mmDP7_DP_DPHY_SYM0 0x56b1 5740 #define mmDP8_DP_DPHY_SYM0 0x57b1 5741 #define mmDP_DPHY_SYM1 0x4ab2 5742 #define mmDP0_DP_DPHY_SYM1 0x4ab2 5743 #define mmDP1_DP_DPHY_SYM1 0x4bb2 5744 #define mmDP2_DP_DPHY_SYM1 0x4cb2 5745 #define mmDP3_DP_DPHY_SYM1 0x4db2 5746 #define mmDP4_DP_DPHY_SYM1 0x4eb2 5747 #define mmDP5_DP_DPHY_SYM1 0x4fb2 5748 #define mmDP6_DP_DPHY_SYM1 0x54b2 5749 #define mmDP7_DP_DPHY_SYM1 0x56b2 5750 #define mmDP8_DP_DPHY_SYM1 0x57b2 5751 #define mmDP_DPHY_SYM2 0x4ab3 5752 #define mmDP0_DP_DPHY_SYM2 0x4ab3 5753 #define mmDP1_DP_DPHY_SYM2 0x4bb3 5754 #define mmDP2_DP_DPHY_SYM2 0x4cb3 5755 #define mmDP3_DP_DPHY_SYM2 0x4db3 5756 #define mmDP4_DP_DPHY_SYM2 0x4eb3 5757 #define mmDP5_DP_DPHY_SYM2 0x4fb3 5758 #define mmDP6_DP_DPHY_SYM2 0x54b3 5759 #define mmDP7_DP_DPHY_SYM2 0x56b3 5760 #define mmDP8_DP_DPHY_SYM2 0x57b3 5761 #define mmDP_DPHY_8B10B_CNTL 0x4ab4 5762 #define mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4 5763 #define mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4 5764 #define mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4 5765 #define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 5766 #define mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4 5767 #define mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4 5768 #define mmDP6_DP_DPHY_8B10B_CNTL 0x54b4 5769 #define mmDP7_DP_DPHY_8B10B_CNTL 0x56b4 5770 #define mmDP8_DP_DPHY_8B10B_CNTL 0x57b4 5771 #define mmDP_DPHY_PRBS_CNTL 0x4ab5 5772 #define mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5 5773 #define mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5 5774 #define mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5 5775 #define mmDP3_DP_DPHY_PRBS_CNTL 0x4db5 5776 #define mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5 5777 #define mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5 5778 #define mmDP6_DP_DPHY_PRBS_CNTL 0x54b5 5779 #define mmDP7_DP_DPHY_PRBS_CNTL 0x56b5 5780 #define mmDP8_DP_DPHY_PRBS_CNTL 0x57b5 5781 #define mmDP_DPHY_SCRAM_CNTL 0x4ab6 5782 #define mmDP0_DP_DPHY_SCRAM_CNTL 0x4ab6 5783 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 5784 #define mmDP2_DP_DPHY_SCRAM_CNTL 0x4cb6 5785 #define mmDP3_DP_DPHY_SCRAM_CNTL 0x4db6 5786 #define mmDP4_DP_DPHY_SCRAM_CNTL 0x4eb6 5787 #define mmDP5_DP_DPHY_SCRAM_CNTL 0x4fb6 5788 #define mmDP6_DP_DPHY_SCRAM_CNTL 0x54b6 5789 #define mmDP8_DP_DPHY_SCRAM_CNTL 0x56b6 5790 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc 5791 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc 5792 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc 5793 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc 5794 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc 5795 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc 5796 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc 5797 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc 5798 #define mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc 5799 #define mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc 5800 #define mmDP_DPHY_CRC_EN 0x4ab7 5801 #define mmDP0_DP_DPHY_CRC_EN 0x4ab7 5802 #define mmDP1_DP_DPHY_CRC_EN 0x4bb7 5803 #define mmDP2_DP_DPHY_CRC_EN 0x4cb7 5804 #define mmDP3_DP_DPHY_CRC_EN 0x4db7 5805 #define mmDP4_DP_DPHY_CRC_EN 0x4eb7 5806 #define mmDP5_DP_DPHY_CRC_EN 0x4fb7 5807 #define mmDP6_DP_DPHY_CRC_EN 0x54b7 5808 #define mmDP7_DP_DPHY_CRC_EN 0x56b7 5809 #define mmDP8_DP_DPHY_CRC_EN 0x57b7 5810 #define mmDP_DPHY_CRC_CNTL 0x4ab8 5811 #define mmDP0_DP_DPHY_CRC_CNTL 0x4ab8 5812 #define mmDP1_DP_DPHY_CRC_CNTL 0x4bb8 5813 #define mmDP2_DP_DPHY_CRC_CNTL 0x4cb8 5814 #define mmDP3_DP_DPHY_CRC_CNTL 0x4db8 5815 #define mmDP4_DP_DPHY_CRC_CNTL 0x4eb8 5816 #define mmDP5_DP_DPHY_CRC_CNTL 0x4fb8 5817 #define mmDP6_DP_DPHY_CRC_CNTL 0x54b8 5818 #define mmDP7_DP_DPHY_CRC_CNTL 0x56b8 5819 #define mmDP8_DP_DPHY_CRC_CNTL 0x57b8 5820 #define mmDP_DPHY_CRC_RESULT 0x4ab9 5821 #define mmDP0_DP_DPHY_CRC_RESULT 0x4ab9 5822 #define mmDP1_DP_DPHY_CRC_RESULT 0x4bb9 5823 #define mmDP2_DP_DPHY_CRC_RESULT 0x4cb9 5824 #define mmDP3_DP_DPHY_CRC_RESULT 0x4db9 5825 #define mmDP4_DP_DPHY_CRC_RESULT 0x4eb9 5826 #define mmDP5_DP_DPHY_CRC_RESULT 0x4fb9 5827 #define mmDP6_DP_DPHY_CRC_RESULT 0x54b9 5828 #define mmDP7_DP_DPHY_CRC_RESULT 0x56b9 5829 #define mmDP8_DP_DPHY_CRC_RESULT 0x57b9 5830 #define mmDP_DPHY_CRC_MST_CNTL 0x4aba 5831 #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba 5832 #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba 5833 #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba 5834 #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba 5835 #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba 5836 #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba 5837 #define mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba 5838 #define mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba 5839 #define mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba 5840 #define mmDP_DPHY_CRC_MST_STATUS 0x4abb 5841 #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb 5842 #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb 5843 #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb 5844 #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb 5845 #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb 5846 #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb 5847 #define mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb 5848 #define mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb 5849 #define mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb 5850 #define mmDP_DPHY_FAST_TRAINING 0x4abc 5851 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4abc 5852 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc 5853 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc 5854 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc 5855 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc 5856 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc 5857 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54bc 5858 #define mmDP7_DP_DPHY_FAST_TRAINING 0x56bc 5859 #define mmDP8_DP_DPHY_FAST_TRAINING 0x57bc 5860 #define mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd 5861 #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd 5862 #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd 5863 #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd 5864 #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd 5865 #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd 5866 #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd 5867 #define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd 5868 #define mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd 5869 #define mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd 5870 #define mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add 5871 #define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add 5872 #define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd 5873 #define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd 5874 #define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd 5875 #define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd 5876 #define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd 5877 #define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd 5878 #define mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd 5879 #define mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd 5880 #define mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe 5881 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe 5882 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe 5883 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe 5884 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe 5885 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe 5886 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe 5887 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be 5888 #define mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be 5889 #define mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be 5890 #define mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf 5891 #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf 5892 #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf 5893 #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf 5894 #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf 5895 #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf 5896 #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf 5897 #define mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf 5898 #define mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf 5899 #define mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf 5900 #define mmDP_SEC_CNTL 0x4ac3 5901 #define mmDP0_DP_SEC_CNTL 0x4ac3 5902 #define mmDP1_DP_SEC_CNTL 0x4bc3 5903 #define mmDP2_DP_SEC_CNTL 0x4cc3 5904 #define mmDP3_DP_SEC_CNTL 0x4dc3 5905 #define mmDP4_DP_SEC_CNTL 0x4ec3 5906 #define mmDP5_DP_SEC_CNTL 0x4fc3 5907 #define mmDP6_DP_SEC_CNTL 0x54c3 5908 #define mmDP7_DP_SEC_CNTL 0x56c3 5909 #define mmDP8_DP_SEC_CNTL 0x57c3 5910 #define mmDP_SEC_CNTL1 0x4ac4 5911 #define mmDP0_DP_SEC_CNTL1 0x4ac4 5912 #define mmDP1_DP_SEC_CNTL1 0x4bc4 5913 #define mmDP2_DP_SEC_CNTL1 0x4cc4 5914 #define mmDP3_DP_SEC_CNTL1 0x4dc4 5915 #define mmDP4_DP_SEC_CNTL1 0x4ec4 5916 #define mmDP5_DP_SEC_CNTL1 0x4fc4 5917 #define mmDP6_DP_SEC_CNTL1 0x54c4 5918 #define mmDP7_DP_SEC_CNTL1 0x56c4 5919 #define mmDP8_DP_SEC_CNTL1 0x57c4 5920 #define mmDP_SEC_FRAMING1 0x4ac5 5921 #define mmDP0_DP_SEC_FRAMING1 0x4ac5 5922 #define mmDP1_DP_SEC_FRAMING1 0x4bc5 5923 #define mmDP2_DP_SEC_FRAMING1 0x4cc5 5924 #define mmDP3_DP_SEC_FRAMING1 0x4dc5 5925 #define mmDP4_DP_SEC_FRAMING1 0x4ec5 5926 #define mmDP5_DP_SEC_FRAMING1 0x4fc5 5927 #define mmDP6_DP_SEC_FRAMING1 0x54c5 5928 #define mmDP7_DP_SEC_FRAMING1 0x56c5 5929 #define mmDP8_DP_SEC_FRAMING1 0x57c5 5930 #define mmDP_SEC_FRAMING2 0x4ac6 5931 #define mmDP0_DP_SEC_FRAMING2 0x4ac6 5932 #define mmDP1_DP_SEC_FRAMING2 0x4bc6 5933 #define mmDP2_DP_SEC_FRAMING2 0x4cc6 5934 #define mmDP3_DP_SEC_FRAMING2 0x4dc6 5935 #define mmDP4_DP_SEC_FRAMING2 0x4ec6 5936 #define mmDP5_DP_SEC_FRAMING2 0x4fc6 5937 #define mmDP6_DP_SEC_FRAMING2 0x54c6 5938 #define mmDP7_DP_SEC_FRAMING2 0x56c6 5939 #define mmDP8_DP_SEC_FRAMING2 0x57c6 5940 #define mmDP_SEC_FRAMING3 0x4ac7 5941 #define mmDP0_DP_SEC_FRAMING3 0x4ac7 5942 #define mmDP1_DP_SEC_FRAMING3 0x4bc7 5943 #define mmDP2_DP_SEC_FRAMING3 0x4cc7 5944 #define mmDP3_DP_SEC_FRAMING3 0x4dc7 5945 #define mmDP4_DP_SEC_FRAMING3 0x4ec7 5946 #define mmDP5_DP_SEC_FRAMING3 0x4fc7 5947 #define mmDP6_DP_SEC_FRAMING3 0x54c7 5948 #define mmDP7_DP_SEC_FRAMING3 0x56c7 5949 #define mmDP8_DP_SEC_FRAMING3 0x57c7 5950 #define mmDP_SEC_FRAMING4 0x4ac8 5951 #define mmDP0_DP_SEC_FRAMING4 0x4ac8 5952 #define mmDP1_DP_SEC_FRAMING4 0x4bc8 5953 #define mmDP2_DP_SEC_FRAMING4 0x4cc8 5954 #define mmDP3_DP_SEC_FRAMING4 0x4dc8 5955 #define mmDP4_DP_SEC_FRAMING4 0x4ec8 5956 #define mmDP5_DP_SEC_FRAMING4 0x4fc8 5957 #define mmDP6_DP_SEC_FRAMING4 0x54c8 5958 #define mmDP7_DP_SEC_FRAMING4 0x56c8 5959 #define mmDP8_DP_SEC_FRAMING4 0x57c8 5960 #define mmDP_SEC_AUD_N 0x4ac9 5961 #define mmDP0_DP_SEC_AUD_N 0x4ac9 5962 #define mmDP1_DP_SEC_AUD_N 0x4bc9 5963 #define mmDP2_DP_SEC_AUD_N 0x4cc9 5964 #define mmDP3_DP_SEC_AUD_N 0x4dc9 5965 #define mmDP4_DP_SEC_AUD_N 0x4ec9 5966 #define mmDP5_DP_SEC_AUD_N 0x4fc9 5967 #define mmDP6_DP_SEC_AUD_N 0x54c9 5968 #define mmDP7_DP_SEC_AUD_N 0x56c9 5969 #define mmDP8_DP_SEC_AUD_N 0x57c9 5970 #define mmDP_SEC_AUD_N_READBACK 0x4aca 5971 #define mmDP0_DP_SEC_AUD_N_READBACK 0x4aca 5972 #define mmDP1_DP_SEC_AUD_N_READBACK 0x4bca 5973 #define mmDP2_DP_SEC_AUD_N_READBACK 0x4cca 5974 #define mmDP3_DP_SEC_AUD_N_READBACK 0x4dca 5975 #define mmDP4_DP_SEC_AUD_N_READBACK 0x4eca 5976 #define mmDP5_DP_SEC_AUD_N_READBACK 0x4fca 5977 #define mmDP6_DP_SEC_AUD_N_READBACK 0x54ca 5978 #define mmDP7_DP_SEC_AUD_N_READBACK 0x56ca 5979 #define mmDP8_DP_SEC_AUD_N_READBACK 0x57ca 5980 #define mmDP_SEC_AUD_M 0x4acb 5981 #define mmDP0_DP_SEC_AUD_M 0x4acb 5982 #define mmDP1_DP_SEC_AUD_M 0x4bcb 5983 #define mmDP2_DP_SEC_AUD_M 0x4ccb 5984 #define mmDP3_DP_SEC_AUD_M 0x4dcb 5985 #define mmDP4_DP_SEC_AUD_M 0x4ecb 5986 #define mmDP5_DP_SEC_AUD_M 0x4fcb 5987 #define mmDP6_DP_SEC_AUD_M 0x54cb 5988 #define mmDP7_DP_SEC_AUD_M 0x56cb 5989 #define mmDP8_DP_SEC_AUD_M 0x57cb 5990 #define mmDP_SEC_AUD_M_READBACK 0x4acc 5991 #define mmDP0_DP_SEC_AUD_M_READBACK 0x4acc 5992 #define mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc 5993 #define mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc 5994 #define mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc 5995 #define mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc 5996 #define mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc 5997 #define mmDP6_DP_SEC_AUD_M_READBACK 0x54cc 5998 #define mmDP7_DP_SEC_AUD_M_READBACK 0x56cc 5999 #define mmDP8_DP_SEC_AUD_M_READBACK 0x57cc 6000 #define mmDP_SEC_TIMESTAMP 0x4acd 6001 #define mmDP0_DP_SEC_TIMESTAMP 0x4acd 6002 #define mmDP1_DP_SEC_TIMESTAMP 0x4bcd 6003 #define mmDP2_DP_SEC_TIMESTAMP 0x4ccd 6004 #define mmDP3_DP_SEC_TIMESTAMP 0x4dcd 6005 #define mmDP4_DP_SEC_TIMESTAMP 0x4ecd 6006 #define mmDP5_DP_SEC_TIMESTAMP 0x4fcd 6007 #define mmDP6_DP_SEC_TIMESTAMP 0x54cd 6008 #define mmDP7_DP_SEC_TIMESTAMP 0x56cd 6009 #define mmDP8_DP_SEC_TIMESTAMP 0x57cd 6010 #define mmDP_SEC_PACKET_CNTL 0x4ace 6011 #define mmDP0_DP_SEC_PACKET_CNTL 0x4ace 6012 #define mmDP1_DP_SEC_PACKET_CNTL 0x4bce 6013 #define mmDP2_DP_SEC_PACKET_CNTL 0x4cce 6014 #define mmDP3_DP_SEC_PACKET_CNTL 0x4dce 6015 #define mmDP4_DP_SEC_PACKET_CNTL 0x4ece 6016 #define mmDP5_DP_SEC_PACKET_CNTL 0x4fce 6017 #define mmDP6_DP_SEC_PACKET_CNTL 0x54ce 6018 #define mmDP7_DP_SEC_PACKET_CNTL 0x56ce 6019 #define mmDP8_DP_SEC_PACKET_CNTL 0x57ce 6020 #define mmDP_MSE_RATE_CNTL 0x4acf 6021 #define mmDP0_DP_MSE_RATE_CNTL 0x4acf 6022 #define mmDP1_DP_MSE_RATE_CNTL 0x4bcf 6023 #define mmDP2_DP_MSE_RATE_CNTL 0x4ccf 6024 #define mmDP3_DP_MSE_RATE_CNTL 0x4dcf 6025 #define mmDP4_DP_MSE_RATE_CNTL 0x4ecf 6026 #define mmDP5_DP_MSE_RATE_CNTL 0x4fcf 6027 #define mmDP6_DP_MSE_RATE_CNTL 0x54cf 6028 #define mmDP7_DP_MSE_RATE_CNTL 0x56cf 6029 #define mmDP8_DP_MSE_RATE_CNTL 0x57cf 6030 #define mmDP_MSE_RATE_UPDATE 0x4ad1 6031 #define mmDP0_DP_MSE_RATE_UPDATE 0x4ad1 6032 #define mmDP1_DP_MSE_RATE_UPDATE 0x4bd1 6033 #define mmDP2_DP_MSE_RATE_UPDATE 0x4cd1 6034 #define mmDP3_DP_MSE_RATE_UPDATE 0x4dd1 6035 #define mmDP4_DP_MSE_RATE_UPDATE 0x4ed1 6036 #define mmDP5_DP_MSE_RATE_UPDATE 0x4fd1 6037 #define mmDP6_DP_MSE_RATE_UPDATE 0x54d1 6038 #define mmDP7_DP_MSE_RATE_UPDATE 0x56d1 6039 #define mmDP8_DP_MSE_RATE_UPDATE 0x57d1 6040 #define mmDP_MSE_SAT0 0x4ad2 6041 #define mmDP0_DP_MSE_SAT0 0x4ad2 6042 #define mmDP1_DP_MSE_SAT0 0x4bd2 6043 #define mmDP2_DP_MSE_SAT0 0x4cd2 6044 #define mmDP3_DP_MSE_SAT0 0x4dd2 6045 #define mmDP4_DP_MSE_SAT0 0x4ed2 6046 #define mmDP5_DP_MSE_SAT0 0x4fd2 6047 #define mmDP6_DP_MSE_SAT0 0x54d2 6048 #define mmDP7_DP_MSE_SAT0 0x56d2 6049 #define mmDP8_DP_MSE_SAT0 0x57d2 6050 #define mmDP_MSE_SAT1 0x4ad3 6051 #define mmDP0_DP_MSE_SAT1 0x4ad3 6052 #define mmDP1_DP_MSE_SAT1 0x4bd3 6053 #define mmDP2_DP_MSE_SAT1 0x4cd3 6054 #define mmDP3_DP_MSE_SAT1 0x4dd3 6055 #define mmDP4_DP_MSE_SAT1 0x4ed3 6056 #define mmDP5_DP_MSE_SAT1 0x4fd3 6057 #define mmDP6_DP_MSE_SAT1 0x54d3 6058 #define mmDP7_DP_MSE_SAT1 0x56d3 6059 #define mmDP8_DP_MSE_SAT1 0x57d3 6060 #define mmDP_MSE_SAT2 0x4ad4 6061 #define mmDP0_DP_MSE_SAT2 0x4ad4 6062 #define mmDP1_DP_MSE_SAT2 0x4bd4 6063 #define mmDP2_DP_MSE_SAT2 0x4cd4 6064 #define mmDP3_DP_MSE_SAT2 0x4dd4 6065 #define mmDP4_DP_MSE_SAT2 0x4ed4 6066 #define mmDP5_DP_MSE_SAT2 0x4fd4 6067 #define mmDP6_DP_MSE_SAT2 0x54d4 6068 #define mmDP7_DP_MSE_SAT2 0x56d4 6069 #define mmDP8_DP_MSE_SAT2 0x57d4 6070 #define mmDP_MSE_SAT_UPDATE 0x4ad5 6071 #define mmDP0_DP_MSE_SAT_UPDATE 0x4ad5 6072 #define mmDP1_DP_MSE_SAT_UPDATE 0x4bd5 6073 #define mmDP2_DP_MSE_SAT_UPDATE 0x4cd5 6074 #define mmDP3_DP_MSE_SAT_UPDATE 0x4dd5 6075 #define mmDP4_DP_MSE_SAT_UPDATE 0x4ed5 6076 #define mmDP5_DP_MSE_SAT_UPDATE 0x4fd5 6077 #define mmDP6_DP_MSE_SAT_UPDATE 0x54d5 6078 #define mmDP7_DP_MSE_SAT_UPDATE 0x56d5 6079 #define mmDP8_DP_MSE_SAT_UPDATE 0x57d5 6080 #define mmDP_MSE_LINK_TIMING 0x4ad6 6081 #define mmDP0_DP_MSE_LINK_TIMING 0x4ad6 6082 #define mmDP1_DP_MSE_LINK_TIMING 0x4bd6 6083 #define mmDP2_DP_MSE_LINK_TIMING 0x4cd6 6084 #define mmDP3_DP_MSE_LINK_TIMING 0x4dd6 6085 #define mmDP4_DP_MSE_LINK_TIMING 0x4ed6 6086 #define mmDP5_DP_MSE_LINK_TIMING 0x4fd6 6087 #define mmDP6_DP_MSE_LINK_TIMING 0x54d6 6088 #define mmDP7_DP_MSE_LINK_TIMING 0x56d6 6089 #define mmDP8_DP_MSE_LINK_TIMING 0x57d6 6090 #define mmDP_MSE_MISC_CNTL 0x4ad7 6091 #define mmDP0_DP_MSE_MISC_CNTL 0x4ad7 6092 #define mmDP1_DP_MSE_MISC_CNTL 0x4bd7 6093 #define mmDP2_DP_MSE_MISC_CNTL 0x4cd7 6094 #define mmDP3_DP_MSE_MISC_CNTL 0x4dd7 6095 #define mmDP4_DP_MSE_MISC_CNTL 0x4ed7 6096 #define mmDP5_DP_MSE_MISC_CNTL 0x4fd7 6097 #define mmDP6_DP_MSE_MISC_CNTL 0x54d7 6098 #define mmDP7_DP_MSE_MISC_CNTL 0x56d7 6099 #define mmDP8_DP_MSE_MISC_CNTL 0x57d7 6100 #define mmDP_MSE_SAT0_STATUS 0x4adf 6101 #define mmDP0_DP_MSE_SAT0_STATUS 0x4adf 6102 #define mmDP1_DP_MSE_SAT0_STATUS 0x4bdf 6103 #define mmDP2_DP_MSE_SAT0_STATUS 0x4cdf 6104 #define mmDP3_DP_MSE_SAT0_STATUS 0x4ddf 6105 #define mmDP4_DP_MSE_SAT0_STATUS 0x4edf 6106 #define mmDP5_DP_MSE_SAT0_STATUS 0x4fdf 6107 #define mmDP6_DP_MSE_SAT0_STATUS 0x54df 6108 #define mmDP7_DP_MSE_SAT0_STATUS 0x56df 6109 #define mmDP8_DP_MSE_SAT0_STATUS 0x57df 6110 #define mmDP_MSE_SAT1_STATUS 0x4ae0 6111 #define mmDP0_DP_MSE_SAT1_STATUS 0x4ae0 6112 #define mmDP1_DP_MSE_SAT1_STATUS 0x4be0 6113 #define mmDP2_DP_MSE_SAT1_STATUS 0x4ce0 6114 #define mmDP3_DP_MSE_SAT1_STATUS 0x4de0 6115 #define mmDP4_DP_MSE_SAT1_STATUS 0x4ee0 6116 #define mmDP5_DP_MSE_SAT1_STATUS 0x4fe0 6117 #define mmDP6_DP_MSE_SAT1_STATUS 0x54e0 6118 #define mmDP7_DP_MSE_SAT1_STATUS 0x56e0 6119 #define mmDP8_DP_MSE_SAT1_STATUS 0x57e0 6120 #define mmDP_MSE_SAT2_STATUS 0x4ae1 6121 #define mmDP0_DP_MSE_SAT2_STATUS 0x4ae1 6122 #define mmDP1_DP_MSE_SAT2_STATUS 0x4be1 6123 #define mmDP2_DP_MSE_SAT2_STATUS 0x4ce1 6124 #define mmDP3_DP_MSE_SAT2_STATUS 0x4de1 6125 #define mmDP4_DP_MSE_SAT2_STATUS 0x4ee1 6126 #define mmDP5_DP_MSE_SAT2_STATUS 0x4fe1 6127 #define mmDP6_DP_MSE_SAT2_STATUS 0x54e1 6128 #define mmDP7_DP_MSE_SAT2_STATUS 0x56e1 6129 #define mmDP8_DP_MSE_SAT2_STATUS 0x57e1 6130 #define mmDP_TEST_DEBUG_INDEX 0x4ad8 6131 #define mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8 6132 #define mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8 6133 #define mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8 6134 #define mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8 6135 #define mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8 6136 #define mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8 6137 #define mmDP6_DP_TEST_DEBUG_INDEX 0x54d8 6138 #define mmDP7_DP_TEST_DEBUG_INDEX 0x56d8 6139 #define mmDP8_DP_TEST_DEBUG_INDEX 0x57d8 6140 #define mmDP_TEST_DEBUG_DATA 0x4ad9 6141 #define mmDP0_DP_TEST_DEBUG_DATA 0x4ad9 6142 #define mmDP1_DP_TEST_DEBUG_DATA 0x4bd9 6143 #define mmDP2_DP_TEST_DEBUG_DATA 0x4cd9 6144 #define mmDP3_DP_TEST_DEBUG_DATA 0x4dd9 6145 #define mmDP4_DP_TEST_DEBUG_DATA 0x4ed9 6146 #define mmDP5_DP_TEST_DEBUG_DATA 0x4fd9 6147 #define mmDP6_DP_TEST_DEBUG_DATA 0x54d9 6148 #define mmDP7_DP_TEST_DEBUG_DATA 0x56d9 6149 #define mmDP8_DP_TEST_DEBUG_DATA 0x57d9 6150 #define mmDP_FE_TEST_DEBUG_INDEX 0x4ada 6151 #define mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada 6152 #define mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda 6153 #define mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda 6154 #define mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda 6155 #define mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda 6156 #define mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda 6157 #define mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da 6158 #define mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da 6159 #define mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da 6160 #define mmDP_FE_TEST_DEBUG_DATA 0x4adb 6161 #define mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb 6162 #define mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb 6163 #define mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb 6164 #define mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb 6165 #define mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb 6166 #define mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb 6167 #define mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db 6168 #define mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db 6169 #define mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db 6170 #define mmAUX_CONTROL 0x5c00 6171 #define mmDP_AUX0_AUX_CONTROL 0x5c00 6172 #define mmDP_AUX1_AUX_CONTROL 0x5c1c 6173 #define mmDP_AUX2_AUX_CONTROL 0x5c38 6174 #define mmDP_AUX3_AUX_CONTROL 0x5c54 6175 #define mmDP_AUX4_AUX_CONTROL 0x5c70 6176 #define mmDP_AUX5_AUX_CONTROL 0x5c8c 6177 #define mmAUX_SW_CONTROL 0x5c01 6178 #define mmDP_AUX0_AUX_SW_CONTROL 0x5c01 6179 #define mmDP_AUX1_AUX_SW_CONTROL 0x5c1d 6180 #define mmDP_AUX2_AUX_SW_CONTROL 0x5c39 6181 #define mmDP_AUX3_AUX_SW_CONTROL 0x5c55 6182 #define mmDP_AUX4_AUX_SW_CONTROL 0x5c71 6183 #define mmDP_AUX5_AUX_SW_CONTROL 0x5c8d 6184 #define mmAUX_ARB_CONTROL 0x5c02 6185 #define mmDP_AUX0_AUX_ARB_CONTROL 0x5c02 6186 #define mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e 6187 #define mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a 6188 #define mmDP_AUX3_AUX_ARB_CONTROL 0x5c56 6189 #define mmDP_AUX4_AUX_ARB_CONTROL 0x5c72 6190 #define mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e 6191 #define mmAUX_INTERRUPT_CONTROL 0x5c03 6192 #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03 6193 #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f 6194 #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b 6195 #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57 6196 #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73 6197 #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f 6198 #define mmAUX_SW_STATUS 0x5c04 6199 #define mmDP_AUX0_AUX_SW_STATUS 0x5c04 6200 #define mmDP_AUX1_AUX_SW_STATUS 0x5c20 6201 #define mmDP_AUX2_AUX_SW_STATUS 0x5c3c 6202 #define mmDP_AUX3_AUX_SW_STATUS 0x5c58 6203 #define mmDP_AUX4_AUX_SW_STATUS 0x5c74 6204 #define mmDP_AUX5_AUX_SW_STATUS 0x5c90 6205 #define mmAUX_LS_STATUS 0x5c05 6206 #define mmDP_AUX0_AUX_LS_STATUS 0x5c05 6207 #define mmDP_AUX1_AUX_LS_STATUS 0x5c21 6208 #define mmDP_AUX2_AUX_LS_STATUS 0x5c3d 6209 #define mmDP_AUX3_AUX_LS_STATUS 0x5c59 6210 #define mmDP_AUX4_AUX_LS_STATUS 0x5c75 6211 #define mmDP_AUX5_AUX_LS_STATUS 0x5c91 6212 #define mmAUX_SW_DATA 0x5c06 6213 #define mmDP_AUX0_AUX_SW_DATA 0x5c06 6214 #define mmDP_AUX1_AUX_SW_DATA 0x5c22 6215 #define mmDP_AUX2_AUX_SW_DATA 0x5c3e 6216 #define mmDP_AUX3_AUX_SW_DATA 0x5c5a 6217 #define mmDP_AUX4_AUX_SW_DATA 0x5c76 6218 #define mmDP_AUX5_AUX_SW_DATA 0x5c92 6219 #define mmAUX_LS_DATA 0x5c07 6220 #define mmDP_AUX0_AUX_LS_DATA 0x5c07 6221 #define mmDP_AUX1_AUX_LS_DATA 0x5c23 6222 #define mmDP_AUX2_AUX_LS_DATA 0x5c3f 6223 #define mmDP_AUX3_AUX_LS_DATA 0x5c5b 6224 #define mmDP_AUX4_AUX_LS_DATA 0x5c77 6225 #define mmDP_AUX5_AUX_LS_DATA 0x5c93 6226 #define mmAUX_DPHY_TX_REF_CONTROL 0x5c08 6227 #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08 6228 #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24 6229 #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40 6230 #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c 6231 #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78 6232 #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94 6233 #define mmAUX_DPHY_TX_CONTROL 0x5c09 6234 #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09 6235 #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25 6236 #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41 6237 #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d 6238 #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79 6239 #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95 6240 #define mmAUX_DPHY_RX_CONTROL0 0x5c0a 6241 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a 6242 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26 6243 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42 6244 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e 6245 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a 6246 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96 6247 #define mmAUX_DPHY_RX_CONTROL1 0x5c0b 6248 #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b 6249 #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27 6250 #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43 6251 #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f 6252 #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b 6253 #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97 6254 #define mmAUX_DPHY_TX_STATUS 0x5c0c 6255 #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c 6256 #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28 6257 #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44 6258 #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60 6259 #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c 6260 #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98 6261 #define mmAUX_DPHY_RX_STATUS 0x5c0d 6262 #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d 6263 #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29 6264 #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45 6265 #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61 6266 #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d 6267 #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99 6268 #define mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f 6269 #define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f 6270 #define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b 6271 #define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47 6272 #define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63 6273 #define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f 6274 #define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b 6275 #define mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 6276 #define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10 6277 #define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c 6278 #define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48 6279 #define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64 6280 #define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80 6281 #define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c 6282 #define mmAUX_GTC_SYNC_STATUS 0x5c11 6283 #define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11 6284 #define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d 6285 #define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49 6286 #define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65 6287 #define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81 6288 #define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d 6289 #define mmAUX_TEST_DEBUG_INDEX 0x5c14 6290 #define mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14 6291 #define mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30 6292 #define mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c 6293 #define mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68 6294 #define mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84 6295 #define mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0 6296 #define mmAUX_TEST_DEBUG_DATA 0x5c15 6297 #define mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15 6298 #define mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31 6299 #define mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d 6300 #define mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69 6301 #define mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85 6302 #define mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1 6303 #define ixDP_AUX_DEBUG_A 0x10 6304 #define ixDP_AUX_DEBUG_B 0x11 6305 #define ixDP_AUX_DEBUG_C 0x12 6306 #define ixDP_AUX_DEBUG_D 0x13 6307 #define ixDP_AUX_DEBUG_E 0x14 6308 #define ixDP_AUX_DEBUG_F 0x15 6309 #define ixDP_AUX_DEBUG_G 0x16 6310 #define ixDP_AUX_DEBUG_H 0x17 6311 #define ixDP_AUX_DEBUG_I 0x18 6312 #define ixDP_AUX_DEBUG_J 0x19 6313 #define ixDP_AUX_DEBUG_K 0x1a 6314 #define ixDP_AUX_DEBUG_L 0x1b 6315 #define ixDP_AUX_DEBUG_M 0x1c 6316 #define ixDP_AUX_DEBUG_N 0x1d 6317 #define ixDP_AUX_DEBUG_O 0x1e 6318 #define ixDP_AUX_DEBUG_P 0x1f 6319 #define ixDP_AUX_DEBUG_Q 0x20 6320 #define mmDVO_ENABLE 0x16a0 6321 #define mmDVO_SOURCE_SELECT 0x16a1 6322 #define mmDVO_OUTPUT 0x16a2 6323 #define mmDVO_CONTROL 0x16a3 6324 #define mmDVO_CRC_EN 0x16a4 6325 #define mmDVO_CRC2_SIG_MASK 0x16a5 6326 #define mmDVO_CRC2_SIG_RESULT 0x16a6 6327 #define mmDVO_FIFO_ERROR_STATUS 0x16a7 6328 #define mmDVO_TEST_DEBUG_INDEX 0x16a8 6329 #define mmDVO_TEST_DEBUG_DATA 0x16a9 6330 #define mmFBC_CNTL 0x280 6331 #define mmFBC_IDLE_FORCE_CLEAR_MASK 0x282 6332 #define mmFBC_START_STOP_DELAY 0x283 6333 #define mmFBC_COMP_CNTL 0x284 6334 #define mmFBC_COMP_MODE 0x285 6335 #define mmFBC_DEBUG0 0x286 6336 #define mmFBC_DEBUG1 0x287 6337 #define mmFBC_DEBUG2 0x288 6338 #define mmFBC_IND_LUT0 0x289 6339 #define mmFBC_IND_LUT1 0x28a 6340 #define mmFBC_IND_LUT2 0x28b 6341 #define mmFBC_IND_LUT3 0x28c 6342 #define mmFBC_IND_LUT4 0x28d 6343 #define mmFBC_IND_LUT5 0x28e 6344 #define mmFBC_IND_LUT6 0x28f 6345 #define mmFBC_IND_LUT7 0x290 6346 #define mmFBC_IND_LUT8 0x291 6347 #define mmFBC_IND_LUT9 0x292 6348 #define mmFBC_IND_LUT10 0x293 6349 #define mmFBC_IND_LUT11 0x294 6350 #define mmFBC_IND_LUT12 0x295 6351 #define mmFBC_IND_LUT13 0x296 6352 #define mmFBC_IND_LUT14 0x297 6353 #define mmFBC_IND_LUT15 0x298 6354 #define mmFBC_CSM_REGION_OFFSET_01 0x299 6355 #define mmFBC_CSM_REGION_OFFSET_23 0x29a 6356 #define mmFBC_CLIENT_REGION_MASK 0x29b 6357 #define mmFBC_DEBUG_COMP 0x29c 6358 #define mmFBC_DEBUG_CSR 0x29d 6359 #define mmFBC_DEBUG_CSR_RDATA 0x29e 6360 #define mmFBC_DEBUG_CSR_WDATA 0x29f 6361 #define mmFBC_DEBUG_CSR_RDATA_HI 0x2a0 6362 #define mmFBC_DEBUG_CSR_WDATA_HI 0x2a1 6363 #define mmFBC_MISC 0x2a2 6364 #define mmFBC_STATUS 0x2a3 6365 #define mmFBC_ALPHA_CNTL 0x2a6 6366 #define mmFBC_ALPHA_RGB_OVERRIDE 0x2a7 6367 #define mmFBC_TEST_DEBUG_INDEX 0x2a4 6368 #define mmFBC_TEST_DEBUG_DATA 0x2a5 6369 #define mmFMT_CLAMP_COMPONENT_R 0x1be8 6370 #define mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8 6371 #define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8 6372 #define mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8 6373 #define mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8 6374 #define mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8 6375 #define mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8 6376 #define mmFMT_CLAMP_COMPONENT_G 0x1be9 6377 #define mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9 6378 #define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9 6379 #define mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9 6380 #define mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9 6381 #define mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9 6382 #define mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9 6383 #define mmFMT_CLAMP_COMPONENT_B 0x1bea 6384 #define mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea 6385 #define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea 6386 #define mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea 6387 #define mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea 6388 #define mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea 6389 #define mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea 6390 #define mmFMT_DYNAMIC_EXP_CNTL 0x1bed 6391 #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed 6392 #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded 6393 #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed 6394 #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed 6395 #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed 6396 #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed 6397 #define mmFMT_CONTROL 0x1bee 6398 #define mmFMT0_FMT_CONTROL 0x1bee 6399 #define mmFMT1_FMT_CONTROL 0x1dee 6400 #define mmFMT2_FMT_CONTROL 0x1fee 6401 #define mmFMT3_FMT_CONTROL 0x41ee 6402 #define mmFMT4_FMT_CONTROL 0x43ee 6403 #define mmFMT5_FMT_CONTROL 0x45ee 6404 #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 6405 #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2 6406 #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2 6407 #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2 6408 #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2 6409 #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2 6410 #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2 6411 #define mmFMT_DITHER_RAND_R_SEED 0x1bf3 6412 #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3 6413 #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3 6414 #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3 6415 #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3 6416 #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3 6417 #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3 6418 #define mmFMT_DITHER_RAND_G_SEED 0x1bf4 6419 #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4 6420 #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4 6421 #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4 6422 #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4 6423 #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4 6424 #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4 6425 #define mmFMT_DITHER_RAND_B_SEED 0x1bf5 6426 #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5 6427 #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5 6428 #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5 6429 #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5 6430 #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5 6431 #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5 6432 #define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 6433 #define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6 6434 #define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6 6435 #define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6 6436 #define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6 6437 #define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6 6438 #define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6 6439 #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 6440 #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7 6441 #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7 6442 #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7 6443 #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7 6444 #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7 6445 #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7 6446 #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 6447 #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8 6448 #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8 6449 #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8 6450 #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8 6451 #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8 6452 #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8 6453 #define mmFMT_CLAMP_CNTL 0x1bf9 6454 #define mmFMT0_FMT_CLAMP_CNTL 0x1bf9 6455 #define mmFMT1_FMT_CLAMP_CNTL 0x1df9 6456 #define mmFMT2_FMT_CLAMP_CNTL 0x1ff9 6457 #define mmFMT3_FMT_CLAMP_CNTL 0x41f9 6458 #define mmFMT4_FMT_CLAMP_CNTL 0x43f9 6459 #define mmFMT5_FMT_CLAMP_CNTL 0x45f9 6460 #define mmFMT_CRC_CNTL 0x1bfa 6461 #define mmFMT0_FMT_CRC_CNTL 0x1bfa 6462 #define mmFMT1_FMT_CRC_CNTL 0x1dfa 6463 #define mmFMT2_FMT_CRC_CNTL 0x1ffa 6464 #define mmFMT3_FMT_CRC_CNTL 0x41fa 6465 #define mmFMT4_FMT_CRC_CNTL 0x43fa 6466 #define mmFMT5_FMT_CRC_CNTL 0x45fa 6467 #define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb 6468 #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb 6469 #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb 6470 #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb 6471 #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb 6472 #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb 6473 #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb 6474 #define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc 6475 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc 6476 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc 6477 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc 6478 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc 6479 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc 6480 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc 6481 #define mmFMT_CRC_SIG_RED_GREEN 0x1bfd 6482 #define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd 6483 #define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd 6484 #define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd 6485 #define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd 6486 #define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd 6487 #define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd 6488 #define mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe 6489 #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe 6490 #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe 6491 #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe 6492 #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe 6493 #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe 6494 #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe 6495 #define mmFMT_DEBUG_CNTL 0x1bff 6496 #define mmFMT0_FMT_DEBUG_CNTL 0x1bff 6497 #define mmFMT1_FMT_DEBUG_CNTL 0x1dff 6498 #define mmFMT2_FMT_DEBUG_CNTL 0x1fff 6499 #define mmFMT3_FMT_DEBUG_CNTL 0x41ff 6500 #define mmFMT4_FMT_DEBUG_CNTL 0x43ff 6501 #define mmFMT5_FMT_DEBUG_CNTL 0x45ff 6502 #define mmFMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1bf0 6503 #define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1bf0 6504 #define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1df0 6505 #define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1ff0 6506 #define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x41f0 6507 #define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x43f0 6508 #define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x45f0 6509 #define mmFMT_420_HBLANK_EARLY_START 0x1bf1 6510 #define mmFMT0_FMT_420_HBLANK_EARLY_START 0x1bf1 6511 #define mmFMT1_FMT_420_HBLANK_EARLY_START 0x1df1 6512 #define mmFMT2_FMT_420_HBLANK_EARLY_START 0x1ff1 6513 #define mmFMT3_FMT_420_HBLANK_EARLY_START 0x41f1 6514 #define mmFMT4_FMT_420_HBLANK_EARLY_START 0x43f1 6515 #define mmFMT5_FMT_420_HBLANK_EARLY_START 0x45f1 6516 #define mmFMT_TEST_DEBUG_INDEX 0x1beb 6517 #define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb 6518 #define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb 6519 #define mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb 6520 #define mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb 6521 #define mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb 6522 #define mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb 6523 #define mmFMT_TEST_DEBUG_DATA 0x1bec 6524 #define mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec 6525 #define mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec 6526 #define mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec 6527 #define mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec 6528 #define mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec 6529 #define mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec 6530 #define ixFMT_DEBUG0 0x1 6531 #define ixFMT_DEBUG1 0x2 6532 #define ixFMT_DEBUG2 0x3 6533 #define ixFMT_DEBUG3 0x4 6534 #define ixFMT_DEBUG_ID 0x0 6535 #define mmLB_DATA_FORMAT 0x1ac0 6536 #define mmLB0_LB_DATA_FORMAT 0x1ac0 6537 #define mmLB1_LB_DATA_FORMAT 0x1cc0 6538 #define mmLB2_LB_DATA_FORMAT 0x1ec0 6539 #define mmLB3_LB_DATA_FORMAT 0x40c0 6540 #define mmLB4_LB_DATA_FORMAT 0x42c0 6541 #define mmLB5_LB_DATA_FORMAT 0x44c0 6542 #define mmLB_MEMORY_CTRL 0x1ac1 6543 #define mmLB0_LB_MEMORY_CTRL 0x1ac1 6544 #define mmLB1_LB_MEMORY_CTRL 0x1cc1 6545 #define mmLB2_LB_MEMORY_CTRL 0x1ec1 6546 #define mmLB3_LB_MEMORY_CTRL 0x40c1 6547 #define mmLB4_LB_MEMORY_CTRL 0x42c1 6548 #define mmLB5_LB_MEMORY_CTRL 0x44c1 6549 #define mmLB_MEMORY_SIZE_STATUS 0x1ac2 6550 #define mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2 6551 #define mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2 6552 #define mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2 6553 #define mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2 6554 #define mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2 6555 #define mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2 6556 #define mmLB_DESKTOP_HEIGHT 0x1ac3 6557 #define mmLB0_LB_DESKTOP_HEIGHT 0x1ac3 6558 #define mmLB1_LB_DESKTOP_HEIGHT 0x1cc3 6559 #define mmLB2_LB_DESKTOP_HEIGHT 0x1ec3 6560 #define mmLB3_LB_DESKTOP_HEIGHT 0x40c3 6561 #define mmLB4_LB_DESKTOP_HEIGHT 0x42c3 6562 #define mmLB5_LB_DESKTOP_HEIGHT 0x44c3 6563 #define mmLB_VLINE_START_END 0x1ac4 6564 #define mmLB0_LB_VLINE_START_END 0x1ac4 6565 #define mmLB1_LB_VLINE_START_END 0x1cc4 6566 #define mmLB2_LB_VLINE_START_END 0x1ec4 6567 #define mmLB3_LB_VLINE_START_END 0x40c4 6568 #define mmLB4_LB_VLINE_START_END 0x42c4 6569 #define mmLB5_LB_VLINE_START_END 0x44c4 6570 #define mmLB_VLINE2_START_END 0x1ac5 6571 #define mmLB0_LB_VLINE2_START_END 0x1ac5 6572 #define mmLB1_LB_VLINE2_START_END 0x1cc5 6573 #define mmLB2_LB_VLINE2_START_END 0x1ec5 6574 #define mmLB3_LB_VLINE2_START_END 0x40c5 6575 #define mmLB4_LB_VLINE2_START_END 0x42c5 6576 #define mmLB5_LB_VLINE2_START_END 0x44c5 6577 #define mmLB_V_COUNTER 0x1ac6 6578 #define mmLB0_LB_V_COUNTER 0x1ac6 6579 #define mmLB1_LB_V_COUNTER 0x1cc6 6580 #define mmLB2_LB_V_COUNTER 0x1ec6 6581 #define mmLB3_LB_V_COUNTER 0x40c6 6582 #define mmLB4_LB_V_COUNTER 0x42c6 6583 #define mmLB5_LB_V_COUNTER 0x44c6 6584 #define mmLB_SNAPSHOT_V_COUNTER 0x1ac7 6585 #define mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7 6586 #define mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7 6587 #define mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7 6588 #define mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7 6589 #define mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7 6590 #define mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7 6591 #define mmLB_INTERRUPT_MASK 0x1ac8 6592 #define mmLB0_LB_INTERRUPT_MASK 0x1ac8 6593 #define mmLB1_LB_INTERRUPT_MASK 0x1cc8 6594 #define mmLB2_LB_INTERRUPT_MASK 0x1ec8 6595 #define mmLB3_LB_INTERRUPT_MASK 0x40c8 6596 #define mmLB4_LB_INTERRUPT_MASK 0x42c8 6597 #define mmLB5_LB_INTERRUPT_MASK 0x44c8 6598 #define mmLB_VLINE_STATUS 0x1ac9 6599 #define mmLB0_LB_VLINE_STATUS 0x1ac9 6600 #define mmLB1_LB_VLINE_STATUS 0x1cc9 6601 #define mmLB2_LB_VLINE_STATUS 0x1ec9 6602 #define mmLB3_LB_VLINE_STATUS 0x40c9 6603 #define mmLB4_LB_VLINE_STATUS 0x42c9 6604 #define mmLB5_LB_VLINE_STATUS 0x44c9 6605 #define mmLB_VLINE2_STATUS 0x1aca 6606 #define mmLB0_LB_VLINE2_STATUS 0x1aca 6607 #define mmLB1_LB_VLINE2_STATUS 0x1cca 6608 #define mmLB2_LB_VLINE2_STATUS 0x1eca 6609 #define mmLB3_LB_VLINE2_STATUS 0x40ca 6610 #define mmLB4_LB_VLINE2_STATUS 0x42ca 6611 #define mmLB5_LB_VLINE2_STATUS 0x44ca 6612 #define mmLB_VBLANK_STATUS 0x1acb 6613 #define mmLB0_LB_VBLANK_STATUS 0x1acb 6614 #define mmLB1_LB_VBLANK_STATUS 0x1ccb 6615 #define mmLB2_LB_VBLANK_STATUS 0x1ecb 6616 #define mmLB3_LB_VBLANK_STATUS 0x40cb 6617 #define mmLB4_LB_VBLANK_STATUS 0x42cb 6618 #define mmLB5_LB_VBLANK_STATUS 0x44cb 6619 #define mmLB_SYNC_RESET_SEL 0x1acc 6620 #define mmLB0_LB_SYNC_RESET_SEL 0x1acc 6621 #define mmLB1_LB_SYNC_RESET_SEL 0x1ccc 6622 #define mmLB2_LB_SYNC_RESET_SEL 0x1ecc 6623 #define mmLB3_LB_SYNC_RESET_SEL 0x40cc 6624 #define mmLB4_LB_SYNC_RESET_SEL 0x42cc 6625 #define mmLB5_LB_SYNC_RESET_SEL 0x44cc 6626 #define mmLB_BLACK_KEYER_R_CR 0x1acd 6627 #define mmLB0_LB_BLACK_KEYER_R_CR 0x1acd 6628 #define mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd 6629 #define mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd 6630 #define mmLB3_LB_BLACK_KEYER_R_CR 0x40cd 6631 #define mmLB4_LB_BLACK_KEYER_R_CR 0x42cd 6632 #define mmLB5_LB_BLACK_KEYER_R_CR 0x44cd 6633 #define mmLB_BLACK_KEYER_G_Y 0x1ace 6634 #define mmLB0_LB_BLACK_KEYER_G_Y 0x1ace 6635 #define mmLB1_LB_BLACK_KEYER_G_Y 0x1cce 6636 #define mmLB2_LB_BLACK_KEYER_G_Y 0x1ece 6637 #define mmLB3_LB_BLACK_KEYER_G_Y 0x40ce 6638 #define mmLB4_LB_BLACK_KEYER_G_Y 0x42ce 6639 #define mmLB5_LB_BLACK_KEYER_G_Y 0x44ce 6640 #define mmLB_BLACK_KEYER_B_CB 0x1acf 6641 #define mmLB0_LB_BLACK_KEYER_B_CB 0x1acf 6642 #define mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf 6643 #define mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf 6644 #define mmLB3_LB_BLACK_KEYER_B_CB 0x40cf 6645 #define mmLB4_LB_BLACK_KEYER_B_CB 0x42cf 6646 #define mmLB5_LB_BLACK_KEYER_B_CB 0x44cf 6647 #define mmLB_KEYER_COLOR_CTRL 0x1ad0 6648 #define mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0 6649 #define mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0 6650 #define mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0 6651 #define mmLB3_LB_KEYER_COLOR_CTRL 0x40d0 6652 #define mmLB4_LB_KEYER_COLOR_CTRL 0x42d0 6653 #define mmLB5_LB_KEYER_COLOR_CTRL 0x44d0 6654 #define mmLB_KEYER_COLOR_R_CR 0x1ad1 6655 #define mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1 6656 #define mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1 6657 #define mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1 6658 #define mmLB3_LB_KEYER_COLOR_R_CR 0x40d1 6659 #define mmLB4_LB_KEYER_COLOR_R_CR 0x42d1 6660 #define mmLB5_LB_KEYER_COLOR_R_CR 0x44d1 6661 #define mmLB_KEYER_COLOR_G_Y 0x1ad2 6662 #define mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2 6663 #define mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2 6664 #define mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2 6665 #define mmLB3_LB_KEYER_COLOR_G_Y 0x40d2 6666 #define mmLB4_LB_KEYER_COLOR_G_Y 0x42d2 6667 #define mmLB5_LB_KEYER_COLOR_G_Y 0x44d2 6668 #define mmLB_KEYER_COLOR_B_CB 0x1ad3 6669 #define mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3 6670 #define mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3 6671 #define mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3 6672 #define mmLB3_LB_KEYER_COLOR_B_CB 0x40d3 6673 #define mmLB4_LB_KEYER_COLOR_B_CB 0x42d3 6674 #define mmLB5_LB_KEYER_COLOR_B_CB 0x44d3 6675 #define mmLB_KEYER_COLOR_REP_R_CR 0x1ad4 6676 #define mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4 6677 #define mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4 6678 #define mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4 6679 #define mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4 6680 #define mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4 6681 #define mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4 6682 #define mmLB_KEYER_COLOR_REP_G_Y 0x1ad5 6683 #define mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5 6684 #define mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5 6685 #define mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5 6686 #define mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5 6687 #define mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5 6688 #define mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5 6689 #define mmLB_KEYER_COLOR_REP_B_CB 0x1ad6 6690 #define mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6 6691 #define mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6 6692 #define mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6 6693 #define mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6 6694 #define mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6 6695 #define mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6 6696 #define mmLB_BUFFER_LEVEL_STATUS 0x1ad7 6697 #define mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7 6698 #define mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7 6699 #define mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7 6700 #define mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7 6701 #define mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7 6702 #define mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7 6703 #define mmLB_BUFFER_URGENCY_CTRL 0x1ad8 6704 #define mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8 6705 #define mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8 6706 #define mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8 6707 #define mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8 6708 #define mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8 6709 #define mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8 6710 #define mmLB_BUFFER_URGENCY_STATUS 0x1ad9 6711 #define mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9 6712 #define mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9 6713 #define mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9 6714 #define mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9 6715 #define mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9 6716 #define mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9 6717 #define mmLB_BUFFER_STATUS 0x1ada 6718 #define mmLB0_LB_BUFFER_STATUS 0x1ada 6719 #define mmLB1_LB_BUFFER_STATUS 0x1cda 6720 #define mmLB2_LB_BUFFER_STATUS 0x1eda 6721 #define mmLB3_LB_BUFFER_STATUS 0x40da 6722 #define mmLB4_LB_BUFFER_STATUS 0x42da 6723 #define mmLB5_LB_BUFFER_STATUS 0x44da 6724 #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc 6725 #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc 6726 #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc 6727 #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc 6728 #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc 6729 #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc 6730 #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc 6731 #define mmMVP_AFR_FLIP_MODE 0x1ae0 6732 #define mmLB0_MVP_AFR_FLIP_MODE 0x1ae0 6733 #define mmLB1_MVP_AFR_FLIP_MODE 0x1ce0 6734 #define mmLB2_MVP_AFR_FLIP_MODE 0x1ee0 6735 #define mmLB3_MVP_AFR_FLIP_MODE 0x40e0 6736 #define mmLB4_MVP_AFR_FLIP_MODE 0x42e0 6737 #define mmLB5_MVP_AFR_FLIP_MODE 0x44e0 6738 #define mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1 6739 #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1 6740 #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1 6741 #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1 6742 #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1 6743 #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1 6744 #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1 6745 #define mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2 6746 #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2 6747 #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2 6748 #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2 6749 #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2 6750 #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2 6751 #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2 6752 #define mmDC_MVP_LB_CONTROL 0x1ae3 6753 #define mmLB0_DC_MVP_LB_CONTROL 0x1ae3 6754 #define mmLB1_DC_MVP_LB_CONTROL 0x1ce3 6755 #define mmLB2_DC_MVP_LB_CONTROL 0x1ee3 6756 #define mmLB3_DC_MVP_LB_CONTROL 0x40e3 6757 #define mmLB4_DC_MVP_LB_CONTROL 0x42e3 6758 #define mmLB5_DC_MVP_LB_CONTROL 0x44e3 6759 #define mmLB_DEBUG 0x1ae4 6760 #define mmLB0_LB_DEBUG 0x1ae4 6761 #define mmLB1_LB_DEBUG 0x1ce4 6762 #define mmLB2_LB_DEBUG 0x1ee4 6763 #define mmLB3_LB_DEBUG 0x40e4 6764 #define mmLB4_LB_DEBUG 0x42e4 6765 #define mmLB5_LB_DEBUG 0x44e4 6766 #define mmLB_DEBUG2 0x1ae5 6767 #define mmLB0_LB_DEBUG2 0x1ae5 6768 #define mmLB1_LB_DEBUG2 0x1ce5 6769 #define mmLB2_LB_DEBUG2 0x1ee5 6770 #define mmLB3_LB_DEBUG2 0x40e5 6771 #define mmLB4_LB_DEBUG2 0x42e5 6772 #define mmLB5_LB_DEBUG2 0x44e5 6773 #define mmLB_DEBUG3 0x1ae6 6774 #define mmLB0_LB_DEBUG3 0x1ae6 6775 #define mmLB1_LB_DEBUG3 0x1ce6 6776 #define mmLB2_LB_DEBUG3 0x1ee6 6777 #define mmLB3_LB_DEBUG3 0x40e6 6778 #define mmLB4_LB_DEBUG3 0x42e6 6779 #define mmLB5_LB_DEBUG3 0x44e6 6780 #define mmLB_TEST_DEBUG_INDEX 0x1afe 6781 #define mmLB0_LB_TEST_DEBUG_INDEX 0x1afe 6782 #define mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe 6783 #define mmLB2_LB_TEST_DEBUG_INDEX 0x1efe 6784 #define mmLB3_LB_TEST_DEBUG_INDEX 0x40fe 6785 #define mmLB4_LB_TEST_DEBUG_INDEX 0x42fe 6786 #define mmLB5_LB_TEST_DEBUG_INDEX 0x44fe 6787 #define mmLB_TEST_DEBUG_DATA 0x1aff 6788 #define mmLB0_LB_TEST_DEBUG_DATA 0x1aff 6789 #define mmLB1_LB_TEST_DEBUG_DATA 0x1cff 6790 #define mmLB2_LB_TEST_DEBUG_DATA 0x1eff 6791 #define mmLB3_LB_TEST_DEBUG_DATA 0x40ff 6792 #define mmLB4_LB_TEST_DEBUG_DATA 0x42ff 6793 #define mmLB5_LB_TEST_DEBUG_DATA 0x44ff 6794 #define mmLBV_DATA_FORMAT 0x463c 6795 #define mmLBV0_LBV_DATA_FORMAT 0x463c 6796 #define mmLBV1_LBV_DATA_FORMAT 0x983c 6797 #define mmLBV_MEMORY_CTRL 0x463d 6798 #define mmLBV0_LBV_MEMORY_CTRL 0x463d 6799 #define mmLBV1_LBV_MEMORY_CTRL 0x983d 6800 #define mmLBV_MEMORY_SIZE_STATUS 0x463e 6801 #define mmLBV0_LBV_MEMORY_SIZE_STATUS 0x463e 6802 #define mmLBV1_LBV_MEMORY_SIZE_STATUS 0x983e 6803 #define mmLBV_DESKTOP_HEIGHT 0x463f 6804 #define mmLBV0_LBV_DESKTOP_HEIGHT 0x463f 6805 #define mmLBV1_LBV_DESKTOP_HEIGHT 0x983f 6806 #define mmLBV_VLINE_START_END 0x4640 6807 #define mmLBV0_LBV_VLINE_START_END 0x4640 6808 #define mmLBV1_LBV_VLINE_START_END 0x9840 6809 #define mmLBV_VLINE2_START_END 0x4641 6810 #define mmLBV0_LBV_VLINE2_START_END 0x4641 6811 #define mmLBV1_LBV_VLINE2_START_END 0x9841 6812 #define mmLBV_V_COUNTER 0x4642 6813 #define mmLBV0_LBV_V_COUNTER 0x4642 6814 #define mmLBV1_LBV_V_COUNTER 0x9842 6815 #define mmLBV_SNAPSHOT_V_COUNTER 0x4643 6816 #define mmLBV0_LBV_SNAPSHOT_V_COUNTER 0x4643 6817 #define mmLBV1_LBV_SNAPSHOT_V_COUNTER 0x9843 6818 #define mmLBV_V_COUNTER_CHROMA 0x4644 6819 #define mmLBV0_LBV_V_COUNTER_CHROMA 0x4644 6820 #define mmLBV1_LBV_V_COUNTER_CHROMA 0x9844 6821 #define mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 6822 #define mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645 6823 #define mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA 0x9845 6824 #define mmLBV_INTERRUPT_MASK 0x4646 6825 #define mmLBV0_LBV_INTERRUPT_MASK 0x4646 6826 #define mmLBV1_LBV_INTERRUPT_MASK 0x9846 6827 #define mmLBV_VLINE_STATUS 0x4647 6828 #define mmLBV0_LBV_VLINE_STATUS 0x4647 6829 #define mmLBV1_LBV_VLINE_STATUS 0x9847 6830 #define mmLBV_VLINE2_STATUS 0x4648 6831 #define mmLBV0_LBV_VLINE2_STATUS 0x4648 6832 #define mmLBV1_LBV_VLINE2_STATUS 0x9848 6833 #define mmLBV_VBLANK_STATUS 0x4649 6834 #define mmLBV0_LBV_VBLANK_STATUS 0x4649 6835 #define mmLBV1_LBV_VBLANK_STATUS 0x9849 6836 #define mmLBV_SYNC_RESET_SEL 0x464a 6837 #define mmLBV0_LBV_SYNC_RESET_SEL 0x464a 6838 #define mmLBV1_LBV_SYNC_RESET_SEL 0x984a 6839 #define mmLBV_BLACK_KEYER_R_CR 0x464b 6840 #define mmLBV0_LBV_BLACK_KEYER_R_CR 0x464b 6841 #define mmLBV1_LBV_BLACK_KEYER_R_CR 0x984b 6842 #define mmLBV_BLACK_KEYER_G_Y 0x464c 6843 #define mmLBV0_LBV_BLACK_KEYER_G_Y 0x464c 6844 #define mmLBV1_LBV_BLACK_KEYER_G_Y 0x984c 6845 #define mmLBV_BLACK_KEYER_B_CB 0x464d 6846 #define mmLBV0_LBV_BLACK_KEYER_B_CB 0x464d 6847 #define mmLBV1_LBV_BLACK_KEYER_B_CB 0x984d 6848 #define mmLBV_KEYER_COLOR_CTRL 0x464e 6849 #define mmLBV0_LBV_KEYER_COLOR_CTRL 0x464e 6850 #define mmLBV1_LBV_KEYER_COLOR_CTRL 0x984e 6851 #define mmLBV_KEYER_COLOR_R_CR 0x464f 6852 #define mmLBV0_LBV_KEYER_COLOR_R_CR 0x464f 6853 #define mmLBV1_LBV_KEYER_COLOR_R_CR 0x984f 6854 #define mmLBV_KEYER_COLOR_G_Y 0x4650 6855 #define mmLBV0_LBV_KEYER_COLOR_G_Y 0x4650 6856 #define mmLBV1_LBV_KEYER_COLOR_G_Y 0x9850 6857 #define mmLBV_KEYER_COLOR_B_CB 0x4651 6858 #define mmLBV0_LBV_KEYER_COLOR_B_CB 0x4651 6859 #define mmLBV1_LBV_KEYER_COLOR_B_CB 0x9851 6860 #define mmLBV_KEYER_COLOR_REP_R_CR 0x4652 6861 #define mmLBV0_LBV_KEYER_COLOR_REP_R_CR 0x4652 6862 #define mmLBV1_LBV_KEYER_COLOR_REP_R_CR 0x9852 6863 #define mmLBV_KEYER_COLOR_REP_G_Y 0x4653 6864 #define mmLBV0_LBV_KEYER_COLOR_REP_G_Y 0x4653 6865 #define mmLBV1_LBV_KEYER_COLOR_REP_G_Y 0x9853 6866 #define mmLBV_KEYER_COLOR_REP_B_CB 0x4654 6867 #define mmLBV0_LBV_KEYER_COLOR_REP_B_CB 0x4654 6868 #define mmLBV1_LBV_KEYER_COLOR_REP_B_CB 0x9854 6869 #define mmLBV_BUFFER_LEVEL_STATUS 0x4655 6870 #define mmLBV0_LBV_BUFFER_LEVEL_STATUS 0x4655 6871 #define mmLBV1_LBV_BUFFER_LEVEL_STATUS 0x9855 6872 #define mmLBV_BUFFER_URGENCY_CTRL 0x4656 6873 #define mmLBV0_LBV_BUFFER_URGENCY_CTRL 0x4656 6874 #define mmLBV1_LBV_BUFFER_URGENCY_CTRL 0x9856 6875 #define mmLBV_BUFFER_URGENCY_STATUS 0x4657 6876 #define mmLBV0_LBV_BUFFER_URGENCY_STATUS 0x4657 6877 #define mmLBV1_LBV_BUFFER_URGENCY_STATUS 0x9857 6878 #define mmLBV_BUFFER_STATUS 0x4658 6879 #define mmLBV0_LBV_BUFFER_STATUS 0x4658 6880 #define mmLBV1_LBV_BUFFER_STATUS 0x9858 6881 #define mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659 6882 #define mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS 0x4659 6883 #define mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS 0x9859 6884 #define mmLBV_DEBUG 0x465a 6885 #define mmLBV0_LBV_DEBUG 0x465a 6886 #define mmLBV1_LBV_DEBUG 0x985a 6887 #define mmLBV_DEBUG2 0x465b 6888 #define mmLBV0_LBV_DEBUG2 0x465b 6889 #define mmLBV1_LBV_DEBUG2 0x985b 6890 #define mmLBV_DEBUG3 0x465c 6891 #define mmLBV0_LBV_DEBUG3 0x465c 6892 #define mmLBV1_LBV_DEBUG3 0x985c 6893 #define mmLBV_TEST_DEBUG_INDEX 0x4666 6894 #define mmLBV0_LBV_TEST_DEBUG_INDEX 0x4666 6895 #define mmLBV1_LBV_TEST_DEBUG_INDEX 0x9866 6896 #define mmLBV_TEST_DEBUG_DATA 0x4667 6897 #define mmLBV0_LBV_TEST_DEBUG_DATA 0x4667 6898 #define mmLBV1_LBV_TEST_DEBUG_DATA 0x9867 6899 #define mmMVP_CONTROL1 0x2ac 6900 #define mmMVP_CONTROL2 0x2ad 6901 #define mmMVP_FIFO_CONTROL 0x2ae 6902 #define mmMVP_FIFO_STATUS 0x2af 6903 #define mmMVP_SLAVE_STATUS 0x2b0 6904 #define mmMVP_INBAND_CNTL_CAP 0x2b1 6905 #define mmMVP_BLACK_KEYER 0x2b2 6906 #define mmMVP_CRC_CNTL 0x2b3 6907 #define mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4 6908 #define mmMVP_CRC_RESULT_RED 0x2b5 6909 #define mmMVP_CONTROL3 0x2b6 6910 #define mmMVP_RECEIVE_CNT_CNTL1 0x2b7 6911 #define mmMVP_RECEIVE_CNT_CNTL2 0x2b8 6912 #define mmMVP_DEBUG 0x2bb 6913 #define mmMVP_TEST_DEBUG_INDEX 0x2b9 6914 #define mmMVP_TEST_DEBUG_DATA 0x2ba 6915 #define ixMVP_DEBUG_12 0xc 6916 #define ixMVP_DEBUG_13 0xd 6917 #define ixMVP_DEBUG_14 0xe 6918 #define ixMVP_DEBUG_15 0xf 6919 #define ixMVP_DEBUG_16 0x10 6920 #define ixMVP_DEBUG_17 0x11 6921 #define mmSCL_COEF_RAM_SELECT 0x1b40 6922 #define mmSCL0_SCL_COEF_RAM_SELECT 0x1b40 6923 #define mmSCL1_SCL_COEF_RAM_SELECT 0x1d40 6924 #define mmSCL2_SCL_COEF_RAM_SELECT 0x1f40 6925 #define mmSCL3_SCL_COEF_RAM_SELECT 0x4140 6926 #define mmSCL4_SCL_COEF_RAM_SELECT 0x4340 6927 #define mmSCL5_SCL_COEF_RAM_SELECT 0x4540 6928 #define mmSCL_COEF_RAM_TAP_DATA 0x1b41 6929 #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41 6930 #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41 6931 #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41 6932 #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141 6933 #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341 6934 #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541 6935 #define mmSCL_MODE 0x1b42 6936 #define mmSCL0_SCL_MODE 0x1b42 6937 #define mmSCL1_SCL_MODE 0x1d42 6938 #define mmSCL2_SCL_MODE 0x1f42 6939 #define mmSCL3_SCL_MODE 0x4142 6940 #define mmSCL4_SCL_MODE 0x4342 6941 #define mmSCL5_SCL_MODE 0x4542 6942 #define mmSCL_TAP_CONTROL 0x1b43 6943 #define mmSCL0_SCL_TAP_CONTROL 0x1b43 6944 #define mmSCL1_SCL_TAP_CONTROL 0x1d43 6945 #define mmSCL2_SCL_TAP_CONTROL 0x1f43 6946 #define mmSCL3_SCL_TAP_CONTROL 0x4143 6947 #define mmSCL4_SCL_TAP_CONTROL 0x4343 6948 #define mmSCL5_SCL_TAP_CONTROL 0x4543 6949 #define mmSCL_CONTROL 0x1b44 6950 #define mmSCL0_SCL_CONTROL 0x1b44 6951 #define mmSCL1_SCL_CONTROL 0x1d44 6952 #define mmSCL2_SCL_CONTROL 0x1f44 6953 #define mmSCL3_SCL_CONTROL 0x4144 6954 #define mmSCL4_SCL_CONTROL 0x4344 6955 #define mmSCL5_SCL_CONTROL 0x4544 6956 #define mmSCL_BYPASS_CONTROL 0x1b45 6957 #define mmSCL0_SCL_BYPASS_CONTROL 0x1b45 6958 #define mmSCL1_SCL_BYPASS_CONTROL 0x1d45 6959 #define mmSCL2_SCL_BYPASS_CONTROL 0x1f45 6960 #define mmSCL3_SCL_BYPASS_CONTROL 0x4145 6961 #define mmSCL4_SCL_BYPASS_CONTROL 0x4345 6962 #define mmSCL5_SCL_BYPASS_CONTROL 0x4545 6963 #define mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46 6964 #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46 6965 #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46 6966 #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46 6967 #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146 6968 #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346 6969 #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546 6970 #define mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47 6971 #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47 6972 #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47 6973 #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47 6974 #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147 6975 #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347 6976 #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547 6977 #define mmSCL_HORZ_FILTER_CONTROL 0x1b48 6978 #define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48 6979 #define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48 6980 #define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48 6981 #define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148 6982 #define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348 6983 #define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548 6984 #define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49 6985 #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49 6986 #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49 6987 #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49 6988 #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149 6989 #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349 6990 #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549 6991 #define mmSCL_HORZ_FILTER_INIT 0x1b4a 6992 #define mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a 6993 #define mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a 6994 #define mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a 6995 #define mmSCL3_SCL_HORZ_FILTER_INIT 0x414a 6996 #define mmSCL4_SCL_HORZ_FILTER_INIT 0x434a 6997 #define mmSCL5_SCL_HORZ_FILTER_INIT 0x454a 6998 #define mmSCL_VERT_FILTER_CONTROL 0x1b4b 6999 #define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b 7000 #define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b 7001 #define mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b 7002 #define mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b 7003 #define mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b 7004 #define mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b 7005 #define mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c 7006 #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c 7007 #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c 7008 #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c 7009 #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c 7010 #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c 7011 #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c 7012 #define mmSCL_VERT_FILTER_INIT 0x1b4d 7013 #define mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d 7014 #define mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d 7015 #define mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d 7016 #define mmSCL3_SCL_VERT_FILTER_INIT 0x414d 7017 #define mmSCL4_SCL_VERT_FILTER_INIT 0x434d 7018 #define mmSCL5_SCL_VERT_FILTER_INIT 0x454d 7019 #define mmSCL_VERT_FILTER_INIT_BOT 0x1b4e 7020 #define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e 7021 #define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e 7022 #define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e 7023 #define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e 7024 #define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e 7025 #define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e 7026 #define mmSCL_ROUND_OFFSET 0x1b4f 7027 #define mmSCL0_SCL_ROUND_OFFSET 0x1b4f 7028 #define mmSCL1_SCL_ROUND_OFFSET 0x1d4f 7029 #define mmSCL2_SCL_ROUND_OFFSET 0x1f4f 7030 #define mmSCL3_SCL_ROUND_OFFSET 0x414f 7031 #define mmSCL4_SCL_ROUND_OFFSET 0x434f 7032 #define mmSCL5_SCL_ROUND_OFFSET 0x454f 7033 #define mmSCL_UPDATE 0x1b51 7034 #define mmSCL0_SCL_UPDATE 0x1b51 7035 #define mmSCL1_SCL_UPDATE 0x1d51 7036 #define mmSCL2_SCL_UPDATE 0x1f51 7037 #define mmSCL3_SCL_UPDATE 0x4151 7038 #define mmSCL4_SCL_UPDATE 0x4351 7039 #define mmSCL5_SCL_UPDATE 0x4551 7040 #define mmSCL_F_SHARP_CONTROL 0x1b53 7041 #define mmSCL0_SCL_F_SHARP_CONTROL 0x1b53 7042 #define mmSCL1_SCL_F_SHARP_CONTROL 0x1d53 7043 #define mmSCL2_SCL_F_SHARP_CONTROL 0x1f53 7044 #define mmSCL3_SCL_F_SHARP_CONTROL 0x4153 7045 #define mmSCL4_SCL_F_SHARP_CONTROL 0x4353 7046 #define mmSCL5_SCL_F_SHARP_CONTROL 0x4553 7047 #define mmSCL_ALU_CONTROL 0x1b54 7048 #define mmSCL0_SCL_ALU_CONTROL 0x1b54 7049 #define mmSCL1_SCL_ALU_CONTROL 0x1d54 7050 #define mmSCL2_SCL_ALU_CONTROL 0x1f54 7051 #define mmSCL3_SCL_ALU_CONTROL 0x4154 7052 #define mmSCL4_SCL_ALU_CONTROL 0x4354 7053 #define mmSCL5_SCL_ALU_CONTROL 0x4554 7054 #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55 7055 #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55 7056 #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55 7057 #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55 7058 #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 7059 #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355 7060 #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555 7061 #define mmVIEWPORT_START_SECONDARY 0x1b5b 7062 #define mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b 7063 #define mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b 7064 #define mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b 7065 #define mmSCL3_VIEWPORT_START_SECONDARY 0x415b 7066 #define mmSCL4_VIEWPORT_START_SECONDARY 0x435b 7067 #define mmSCL5_VIEWPORT_START_SECONDARY 0x455b 7068 #define mmVIEWPORT_START 0x1b5c 7069 #define mmSCL0_VIEWPORT_START 0x1b5c 7070 #define mmSCL1_VIEWPORT_START 0x1d5c 7071 #define mmSCL2_VIEWPORT_START 0x1f5c 7072 #define mmSCL3_VIEWPORT_START 0x415c 7073 #define mmSCL4_VIEWPORT_START 0x435c 7074 #define mmSCL5_VIEWPORT_START 0x455c 7075 #define mmVIEWPORT_SIZE 0x1b5d 7076 #define mmSCL0_VIEWPORT_SIZE 0x1b5d 7077 #define mmSCL1_VIEWPORT_SIZE 0x1d5d 7078 #define mmSCL2_VIEWPORT_SIZE 0x1f5d 7079 #define mmSCL3_VIEWPORT_SIZE 0x415d 7080 #define mmSCL4_VIEWPORT_SIZE 0x435d 7081 #define mmSCL5_VIEWPORT_SIZE 0x455d 7082 #define mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e 7083 #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e 7084 #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e 7085 #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e 7086 #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e 7087 #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e 7088 #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e 7089 #define mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f 7090 #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f 7091 #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f 7092 #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f 7093 #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f 7094 #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f 7095 #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f 7096 #define mmSCL_MODE_CHANGE_DET1 0x1b60 7097 #define mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60 7098 #define mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60 7099 #define mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60 7100 #define mmSCL3_SCL_MODE_CHANGE_DET1 0x4160 7101 #define mmSCL4_SCL_MODE_CHANGE_DET1 0x4360 7102 #define mmSCL5_SCL_MODE_CHANGE_DET1 0x4560 7103 #define mmSCL_MODE_CHANGE_DET2 0x1b61 7104 #define mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61 7105 #define mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61 7106 #define mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61 7107 #define mmSCL3_SCL_MODE_CHANGE_DET2 0x4161 7108 #define mmSCL4_SCL_MODE_CHANGE_DET2 0x4361 7109 #define mmSCL5_SCL_MODE_CHANGE_DET2 0x4561 7110 #define mmSCL_MODE_CHANGE_DET3 0x1b62 7111 #define mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62 7112 #define mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62 7113 #define mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62 7114 #define mmSCL3_SCL_MODE_CHANGE_DET3 0x4162 7115 #define mmSCL4_SCL_MODE_CHANGE_DET3 0x4362 7116 #define mmSCL5_SCL_MODE_CHANGE_DET3 0x4562 7117 #define mmSCL_MODE_CHANGE_MASK 0x1b63 7118 #define mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63 7119 #define mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63 7120 #define mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63 7121 #define mmSCL3_SCL_MODE_CHANGE_MASK 0x4163 7122 #define mmSCL4_SCL_MODE_CHANGE_MASK 0x4363 7123 #define mmSCL5_SCL_MODE_CHANGE_MASK 0x4563 7124 #define mmSCL_DEBUG2 0x1b69 7125 #define mmSCL0_SCL_DEBUG2 0x1b69 7126 #define mmSCL1_SCL_DEBUG2 0x1d69 7127 #define mmSCL2_SCL_DEBUG2 0x1f69 7128 #define mmSCL3_SCL_DEBUG2 0x4169 7129 #define mmSCL4_SCL_DEBUG2 0x4369 7130 #define mmSCL5_SCL_DEBUG2 0x4569 7131 #define mmSCL_DEBUG 0x1b6a 7132 #define mmSCL0_SCL_DEBUG 0x1b6a 7133 #define mmSCL1_SCL_DEBUG 0x1d6a 7134 #define mmSCL2_SCL_DEBUG 0x1f6a 7135 #define mmSCL3_SCL_DEBUG 0x416a 7136 #define mmSCL4_SCL_DEBUG 0x436a 7137 #define mmSCL5_SCL_DEBUG 0x456a 7138 #define mmSCL_TEST_DEBUG_INDEX 0x1b6b 7139 #define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b 7140 #define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b 7141 #define mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b 7142 #define mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b 7143 #define mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b 7144 #define mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b 7145 #define mmSCL_TEST_DEBUG_DATA 0x1b6c 7146 #define mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c 7147 #define mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c 7148 #define mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c 7149 #define mmSCL3_SCL_TEST_DEBUG_DATA 0x416c 7150 #define mmSCL4_SCL_TEST_DEBUG_DATA 0x436c 7151 #define mmSCL5_SCL_TEST_DEBUG_DATA 0x456c 7152 #define mmSCLV_COEF_RAM_SELECT 0x4670 7153 #define mmSCLV0_SCLV_COEF_RAM_SELECT 0x4670 7154 #define mmSCLV1_SCLV_COEF_RAM_SELECT 0x9870 7155 #define mmSCLV_COEF_RAM_TAP_DATA 0x4671 7156 #define mmSCLV0_SCLV_COEF_RAM_TAP_DATA 0x4671 7157 #define mmSCLV1_SCLV_COEF_RAM_TAP_DATA 0x9871 7158 #define mmSCLV_MODE 0x4672 7159 #define mmSCLV0_SCLV_MODE 0x4672 7160 #define mmSCLV1_SCLV_MODE 0x9872 7161 #define mmSCLV_TAP_CONTROL 0x4673 7162 #define mmSCLV0_SCLV_TAP_CONTROL 0x4673 7163 #define mmSCLV1_SCLV_TAP_CONTROL 0x9873 7164 #define mmSCLV_CONTROL 0x4674 7165 #define mmSCLV0_SCLV_CONTROL 0x4674 7166 #define mmSCLV1_SCLV_CONTROL 0x9874 7167 #define mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675 7168 #define mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL 0x4675 7169 #define mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL 0x9875 7170 #define mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676 7171 #define mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL 0x4676 7172 #define mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL 0x9876 7173 #define mmSCLV_HORZ_FILTER_CONTROL 0x4677 7174 #define mmSCLV0_SCLV_HORZ_FILTER_CONTROL 0x4677 7175 #define mmSCLV1_SCLV_HORZ_FILTER_CONTROL 0x9877 7176 #define mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678 7177 #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO 0x4678 7178 #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO 0x9878 7179 #define mmSCLV_HORZ_FILTER_INIT 0x4679 7180 #define mmSCLV0_SCLV_HORZ_FILTER_INIT 0x4679 7181 #define mmSCLV1_SCLV_HORZ_FILTER_INIT 0x9879 7182 #define mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a 7183 #define mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a 7184 #define mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C 0x987a 7185 #define mmSCLV_HORZ_FILTER_INIT_C 0x467b 7186 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_C 0x467b 7187 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_C 0x987b 7188 #define mmSCLV_VERT_FILTER_CONTROL 0x467c 7189 #define mmSCLV0_SCLV_VERT_FILTER_CONTROL 0x467c 7190 #define mmSCLV1_SCLV_VERT_FILTER_CONTROL 0x987c 7191 #define mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d 7192 #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO 0x467d 7193 #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO 0x987d 7194 #define mmSCLV_VERT_FILTER_INIT 0x467e 7195 #define mmSCLV0_SCLV_VERT_FILTER_INIT 0x467e 7196 #define mmSCLV1_SCLV_VERT_FILTER_INIT 0x987e 7197 #define mmSCLV_VERT_FILTER_INIT_BOT 0x467f 7198 #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT 0x467f 7199 #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT 0x987f 7200 #define mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 7201 #define mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C 0x4680 7202 #define mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C 0x9880 7203 #define mmSCLV_VERT_FILTER_INIT_C 0x4681 7204 #define mmSCLV0_SCLV_VERT_FILTER_INIT_C 0x4681 7205 #define mmSCLV1_SCLV_VERT_FILTER_INIT_C 0x9881 7206 #define mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682 7207 #define mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C 0x4682 7208 #define mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C 0x9882 7209 #define mmSCLV_ROUND_OFFSET 0x4683 7210 #define mmSCLV0_SCLV_ROUND_OFFSET 0x4683 7211 #define mmSCLV1_SCLV_ROUND_OFFSET 0x9883 7212 #define mmSCLV_UPDATE 0x4684 7213 #define mmSCLV0_SCLV_UPDATE 0x4684 7214 #define mmSCLV1_SCLV_UPDATE 0x9884 7215 #define mmSCLV_ALU_CONTROL 0x4685 7216 #define mmSCLV0_SCLV_ALU_CONTROL 0x4685 7217 #define mmSCLV1_SCLV_ALU_CONTROL 0x9885 7218 #define mmSCLV_VIEWPORT_START 0x4686 7219 #define mmSCLV0_SCLV_VIEWPORT_START 0x4686 7220 #define mmSCLV1_SCLV_VIEWPORT_START 0x9886 7221 #define mmSCLV_VIEWPORT_START_SECONDARY 0x4687 7222 #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY 0x4687 7223 #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY 0x9887 7224 #define mmSCLV_VIEWPORT_SIZE 0x4688 7225 #define mmSCLV0_SCLV_VIEWPORT_SIZE 0x4688 7226 #define mmSCLV1_SCLV_VIEWPORT_SIZE 0x9888 7227 #define mmSCLV_VIEWPORT_START_C 0x4689 7228 #define mmSCLV0_SCLV_VIEWPORT_START_C 0x4689 7229 #define mmSCLV1_SCLV_VIEWPORT_START_C 0x9889 7230 #define mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a 7231 #define mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C 0x468a 7232 #define mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C 0x988a 7233 #define mmSCLV_VIEWPORT_SIZE_C 0x468b 7234 #define mmSCLV0_SCLV_VIEWPORT_SIZE_C 0x468b 7235 #define mmSCLV1_SCLV_VIEWPORT_SIZE_C 0x988b 7236 #define mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c 7237 #define mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c 7238 #define mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT 0x988c 7239 #define mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d 7240 #define mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d 7241 #define mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM 0x988d 7242 #define mmSCLV_MODE_CHANGE_DET1 0x468e 7243 #define mmSCLV0_SCLV_MODE_CHANGE_DET1 0x468e 7244 #define mmSCLV1_SCLV_MODE_CHANGE_DET1 0x988e 7245 #define mmSCLV_MODE_CHANGE_DET2 0x468f 7246 #define mmSCLV0_SCLV_MODE_CHANGE_DET2 0x468f 7247 #define mmSCLV1_SCLV_MODE_CHANGE_DET2 0x988f 7248 #define mmSCLV_MODE_CHANGE_DET3 0x4690 7249 #define mmSCLV0_SCLV_MODE_CHANGE_DET3 0x4690 7250 #define mmSCLV1_SCLV_MODE_CHANGE_DET3 0x9890 7251 #define mmSCLV_MODE_CHANGE_MASK 0x4691 7252 #define mmSCLV0_SCLV_MODE_CHANGE_MASK 0x4691 7253 #define mmSCLV1_SCLV_MODE_CHANGE_MASK 0x9891 7254 #define mmSCLV_HORZ_FILTER_INIT_BOT 0x4692 7255 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT 0x4692 7256 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT 0x9892 7257 #define mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693 7258 #define mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C 0x4693 7259 #define mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C 0x9893 7260 #define mmSCLV_DEBUG2 0x4694 7261 #define mmSCLV0_SCLV_DEBUG2 0x4694 7262 #define mmSCLV1_SCLV_DEBUG2 0x9894 7263 #define mmSCLV_DEBUG 0x4695 7264 #define mmSCLV0_SCLV_DEBUG 0x4695 7265 #define mmSCLV1_SCLV_DEBUG 0x9895 7266 #define mmSCLV_TEST_DEBUG_INDEX 0x4696 7267 #define mmSCLV0_SCLV_TEST_DEBUG_INDEX 0x4696 7268 #define mmSCLV1_SCLV_TEST_DEBUG_INDEX 0x9896 7269 #define mmSCLV_TEST_DEBUG_DATA 0x4697 7270 #define mmSCLV0_SCLV_TEST_DEBUG_DATA 0x4697 7271 #define mmSCLV1_SCLV_TEST_DEBUG_DATA 0x9897 7272 #define mmCOL_MAN_UPDATE 0x46a4 7273 #define mmCOL_MAN0_COL_MAN_UPDATE 0x46a4 7274 #define mmCOL_MAN1_COL_MAN_UPDATE 0x98a4 7275 #define mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5 7276 #define mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL 0x46a5 7277 #define mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL 0x98a5 7278 #define mmINPUT_CSC_C11_C12_A 0x46a6 7279 #define mmCOL_MAN0_INPUT_CSC_C11_C12_A 0x46a6 7280 #define mmCOL_MAN1_INPUT_CSC_C11_C12_A 0x98a6 7281 #define mmINPUT_CSC_C13_C14_A 0x46a7 7282 #define mmCOL_MAN0_INPUT_CSC_C13_C14_A 0x46a7 7283 #define mmCOL_MAN1_INPUT_CSC_C13_C14_A 0x98a7 7284 #define mmINPUT_CSC_C21_C22_A 0x46a8 7285 #define mmCOL_MAN0_INPUT_CSC_C21_C22_A 0x46a8 7286 #define mmCOL_MAN1_INPUT_CSC_C21_C22_A 0x98a8 7287 #define mmINPUT_CSC_C23_C24_A 0x46a9 7288 #define mmCOL_MAN0_INPUT_CSC_C23_C24_A 0x46a9 7289 #define mmCOL_MAN1_INPUT_CSC_C23_C24_A 0x98a9 7290 #define mmINPUT_CSC_C31_C32_A 0x46aa 7291 #define mmCOL_MAN0_INPUT_CSC_C31_C32_A 0x46aa 7292 #define mmCOL_MAN1_INPUT_CSC_C31_C32_A 0x98aa 7293 #define mmINPUT_CSC_C33_C34_A 0x46ab 7294 #define mmCOL_MAN0_INPUT_CSC_C33_C34_A 0x46ab 7295 #define mmCOL_MAN1_INPUT_CSC_C33_C34_A 0x98ab 7296 #define mmINPUT_CSC_C11_C12_B 0x46ac 7297 #define mmCOL_MAN0_INPUT_CSC_C11_C12_B 0x46ac 7298 #define mmCOL_MAN1_INPUT_CSC_C11_C12_B 0x98ac 7299 #define mmINPUT_CSC_C13_C14_B 0x46ad 7300 #define mmCOL_MAN0_INPUT_CSC_C13_C14_B 0x46ad 7301 #define mmCOL_MAN1_INPUT_CSC_C13_C14_B 0x98ad 7302 #define mmINPUT_CSC_C21_C22_B 0x46ae 7303 #define mmCOL_MAN0_INPUT_CSC_C21_C22_B 0x46ae 7304 #define mmCOL_MAN1_INPUT_CSC_C21_C22_B 0x98ae 7305 #define mmINPUT_CSC_C23_C24_B 0x46af 7306 #define mmCOL_MAN0_INPUT_CSC_C23_C24_B 0x46af 7307 #define mmCOL_MAN1_INPUT_CSC_C23_C24_B 0x98af 7308 #define mmINPUT_CSC_C31_C32_B 0x46b0 7309 #define mmCOL_MAN0_INPUT_CSC_C31_C32_B 0x46b0 7310 #define mmCOL_MAN1_INPUT_CSC_C31_C32_B 0x98b0 7311 #define mmINPUT_CSC_C33_C34_B 0x46b1 7312 #define mmCOL_MAN0_INPUT_CSC_C33_C34_B 0x46b1 7313 #define mmCOL_MAN1_INPUT_CSC_C33_C34_B 0x98b1 7314 #define mmPRESCALE_CONTROL 0x46b2 7315 #define mmCOL_MAN0_PRESCALE_CONTROL 0x46b2 7316 #define mmCOL_MAN1_PRESCALE_CONTROL 0x98b2 7317 #define mmPRESCALE_VALUES_R 0x46b3 7318 #define mmCOL_MAN0_PRESCALE_VALUES_R 0x46b3 7319 #define mmCOL_MAN1_PRESCALE_VALUES_R 0x98b3 7320 #define mmPRESCALE_VALUES_G 0x46b4 7321 #define mmCOL_MAN0_PRESCALE_VALUES_G 0x46b4 7322 #define mmCOL_MAN1_PRESCALE_VALUES_G 0x98b4 7323 #define mmPRESCALE_VALUES_B 0x46b5 7324 #define mmCOL_MAN0_PRESCALE_VALUES_B 0x46b5 7325 #define mmCOL_MAN1_PRESCALE_VALUES_B 0x98b5 7326 #define mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6 7327 #define mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL 0x46b6 7328 #define mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL 0x98b6 7329 #define mmOUTPUT_CSC_C11_C12_A 0x46b7 7330 #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_A 0x46b7 7331 #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_A 0x98b7 7332 #define mmOUTPUT_CSC_C13_C14_A 0x46b8 7333 #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_A 0x46b8 7334 #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_A 0x98b8 7335 #define mmOUTPUT_CSC_C21_C22_A 0x46b9 7336 #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_A 0x46b9 7337 #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_A 0x98b9 7338 #define mmOUTPUT_CSC_C23_C24_A 0x46ba 7339 #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_A 0x46ba 7340 #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_A 0x98ba 7341 #define mmOUTPUT_CSC_C31_C32_A 0x46bb 7342 #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_A 0x46bb 7343 #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_A 0x98bb 7344 #define mmOUTPUT_CSC_C33_C34_A 0x46bc 7345 #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_A 0x46bc 7346 #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_A 0x98bc 7347 #define mmOUTPUT_CSC_C11_C12_B 0x46bd 7348 #define mmCOL_MAN0_OUTPUT_CSC_C11_C12_B 0x46bd 7349 #define mmCOL_MAN1_OUTPUT_CSC_C11_C12_B 0x98bd 7350 #define mmOUTPUT_CSC_C13_C14_B 0x46be 7351 #define mmCOL_MAN0_OUTPUT_CSC_C13_C14_B 0x46be 7352 #define mmCOL_MAN1_OUTPUT_CSC_C13_C14_B 0x98be 7353 #define mmOUTPUT_CSC_C21_C22_B 0x46bf 7354 #define mmCOL_MAN0_OUTPUT_CSC_C21_C22_B 0x46bf 7355 #define mmCOL_MAN1_OUTPUT_CSC_C21_C22_B 0x98bf 7356 #define mmOUTPUT_CSC_C23_C24_B 0x46c0 7357 #define mmCOL_MAN0_OUTPUT_CSC_C23_C24_B 0x46c0 7358 #define mmCOL_MAN1_OUTPUT_CSC_C23_C24_B 0x98c0 7359 #define mmOUTPUT_CSC_C31_C32_B 0x46c1 7360 #define mmCOL_MAN0_OUTPUT_CSC_C31_C32_B 0x46c1 7361 #define mmCOL_MAN1_OUTPUT_CSC_C31_C32_B 0x98c1 7362 #define mmOUTPUT_CSC_C33_C34_B 0x46c2 7363 #define mmCOL_MAN0_OUTPUT_CSC_C33_C34_B 0x46c2 7364 #define mmCOL_MAN1_OUTPUT_CSC_C33_C34_B 0x98c2 7365 #define mmDENORM_CLAMP_CONTROL 0x46c3 7366 #define mmCOL_MAN0_DENORM_CLAMP_CONTROL 0x46c3 7367 #define mmCOL_MAN1_DENORM_CLAMP_CONTROL 0x98c3 7368 #define mmDENORM_CLAMP_RANGE_R_CR 0x46c4 7369 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR 0x46c4 7370 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR 0x98c4 7371 #define mmDENORM_CLAMP_RANGE_G_Y 0x46c5 7372 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y 0x46c5 7373 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y 0x98c5 7374 #define mmDENORM_CLAMP_RANGE_B_CB 0x46c6 7375 #define mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB 0x46c6 7376 #define mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB 0x98c6 7377 #define mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7 7378 #define mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD 0x46c7 7379 #define mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD 0x98c7 7380 #define mmGAMMA_CORR_CONTROL 0x46c8 7381 #define mmCOL_MAN0_GAMMA_CORR_CONTROL 0x46c8 7382 #define mmCOL_MAN1_GAMMA_CORR_CONTROL 0x98c8 7383 #define mmGAMMA_CORR_LUT_INDEX 0x46c9 7384 #define mmCOL_MAN0_GAMMA_CORR_LUT_INDEX 0x46c9 7385 #define mmCOL_MAN1_GAMMA_CORR_LUT_INDEX 0x98c9 7386 #define mmGAMMA_CORR_LUT_DATA 0x46ca 7387 #define mmCOL_MAN0_GAMMA_CORR_LUT_DATA 0x46ca 7388 #define mmCOL_MAN1_GAMMA_CORR_LUT_DATA 0x98ca 7389 #define mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb 7390 #define mmCOL_MAN0_GAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb 7391 #define mmCOL_MAN1_GAMMA_CORR_LUT_WRITE_EN_MASK 0x98cb 7392 #define mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc 7393 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_START_CNTL 0x46cc 7394 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_START_CNTL 0x98cc 7395 #define mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd 7396 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd 7397 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_SLOPE_CNTL 0x98cd 7398 #define mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce 7399 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL1 0x46ce 7400 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL1 0x98ce 7401 #define mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf 7402 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL2 0x46cf 7403 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL2 0x98cf 7404 #define mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0 7405 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_0_1 0x46d0 7406 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_0_1 0x98d0 7407 #define mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1 7408 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_2_3 0x46d1 7409 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_2_3 0x98d1 7410 #define mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2 7411 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_4_5 0x46d2 7412 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_4_5 0x98d2 7413 #define mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3 7414 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_6_7 0x46d3 7415 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_6_7 0x98d3 7416 #define mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4 7417 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_8_9 0x46d4 7418 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_8_9 0x98d4 7419 #define mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5 7420 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_10_11 0x46d5 7421 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_10_11 0x98d5 7422 #define mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6 7423 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_12_13 0x46d6 7424 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_12_13 0x98d6 7425 #define mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7 7426 #define mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_14_15 0x46d7 7427 #define mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_14_15 0x98d7 7428 #define mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8 7429 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_START_CNTL 0x46d8 7430 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_START_CNTL 0x98d8 7431 #define mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 7432 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9 7433 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_SLOPE_CNTL 0x98d9 7434 #define mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da 7435 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL1 0x46da 7436 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL1 0x98da 7437 #define mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db 7438 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL2 0x46db 7439 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL2 0x98db 7440 #define mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc 7441 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_0_1 0x46dc 7442 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_0_1 0x98dc 7443 #define mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd 7444 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_2_3 0x46dd 7445 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_2_3 0x98dd 7446 #define mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de 7447 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_4_5 0x46de 7448 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_4_5 0x98de 7449 #define mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df 7450 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_6_7 0x46df 7451 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_6_7 0x98df 7452 #define mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0 7453 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_8_9 0x46e0 7454 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_8_9 0x98e0 7455 #define mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1 7456 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_10_11 0x46e1 7457 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_10_11 0x98e1 7458 #define mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2 7459 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_12_13 0x46e2 7460 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_12_13 0x98e2 7461 #define mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3 7462 #define mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_14_15 0x46e3 7463 #define mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_14_15 0x98e3 7464 #define mmPACK_FIFO_ERROR 0x46e4 7465 #define mmCOL_MAN0_PACK_FIFO_ERROR 0x46e4 7466 #define mmCOL_MAN1_PACK_FIFO_ERROR 0x98e4 7467 #define mmOUTPUT_FIFO_ERROR 0x46e5 7468 #define mmCOL_MAN0_OUTPUT_FIFO_ERROR 0x46e5 7469 #define mmCOL_MAN1_OUTPUT_FIFO_ERROR 0x98e5 7470 #define mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6 7471 #define mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL 0x46e6 7472 #define mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL 0x98e6 7473 #define mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7 7474 #define mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX 0x46e7 7475 #define mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX 0x98e7 7476 #define mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 7477 #define mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR 0x46e8 7478 #define mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR 0x98e8 7479 #define mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9 7480 #define mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA 0x46e9 7481 #define mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA 0x98e9 7482 #define mmINPUT_GAMMA_LUT_30_COLOR 0x46ea 7483 #define mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR 0x46ea 7484 #define mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR 0x98ea 7485 #define mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb 7486 #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1 0x46eb 7487 #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1 0x98eb 7488 #define mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec 7489 #define mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2 0x46ec 7490 #define mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2 0x98ec 7491 #define mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed 7492 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B 0x46ed 7493 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B 0x98ed 7494 #define mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee 7495 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G 0x46ee 7496 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G 0x98ee 7497 #define mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef 7498 #define mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R 0x46ef 7499 #define mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R 0x98ef 7500 #define mmCOL_MAN_DEBUG_CONTROL 0x46f0 7501 #define mmCOL_MAN0_COL_MAN_DEBUG_CONTROL 0x46f0 7502 #define mmCOL_MAN1_COL_MAN_DEBUG_CONTROL 0x98f0 7503 #define mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1 7504 #define mmCOL_MAN0_COL_MAN_TEST_DEBUG_INDEX 0x46f1 7505 #define mmCOL_MAN1_COL_MAN_TEST_DEBUG_INDEX 0x98f1 7506 #define mmCOL_MAN_TEST_DEBUG_DATA 0x46f3 7507 #define mmCOL_MAN0_COL_MAN_TEST_DEBUG_DATA 0x46f3 7508 #define mmCOL_MAN1_COL_MAN_TEST_DEBUG_DATA 0x98f3 7509 #define mmUNP_GRPH_ENABLE 0x4600 7510 #define mmUNP0_UNP_GRPH_ENABLE 0x4600 7511 #define mmUNP1_UNP_GRPH_ENABLE 0x9800 7512 #define mmUNP_GRPH_CONTROL 0x4601 7513 #define mmUNP0_UNP_GRPH_CONTROL 0x4601 7514 #define mmUNP1_UNP_GRPH_CONTROL 0x9801 7515 #define mmUNP_GRPH_CONTROL_C 0x4602 7516 #define mmUNP0_UNP_GRPH_CONTROL_C 0x4602 7517 #define mmUNP1_UNP_GRPH_CONTROL_C 0x9802 7518 #define mmUNP_GRPH_CONTROL_EXP 0x4603 7519 #define mmUNP0_UNP_GRPH_CONTROL_EXP 0x4603 7520 #define mmUNP1_UNP_GRPH_CONTROL_EXP 0x9803 7521 #define mmUNP_GRPH_SWAP_CNTL 0x4605 7522 #define mmUNP0_UNP_GRPH_SWAP_CNTL 0x4605 7523 #define mmUNP1_UNP_GRPH_SWAP_CNTL 0x9805 7524 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 7525 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606 7526 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x9806 7527 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 7528 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607 7529 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x9807 7530 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 7531 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608 7532 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x9808 7533 #define mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 7534 #define mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609 7535 #define mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x9809 7536 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a 7537 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a 7538 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x980a 7539 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b 7540 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b 7541 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x980b 7542 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c 7543 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c 7544 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x980c 7545 #define mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d 7546 #define mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d 7547 #define mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x980d 7548 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e 7549 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e 7550 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x980e 7551 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f 7552 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f 7553 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x980f 7554 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 7555 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610 7556 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x9810 7557 #define mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 7558 #define mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611 7559 #define mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x9811 7560 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 7561 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612 7562 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x9812 7563 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 7564 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613 7565 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x9813 7566 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 7567 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614 7568 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x9814 7569 #define mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 7570 #define mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615 7571 #define mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x9815 7572 #define mmUNP_GRPH_PITCH_L 0x4616 7573 #define mmUNP0_UNP_GRPH_PITCH_L 0x4616 7574 #define mmUNP1_UNP_GRPH_PITCH_L 0x9816 7575 #define mmUNP_GRPH_PITCH_C 0x4617 7576 #define mmUNP0_UNP_GRPH_PITCH_C 0x4617 7577 #define mmUNP1_UNP_GRPH_PITCH_C 0x9817 7578 #define mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618 7579 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L 0x4618 7580 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L 0x9818 7581 #define mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619 7582 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C 0x4619 7583 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C 0x9819 7584 #define mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a 7585 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L 0x461a 7586 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L 0x981a 7587 #define mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b 7588 #define mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C 0x461b 7589 #define mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C 0x981b 7590 #define mmUNP_GRPH_X_START_L 0x461c 7591 #define mmUNP0_UNP_GRPH_X_START_L 0x461c 7592 #define mmUNP1_UNP_GRPH_X_START_L 0x981c 7593 #define mmUNP_GRPH_X_START_C 0x461d 7594 #define mmUNP0_UNP_GRPH_X_START_C 0x461d 7595 #define mmUNP1_UNP_GRPH_X_START_C 0x981d 7596 #define mmUNP_GRPH_Y_START_L 0x461e 7597 #define mmUNP0_UNP_GRPH_Y_START_L 0x461e 7598 #define mmUNP1_UNP_GRPH_Y_START_L 0x981e 7599 #define mmUNP_GRPH_Y_START_C 0x461f 7600 #define mmUNP0_UNP_GRPH_Y_START_C 0x461f 7601 #define mmUNP1_UNP_GRPH_Y_START_C 0x981f 7602 #define mmUNP_GRPH_X_END_L 0x4620 7603 #define mmUNP0_UNP_GRPH_X_END_L 0x4620 7604 #define mmUNP1_UNP_GRPH_X_END_L 0x9820 7605 #define mmUNP_GRPH_X_END_C 0x4621 7606 #define mmUNP0_UNP_GRPH_X_END_C 0x4621 7607 #define mmUNP1_UNP_GRPH_X_END_C 0x9821 7608 #define mmUNP_GRPH_Y_END_L 0x4622 7609 #define mmUNP0_UNP_GRPH_Y_END_L 0x4622 7610 #define mmUNP1_UNP_GRPH_Y_END_L 0x9822 7611 #define mmUNP_GRPH_Y_END_C 0x4623 7612 #define mmUNP0_UNP_GRPH_Y_END_C 0x4623 7613 #define mmUNP1_UNP_GRPH_Y_END_C 0x9823 7614 #define mmUNP_GRPH_UPDATE 0x4624 7615 #define mmUNP0_UNP_GRPH_UPDATE 0x4624 7616 #define mmUNP1_UNP_GRPH_UPDATE 0x9824 7617 #define mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a 7618 #define mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a 7619 #define mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x983a 7620 #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 7621 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625 7622 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x9825 7623 #define mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 7624 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626 7625 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x9826 7626 #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 7627 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627 7628 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x9827 7629 #define mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 7630 #define mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628 7631 #define mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x9828 7632 #define mmUNP_DVMM_PTE_CONTROL 0x4629 7633 #define mmUNP_GRPH_INTERRUPT_STATUS 0x462b 7634 #define mmUNP0_UNP_GRPH_INTERRUPT_STATUS 0x462b 7635 #define mmUNP1_UNP_GRPH_INTERRUPT_STATUS 0x982b 7636 #define mmUNP_GRPH_INTERRUPT_CONTROL 0x462c 7637 #define mmUNP0_UNP_GRPH_INTERRUPT_CONTROL 0x462c 7638 #define mmUNP1_UNP_GRPH_INTERRUPT_CONTROL 0x982c 7639 #define mmUNP_GRPH_STEREOSYNC_FLIP 0x462e 7640 #define mmUNP0_UNP_GRPH_STEREOSYNC_FLIP 0x462e 7641 #define mmUNP1_UNP_GRPH_STEREOSYNC_FLIP 0x982e 7642 #define mmUNP_FLIP_CONTROL 0x462f 7643 #define mmUNP0_UNP_FLIP_CONTROL 0x462f 7644 #define mmUNP1_UNP_FLIP_CONTROL 0x982f 7645 #define mmUNP_CRC_CONTROL 0x4630 7646 #define mmUNP0_UNP_CRC_CONTROL 0x4630 7647 #define mmUNP1_UNP_CRC_CONTROL 0x9830 7648 #define mmUNP_CRC_MASK 0x4631 7649 #define mmUNP0_UNP_CRC_MASK 0x4631 7650 #define mmUNP1_UNP_CRC_MASK 0x9831 7651 #define mmUNP_CRC_CURRENT 0x4632 7652 #define mmUNP0_UNP_CRC_CURRENT 0x4632 7653 #define mmUNP1_UNP_CRC_CURRENT 0x9832 7654 #define mmUNP_CRC_LAST 0x4633 7655 #define mmUNP0_UNP_CRC_LAST 0x4633 7656 #define mmUNP1_UNP_CRC_LAST 0x9833 7657 #define mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 7658 #define mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634 7659 #define mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK 0x9834 7660 #define mmUNP_HW_ROTATION 0x4635 7661 #define mmUNP0_UNP_HW_ROTATION 0x4635 7662 #define mmUNP1_UNP_HW_ROTATION 0x9835 7663 #define mmUNP_DEBUG 0x4636 7664 #define mmUNP0_UNP_DEBUG 0x4636 7665 #define mmUNP1_UNP_DEBUG 0x9836 7666 #define mmUNP_DEBUG2 0x4637 7667 #define mmUNP0_UNP_DEBUG2 0x4637 7668 #define mmUNP1_UNP_DEBUG2 0x9837 7669 #define mmUNP_DVMM_DEBUG 0x463b 7670 #define mmUNP0_UNP_DVMM_DEBUG 0x463b 7671 #define mmUNP1_UNP_DVMM_DEBUG 0x983b 7672 #define mmUNP_TEST_DEBUG_INDEX 0x4638 7673 #define mmUNP0_UNP_TEST_DEBUG_INDEX 0x4638 7674 #define mmUNP1_UNP_TEST_DEBUG_INDEX 0x9838 7675 #define mmUNP_TEST_DEBUG_DATA 0x4639 7676 #define mmUNP0_UNP_TEST_DEBUG_DATA 0x4639 7677 #define mmUNP1_UNP_TEST_DEBUG_DATA 0x9839 7678 #define mmGENMO_WT 0xf0 7679 #define mmGENMO_RD 0xf3 7680 #define mmGENENB 0xf0 7681 #define mmGENFC_WT 0xee 7682 #define mmVGA0_GENFC_WT 0xee 7683 #define mmVGA1_GENFC_WT 0xf6 7684 #define mmGENFC_RD 0xf2 7685 #define mmGENS0 0xf0 7686 #define mmGENS1 0xee 7687 #define mmVGA0_GENS1 0xee 7688 #define mmVGA1_GENS1 0xf6 7689 #define mmDAC_DATA 0xf2 7690 #define mmDAC_MASK 0xf1 7691 #define mmDAC_R_INDEX 0xf1 7692 #define mmDAC_W_INDEX 0xf2 7693 #define mmSEQ8_IDX 0xf1 7694 #define mmSEQ8_DATA 0xf1 7695 #define ixSEQ00 0x0 7696 #define ixSEQ01 0x1 7697 #define ixSEQ02 0x2 7698 #define ixSEQ03 0x3 7699 #define ixSEQ04 0x4 7700 #define mmCRTC8_IDX 0xed 7701 #define mmVGA0_CRTC8_IDX 0xed 7702 #define mmVGA1_CRTC8_IDX 0xf5 7703 #define mmCRTC8_DATA 0xed 7704 #define mmVGA0_CRTC8_DATA 0xed 7705 #define mmVGA1_CRTC8_DATA 0xf5 7706 #define ixCRT00 0x0 7707 #define ixCRT01 0x1 7708 #define ixCRT02 0x2 7709 #define ixCRT03 0x3 7710 #define ixCRT04 0x4 7711 #define ixCRT05 0x5 7712 #define ixCRT06 0x6 7713 #define ixCRT07 0x7 7714 #define ixCRT08 0x8 7715 #define ixCRT09 0x9 7716 #define ixCRT0A 0xa 7717 #define ixCRT0B 0xb 7718 #define ixCRT0C 0xc 7719 #define ixCRT0D 0xd 7720 #define ixCRT0E 0xe 7721 #define ixCRT0F 0xf 7722 #define ixCRT10 0x10 7723 #define ixCRT11 0x11 7724 #define ixCRT12 0x12 7725 #define ixCRT13 0x13 7726 #define ixCRT14 0x14 7727 #define ixCRT15 0x15 7728 #define ixCRT16 0x16 7729 #define ixCRT17 0x17 7730 #define ixCRT18 0x18 7731 #define ixCRT1E 0x1e 7732 #define ixCRT1F 0x1f 7733 #define ixCRT22 0x22 7734 #define mmGRPH8_IDX 0xf3 7735 #define mmGRPH8_DATA 0xf3 7736 #define ixGRA00 0x0 7737 #define ixGRA01 0x1 7738 #define ixGRA02 0x2 7739 #define ixGRA03 0x3 7740 #define ixGRA04 0x4 7741 #define ixGRA05 0x5 7742 #define ixGRA06 0x6 7743 #define ixGRA07 0x7 7744 #define ixGRA08 0x8 7745 #define mmATTRX 0xf0 7746 #define mmATTRDW 0xf0 7747 #define mmATTRDR 0xf0 7748 #define ixATTR00 0x0 7749 #define ixATTR01 0x1 7750 #define ixATTR02 0x2 7751 #define ixATTR03 0x3 7752 #define ixATTR04 0x4 7753 #define ixATTR05 0x5 7754 #define ixATTR06 0x6 7755 #define ixATTR07 0x7 7756 #define ixATTR08 0x8 7757 #define ixATTR09 0x9 7758 #define ixATTR0A 0xa 7759 #define ixATTR0B 0xb 7760 #define ixATTR0C 0xc 7761 #define ixATTR0D 0xd 7762 #define ixATTR0E 0xe 7763 #define ixATTR0F 0xf 7764 #define ixATTR10 0x10 7765 #define ixATTR11 0x11 7766 #define ixATTR12 0x12 7767 #define ixATTR13 0x13 7768 #define ixATTR14 0x14 7769 #define mmVGA_RENDER_CONTROL 0xc0 7770 #define mmVGA_SOURCE_SELECT 0xfc 7771 #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 7772 #define mmVGA_MODE_CONTROL 0xc2 7773 #define mmVGA_SURFACE_PITCH_SELECT 0xc3 7774 #define mmVGA_MEMORY_BASE_ADDRESS 0xc4 7775 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9 7776 #define mmVGA_DISPBUF1_SURFACE_ADDR 0xc6 7777 #define mmVGA_DISPBUF2_SURFACE_ADDR 0xc8 7778 #define mmVGA_HDP_CONTROL 0xca 7779 #define mmVGA_CACHE_CONTROL 0xcb 7780 #define mmD1VGA_CONTROL 0xcc 7781 #define mmD2VGA_CONTROL 0xce 7782 #define mmD3VGA_CONTROL 0xf8 7783 #define mmD4VGA_CONTROL 0xf9 7784 #define mmD5VGA_CONTROL 0xfa 7785 #define mmD6VGA_CONTROL 0xfb 7786 #define mmVGA_HW_DEBUG 0xcf 7787 #define mmVGA_STATUS 0xd0 7788 #define mmVGA_INTERRUPT_CONTROL 0xd1 7789 #define mmVGA_STATUS_CLEAR 0xd2 7790 #define mmVGA_INTERRUPT_STATUS 0xd3 7791 #define mmVGA_MAIN_CONTROL 0xd4 7792 #define mmVGA_TEST_CONTROL 0xd5 7793 #define mmVGA_DEBUG_READBACK_INDEX 0xd6 7794 #define mmVGA_DEBUG_READBACK_DATA 0xd7 7795 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x12 7796 #define mmVGA_MEM_READ_PAGE_ADDR 0x13 7797 #define mmVGA_TEST_DEBUG_INDEX 0xc5 7798 #define mmVGA_TEST_DEBUG_DATA 0xc7 7799 #define ixVGADCC_DBG_DCCIF_C 0x7e 7800 #define mmBPHYC_DAC_MACRO_CNTL 0x48b9 7801 #define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba 7802 #define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30 7803 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30 7804 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30 7805 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30 7806 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 7807 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330 7808 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530 7809 #define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31 7810 #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31 7811 #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31 7812 #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31 7813 #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 7814 #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331 7815 #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531 7816 #define mmDPG_WATERMARK_MASK_CONTROL 0x1b32 7817 #define mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32 7818 #define mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32 7819 #define mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32 7820 #define mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132 7821 #define mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332 7822 #define mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532 7823 #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 7824 #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33 7825 #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33 7826 #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33 7827 #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133 7828 #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333 7829 #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533 7830 #define mmDPG_PIPE_DPM_CONTROL 0x1b34 7831 #define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34 7832 #define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34 7833 #define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34 7834 #define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134 7835 #define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334 7836 #define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534 7837 #define mmDPG_PIPE_STUTTER_CONTROL 0x1b35 7838 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35 7839 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35 7840 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35 7841 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135 7842 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335 7843 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535 7844 #define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 7845 #define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36 7846 #define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36 7847 #define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36 7848 #define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 7849 #define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336 7850 #define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536 7851 #define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 7852 #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37 7853 #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37 7854 #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37 7855 #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 7856 #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337 7857 #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537 7858 #define mmDPG_REPEATER_PROGRAM 0x1b3a 7859 #define mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a 7860 #define mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a 7861 #define mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a 7862 #define mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a 7863 #define mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a 7864 #define mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a 7865 #define mmDPG_HW_DEBUG_A 0x1b3b 7866 #define mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b 7867 #define mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b 7868 #define mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b 7869 #define mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b 7870 #define mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b 7871 #define mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b 7872 #define mmDPG_HW_DEBUG_B 0x1b3c 7873 #define mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c 7874 #define mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c 7875 #define mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c 7876 #define mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c 7877 #define mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c 7878 #define mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c 7879 #define mmDPG_HW_DEBUG_11 0x1b3d 7880 #define mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d 7881 #define mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d 7882 #define mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d 7883 #define mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d 7884 #define mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d 7885 #define mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d 7886 #define mmDPG_CHK_PRE_PROC_CNTL 0x1b3e 7887 #define mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e 7888 #define mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e 7889 #define mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e 7890 #define mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e 7891 #define mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e 7892 #define mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e 7893 #define mmDPG_DVMM_STATUS 0x1b3f 7894 #define mmDMIF_PG0_DPG_DVMM_STATUS 0x1b3f 7895 #define mmDMIF_PG1_DPG_DVMM_STATUS 0x1d3f 7896 #define mmDMIF_PG2_DPG_DVMM_STATUS 0x1f3f 7897 #define mmDMIF_PG3_DPG_DVMM_STATUS 0x413f 7898 #define mmDMIF_PG4_DPG_DVMM_STATUS 0x433f 7899 #define mmDMIF_PG5_DPG_DVMM_STATUS 0x453f 7900 #define mmDPG_TEST_DEBUG_INDEX 0x1b38 7901 #define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38 7902 #define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38 7903 #define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38 7904 #define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138 7905 #define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338 7906 #define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538 7907 #define mmDPG_TEST_DEBUG_DATA 0x1b39 7908 #define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39 7909 #define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39 7910 #define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39 7911 #define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139 7912 #define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339 7913 #define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539 7914 #define mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 7915 #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1 0x4730 7916 #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1 0x9930 7917 #define mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d 7918 #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1 0x473d 7919 #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1 0x993d 7920 #define mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 7921 #define mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2 0x4731 7922 #define mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2 0x9931 7923 #define mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e 7924 #define mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2 0x473e 7925 #define mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2 0x993e 7926 #define mmDPGV0_WATERMARK_MASK_CONTROL 0x4732 7927 #define mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL 0x4732 7928 #define mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL 0x9932 7929 #define mmDPGV1_WATERMARK_MASK_CONTROL 0x473f 7930 #define mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL 0x473f 7931 #define mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL 0x993f 7932 #define mmDPGV0_PIPE_URGENCY_CONTROL 0x4733 7933 #define mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL 0x4733 7934 #define mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL 0x9933 7935 #define mmDPGV1_PIPE_URGENCY_CONTROL 0x4740 7936 #define mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL 0x4740 7937 #define mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL 0x9940 7938 #define mmDPGV0_PIPE_DPM_CONTROL 0x4734 7939 #define mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL 0x4734 7940 #define mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL 0x9934 7941 #define mmDPGV1_PIPE_DPM_CONTROL 0x4741 7942 #define mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL 0x4741 7943 #define mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL 0x9941 7944 #define mmDPGV0_PIPE_STUTTER_CONTROL 0x4735 7945 #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL 0x4735 7946 #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL 0x9935 7947 #define mmDPGV1_PIPE_STUTTER_CONTROL 0x4742 7948 #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL 0x4742 7949 #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL 0x9942 7950 #define mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 7951 #define mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 7952 #define mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x9936 7953 #define mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 7954 #define mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743 7955 #define mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x9943 7956 #define mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 7957 #define mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 7958 #define mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x9937 7959 #define mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 7960 #define mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744 7961 #define mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x9944 7962 #define mmDPGV0_REPEATER_PROGRAM 0x4738 7963 #define mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM 0x4738 7964 #define mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM 0x9938 7965 #define mmDPGV1_REPEATER_PROGRAM 0x4745 7966 #define mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM 0x4745 7967 #define mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM 0x9945 7968 #define mmDPGV0_HW_DEBUG_A 0x4739 7969 #define mmDMIFV_PG0_DPGV0_HW_DEBUG_A 0x4739 7970 #define mmDMIFV_PG1_DPGV0_HW_DEBUG_A 0x9939 7971 #define mmDPGV1_HW_DEBUG_A 0x4746 7972 #define mmDMIFV_PG0_DPGV1_HW_DEBUG_A 0x4746 7973 #define mmDMIFV_PG1_DPGV1_HW_DEBUG_A 0x9946 7974 #define mmDPGV0_HW_DEBUG_B 0x473a 7975 #define mmDMIFV_PG0_DPGV0_HW_DEBUG_B 0x473a 7976 #define mmDMIFV_PG1_DPGV0_HW_DEBUG_B 0x993a 7977 #define mmDPGV1_HW_DEBUG_B 0x4747 7978 #define mmDMIFV_PG0_DPGV1_HW_DEBUG_B 0x4747 7979 #define mmDMIFV_PG1_DPGV1_HW_DEBUG_B 0x9947 7980 #define mmDPGV0_HW_DEBUG_11 0x473b 7981 #define mmDMIFV_PG0_DPGV0_HW_DEBUG_11 0x473b 7982 #define mmDMIFV_PG1_DPGV0_HW_DEBUG_11 0x993b 7983 #define mmDPGV1_HW_DEBUG_11 0x4748 7984 #define mmDMIFV_PG0_DPGV1_HW_DEBUG_11 0x4748 7985 #define mmDMIFV_PG1_DPGV1_HW_DEBUG_11 0x9948 7986 #define mmDPGV0_CHK_PRE_PROC_CNTL 0x473c 7987 #define mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL 0x473c 7988 #define mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL 0x993c 7989 #define mmDPGV1_CHK_PRE_PROC_CNTL 0x4749 7990 #define mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL 0x4749 7991 #define mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL 0x9949 7992 #define mmDPGV_TEST_DEBUG_INDEX 0x474e 7993 #define mmDMIFV_PG0_DPGV_TEST_DEBUG_INDEX 0x474e 7994 #define mmDMIFV_PG1_DPGV_TEST_DEBUG_INDEX 0x994e 7995 #define mmDPGV_TEST_DEBUG_DATA 0x474f 7996 #define mmDMIFV_PG0_DPGV_TEST_DEBUG_DATA 0x474f 7997 #define mmDMIFV_PG1_DPGV_TEST_DEBUG_DATA 0x994f 7998 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 7999 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 8000 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00 8001 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02 8002 #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04 8003 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 8004 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 8005 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 8006 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 8007 #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 8008 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 8009 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 8010 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 8011 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 8012 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 8013 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 8014 #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 8015 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828 8016 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829 8017 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a 8018 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b 8019 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c 8020 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d 8021 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e 8022 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f 8023 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830 8024 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831 8025 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832 8026 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833 8027 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834 8028 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835 8029 #define mmAZALIA_F0_CODEC_DEBUG 0x1836 8030 #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837 8031 #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838 8032 #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839 8033 #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a 8034 #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b 8035 #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c 8036 #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d 8037 #define mmGLOBAL_CAPABILITIES 0x0 8038 #define mmMINOR_VERSION 0x0 8039 #define mmMAJOR_VERSION 0x0 8040 #define mmOUTPUT_PAYLOAD_CAPABILITY 0x1 8041 #define mmINPUT_PAYLOAD_CAPABILITY 0x1 8042 #define mmGLOBAL_CONTROL 0x2 8043 #define mmWAKE_ENABLE 0x3 8044 #define mmSTATE_CHANGE_STATUS 0x3 8045 #define mmGLOBAL_STATUS 0x4 8046 #define mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6 8047 #define mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6 8048 #define mmINTERRUPT_CONTROL 0x8 8049 #define mmINTERRUPT_STATUS 0x9 8050 #define mmWALL_CLOCK_COUNTER 0xc 8051 #define mmSTREAM_SYNCHRONIZATION 0xe 8052 #define mmCORB_LOWER_BASE_ADDRESS 0x10 8053 #define mmCORB_UPPER_BASE_ADDRESS 0x11 8054 #define mmCORB_WRITE_POINTER 0x12 8055 #define mmCORB_READ_POINTER 0x12 8056 #define mmCORB_CONTROL 0x13 8057 #define mmCORB_STATUS 0x13 8058 #define mmCORB_SIZE 0x13 8059 #define mmRIRB_LOWER_BASE_ADDRESS 0x14 8060 #define mmRIRB_UPPER_BASE_ADDRESS 0x15 8061 #define mmRIRB_WRITE_POINTER 0x16 8062 #define mmRESPONSE_INTERRUPT_COUNT 0x16 8063 #define mmRIRB_CONTROL 0x17 8064 #define mmRIRB_STATUS 0x17 8065 #define mmRIRB_SIZE 0x17 8066 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18 8067 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 8068 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 8069 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19 8070 #define mmIMMEDIATE_COMMAND_STATUS 0x1a 8071 #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c 8072 #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d 8073 #define mmWALL_CLOCK_COUNTER_ALIAS 0x80c 8074 #define mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20 8075 #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21 8076 #define mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22 8077 #define mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23 8078 #define mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24 8079 #define mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24 8080 #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26 8081 #define mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27 8082 #define mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821 8083 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18 8084 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18 8085 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 8086 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 8087 #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 8088 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 8089 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 8090 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 8091 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 8092 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 8093 #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 8094 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 8095 #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 8096 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 8097 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 8098 #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 8099 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 8100 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 8101 #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 8102 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 8103 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 8104 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 8105 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 8106 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 8107 #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 8108 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 8109 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 8110 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 8111 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 8112 #define ixAUDIO_DESCRIPTOR0 0x1 8113 #define ixAUDIO_DESCRIPTOR1 0x2 8114 #define ixAUDIO_DESCRIPTOR2 0x3 8115 #define ixAUDIO_DESCRIPTOR3 0x4 8116 #define ixAUDIO_DESCRIPTOR4 0x5 8117 #define ixAUDIO_DESCRIPTOR5 0x6 8118 #define ixAUDIO_DESCRIPTOR6 0x7 8119 #define ixAUDIO_DESCRIPTOR7 0x8 8120 #define ixAUDIO_DESCRIPTOR8 0x9 8121 #define ixAUDIO_DESCRIPTOR9 0xa 8122 #define ixAUDIO_DESCRIPTOR10 0xb 8123 #define ixAUDIO_DESCRIPTOR11 0xc 8124 #define ixAUDIO_DESCRIPTOR12 0xd 8125 #define ixAUDIO_DESCRIPTOR13 0xe 8126 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 8127 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 8128 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 8129 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 8130 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 8131 #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 8132 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 8133 #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 8134 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0 8135 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1 8136 #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2 8137 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3 8138 #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4 8139 #define ixSINK_DESCRIPTION0 0x5 8140 #define ixSINK_DESCRIPTION1 0x6 8141 #define ixSINK_DESCRIPTION2 0x7 8142 #define ixSINK_DESCRIPTION3 0x8 8143 #define ixSINK_DESCRIPTION4 0x9 8144 #define ixSINK_DESCRIPTION5 0xa 8145 #define ixSINK_DESCRIPTION6 0xb 8146 #define ixSINK_DESCRIPTION7 0xc 8147 #define ixSINK_DESCRIPTION8 0xd 8148 #define ixSINK_DESCRIPTION9 0xe 8149 #define ixSINK_DESCRIPTION10 0xf 8150 #define ixSINK_DESCRIPTION11 0x10 8151 #define ixSINK_DESCRIPTION12 0x11 8152 #define ixSINK_DESCRIPTION13 0x12 8153 #define ixSINK_DESCRIPTION14 0x13 8154 #define ixSINK_DESCRIPTION15 0x14 8155 #define ixSINK_DESCRIPTION16 0x15 8156 #define ixSINK_DESCRIPTION17 0x16 8157 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 8158 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 8159 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 8160 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 8161 #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 8162 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 8163 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 8164 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 8165 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 8166 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 8167 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 8168 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 8169 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 8170 #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 8171 #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 8172 #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 8173 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 8174 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 8175 #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 8176 #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 8177 #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 8178 #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d 8179 #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 8180 #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4 8181 #define mmAZALIA_AUDIO_DTO 0x17e5 8182 #define mmAZALIA_AUDIO_DTO_CONTROL 0x17e6 8183 #define mmAZALIA_SCLK_CONTROL 0x17e7 8184 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8 8185 #define mmAZALIA_DATA_DMA_CONTROL 0x17e9 8186 #define mmAZALIA_BDL_DMA_CONTROL 0x17ea 8187 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb 8188 #define mmAZALIA_CORB_DMA_CONTROL 0x17ec 8189 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3 8190 #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4 8191 #define mmAZALIA_GLOBAL_CAPABILITIES 0x17f5 8192 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6 8193 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7 8194 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8 8195 #define mmAZALIA_CONTROLLER_DEBUG 0x17f9 8196 #define mmAZALIA_MEM_PWR_CTRL 0x1810 8197 #define mmAZALIA_MEM_PWR_STATUS 0x1811 8198 #define mmDCI_PG_DEBUG_CONFIG 0x1812 8199 #define mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb 8200 #define mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc 8201 #define mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd 8202 #define mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe 8203 #define mmAZALIA_INPUT_CRC0_RESULT 0x17ff 8204 #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0 8205 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 8206 #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x2 8207 #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x3 8208 #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x4 8209 #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x5 8210 #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x6 8211 #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x7 8212 #define mmAZALIA_INPUT_CRC1_CONTROL0 0x1800 8213 #define mmAZALIA_INPUT_CRC1_CONTROL1 0x1801 8214 #define mmAZALIA_INPUT_CRC1_CONTROL2 0x1802 8215 #define mmAZALIA_INPUT_CRC1_CONTROL3 0x1803 8216 #define mmAZALIA_INPUT_CRC1_RESULT 0x1804 8217 #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0 8218 #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x1 8219 #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x2 8220 #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x3 8221 #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x4 8222 #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x5 8223 #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x6 8224 #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x7 8225 #define mmAZALIA_CRC0_CONTROL0 0x1805 8226 #define mmAZALIA_CRC0_CONTROL1 0x1806 8227 #define mmAZALIA_CRC0_CONTROL2 0x1807 8228 #define mmAZALIA_CRC0_CONTROL3 0x1808 8229 #define mmAZALIA_CRC0_RESULT 0x1809 8230 #define ixAZALIA_CRC0_CHANNEL0 0x0 8231 #define ixAZALIA_CRC0_CHANNEL1 0x1 8232 #define ixAZALIA_CRC0_CHANNEL2 0x2 8233 #define ixAZALIA_CRC0_CHANNEL3 0x3 8234 #define ixAZALIA_CRC0_CHANNEL4 0x4 8235 #define ixAZALIA_CRC0_CHANNEL5 0x5 8236 #define ixAZALIA_CRC0_CHANNEL6 0x6 8237 #define ixAZALIA_CRC0_CHANNEL7 0x7 8238 #define mmAZALIA_CRC1_CONTROL0 0x180a 8239 #define mmAZALIA_CRC1_CONTROL1 0x180b 8240 #define mmAZALIA_CRC1_CONTROL2 0x180c 8241 #define mmAZALIA_CRC1_CONTROL3 0x180d 8242 #define mmAZALIA_CRC1_RESULT 0x180e 8243 #define ixAZALIA_CRC1_CHANNEL0 0x0 8244 #define ixAZALIA_CRC1_CHANNEL1 0x1 8245 #define ixAZALIA_CRC1_CHANNEL2 0x2 8246 #define ixAZALIA_CRC1_CHANNEL3 0x3 8247 #define ixAZALIA_CRC1_CHANNEL4 0x4 8248 #define ixAZALIA_CRC1_CHANNEL5 0x5 8249 #define ixAZALIA_CRC1_CHANNEL6 0x6 8250 #define ixAZALIA_CRC1_CHANNEL7 0x7 8251 #define mmAZ_TEST_DEBUG_INDEX 0x181f 8252 #define mmAZ_TEST_DEBUG_DATA 0x1820 8253 #define mmAZALIA_STREAM_INDEX 0x1780 8254 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780 8255 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782 8256 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784 8257 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786 8258 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788 8259 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a 8260 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c 8261 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e 8262 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0 8263 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2 8264 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4 8265 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6 8266 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8 8267 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca 8268 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc 8269 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce 8270 #define mmAZALIA_STREAM_DATA 0x1781 8271 #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781 8272 #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783 8273 #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785 8274 #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787 8275 #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789 8276 #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b 8277 #define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d 8278 #define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f 8279 #define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1 8280 #define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3 8281 #define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5 8282 #define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7 8283 #define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9 8284 #define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb 8285 #define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd 8286 #define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf 8287 #define ixAZALIA_FIFO_SIZE_CONTROL 0x0 8288 #define ixAZALIA_LATENCY_COUNTER_CONTROL 0x1 8289 #define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2 8290 #define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3 8291 #define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4 8292 #define ixAZALIA_STREAM_DEBUG 0x5 8293 #define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 8294 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8 8295 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac 8296 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0 8297 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4 8298 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8 8299 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc 8300 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0 8301 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4 8302 #define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 8303 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9 8304 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad 8305 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1 8306 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5 8307 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9 8308 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd 8309 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1 8310 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5 8311 #define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0 8312 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 8313 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 8314 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 8315 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 8316 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 8317 #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 8318 #define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7 8319 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8 8320 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9 8321 #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa 8322 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc 8323 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd 8324 #define ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe 8325 #define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 8326 #define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21 8327 #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 8328 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23 8329 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24 8330 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 8331 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 8332 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 8333 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a 8334 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b 8335 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c 8336 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d 8337 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e 8338 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f 8339 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 8340 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 8341 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 8342 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 8343 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 8344 #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 8345 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 8346 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57 8347 #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58 8348 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 8349 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 8350 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a 8351 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b 8352 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c 8353 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d 8354 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e 8355 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f 8356 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 8357 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 8358 #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 8359 #define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 8360 #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 8361 #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 8362 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59 8363 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a 8364 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b 8365 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c 8366 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d 8367 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e 8368 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f 8369 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60 8370 #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61 8371 #define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62 8372 #define ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63 8373 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 8374 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65 8375 #define ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 8376 #define ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67 8377 #define ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68 8378 #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69 8379 #define ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a 8380 #define ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b 8381 #define ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c 8382 #define ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d 8383 #define ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e 8384 #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 8385 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4 8386 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8 8387 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc 8388 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0 8389 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4 8390 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8 8391 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec 8392 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0 8393 #define mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 8394 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5 8395 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9 8396 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd 8397 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1 8398 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5 8399 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9 8400 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed 8401 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1 8402 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0 8403 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1 8404 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2 8405 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3 8406 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4 8407 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5 8408 #define ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6 8409 #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20 8410 #define ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21 8411 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22 8412 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23 8413 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24 8414 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36 8415 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37 8416 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38 8417 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53 8418 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 8419 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55 8420 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 8421 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67 8422 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68 8423 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64 8424 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65 8425 #define ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66 8426 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18 8427 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18 8428 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 8429 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 8430 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 8431 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 8432 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 8433 #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 8434 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 8435 #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 8436 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 8437 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 8438 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 8439 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 8440 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 8441 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 8442 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 8443 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 8444 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 8445 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 8446 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 8447 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 8448 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 8449 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 8450 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 8451 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 8452 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 8453 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 8454 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 8455 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 8456 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 8457 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 8458 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 8459 #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 8460 #define mmBLND_CONTROL 0x1b6d 8461 #define mmBLND0_BLND_CONTROL 0x1b6d 8462 #define mmBLND1_BLND_CONTROL 0x1d6d 8463 #define mmBLND2_BLND_CONTROL 0x1f6d 8464 #define mmBLND3_BLND_CONTROL 0x416d 8465 #define mmBLND4_BLND_CONTROL 0x436d 8466 #define mmBLND5_BLND_CONTROL 0x456d 8467 #define mmBLND_SM_CONTROL2 0x1b6e 8468 #define mmBLND0_BLND_SM_CONTROL2 0x1b6e 8469 #define mmBLND1_BLND_SM_CONTROL2 0x1d6e 8470 #define mmBLND2_BLND_SM_CONTROL2 0x1f6e 8471 #define mmBLND3_BLND_SM_CONTROL2 0x416e 8472 #define mmBLND4_BLND_SM_CONTROL2 0x436e 8473 #define mmBLND5_BLND_SM_CONTROL2 0x456e 8474 #define mmBLND_CONTROL2 0x1b6f 8475 #define mmBLND0_BLND_CONTROL2 0x1b6f 8476 #define mmBLND1_BLND_CONTROL2 0x1d6f 8477 #define mmBLND2_BLND_CONTROL2 0x1f6f 8478 #define mmBLND3_BLND_CONTROL2 0x416f 8479 #define mmBLND4_BLND_CONTROL2 0x436f 8480 #define mmBLND5_BLND_CONTROL2 0x456f 8481 #define mmBLND_UPDATE 0x1b70 8482 #define mmBLND0_BLND_UPDATE 0x1b70 8483 #define mmBLND1_BLND_UPDATE 0x1d70 8484 #define mmBLND2_BLND_UPDATE 0x1f70 8485 #define mmBLND3_BLND_UPDATE 0x4170 8486 #define mmBLND4_BLND_UPDATE 0x4370 8487 #define mmBLND5_BLND_UPDATE 0x4570 8488 #define mmBLND_UNDERFLOW_INTERRUPT 0x1b71 8489 #define mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71 8490 #define mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71 8491 #define mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71 8492 #define mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171 8493 #define mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371 8494 #define mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571 8495 #define mmBLND_V_UPDATE_LOCK 0x1b73 8496 #define mmBLND0_BLND_V_UPDATE_LOCK 0x1b73 8497 #define mmBLND1_BLND_V_UPDATE_LOCK 0x1d73 8498 #define mmBLND2_BLND_V_UPDATE_LOCK 0x1f73 8499 #define mmBLND3_BLND_V_UPDATE_LOCK 0x4173 8500 #define mmBLND4_BLND_V_UPDATE_LOCK 0x4373 8501 #define mmBLND5_BLND_V_UPDATE_LOCK 0x4573 8502 #define mmBLND_REG_UPDATE_STATUS 0x1b77 8503 #define mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77 8504 #define mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77 8505 #define mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77 8506 #define mmBLND3_BLND_REG_UPDATE_STATUS 0x4177 8507 #define mmBLND4_BLND_REG_UPDATE_STATUS 0x4377 8508 #define mmBLND5_BLND_REG_UPDATE_STATUS 0x4577 8509 #define mmBLND_DEBUG 0x1b74 8510 #define mmBLND0_BLND_DEBUG 0x1b74 8511 #define mmBLND1_BLND_DEBUG 0x1d74 8512 #define mmBLND2_BLND_DEBUG 0x1f74 8513 #define mmBLND3_BLND_DEBUG 0x4174 8514 #define mmBLND4_BLND_DEBUG 0x4374 8515 #define mmBLND5_BLND_DEBUG 0x4574 8516 #define mmBLND_TEST_DEBUG_INDEX 0x1b75 8517 #define mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75 8518 #define mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75 8519 #define mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75 8520 #define mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175 8521 #define mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375 8522 #define mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575 8523 #define mmBLND_TEST_DEBUG_DATA 0x1b76 8524 #define mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76 8525 #define mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76 8526 #define mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76 8527 #define mmBLND3_BLND_TEST_DEBUG_DATA 0x4176 8528 #define mmBLND4_BLND_TEST_DEBUG_DATA 0x4376 8529 #define mmBLND5_BLND_TEST_DEBUG_DATA 0x4576 8530 #define mmWB_ENABLE 0x5e18 8531 #define mmWB_EC_CONFIG 0x5e19 8532 #define mmCNV_MODE 0x5e1a 8533 #define mmCNV_WINDOW_START 0x5e1b 8534 #define mmCNV_WINDOW_SIZE 0x5e1c 8535 #define mmCNV_UPDATE 0x5e1d 8536 #define mmCNV_SOURCE_SIZE 0x5e1e 8537 #define mmCNV_CSC_CONTROL 0x5e1f 8538 #define mmCNV_CSC_C11_C12 0x5e20 8539 #define mmCNV_CSC_C13_C14 0x5e21 8540 #define mmCNV_CSC_C21_C22 0x5e22 8541 #define mmCNV_CSC_C23_C24 0x5e23 8542 #define mmCNV_CSC_C31_C32 0x5e24 8543 #define mmCNV_CSC_C33_C34 0x5e25 8544 #define mmCNV_CSC_ROUND_OFFSET_R 0x5e26 8545 #define mmCNV_CSC_ROUND_OFFSET_G 0x5e27 8546 #define mmCNV_CSC_ROUND_OFFSET_B 0x5e28 8547 #define mmCNV_CSC_CLAMP_R 0x5e29 8548 #define mmCNV_CSC_CLAMP_G 0x5e2a 8549 #define mmCNV_CSC_CLAMP_B 0x5e2b 8550 #define mmCNV_TEST_CNTL 0x5e2c 8551 #define mmCNV_TEST_CRC_RED 0x5e2d 8552 #define mmCNV_TEST_CRC_GREEN 0x5e2e 8553 #define mmCNV_TEST_CRC_BLUE 0x5e2f 8554 #define mmWB_DEBUG_CTRL 0x5e30 8555 #define mmWB_DBG_MODE 0x5e31 8556 #define mmWB_HW_DEBUG 0x5e32 8557 #define mmCNV_INPUT_SELECT 0x5e33 8558 #define mmWB_SOFT_RESET 0x5e36 8559 #define mmWB_WARM_UP_MODE_CTL1 0x5e37 8560 #define mmWB_WARM_UP_MODE_CTL2 0x5e38 8561 #define mmCNV_TEST_DEBUG_INDEX 0x5e34 8562 #define mmCNV_TEST_DEBUG_DATA 0x5e35 8563 #define mmDCFE_CLOCK_CONTROL 0x1b00 8564 #define mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00 8565 #define mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00 8566 #define mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00 8567 #define mmDCFE3_DCFE_CLOCK_CONTROL 0x4100 8568 #define mmDCFE4_DCFE_CLOCK_CONTROL 0x4300 8569 #define mmDCFE5_DCFE_CLOCK_CONTROL 0x4500 8570 #define mmDCFE_SOFT_RESET 0x1b01 8571 #define mmDCFE0_DCFE_SOFT_RESET 0x1b01 8572 #define mmDCFE1_DCFE_SOFT_RESET 0x1d01 8573 #define mmDCFE2_DCFE_SOFT_RESET 0x1f01 8574 #define mmDCFE3_DCFE_SOFT_RESET 0x4101 8575 #define mmDCFE4_DCFE_SOFT_RESET 0x4301 8576 #define mmDCFE5_DCFE_SOFT_RESET 0x4501 8577 #define mmDCFE_DBG_CONFIG 0x1b02 8578 #define mmDCFE0_DCFE_DBG_CONFIG 0x1b02 8579 #define mmDCFE1_DCFE_DBG_CONFIG 0x1d02 8580 #define mmDCFE2_DCFE_DBG_CONFIG 0x1f02 8581 #define mmDCFE3_DCFE_DBG_CONFIG 0x4102 8582 #define mmDCFE4_DCFE_DBG_CONFIG 0x4302 8583 #define mmDCFE5_DCFE_DBG_CONFIG 0x4502 8584 #define mmDCFE_MEM_PWR_CTRL 0x1b03 8585 #define mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03 8586 #define mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03 8587 #define mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03 8588 #define mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103 8589 #define mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303 8590 #define mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503 8591 #define mmDCFE_MEM_PWR_CTRL2 0x1b04 8592 #define mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04 8593 #define mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04 8594 #define mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04 8595 #define mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104 8596 #define mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304 8597 #define mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504 8598 #define mmDCFE_MEM_PWR_STATUS 0x1b05 8599 #define mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05 8600 #define mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05 8601 #define mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05 8602 #define mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105 8603 #define mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305 8604 #define mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505 8605 #define mmDCFE_MISC 0x1b06 8606 #define mmDCFE0_DCFE_MISC 0x1b06 8607 #define mmDCFE1_DCFE_MISC 0x1d06 8608 #define mmDCFE2_DCFE_MISC 0x1f06 8609 #define mmDCFE3_DCFE_MISC 0x4106 8610 #define mmDCFE4_DCFE_MISC 0x4306 8611 #define mmDCFE5_DCFE_MISC 0x4506 8612 #define mmDCFE_FLUSH 0x1b07 8613 #define mmDCFE0_DCFE_FLUSH 0x1b07 8614 #define mmDCFE1_DCFE_FLUSH 0x1d07 8615 #define mmDCFE2_DCFE_FLUSH 0x1f07 8616 #define mmDCFE3_DCFE_FLUSH 0x4107 8617 #define mmDCFE4_DCFE_FLUSH 0x4307 8618 #define mmDCFE5_DCFE_FLUSH 0x4507 8619 #define mmDCFEV_CLOCK_CONTROL 0x46f4 8620 #define mmDCFEV0_DCFEV_CLOCK_CONTROL 0x46f4 8621 #define mmDCFEV1_DCFEV_CLOCK_CONTROL 0x98f4 8622 #define mmDCFEV_SOFT_RESET 0x46f5 8623 #define mmDCFEV0_DCFEV_SOFT_RESET 0x46f5 8624 #define mmDCFEV1_DCFEV_SOFT_RESET 0x98f5 8625 #define mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6 8626 #define mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL 0x46f6 8627 #define mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL 0x98f6 8628 #define mmDCFEV_DBG_CONFIG 0x46f7 8629 #define mmDCFEV0_DCFEV_DBG_CONFIG 0x46f7 8630 #define mmDCFEV1_DCFEV_DBG_CONFIG 0x98f7 8631 #define mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 8632 #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL 0x46f8 8633 #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL 0x98f8 8634 #define mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 8635 #define mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS 0x46f9 8636 #define mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS 0x98f9 8637 #define mmDCFEV_MEM_PWR_CTRL 0x46fa 8638 #define mmDCFEV0_DCFEV_MEM_PWR_CTRL 0x46fa 8639 #define mmDCFEV1_DCFEV_MEM_PWR_CTRL 0x98fa 8640 #define mmDCFEV_MEM_PWR_CTRL2 0x46fb 8641 #define mmDCFEV0_DCFEV_MEM_PWR_CTRL2 0x46fb 8642 #define mmDCFEV1_DCFEV_MEM_PWR_CTRL2 0x98fb 8643 #define mmDCFEV_MEM_PWR_STATUS 0x46fc 8644 #define mmDCFEV0_DCFEV_MEM_PWR_STATUS 0x46fc 8645 #define mmDCFEV1_DCFEV_MEM_PWR_STATUS 0x98fc 8646 #define mmDCFEV_L_FLUSH 0x46ff 8647 #define mmDCFEV0_DCFEV_L_FLUSH 0x46ff 8648 #define mmDCFEV1_DCFEV_L_FLUSH 0x98ff 8649 #define mmDCFEV_C_FLUSH 0x4700 8650 #define mmDCFEV0_DCFEV_C_FLUSH 0x4700 8651 #define mmDCFEV1_DCFEV_C_FLUSH 0x9900 8652 #define mmDCFEV_DMIFV_DEBUG 0x46fd 8653 #define mmDCFEV0_DCFEV_DMIFV_DEBUG 0x46fd 8654 #define mmDCFEV1_DCFEV_DMIFV_DEBUG 0x98fd 8655 #define mmDCFEV_MISC 0x46fe 8656 #define mmDCFEV0_DCFEV_MISC 0x46fe 8657 #define mmDCFEV1_DCFEV_MISC 0x98fe 8658 #define mmDC_HPD_INT_STATUS 0x1898 8659 #define mmHPD0_DC_HPD_INT_STATUS 0x1898 8660 #define mmHPD1_DC_HPD_INT_STATUS 0x18a0 8661 #define mmHPD2_DC_HPD_INT_STATUS 0x18a8 8662 #define mmHPD3_DC_HPD_INT_STATUS 0x18b0 8663 #define mmHPD4_DC_HPD_INT_STATUS 0x18b8 8664 #define mmHPD5_DC_HPD_INT_STATUS 0x18c0 8665 #define mmDC_HPD_INT_CONTROL 0x1899 8666 #define mmHPD0_DC_HPD_INT_CONTROL 0x1899 8667 #define mmHPD1_DC_HPD_INT_CONTROL 0x18a1 8668 #define mmHPD2_DC_HPD_INT_CONTROL 0x18a9 8669 #define mmHPD3_DC_HPD_INT_CONTROL 0x18b1 8670 #define mmHPD4_DC_HPD_INT_CONTROL 0x18b9 8671 #define mmHPD5_DC_HPD_INT_CONTROL 0x18c1 8672 #define mmDC_HPD_CONTROL 0x189a 8673 #define mmHPD0_DC_HPD_CONTROL 0x189a 8674 #define mmHPD1_DC_HPD_CONTROL 0x18a2 8675 #define mmHPD2_DC_HPD_CONTROL 0x18aa 8676 #define mmHPD3_DC_HPD_CONTROL 0x18b2 8677 #define mmHPD4_DC_HPD_CONTROL 0x18ba 8678 #define mmHPD5_DC_HPD_CONTROL 0x18c2 8679 #define mmDC_HPD_FAST_TRAIN_CNTL 0x189b 8680 #define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b 8681 #define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3 8682 #define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab 8683 #define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3 8684 #define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb 8685 #define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3 8686 #define mmDC_HPD_TOGGLE_FILT_CNTL 0x189c 8687 #define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c 8688 #define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4 8689 #define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac 8690 #define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4 8691 #define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc 8692 #define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4 8693 #define mmDCO_SCRATCH0 0x184e 8694 #define mmDCO_SCRATCH1 0x184f 8695 #define mmDCO_SCRATCH2 0x1850 8696 #define mmDCO_SCRATCH3 0x1851 8697 #define mmDCO_SCRATCH4 0x1852 8698 #define mmDCO_SCRATCH5 0x1853 8699 #define mmDCO_SCRATCH6 0x1854 8700 #define mmDCO_SCRATCH7 0x1855 8701 #define mmDCE_VCE_CONTROL 0x1856 8702 #define mmDISP_INTERRUPT_STATUS 0x1857 8703 #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858 8704 #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859 8705 #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a 8706 #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b 8707 #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c 8708 #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d 8709 #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e 8710 #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f 8711 #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860 8712 #define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875 8713 #define mmDCO_MEM_PWR_STATUS 0x1861 8714 #define mmDCO_MEM_PWR_STATUS1 0x1874 8715 #define mmDCO_MEM_PWR_CTRL 0x1862 8716 #define mmDCO_MEM_PWR_CTRL2 0x1863 8717 #define mmFMT_MEMORY0_CONTROL 0x1888 8718 #define mmFMT_MEMORY1_CONTROL 0x1889 8719 #define mmFMT_MEMORY2_CONTROL 0x188a 8720 #define mmFMT_MEMORY3_CONTROL 0x188b 8721 #define mmFMT_MEMORY4_CONTROL 0x188c 8722 #define mmFMT_MEMORY5_CONTROL 0x188d 8723 #define mmDCO_CLK_CNTL 0x1864 8724 #define mmDCO_CLK_CNTL2 0x1876 8725 #define mmDCO_CLK_CNTL3 0x1877 8726 #define mmDPDBG_CNTL 0x1866 8727 #define mmDPDBG_INTERRUPT 0x1867 8728 #define mmDCO_POWER_MANAGEMENT_CNTL 0x1868 8729 #define mmDCO_SOFT_RESET 0x1871 8730 #define mmDIG_SOFT_RESET 0x1872 8731 #define mmDIG_SOFT_RESET_2 0x186a 8732 #define mmDCO_STEREOSYNC_SEL 0x186e 8733 #define mmDCO_HDMI_RXSTATUS_TIMER_CONTROL 0x1883 8734 #define mmDCO_PSP_INTERRUPT_STATUS 0x1884 8735 #define mmDCO_PSP_INTERRUPT_CLEAR 0x1885 8736 #define mmDCO_GENERIC_INTERRUPT_MESSAGE 0x1886 8737 #define mmDCO_GENERIC_INTERRUPT_CLEAR 0x1887 8738 #define mmDCO_TEST_DEBUG_INDEX 0x186f 8739 #define mmDCO_TEST_DEBUG_DATA 0x1870 8740 #define mmDC_I2C_CONTROL 0x16d4 8741 #define mmDC_I2C_ARBITRATION 0x16d5 8742 #define mmDC_I2C_INTERRUPT_CONTROL 0x16d6 8743 #define mmDC_I2C_SW_STATUS 0x16d7 8744 #define mmDC_I2C_DDC1_HW_STATUS 0x16d8 8745 #define mmDC_I2C_DDC2_HW_STATUS 0x16d9 8746 #define mmDC_I2C_DDC3_HW_STATUS 0x16da 8747 #define mmDC_I2C_DDC4_HW_STATUS 0x16db 8748 #define mmDC_I2C_DDC5_HW_STATUS 0x16dc 8749 #define mmDC_I2C_DDC6_HW_STATUS 0x16dd 8750 #define mmDC_I2C_DDC1_SPEED 0x16de 8751 #define mmDC_I2C_DDC1_SETUP 0x16df 8752 #define mmDC_I2C_DDC2_SPEED 0x16e0 8753 #define mmDC_I2C_DDC2_SETUP 0x16e1 8754 #define mmDC_I2C_DDC3_SPEED 0x16e2 8755 #define mmDC_I2C_DDC3_SETUP 0x16e3 8756 #define mmDC_I2C_DDC4_SPEED 0x16e4 8757 #define mmDC_I2C_DDC4_SETUP 0x16e5 8758 #define mmDC_I2C_DDC5_SPEED 0x16e6 8759 #define mmDC_I2C_DDC5_SETUP 0x16e7 8760 #define mmDC_I2C_DDC6_SPEED 0x16e8 8761 #define mmDC_I2C_DDC6_SETUP 0x16e9 8762 #define mmDC_I2C_TRANSACTION0 0x16ea 8763 #define mmDC_I2C_TRANSACTION1 0x16eb 8764 #define mmDC_I2C_TRANSACTION2 0x16ec 8765 #define mmDC_I2C_TRANSACTION3 0x16ed 8766 #define mmDC_I2C_DATA 0x16ee 8767 #define mmDC_I2C_DDCVGA_HW_STATUS 0x16ef 8768 #define mmDC_I2C_DDCVGA_SPEED 0x16f0 8769 #define mmDC_I2C_DDCVGA_SETUP 0x16f1 8770 #define mmDC_I2C_EDID_DETECT_CTRL 0x16f2 8771 #define mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3 8772 #define mmGENERIC_I2C_CONTROL 0x16f4 8773 #define mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5 8774 #define mmGENERIC_I2C_STATUS 0x16f6 8775 #define mmGENERIC_I2C_SPEED 0x16f7 8776 #define mmGENERIC_I2C_SETUP 0x16f8 8777 #define mmGENERIC_I2C_TRANSACTION 0x16f9 8778 #define mmGENERIC_I2C_DATA 0x16fa 8779 #define mmGENERIC_I2C_PIN_SELECTION 0x16fb 8780 #define mmGENERIC_I2C_PIN_DEBUG 0x16fc 8781 #define mmBLNDV_CONTROL 0x476d 8782 #define mmBLNDV0_BLNDV_CONTROL 0x476d 8783 #define mmBLNDV1_BLNDV_CONTROL 0x996d 8784 #define mmBLNDV_SM_CONTROL2 0x476e 8785 #define mmBLNDV0_BLNDV_SM_CONTROL2 0x476e 8786 #define mmBLNDV1_BLNDV_SM_CONTROL2 0x996e 8787 #define mmBLNDV_CONTROL2 0x476f 8788 #define mmBLNDV0_BLNDV_CONTROL2 0x476f 8789 #define mmBLNDV1_BLNDV_CONTROL2 0x996f 8790 #define mmBLNDV_UPDATE 0x4770 8791 #define mmBLNDV0_BLNDV_UPDATE 0x4770 8792 #define mmBLNDV1_BLNDV_UPDATE 0x9970 8793 #define mmBLNDV_UNDERFLOW_INTERRUPT 0x4771 8794 #define mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT 0x4771 8795 #define mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT 0x9971 8796 #define mmBLNDV_V_UPDATE_LOCK 0x4773 8797 #define mmBLNDV0_BLNDV_V_UPDATE_LOCK 0x4773 8798 #define mmBLNDV1_BLNDV_V_UPDATE_LOCK 0x9973 8799 #define mmBLNDV_REG_UPDATE_STATUS 0x4777 8800 #define mmBLNDV0_BLNDV_REG_UPDATE_STATUS 0x4777 8801 #define mmBLNDV1_BLNDV_REG_UPDATE_STATUS 0x9977 8802 #define mmBLNDV_DEBUG 0x4774 8803 #define mmBLNDV0_BLNDV_DEBUG 0x4774 8804 #define mmBLNDV1_BLNDV_DEBUG 0x9974 8805 #define mmBLNDV_TEST_DEBUG_INDEX 0x4775 8806 #define mmBLNDV0_BLNDV_TEST_DEBUG_INDEX 0x4775 8807 #define mmBLNDV1_BLNDV_TEST_DEBUG_INDEX 0x9975 8808 #define mmBLNDV_TEST_DEBUG_DATA 0x4776 8809 #define mmBLNDV0_BLNDV_TEST_DEBUG_DATA 0x4776 8810 #define mmBLNDV1_BLNDV_TEST_DEBUG_DATA 0x9976 8811 #define mmCRTCV_H_TOTAL 0x4780 8812 #define mmCRTCV0_CRTCV_H_TOTAL 0x4780 8813 #define mmCRTCV1_CRTCV_H_TOTAL 0x9980 8814 #define mmCRTCV_H_BLANK_START_END 0x4781 8815 #define mmCRTCV0_CRTCV_H_BLANK_START_END 0x4781 8816 #define mmCRTCV1_CRTCV_H_BLANK_START_END 0x9981 8817 #define mmCRTCV_H_SYNC_A 0x4782 8818 #define mmCRTCV0_CRTCV_H_SYNC_A 0x4782 8819 #define mmCRTCV1_CRTCV_H_SYNC_A 0x9982 8820 #define mmCRTCV_V_TOTAL 0x4787 8821 #define mmCRTCV0_CRTCV_V_TOTAL 0x4787 8822 #define mmCRTCV1_CRTCV_V_TOTAL 0x9987 8823 #define mmCRTCV_V_BLANK_START_END 0x478d 8824 #define mmCRTCV0_CRTCV_V_BLANK_START_END 0x478d 8825 #define mmCRTCV1_CRTCV_V_BLANK_START_END 0x998d 8826 #define mmCRTCV_V_SYNC_A 0x478e 8827 #define mmCRTCV0_CRTCV_V_SYNC_A 0x478e 8828 #define mmCRTCV1_CRTCV_V_SYNC_A 0x998e 8829 #define mmCRTCV_CONTROL 0x479c 8830 #define mmCRTCV0_CRTCV_CONTROL 0x479c 8831 #define mmCRTCV1_CRTCV_CONTROL 0x999c 8832 #define mmCRTCV_START_LINE_CONTROL 0x47b3 8833 #define mmCRTCV0_CRTCV_START_LINE_CONTROL 0x47b3 8834 #define mmCRTCV1_CRTCV_START_LINE_CONTROL 0x99b3 8835 #define mmCRTCV_OVERSCAN_COLOR 0x47c8 8836 #define mmCRTCV0_CRTCV_OVERSCAN_COLOR 0x47c8 8837 #define mmCRTCV1_CRTCV_OVERSCAN_COLOR 0x99c8 8838 #define mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9 8839 #define mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT 0x47c9 8840 #define mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT 0x99c9 8841 #define mmCRTCV_BLACK_COLOR 0x47cc 8842 #define mmCRTCV0_CRTCV_BLACK_COLOR 0x47cc 8843 #define mmCRTCV1_CRTCV_BLACK_COLOR 0x99cc 8844 #define mmCRTCV_BLACK_COLOR_EXT 0x47cd 8845 #define mmCRTCV0_CRTCV_BLACK_COLOR_EXT 0x47cd 8846 #define mmCRTCV1_CRTCV_BLACK_COLOR_EXT 0x99cd 8847 #define mmCRTCV_CRC_CNTL 0x47d4 8848 #define mmCRTCV0_CRTCV_CRC_CNTL 0x47d4 8849 #define mmCRTCV1_CRTCV_CRC_CNTL 0x99d4 8850 #define mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 8851 #define mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5 8852 #define mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL 0x99d5 8853 #define mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 8854 #define mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6 8855 #define mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL 0x99d6 8856 #define mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 8857 #define mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7 8858 #define mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL 0x99d7 8859 #define mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 8860 #define mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8 8861 #define mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL 0x99d8 8862 #define mmCRTCV_CRC0_DATA_RG 0x47d9 8863 #define mmCRTCV0_CRTCV_CRC0_DATA_RG 0x47d9 8864 #define mmCRTCV1_CRTCV_CRC0_DATA_RG 0x99d9 8865 #define mmCRTCV_CRC0_DATA_B 0x47da 8866 #define mmCRTCV0_CRTCV_CRC0_DATA_B 0x47da 8867 #define mmCRTCV1_CRTCV_CRC0_DATA_B 0x99da 8868 #define mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db 8869 #define mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL 0x47db 8870 #define mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL 0x99db 8871 #define mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc 8872 #define mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc 8873 #define mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL 0x99dc 8874 #define mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd 8875 #define mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd 8876 #define mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL 0x99dd 8877 #define mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de 8878 #define mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de 8879 #define mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL 0x99de 8880 #define mmCRTCV_CRC1_DATA_RG 0x47df 8881 #define mmCRTCV0_CRTCV_CRC1_DATA_RG 0x47df 8882 #define mmCRTCV1_CRTCV_CRC1_DATA_RG 0x99df 8883 #define mmCRTCV_CRC1_DATA_B 0x47e0 8884 #define mmCRTCV0_CRTCV_CRC1_DATA_B 0x47e0 8885 #define mmCRTCV1_CRTCV_CRC1_DATA_B 0x99e0 8886 #define mmCRTCV_TEST_DEBUG_INDEX 0x47c6 8887 #define mmCRTCV0_CRTCV_TEST_DEBUG_INDEX 0x47c6 8888 #define mmCRTCV1_CRTCV_TEST_DEBUG_INDEX 0x99c6 8889 #define mmCRTCV_TEST_DEBUG_DATA 0x47c7 8890 #define mmCRTCV0_CRTCV_TEST_DEBUG_DATA 0x47c7 8891 #define mmCRTCV1_CRTCV_TEST_DEBUG_DATA 0x99c7 8892 #define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0 8893 #define mmXDMA_LOCAL_SURFACE_TILING1 0x3e1 8894 #define mmXDMA_LOCAL_SURFACE_TILING2 0x3e2 8895 #define mmXDMA_INTERRUPT 0x3e3 8896 #define mmXDMA_CLOCK_GATING_CNTL 0x3e4 8897 #define mmXDMA_MEM_POWER_CNTL 0x3e6 8898 #define mmXDMA_IF_BIF_STATUS 0x3e7 8899 #define mmXDMA_PERF_MEAS_STATUS 0x3e8 8900 #define mmXDMA_IF_STATUS 0x3e9 8901 #define mmXDMA_TEST_DEBUG_INDEX 0x3ea 8902 #define mmXDMA_TEST_DEBUG_DATA 0x3eb 8903 #define mmXDMA_RBBMIF_RDWR_CNTL 0x3f8 8904 #define mmXDMA_PG_CONTROL 0x3f9 8905 #define mmXDMA_PG_WDATA 0x3fa 8906 #define mmXDMA_PG_STATUS 0x3fb 8907 #define mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc 8908 #define mmXDMA_AON_TEST_DEBUG_DATA 0x3fd 8909 #define mmXDMA_MSTR_CNTL 0x3ec 8910 #define mmXDMA_MSTR_STATUS 0x3ed 8911 #define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee 8912 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef 8913 #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0 8914 #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1 8915 #define mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2 8916 #define mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3 8917 #define mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5 8918 #define mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6 8919 #define mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7 8920 #define mmXDMA_MSTR_PIPE_CNTL 0x400 8921 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400 8922 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410 8923 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420 8924 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430 8925 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440 8926 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450 8927 #define mmXDMA_MSTR_READ_COMMAND 0x401 8928 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401 8929 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411 8930 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421 8931 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431 8932 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441 8933 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451 8934 #define mmXDMA_MSTR_CHANNEL_DIM 0x402 8935 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402 8936 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412 8937 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422 8938 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432 8939 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442 8940 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452 8941 #define mmXDMA_MSTR_HEIGHT 0x403 8942 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403 8943 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413 8944 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423 8945 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433 8946 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443 8947 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453 8948 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404 8949 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404 8950 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414 8951 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424 8952 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434 8953 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444 8954 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454 8955 #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 8956 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405 8957 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415 8958 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425 8959 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435 8960 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445 8961 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455 8962 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 8963 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406 8964 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416 8965 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426 8966 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436 8967 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446 8968 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456 8969 #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 8970 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407 8971 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417 8972 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427 8973 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437 8974 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447 8975 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457 8976 #define mmXDMA_MSTR_CACHE_BASE_ADDR 0x408 8977 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408 8978 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418 8979 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428 8980 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438 8981 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448 8982 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458 8983 #define mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 8984 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409 8985 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419 8986 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429 8987 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439 8988 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449 8989 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459 8990 #define mmXDMA_MSTR_CACHE 0x40a 8991 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a 8992 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a 8993 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a 8994 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a 8995 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a 8996 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a 8997 #define mmXDMA_MSTR_CHANNEL_START 0x40b 8998 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b 8999 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b 9000 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b 9001 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b 9002 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b 9003 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b 9004 #define mmXDMA_MSTR_PERFMEAS_STATUS 0x40e 9005 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e 9006 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e 9007 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e 9008 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e 9009 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e 9010 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e 9011 #define mmXDMA_MSTR_PERFMEAS_CNTL 0x40f 9012 #define mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f 9013 #define mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f 9014 #define mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f 9015 #define mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f 9016 #define mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f 9017 #define mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f 9018 #define mmXDMA_SLV_CNTL 0x460 9019 #define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461 9020 #define mmXDMA_SLV_SLS_PITCH 0x462 9021 #define mmXDMA_SLV_READ_URGENT_CNTL 0x463 9022 #define mmXDMA_SLV_WRITE_URGENT_CNTL 0x464 9023 #define mmXDMA_SLV_WB_RATE_CNTL 0x465 9024 #define mmXDMA_SLV_READ_LATENCY_MINMAX 0x466 9025 #define mmXDMA_SLV_READ_LATENCY_AVE 0x467 9026 #define mmXDMA_SLV_PCIE_NACK_STATUS 0x468 9027 #define mmXDMA_SLV_MEM_NACK_STATUS 0x469 9028 #define mmXDMA_SLV_RDRET_BUF_STATUS 0x46a 9029 #define mmXDMA_SLV_READ_LATENCY_TIMER 0x46b 9030 #define mmXDMA_SLV_FLIP_PENDING 0x46c 9031 #define mmXDMA_SLV_CHANNEL_CNTL 0x470 9032 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470 9033 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478 9034 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480 9035 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488 9036 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490 9037 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498 9038 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471 9039 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471 9040 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479 9041 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481 9042 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489 9043 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491 9044 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499 9045 #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 9046 #define mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472 9047 #define mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a 9048 #define mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482 9049 #define mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a 9050 #define mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492 9051 #define mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a 9052 #define mmCMD_BUS_TX_CONTROL_LANE0 0x48e0 9053 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x48e0 9054 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x4980 9055 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x9a20 9056 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x9ac0 9057 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0 0x9b60 9058 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0 0x9c00 9059 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0 0x9ca0 9060 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE0 0x9d40 9061 #define mmCMD_BUS_TX_CONTROL_LANE1 0x48f0 9062 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x48f0 9063 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x4990 9064 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x9a30 9065 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x9ad0 9066 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1 0x9b70 9067 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1 0x9c10 9068 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1 0x9cb0 9069 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE1 0x9d50 9070 #define mmCMD_BUS_TX_CONTROL_LANE2 0x4900 9071 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x4900 9072 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x49a0 9073 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x9a40 9074 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x9ae0 9075 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2 0x9b80 9076 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2 0x9c20 9077 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2 0x9cc0 9078 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE2 0x9d60 9079 #define mmCMD_BUS_TX_CONTROL_LANE3 0x4910 9080 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x4910 9081 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x49b0 9082 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x9a50 9083 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x9af0 9084 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3 0x9b90 9085 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3 0x9c30 9086 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3 0x9cd0 9087 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE3 0x9d70 9088 #define mmMARGIN_DEEMPH_LANE0 0x48e1 9089 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x48e1 9090 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x4981 9091 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x9a21 9092 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x9ac1 9093 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0 0x9b61 9094 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0 0x9c01 9095 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0 0x9ca1 9096 #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE0 0x9d41 9097 #define mmMARGIN_DEEMPH_LANE1 0x48f1 9098 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x48f1 9099 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x4991 9100 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x9a31 9101 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x9ad1 9102 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1 0x9b71 9103 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1 0x9c11 9104 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1 0x9cb1 9105 #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE1 0x9d51 9106 #define mmMARGIN_DEEMPH_LANE2 0x4901 9107 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x4901 9108 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x49a1 9109 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x9a41 9110 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x9ae1 9111 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2 0x9b81 9112 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2 0x9c21 9113 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2 0x9cc1 9114 #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE2 0x9d61 9115 #define mmMARGIN_DEEMPH_LANE3 0x4911 9116 #define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x4911 9117 #define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x49b1 9118 #define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x9a51 9119 #define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x9af1 9120 #define mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3 0x9b91 9121 #define mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3 0x9c31 9122 #define mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3 0x9cd1 9123 #define mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE3 0x9d71 9124 #define mmCMD_BUS_GLOBAL_FOR_TX_LANE0 0x48e2 9125 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x48e2 9126 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x4982 9127 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9a22 9128 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9ac2 9129 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9b62 9130 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9c02 9131 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9ca2 9132 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x9d42 9133 #define mmCMD_BUS_GLOBAL_FOR_TX_LANE1 0x48f2 9134 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x48f2 9135 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x4992 9136 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9a32 9137 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9ad2 9138 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9b72 9139 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9c12 9140 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9cb2 9141 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x9d52 9142 #define mmCMD_BUS_GLOBAL_FOR_TX_LANE2 0x4902 9143 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x4902 9144 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x49a2 9145 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9a42 9146 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9ae2 9147 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9b82 9148 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9c22 9149 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9cc2 9150 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x9d62 9151 #define mmCMD_BUS_GLOBAL_FOR_TX_LANE3 0x4912 9152 #define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x4912 9153 #define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x49b2 9154 #define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9a52 9155 #define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9af2 9156 #define mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9b92 9157 #define mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9c32 9158 #define mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9cd2 9159 #define mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x9d72 9160 #define mmTX_DISP_RFU0_LANE0 0x48e3 9161 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x48e3 9162 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x4983 9163 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x9a23 9164 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x9ac3 9165 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0 0x9b63 9166 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0 0x9c03 9167 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0 0x9ca3 9168 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE0 0x9d43 9169 #define mmTX_DISP_RFU0_LANE1 0x48f3 9170 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x48f3 9171 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x4993 9172 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x9a33 9173 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x9ad3 9174 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1 0x9b73 9175 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1 0x9c13 9176 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1 0x9cb3 9177 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE1 0x9d53 9178 #define mmTX_DISP_RFU0_LANE2 0x4903 9179 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x4903 9180 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x49a3 9181 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x9a43 9182 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x9ae3 9183 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2 0x9b83 9184 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2 0x9c23 9185 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2 0x9cc3 9186 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE2 0x9d63 9187 #define mmTX_DISP_RFU0_LANE3 0x4913 9188 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x4913 9189 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x49b3 9190 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x9a53 9191 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x9af3 9192 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3 0x9b93 9193 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3 0x9c33 9194 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3 0x9cd3 9195 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE3 0x9d73 9196 #define mmTX_DISP_RFU1_LANE0 0x48e4 9197 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x48e4 9198 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x4984 9199 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x9a24 9200 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x9ac4 9201 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0 0x9b64 9202 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0 0x9c04 9203 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0 0x9ca4 9204 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE0 0x9d44 9205 #define mmTX_DISP_RFU1_LANE1 0x48f4 9206 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x48f4 9207 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x4994 9208 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x9a34 9209 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x9ad4 9210 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1 0x9b74 9211 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1 0x9c14 9212 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1 0x9cb4 9213 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE1 0x9d54 9214 #define mmTX_DISP_RFU1_LANE2 0x4904 9215 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x4904 9216 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x49a4 9217 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x9a44 9218 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x9ae4 9219 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2 0x9b84 9220 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2 0x9c24 9221 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2 0x9cc4 9222 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE2 0x9d64 9223 #define mmTX_DISP_RFU1_LANE3 0x4914 9224 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x4914 9225 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x49b4 9226 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x9a54 9227 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x9af4 9228 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3 0x9b94 9229 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3 0x9c34 9230 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3 0x9cd4 9231 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE3 0x9d74 9232 #define mmTX_DISP_RFU2_LANE0 0x48e5 9233 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x48e5 9234 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x4985 9235 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x9a25 9236 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x9ac5 9237 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0 0x9b65 9238 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0 0x9c05 9239 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0 0x9ca5 9240 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE0 0x9d45 9241 #define mmTX_DISP_RFU2_LANE1 0x48f5 9242 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x48f5 9243 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x4995 9244 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x9a35 9245 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x9ad5 9246 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1 0x9b75 9247 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1 0x9c15 9248 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1 0x9cb5 9249 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE1 0x9d55 9250 #define mmTX_DISP_RFU2_LANE2 0x4905 9251 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x4905 9252 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x49a5 9253 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x9a45 9254 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x9ae5 9255 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2 0x9b85 9256 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2 0x9c25 9257 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2 0x9cc5 9258 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE2 0x9d65 9259 #define mmTX_DISP_RFU2_LANE3 0x4915 9260 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x4915 9261 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x49b5 9262 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x9a55 9263 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x9af5 9264 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3 0x9b95 9265 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3 0x9c35 9266 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3 0x9cd5 9267 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE3 0x9d75 9268 #define mmTX_DISP_RFU3_LANE0 0x48e6 9269 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x48e6 9270 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x4986 9271 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x9a26 9272 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x9ac6 9273 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0 0x9b66 9274 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0 0x9c06 9275 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0 0x9ca6 9276 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE0 0x9d46 9277 #define mmTX_DISP_RFU3_LANE1 0x48f6 9278 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x48f6 9279 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x4996 9280 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x9a36 9281 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x9ad6 9282 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1 0x9b76 9283 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1 0x9c16 9284 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1 0x9cb6 9285 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE1 0x9d56 9286 #define mmTX_DISP_RFU3_LANE2 0x4906 9287 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x4906 9288 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x49a6 9289 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x9a46 9290 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x9ae6 9291 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2 0x9b86 9292 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2 0x9c26 9293 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2 0x9cc6 9294 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE2 0x9d66 9295 #define mmTX_DISP_RFU3_LANE3 0x4916 9296 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x4916 9297 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x49b6 9298 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x9a56 9299 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x9af6 9300 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3 0x9b96 9301 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3 0x9c36 9302 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3 0x9cd6 9303 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE3 0x9d76 9304 #define mmTX_DISP_RFU4_LANE0 0x48e7 9305 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x48e7 9306 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x4987 9307 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x9a27 9308 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x9ac7 9309 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0 0x9b67 9310 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0 0x9c07 9311 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0 0x9ca7 9312 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE0 0x9d47 9313 #define mmTX_DISP_RFU4_LANE1 0x48f7 9314 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x48f7 9315 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x4997 9316 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x9a37 9317 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x9ad7 9318 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1 0x9b77 9319 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1 0x9c17 9320 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1 0x9cb7 9321 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE1 0x9d57 9322 #define mmTX_DISP_RFU4_LANE2 0x4907 9323 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x4907 9324 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x49a7 9325 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x9a47 9326 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x9ae7 9327 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2 0x9b87 9328 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2 0x9c27 9329 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2 0x9cc7 9330 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE2 0x9d67 9331 #define mmTX_DISP_RFU4_LANE3 0x4917 9332 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x4917 9333 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x49b7 9334 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x9a57 9335 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x9af7 9336 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3 0x9b97 9337 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3 0x9c37 9338 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3 0x9cd7 9339 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE3 0x9d77 9340 #define mmTX_DISP_RFU5_LANE0 0x48e8 9341 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x48e8 9342 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x4988 9343 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x9a28 9344 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x9ac8 9345 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0 0x9b68 9346 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0 0x9c08 9347 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0 0x9ca8 9348 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE0 0x9d48 9349 #define mmTX_DISP_RFU5_LANE1 0x48f8 9350 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x48f8 9351 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x4998 9352 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x9a38 9353 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x9ad8 9354 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1 0x9b78 9355 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1 0x9c18 9356 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1 0x9cb8 9357 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE1 0x9d58 9358 #define mmTX_DISP_RFU5_LANE2 0x4908 9359 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x4908 9360 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x49a8 9361 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x9a48 9362 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x9ae8 9363 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2 0x9b88 9364 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2 0x9c28 9365 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2 0x9cc8 9366 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE2 0x9d68 9367 #define mmTX_DISP_RFU5_LANE3 0x4918 9368 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x4918 9369 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x49b8 9370 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x9a58 9371 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x9af8 9372 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3 0x9b98 9373 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3 0x9c38 9374 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3 0x9cd8 9375 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE3 0x9d78 9376 #define mmTX_DISP_RFU6_LANE0 0x48e9 9377 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x48e9 9378 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x4989 9379 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x9a29 9380 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x9ac9 9381 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0 0x9b69 9382 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0 0x9c09 9383 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0 0x9ca9 9384 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE0 0x9d49 9385 #define mmTX_DISP_RFU6_LANE1 0x48f9 9386 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x48f9 9387 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x4999 9388 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x9a39 9389 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x9ad9 9390 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1 0x9b79 9391 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1 0x9c19 9392 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1 0x9cb9 9393 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE1 0x9d59 9394 #define mmTX_DISP_RFU6_LANE2 0x4909 9395 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x4909 9396 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x49a9 9397 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x9a49 9398 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x9ae9 9399 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2 0x9b89 9400 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2 0x9c29 9401 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2 0x9cc9 9402 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE2 0x9d69 9403 #define mmTX_DISP_RFU6_LANE3 0x4919 9404 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x4919 9405 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x49b9 9406 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x9a59 9407 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x9af9 9408 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3 0x9b99 9409 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3 0x9c39 9410 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3 0x9cd9 9411 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE3 0x9d79 9412 #define mmTX_DISP_RFU7_LANE0 0x48ea 9413 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x48ea 9414 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x498a 9415 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x9a2a 9416 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x9aca 9417 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0 0x9b6a 9418 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0 0x9c0a 9419 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0 0x9caa 9420 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE0 0x9d4a 9421 #define mmTX_DISP_RFU7_LANE1 0x48fa 9422 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x48fa 9423 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x499a 9424 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x9a3a 9425 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x9ada 9426 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1 0x9b7a 9427 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1 0x9c1a 9428 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1 0x9cba 9429 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE1 0x9d5a 9430 #define mmTX_DISP_RFU7_LANE2 0x490a 9431 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x490a 9432 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x49aa 9433 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x9a4a 9434 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x9aea 9435 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2 0x9b8a 9436 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2 0x9c2a 9437 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2 0x9cca 9438 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE2 0x9d6a 9439 #define mmTX_DISP_RFU7_LANE3 0x491a 9440 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x491a 9441 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x49ba 9442 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x9a5a 9443 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x9afa 9444 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3 0x9b9a 9445 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3 0x9c3a 9446 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3 0x9cda 9447 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE3 0x9d7a 9448 #define mmTX_DISP_RFU8_LANE0 0x48eb 9449 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x48eb 9450 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x498b 9451 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x9a2b 9452 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x9acb 9453 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0 0x9b6b 9454 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0 0x9c0b 9455 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0 0x9cab 9456 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE0 0x9d4b 9457 #define mmTX_DISP_RFU8_LANE1 0x48fb 9458 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x48fb 9459 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x499b 9460 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x9a3b 9461 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x9adb 9462 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1 0x9b7b 9463 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1 0x9c1b 9464 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1 0x9cbb 9465 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE1 0x9d5b 9466 #define mmTX_DISP_RFU8_LANE2 0x490b 9467 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x490b 9468 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x49ab 9469 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x9a4b 9470 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x9aeb 9471 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2 0x9b8b 9472 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2 0x9c2b 9473 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2 0x9ccb 9474 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE2 0x9d6b 9475 #define mmTX_DISP_RFU8_LANE3 0x491b 9476 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x491b 9477 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x49bb 9478 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x9a5b 9479 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x9afb 9480 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3 0x9b9b 9481 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3 0x9c3b 9482 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3 0x9cdb 9483 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE3 0x9d7b 9484 #define mmTX_DISP_RFU9_LANE0 0x48ec 9485 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x48ec 9486 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x498c 9487 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x9a2c 9488 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x9acc 9489 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0 0x9b6c 9490 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0 0x9c0c 9491 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0 0x9cac 9492 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE0 0x9d4c 9493 #define mmTX_DISP_RFU9_LANE1 0x48fc 9494 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x48fc 9495 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x499c 9496 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x9a3c 9497 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x9adc 9498 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1 0x9b7c 9499 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1 0x9c1c 9500 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1 0x9cbc 9501 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE1 0x9d5c 9502 #define mmTX_DISP_RFU9_LANE2 0x490c 9503 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x490c 9504 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x49ac 9505 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x9a4c 9506 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x9aec 9507 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2 0x9b8c 9508 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2 0x9c2c 9509 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2 0x9ccc 9510 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE2 0x9d6c 9511 #define mmTX_DISP_RFU9_LANE3 0x491c 9512 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x491c 9513 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x49bc 9514 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x9a5c 9515 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x9afc 9516 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3 0x9b9c 9517 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3 0x9c3c 9518 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3 0x9cdc 9519 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE3 0x9d7c 9520 #define mmTX_DISP_RFU10_LANE0 0x48ed 9521 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x48ed 9522 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x498d 9523 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x9a2d 9524 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x9acd 9525 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0 0x9b6d 9526 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0 0x9c0d 9527 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0 0x9cad 9528 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE0 0x9d4d 9529 #define mmTX_DISP_RFU10_LANE1 0x48fd 9530 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x48fd 9531 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x499d 9532 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x9a3d 9533 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x9add 9534 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1 0x9b7d 9535 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1 0x9c1d 9536 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1 0x9cbd 9537 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE1 0x9d5d 9538 #define mmTX_DISP_RFU10_LANE2 0x490d 9539 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x490d 9540 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x49ad 9541 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x9a4d 9542 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x9aed 9543 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2 0x9b8d 9544 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2 0x9c2d 9545 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2 0x9ccd 9546 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE2 0x9d6d 9547 #define mmTX_DISP_RFU10_LANE3 0x491d 9548 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x491d 9549 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x49bd 9550 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x9a5d 9551 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x9afd 9552 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3 0x9b9d 9553 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3 0x9c3d 9554 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3 0x9cdd 9555 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE3 0x9d7d 9556 #define mmTX_DISP_RFU11_LANE0 0x48ee 9557 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x48ee 9558 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x498e 9559 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x9a2e 9560 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x9ace 9561 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0 0x9b6e 9562 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0 0x9c0e 9563 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0 0x9cae 9564 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE0 0x9d4e 9565 #define mmTX_DISP_RFU11_LANE1 0x48fe 9566 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x48fe 9567 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x499e 9568 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x9a3e 9569 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x9ade 9570 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1 0x9b7e 9571 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1 0x9c1e 9572 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1 0x9cbe 9573 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE1 0x9d5e 9574 #define mmTX_DISP_RFU11_LANE2 0x490e 9575 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x490e 9576 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x49ae 9577 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x9a4e 9578 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x9aee 9579 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2 0x9b8e 9580 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2 0x9c2e 9581 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2 0x9cce 9582 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE2 0x9d6e 9583 #define mmTX_DISP_RFU11_LANE3 0x491e 9584 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x491e 9585 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x49be 9586 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x9a5e 9587 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x9afe 9588 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3 0x9b9e 9589 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3 0x9c3e 9590 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3 0x9cde 9591 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE3 0x9d7e 9592 #define mmTX_DISP_RFU12_LANE0 0x48ef 9593 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x48ef 9594 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x498f 9595 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x9a2f 9596 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x9acf 9597 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0 0x9b6f 9598 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0 0x9c0f 9599 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0 0x9caf 9600 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE0 0x9d4f 9601 #define mmTX_DISP_RFU12_LANE1 0x48ff 9602 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x48ff 9603 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x499f 9604 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x9a3f 9605 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x9adf 9606 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1 0x9b7f 9607 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1 0x9c1f 9608 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1 0x9cbf 9609 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE1 0x9d5f 9610 #define mmTX_DISP_RFU12_LANE2 0x490f 9611 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x490f 9612 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x49af 9613 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x9a4f 9614 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x9aef 9615 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2 0x9b8f 9616 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2 0x9c2f 9617 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2 0x9ccf 9618 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE2 0x9d6f 9619 #define mmTX_DISP_RFU12_LANE3 0x491f 9620 #define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x491f 9621 #define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x49bf 9622 #define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x9a5f 9623 #define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x9aff 9624 #define mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3 0x9b9f 9625 #define mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3 0x9c3f 9626 #define mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3 0x9cdf 9627 #define mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE3 0x9d7f 9628 #define mmCOMMON_MAR_DEEMPH_NOM 0x48c3 9629 #define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x48c3 9630 #define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x4963 9631 #define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x9a03 9632 #define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x9aa3 9633 #define mmDC_COMBOPHYCMREGS4_COMMON_MAR_DEEMPH_NOM 0x9b43 9634 #define mmDC_COMBOPHYCMREGS5_COMMON_MAR_DEEMPH_NOM 0x9be3 9635 #define mmDC_COMBOPHYCMREGS6_COMMON_MAR_DEEMPH_NOM 0x9c83 9636 #define mmDC_COMBOPHYCMREGS7_COMMON_MAR_DEEMPH_NOM 0x9d23 9637 #define mmCOMMON_LANE_PWRMGMT 0x48c4 9638 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x48c4 9639 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x4964 9640 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x9a04 9641 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x9aa4 9642 #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT 0x9b44 9643 #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT 0x9be4 9644 #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT 0x9c84 9645 #define mmDC_COMBOPHYCMREGS7_COMMON_LANE_PWRMGMT 0x9d24 9646 #define mmCOMMON_TXCNTRL 0x48c5 9647 #define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x48c5 9648 #define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x4965 9649 #define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x9a05 9650 #define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x9aa5 9651 #define mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL 0x9b45 9652 #define mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL 0x9be5 9653 #define mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL 0x9c85 9654 #define mmDC_COMBOPHYCMREGS7_COMMON_TXCNTRL 0x9d25 9655 #define mmCOMMON_TMDP 0x48c6 9656 #define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x48c6 9657 #define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x4966 9658 #define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x9a06 9659 #define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x9aa6 9660 #define mmDC_COMBOPHYCMREGS4_COMMON_TMDP 0x9b46 9661 #define mmDC_COMBOPHYCMREGS5_COMMON_TMDP 0x9be6 9662 #define mmDC_COMBOPHYCMREGS6_COMMON_TMDP 0x9c86 9663 #define mmDC_COMBOPHYCMREGS7_COMMON_TMDP 0x9d26 9664 #define mmCOMMON_LANE_RESETS 0x48c7 9665 #define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x48c7 9666 #define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x4967 9667 #define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x9a07 9668 #define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x9aa7 9669 #define mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS 0x9b47 9670 #define mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS 0x9be7 9671 #define mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS 0x9c87 9672 #define mmDC_COMBOPHYCMREGS7_COMMON_LANE_RESETS 0x9d27 9673 #define mmCOMMON_ZCALCODE_CTRL 0x48c8 9674 #define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x48c8 9675 #define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x4968 9676 #define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x9a08 9677 #define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x9aa8 9678 #define mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL 0x9b48 9679 #define mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL 0x9be8 9680 #define mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL 0x9c88 9681 #define mmDC_COMBOPHYCMREGS7_COMMON_ZCALCODE_CTRL 0x9d28 9682 #define mmCOMMON_DISP_RFU1 0x48c9 9683 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x48c9 9684 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x4969 9685 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x9a09 9686 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x9aa9 9687 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1 0x9b49 9688 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1 0x9be9 9689 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1 0x9c89 9690 #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU1 0x9d29 9691 #define mmCOMMON_DISP_RFU2 0x48ca 9692 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x48ca 9693 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x496a 9694 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x9a0a 9695 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x9aaa 9696 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2 0x9b4a 9697 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2 0x9bea 9698 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2 0x9c8a 9699 #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU2 0x9d2a 9700 #define mmCOMMON_DISP_RFU3 0x48cb 9701 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x48cb 9702 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x496b 9703 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x9a0b 9704 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x9aab 9705 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3 0x9b4b 9706 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3 0x9beb 9707 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3 0x9c8b 9708 #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU3 0x9d2b 9709 #define mmCOMMON_DISP_RFU4 0x48cc 9710 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x48cc 9711 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x496c 9712 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x9a0c 9713 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x9aac 9714 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4 0x9b4c 9715 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4 0x9bec 9716 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4 0x9c8c 9717 #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU4 0x9d2c 9718 #define mmCOMMON_DISP_RFU5 0x48cd 9719 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x48cd 9720 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x496d 9721 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x9a0d 9722 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x9aad 9723 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5 0x9b4d 9724 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5 0x9bed 9725 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5 0x9c8d 9726 #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU5 0x9d2d 9727 #define mmCOMMON_DISP_RFU6 0x48ce 9728 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x48ce 9729 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x496e 9730 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x9a0e 9731 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x9aae 9732 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6 0x9b4e 9733 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6 0x9bee 9734 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6 0x9c8e 9735 #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU6 0x9d2e 9736 #define mmCOMMON_DISP_RFU7 0x48cf 9737 #define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x48cf 9738 #define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x496f 9739 #define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x9a0f 9740 #define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x9aaf 9741 #define mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7 0x9b4f 9742 #define mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7 0x9bef 9743 #define mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7 0x9c8f 9744 #define mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU7 0x9d2f 9745 #define mmFREQ_CTRL0 0x4920 9746 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x4920 9747 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x49c0 9748 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x9a60 9749 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x9b00 9750 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0 0x9ba0 9751 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0 0x9c40 9752 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0 0x9ce0 9753 #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL0 0x9d80 9754 #define mmFREQ_CTRL1 0x4921 9755 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x4921 9756 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x49c1 9757 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x9a61 9758 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x9b01 9759 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1 0x9ba1 9760 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1 0x9c41 9761 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1 0x9ce1 9762 #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL1 0x9d81 9763 #define mmFREQ_CTRL2 0x4922 9764 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x4922 9765 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x49c2 9766 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x9a62 9767 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x9b02 9768 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2 0x9ba2 9769 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2 0x9c42 9770 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2 0x9ce2 9771 #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL2 0x9d82 9772 #define mmFREQ_CTRL3 0x4923 9773 #define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x4923 9774 #define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x49c3 9775 #define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x9a63 9776 #define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x9b03 9777 #define mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3 0x9ba3 9778 #define mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3 0x9c43 9779 #define mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3 0x9ce3 9780 #define mmDC_COMBOPHYPLLREGS7_FREQ_CTRL3 0x9d83 9781 #define mmBW_CTRL_COARSE 0x4924 9782 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x4924 9783 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x49c4 9784 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x9a64 9785 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x9b04 9786 #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE 0x9ba4 9787 #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE 0x9c44 9788 #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE 0x9ce4 9789 #define mmDC_COMBOPHYPLLREGS7_BW_CTRL_COARSE 0x9d84 9790 #define mmBW_CTRL_FINE 0x4925 9791 #define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x4925 9792 #define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x49c5 9793 #define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x9a65 9794 #define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x9b05 9795 #define mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE 0x9ba5 9796 #define mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE 0x9c45 9797 #define mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE 0x9ce5 9798 #define mmDC_COMBOPHYPLLREGS7_BW_CTRL_FINE 0x9d85 9799 #define mmCAL_CTRL 0x4926 9800 #define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x4926 9801 #define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x49c6 9802 #define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x9a66 9803 #define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x9b06 9804 #define mmDC_COMBOPHYPLLREGS4_CAL_CTRL 0x9ba6 9805 #define mmDC_COMBOPHYPLLREGS5_CAL_CTRL 0x9c46 9806 #define mmDC_COMBOPHYPLLREGS6_CAL_CTRL 0x9ce6 9807 #define mmDC_COMBOPHYPLLREGS7_CAL_CTRL 0x9d86 9808 #define mmLOOP_CTRL 0x4927 9809 #define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x4927 9810 #define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x49c7 9811 #define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x9a67 9812 #define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x9b07 9813 #define mmDC_COMBOPHYPLLREGS4_LOOP_CTRL 0x9ba7 9814 #define mmDC_COMBOPHYPLLREGS5_LOOP_CTRL 0x9c47 9815 #define mmDC_COMBOPHYPLLREGS6_LOOP_CTRL 0x9ce7 9816 #define mmDC_COMBOPHYPLLREGS7_LOOP_CTRL 0x9d87 9817 #define mmDEBUG0 0x4928 9818 #define mmDC_COMBOPHYPLLREGS0_DEBUG0 0x4928 9819 #define mmDC_COMBOPHYPLLREGS1_DEBUG0 0x49c8 9820 #define mmDC_COMBOPHYPLLREGS2_DEBUG0 0x9a68 9821 #define mmDC_COMBOPHYPLLREGS3_DEBUG0 0x9b08 9822 #define mmDC_COMBOPHYPLLREGS4_DEBUG0 0x9ba8 9823 #define mmDC_COMBOPHYPLLREGS5_DEBUG0 0x9c48 9824 #define mmDC_COMBOPHYPLLREGS6_DEBUG0 0x9ce8 9825 #define mmDC_COMBOPHYPLLREGS7_DEBUG0 0x9d88 9826 #define mmVREG_CFG 0x4929 9827 #define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x4929 9828 #define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x49c9 9829 #define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x9a69 9830 #define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x9b09 9831 #define mmDC_COMBOPHYPLLREGS4_VREG_CFG 0x9ba9 9832 #define mmDC_COMBOPHYPLLREGS5_VREG_CFG 0x9c49 9833 #define mmDC_COMBOPHYPLLREGS6_VREG_CFG 0x9ce9 9834 #define mmDC_COMBOPHYPLLREGS7_VREG_CFG 0x9d89 9835 #define mmOBSERVE0 0x492a 9836 #define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x492a 9837 #define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x49ca 9838 #define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x9a6a 9839 #define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x9b0a 9840 #define mmDC_COMBOPHYPLLREGS4_OBSERVE0 0x9baa 9841 #define mmDC_COMBOPHYPLLREGS5_OBSERVE0 0x9c4a 9842 #define mmDC_COMBOPHYPLLREGS6_OBSERVE0 0x9cea 9843 #define mmDC_COMBOPHYPLLREGS7_OBSERVE0 0x9d8a 9844 #define mmOBSERVE1 0x492b 9845 #define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x492b 9846 #define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x49cb 9847 #define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x9a6b 9848 #define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x9b0b 9849 #define mmDC_COMBOPHYPLLREGS4_OBSERVE1 0x9bab 9850 #define mmDC_COMBOPHYPLLREGS5_OBSERVE1 0x9c4b 9851 #define mmDC_COMBOPHYPLLREGS6_OBSERVE1 0x9ceb 9852 #define mmDC_COMBOPHYPLLREGS7_OBSERVE1 0x9d8b 9853 #define mmDFT_OUT 0x492c 9854 #define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x492c 9855 #define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x49cc 9856 #define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x9a6c 9857 #define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x9b0c 9858 #define mmDC_COMBOPHYPLLREGS4_DFT_OUT 0x9bac 9859 #define mmDC_COMBOPHYPLLREGS5_DFT_OUT 0x9c4c 9860 #define mmDC_COMBOPHYPLLREGS6_DFT_OUT 0x9cec 9861 #define mmDC_COMBOPHYPLLREGS7_DFT_OUT 0x9d8c 9862 #define mmPLL_WRAP_CNTRL1 0x495e 9863 #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0x495e 9864 #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0x49fe 9865 #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0x9a9e 9866 #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0x9b3e 9867 #define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL1 0x9bde 9868 #define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL1 0x9c7e 9869 #define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL1 0x9d1e 9870 #define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL1 0x9dbe 9871 #define mmPLL_WRAP_CNTRL 0x495f 9872 #define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0x495f 9873 #define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0x49ff 9874 #define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0x9a9f 9875 #define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0x9b3f 9876 #define mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL 0x9bdf 9877 #define mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL 0x9c7f 9878 #define mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL 0x9d1f 9879 #define mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL 0x9dbf 9880 #define mmPPLL_VREG_CFG 0x1700 9881 #define mmDC_DISPLAYPLLREGS0_PPLL_VREG_CFG 0x1700 9882 #define mmDC_DISPLAYPLLREGS1_PPLL_VREG_CFG 0x172a 9883 #define mmDC_DISPLAYPLLREGS2_PPLL_VREG_CFG 0x1754 9884 #define mmPPLL_MODE_CNTL 0x1701 9885 #define mmDC_DISPLAYPLLREGS0_PPLL_MODE_CNTL 0x1701 9886 #define mmDC_DISPLAYPLLREGS1_PPLL_MODE_CNTL 0x172b 9887 #define mmDC_DISPLAYPLLREGS2_PPLL_MODE_CNTL 0x1755 9888 #define mmPPLL_FREQ_CTRL0 0x1702 9889 #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL0 0x1702 9890 #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL0 0x172c 9891 #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL0 0x1756 9892 #define mmPPLL_FREQ_CTRL1 0x1703 9893 #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL1 0x1703 9894 #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL1 0x172d 9895 #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL1 0x1757 9896 #define mmPPLL_FREQ_CTRL2 0x1704 9897 #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL2 0x1704 9898 #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL2 0x172e 9899 #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL2 0x1758 9900 #define mmPPLL_FREQ_CTRL3 0x1705 9901 #define mmDC_DISPLAYPLLREGS0_PPLL_FREQ_CTRL3 0x1705 9902 #define mmDC_DISPLAYPLLREGS1_PPLL_FREQ_CTRL3 0x172f 9903 #define mmDC_DISPLAYPLLREGS2_PPLL_FREQ_CTRL3 0x1759 9904 #define mmPPLL_BW_CTRL_COARSE 0x1706 9905 #define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_COARSE 0x1706 9906 #define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_COARSE 0x1730 9907 #define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_COARSE 0x175a 9908 #define mmPPLL_BW_CTRL_FINE 0x1708 9909 #define mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_FINE 0x1708 9910 #define mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_FINE 0x1732 9911 #define mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_FINE 0x175c 9912 #define mmPPLL_CAL_CTRL 0x1709 9913 #define mmDC_DISPLAYPLLREGS0_PPLL_CAL_CTRL 0x1709 9914 #define mmDC_DISPLAYPLLREGS1_PPLL_CAL_CTRL 0x1733 9915 #define mmDC_DISPLAYPLLREGS2_PPLL_CAL_CTRL 0x175d 9916 #define mmPPLL_LOOP_CTRL 0x170a 9917 #define mmDC_DISPLAYPLLREGS0_PPLL_LOOP_CTRL 0x170a 9918 #define mmDC_DISPLAYPLLREGS1_PPLL_LOOP_CTRL 0x1734 9919 #define mmDC_DISPLAYPLLREGS2_PPLL_LOOP_CTRL 0x175e 9920 #define mmPPLL_REFCLK_CNTL 0x1718 9921 #define mmDC_DISPLAYPLLREGS0_PPLL_REFCLK_CNTL 0x1718 9922 #define mmDC_DISPLAYPLLREGS1_PPLL_REFCLK_CNTL 0x1742 9923 #define mmDC_DISPLAYPLLREGS2_PPLL_REFCLK_CNTL 0x176c 9924 #define mmPPLL_CLKOUT_CNTL 0x1719 9925 #define mmDC_DISPLAYPLLREGS0_PPLL_CLKOUT_CNTL 0x1719 9926 #define mmDC_DISPLAYPLLREGS1_PPLL_CLKOUT_CNTL 0x1743 9927 #define mmDC_DISPLAYPLLREGS2_PPLL_CLKOUT_CNTL 0x176d 9928 #define mmPPLL_DFT_CNTL 0x171a 9929 #define mmDC_DISPLAYPLLREGS0_PPLL_DFT_CNTL 0x171a 9930 #define mmDC_DISPLAYPLLREGS1_PPLL_DFT_CNTL 0x1744 9931 #define mmDC_DISPLAYPLLREGS2_PPLL_DFT_CNTL 0x176e 9932 #define mmPPLL_ANALOG_CNTL 0x171b 9933 #define mmDC_DISPLAYPLLREGS0_PPLL_ANALOG_CNTL 0x171b 9934 #define mmDC_DISPLAYPLLREGS1_PPLL_ANALOG_CNTL 0x1745 9935 #define mmDC_DISPLAYPLLREGS2_PPLL_ANALOG_CNTL 0x176f 9936 #define mmPPLL_POSTDIV 0x171c 9937 #define mmDC_DISPLAYPLLREGS0_PPLL_POSTDIV 0x171c 9938 #define mmDC_DISPLAYPLLREGS1_PPLL_POSTDIV 0x1746 9939 #define mmDC_DISPLAYPLLREGS2_PPLL_POSTDIV 0x1770 9940 #define mmPPLL_DEBUG0 0x1720 9941 #define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG0 0x1720 9942 #define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG0 0x174a 9943 #define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG0 0x1774 9944 #define mmPPLL_OBSERVE0 0x1721 9945 #define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0 0x1721 9946 #define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0 0x174b 9947 #define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0 0x1775 9948 #define mmPPLL_OBSERVE1 0x1722 9949 #define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE1 0x1722 9950 #define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE1 0x174c 9951 #define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE1 0x1776 9952 #define mmPPLL_UPDATE_CNTL 0x1724 9953 #define mmDC_DISPLAYPLLREGS0_PPLL_UPDATE_CNTL 0x1724 9954 #define mmDC_DISPLAYPLLREGS1_PPLL_UPDATE_CNTL 0x174e 9955 #define mmDC_DISPLAYPLLREGS2_PPLL_UPDATE_CNTL 0x1778 9956 #define mmPPLL_OBSERVE0_OUT 0x1725 9957 #define mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0_OUT 0x1725 9958 #define mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0_OUT 0x174f 9959 #define mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0_OUT 0x1779 9960 #define mmPPLL_STATUS_DEBUG1 0x1726 9961 #define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG1 0x1726 9962 #define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG1 0x1750 9963 #define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG1 0x177a 9964 #define mmPPLL_DEBUG_MUX_CNTL 0x1727 9965 #define mmDC_DISPLAYPLLREGS0_PPLL_DEBUG_MUX_CNTL 0x1727 9966 #define mmDC_DISPLAYPLLREGS1_PPLL_DEBUG_MUX_CNTL 0x1751 9967 #define mmDC_DISPLAYPLLREGS2_PPLL_DEBUG_MUX_CNTL 0x177b 9968 #define mmPPLL_DIV_UPDATE_DEBUG 0x1728 9969 #define mmDC_DISPLAYPLLREGS0_PPLL_DIV_UPDATE_DEBUG 0x1728 9970 #define mmDC_DISPLAYPLLREGS1_PPLL_DIV_UPDATE_DEBUG 0x1752 9971 #define mmDC_DISPLAYPLLREGS2_PPLL_DIV_UPDATE_DEBUG 0x177c 9972 #define mmPPLL_STATUS_DEBUG0 0x1729 9973 #define mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG0 0x1729 9974 #define mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG0 0x1753 9975 #define mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG0 0x177d 9976 #define mmCOMP_EN_CTL 0x9dc0 9977 #define mmDPCSTX_PHY_CNTL 0x48d0 9978 #define mmDPCSTX0_DPCSTX_PHY_CNTL 0x48d0 9979 #define mmDPCSTX1_DPCSTX_PHY_CNTL 0x4970 9980 #define mmDPCSTX2_DPCSTX_PHY_CNTL 0x9a10 9981 #define mmDPCSTX3_DPCSTX_PHY_CNTL 0x9ab0 9982 #define mmDPCSTX4_DPCSTX_PHY_CNTL 0x9b50 9983 #define mmDPCSTX5_DPCSTX_PHY_CNTL 0x9bf0 9984 #define mmDPCSTX6_DPCSTX_PHY_CNTL 0x9c90 9985 #define mmDPCSTX7_DPCSTX_PHY_CNTL 0x9d30 9986 #define mmDPCSTX_TX_CLOCK_CNTL 0x48d1 9987 #define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x48d1 9988 #define mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL 0x4971 9989 #define mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL 0x9a11 9990 #define mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL 0x9ab1 9991 #define mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL 0x9b51 9992 #define mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL 0x9bf1 9993 #define mmDPCSTX6_DPCSTX_TX_CLOCK_CNTL 0x9c91 9994 #define mmDPCSTX7_DPCSTX_TX_CLOCK_CNTL 0x9d31 9995 #define mmDPCSTX_TX_CNTL 0x48d3 9996 #define mmDPCSTX0_DPCSTX_TX_CNTL 0x48d3 9997 #define mmDPCSTX1_DPCSTX_TX_CNTL 0x4973 9998 #define mmDPCSTX2_DPCSTX_TX_CNTL 0x9a13 9999 #define mmDPCSTX3_DPCSTX_TX_CNTL 0x9ab3 10000 #define mmDPCSTX4_DPCSTX_TX_CNTL 0x9b53 10001 #define mmDPCSTX5_DPCSTX_TX_CNTL 0x9bf3 10002 #define mmDPCSTX6_DPCSTX_TX_CNTL 0x9c93 10003 #define mmDPCSTX7_DPCSTX_TX_CNTL 0x9d33 10004 #define mmDPCSTX_CBUS_CNTL 0x48d5 10005 #define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x48d5 10006 #define mmDPCSTX1_DPCSTX_CBUS_CNTL 0x4975 10007 #define mmDPCSTX2_DPCSTX_CBUS_CNTL 0x9a15 10008 #define mmDPCSTX3_DPCSTX_CBUS_CNTL 0x9ab5 10009 #define mmDPCSTX4_DPCSTX_CBUS_CNTL 0x9b55 10010 #define mmDPCSTX5_DPCSTX_CBUS_CNTL 0x9bf5 10011 #define mmDPCSTX6_DPCSTX_CBUS_CNTL 0x9c95 10012 #define mmDPCSTX7_DPCSTX_CBUS_CNTL 0x9d35 10013 #define mmDPCSTX_REG_ERROR_STATUS 0x48d6 10014 #define mmDPCSTX0_DPCSTX_REG_ERROR_STATUS 0x48d6 10015 #define mmDPCSTX1_DPCSTX_REG_ERROR_STATUS 0x4976 10016 #define mmDPCSTX2_DPCSTX_REG_ERROR_STATUS 0x9a16 10017 #define mmDPCSTX3_DPCSTX_REG_ERROR_STATUS 0x9ab6 10018 #define mmDPCSTX4_DPCSTX_REG_ERROR_STATUS 0x9b56 10019 #define mmDPCSTX5_DPCSTX_REG_ERROR_STATUS 0x9bf6 10020 #define mmDPCSTX6_DPCSTX_REG_ERROR_STATUS 0x9c96 10021 #define mmDPCSTX7_DPCSTX_REG_ERROR_STATUS 0x9d36 10022 #define mmDPCSTX_TX_ERROR_STATUS 0x48d7 10023 #define mmDPCSTX0_DPCSTX_TX_ERROR_STATUS 0x48d7 10024 #define mmDPCSTX1_DPCSTX_TX_ERROR_STATUS 0x4977 10025 #define mmDPCSTX2_DPCSTX_TX_ERROR_STATUS 0x9a17 10026 #define mmDPCSTX3_DPCSTX_TX_ERROR_STATUS 0x9ab7 10027 #define mmDPCSTX4_DPCSTX_TX_ERROR_STATUS 0x9b57 10028 #define mmDPCSTX5_DPCSTX_TX_ERROR_STATUS 0x9bf7 10029 #define mmDPCSTX6_DPCSTX_TX_ERROR_STATUS 0x9c97 10030 #define mmDPCSTX7_DPCSTX_TX_ERROR_STATUS 0x9d37 10031 #define mmDPCSTX_PLL_UPDATE_ADDR 0x48d8 10032 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x48d8 10033 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR 0x4978 10034 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR 0x9a18 10035 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR 0x9ab8 10036 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR 0x9b58 10037 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR 0x9bf8 10038 #define mmDPCSTX6_DPCSTX_PLL_UPDATE_ADDR 0x9c98 10039 #define mmDPCSTX7_DPCSTX_PLL_UPDATE_ADDR 0x9d38 10040 #define mmDPCSTX_PLL_UPDATE_DATA 0x48d9 10041 #define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x48d9 10042 #define mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA 0x4979 10043 #define mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA 0x9a19 10044 #define mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA 0x9ab9 10045 #define mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA 0x9b59 10046 #define mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA 0x9bf9 10047 #define mmDPCSTX6_DPCSTX_PLL_UPDATE_DATA 0x9c99 10048 #define mmDPCSTX7_DPCSTX_PLL_UPDATE_DATA 0x9d39 10049 #define mmDPCSTX_INDEX_MODE_ADDR 0x48da 10050 #define mmDPCSTX0_DPCSTX_INDEX_MODE_ADDR 0x48da 10051 #define mmDPCSTX1_DPCSTX_INDEX_MODE_ADDR 0x497a 10052 #define mmDPCSTX2_DPCSTX_INDEX_MODE_ADDR 0x9a1a 10053 #define mmDPCSTX3_DPCSTX_INDEX_MODE_ADDR 0x9aba 10054 #define mmDPCSTX4_DPCSTX_INDEX_MODE_ADDR 0x9b5a 10055 #define mmDPCSTX5_DPCSTX_INDEX_MODE_ADDR 0x9bfa 10056 #define mmDPCSTX6_DPCSTX_INDEX_MODE_ADDR 0x9c9a 10057 #define mmDPCSTX7_DPCSTX_INDEX_MODE_ADDR 0x9d3a 10058 #define mmDPCSTX_INDEX_MODE_DATA 0x48db 10059 #define mmDPCSTX0_DPCSTX_INDEX_MODE_DATA 0x48db 10060 #define mmDPCSTX1_DPCSTX_INDEX_MODE_DATA 0x497b 10061 #define mmDPCSTX2_DPCSTX_INDEX_MODE_DATA 0x9a1b 10062 #define mmDPCSTX3_DPCSTX_INDEX_MODE_DATA 0x9abb 10063 #define mmDPCSTX4_DPCSTX_INDEX_MODE_DATA 0x9b5b 10064 #define mmDPCSTX5_DPCSTX_INDEX_MODE_DATA 0x9bfb 10065 #define mmDPCSTX6_DPCSTX_INDEX_MODE_DATA 0x9c9b 10066 #define mmDPCSTX7_DPCSTX_INDEX_MODE_DATA 0x9d3b 10067 #define mmDPCSTX_DEBUG_CONFIG 0x48dc 10068 #define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x48dc 10069 #define mmDPCSTX1_DPCSTX_DEBUG_CONFIG 0x497c 10070 #define mmDPCSTX2_DPCSTX_DEBUG_CONFIG 0x9a1c 10071 #define mmDPCSTX3_DPCSTX_DEBUG_CONFIG 0x9abc 10072 #define mmDPCSTX4_DPCSTX_DEBUG_CONFIG 0x9b5c 10073 #define mmDPCSTX5_DPCSTX_DEBUG_CONFIG 0x9bfc 10074 #define mmDPCSTX6_DPCSTX_DEBUG_CONFIG 0x9c9c 10075 #define mmDPCSTX7_DPCSTX_DEBUG_CONFIG 0x9d3c 10076 #define mmDPCSTX_TEST_DEBUG_DATA 0x48dd 10077 #define mmDPCSTX0_DPCSTX_TEST_DEBUG_DATA 0x48dd 10078 #define mmDPCSTX1_DPCSTX_TEST_DEBUG_DATA 0x497d 10079 #define mmDPCSTX2_DPCSTX_TEST_DEBUG_DATA 0x9a1d 10080 #define mmDPCSTX3_DPCSTX_TEST_DEBUG_DATA 0x9abd 10081 #define mmDPCSTX4_DPCSTX_TEST_DEBUG_DATA 0x9b5d 10082 #define mmDPCSTX5_DPCSTX_TEST_DEBUG_DATA 0x9bfd 10083 #define mmDPCSTX6_DPCSTX_TEST_DEBUG_DATA 0x9c9d 10084 #define mmDPCSTX7_DPCSTX_TEST_DEBUG_DATA 0x9d3d 10085 10086 #endif /* DCE_11_2_D_H */ 10087