1 /* $NetBSD: dce_10_0_enum.h,v 1.3 2021/12/18 23:45:09 riastradh Exp $ */ 2 3 /* 4 * DCE_10_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef DCE_10_0_ENUM_H 27 #define DCE_10_0_ENUM_H 28 29 typedef enum DCIO_DC_GENERICA_SEL { 30 DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0, 31 DCIO_GENERICA_SEL_STEREOSYNC = 0x1, 32 DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2, 33 DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3, 34 DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4, 35 DCIO_GENERICA_SEL_P1_PLLCLK = 0x5, 36 DCIO_GENERICA_SEL_P2_PLLCLK = 0x6, 37 DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7, 38 DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8, 39 DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9, 40 DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa, 41 DCIO_GENERICA_SEL_SYNCEN = 0xb, 42 DCIO_GENERICA_SEL_GENERICA_SCG = 0xc, 43 DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd, 44 DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe, 45 DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf, 46 DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10, 47 DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11, 48 } DCIO_DC_GENERICA_SEL; 49 typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL { 50 DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0, 51 DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1, 52 DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2, 53 DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3, 54 DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4, 55 DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5, 56 } DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; 57 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL { 58 DCIO_UNIPHYA_FBDIV_CLK = 0x0, 59 DCIO_UNIPHYB_FBDIV_CLK = 0x1, 60 DCIO_UNIPHYC_FBDIV_CLK = 0x2, 61 DCIO_UNIPHYD_FBDIV_CLK = 0x3, 62 DCIO_UNIPHYE_FBDIV_CLK = 0x4, 63 DCIO_UNIPHYF_FBDIV_CLK = 0x5, 64 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; 65 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL { 66 DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0, 67 DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1, 68 DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2, 69 DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3, 70 DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4, 71 DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5, 72 } DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; 73 typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL { 74 DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0, 75 DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1, 76 DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2, 77 DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3, 78 DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4, 79 DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5, 80 } DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; 81 typedef enum DCIO_DC_GENERICB_SEL { 82 DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0, 83 DCIO_GENERICB_SEL_STEREOSYNC = 0x1, 84 DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2, 85 DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3, 86 DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4, 87 DCIO_GENERICB_SEL_P1_PLLCLK = 0x5, 88 DCIO_GENERICB_SEL_P2_PLLCLK = 0x6, 89 DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7, 90 DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8, 91 DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9, 92 DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa, 93 DCIO_GENERICB_SEL_SYNCEN = 0xb, 94 DCIO_GENERICB_SEL_GENERICA_SCG = 0xc, 95 DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd, 96 DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe, 97 DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf, 98 } DCIO_DC_GENERICB_SEL; 99 typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL { 100 DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0, 101 DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1, 102 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2, 103 DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3, 104 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4, 105 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5, 106 DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6, 107 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7, 108 DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8, 109 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9, 110 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa, 111 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb, 112 DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc, 113 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd, 114 DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe, 115 DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf, 116 } DCIO_DC_PAD_EXTERN_SIG_SEL; 117 typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS { 118 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0, 119 DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1, 120 DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2, 121 DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3, 122 } DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS; 123 typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL { 124 DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0, 125 DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1, 126 DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2, 127 DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3, 128 } DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; 129 typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL { 130 DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0, 131 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1, 132 DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2, 133 DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3, 134 } DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; 135 typedef enum DCIO_DC_GPIO_VIP_DEBUG { 136 DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0, 137 DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1, 138 } DCIO_DC_GPIO_VIP_DEBUG; 139 typedef enum DCIO_DC_GPIO_MACRO_DEBUG { 140 DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0, 141 DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1, 142 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2, 143 DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3, 144 } DCIO_DC_GPIO_MACRO_DEBUG; 145 typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL { 146 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0, 147 DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1, 148 } DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL; 149 typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN { 150 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0, 151 DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1, 152 } DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN; 153 typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE { 154 DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0, 155 DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1, 156 } DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; 157 typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION { 158 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0, 159 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1, 160 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2, 161 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3, 162 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4, 163 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5, 164 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6, 165 DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7, 166 } DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION; 167 typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT { 168 DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0, 169 DCIO_UNIPHY_CHANNEL_INVERTED = 0x1, 170 } DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; 171 typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK { 172 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0, 173 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1, 174 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2, 175 DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3, 176 } DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; 177 typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE { 178 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0, 179 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1, 180 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2, 181 DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3, 182 } DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; 183 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN { 184 DCIO_VIP_MUX_EN_DVO = 0x0, 185 DCIO_VIP_MUX_EN_VIP = 0x1, 186 } DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN; 187 typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN { 188 DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0, 189 DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, 190 } DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN; 191 typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN { 192 DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0, 193 DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1, 194 } DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN; 195 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN { 196 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0, 197 DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1, 198 } DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN; 199 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE { 200 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0, 201 DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1, 202 } DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE; 203 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL { 204 DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0, 205 DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1, 206 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL; 207 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON { 208 DCIO_LVTMA_DIGON_OFF = 0x0, 209 DCIO_LVTMA_DIGON_ON = 0x1, 210 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON; 211 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL { 212 DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0, 213 DCIO_LVTMA_DIGON_POL_INVERT = 0x1, 214 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL; 215 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON { 216 DCIO_LVTMA_BLON_OFF = 0x0, 217 DCIO_LVTMA_BLON_ON = 0x1, 218 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON; 219 typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL { 220 DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0, 221 DCIO_LVTMA_BLON_POL_INVERT = 0x1, 222 } DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL; 223 typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN { 224 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0, 225 DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1, 226 } DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN; 227 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN { 228 DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0, 229 DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1, 230 } DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; 231 typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN { 232 DCIO_BL_PWM_DISABLE = 0x0, 233 DCIO_BL_PWM_ENABLE = 0x1, 234 } DCIO_BL_PWM_CNTL_BL_PWM_EN; 235 typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT { 236 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0, 237 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1, 238 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2, 239 DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3, 240 } DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; 241 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE { 242 DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0, 243 DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1, 244 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; 245 typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN { 246 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0, 247 DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1, 248 } DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN; 249 typedef enum DCIO_BL_PWM_GRP1_REG_LOCK { 250 DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0, 251 DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1, 252 } DCIO_BL_PWM_GRP1_REG_LOCK; 253 typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START { 254 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0, 255 DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1, 256 } DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START; 257 typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL { 258 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0, 259 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1, 260 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2, 261 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3, 262 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4, 263 DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5, 264 } DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; 265 typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN { 266 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0, 267 DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1, 268 } DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; 269 typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN { 270 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0, 271 DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1, 272 } DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; 273 typedef enum DCIO_GSL_SEL { 274 DCIO_GSL_SEL_GROUP_0 = 0x0, 275 DCIO_GSL_SEL_GROUP_1 = 0x1, 276 DCIO_GSL_SEL_GROUP_2 = 0x2, 277 } DCIO_GSL_SEL; 278 typedef enum DCIO_GENLK_CLK_GSL_MASK { 279 DCIO_GENLK_CLK_GSL_MASK_NO = 0x0, 280 DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1, 281 DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2, 282 } DCIO_GENLK_CLK_GSL_MASK; 283 typedef enum DCIO_GENLK_VSYNC_GSL_MASK { 284 DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0, 285 DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1, 286 DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2, 287 } DCIO_GENLK_VSYNC_GSL_MASK; 288 typedef enum DCIO_SWAPLOCK_A_GSL_MASK { 289 DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0, 290 DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1, 291 DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2, 292 } DCIO_SWAPLOCK_A_GSL_MASK; 293 typedef enum DCIO_SWAPLOCK_B_GSL_MASK { 294 DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0, 295 DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1, 296 DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2, 297 } DCIO_SWAPLOCK_B_GSL_MASK; 298 typedef enum DCIO_GSL_VSYNC_SEL { 299 DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0, 300 DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1, 301 DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2, 302 DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3, 303 DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4, 304 DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5, 305 } DCIO_GSL_VSYNC_SEL; 306 typedef enum DCIO_GSL0_TIMING_SYNC_SEL { 307 DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0, 308 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, 309 DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, 310 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, 311 DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, 312 } DCIO_GSL0_TIMING_SYNC_SEL; 313 typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL { 314 DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, 315 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, 316 DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, 317 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, 318 DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, 319 } DCIO_GSL0_GLOBAL_UNLOCK_SEL; 320 typedef enum DCIO_GSL1_TIMING_SYNC_SEL { 321 DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0, 322 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, 323 DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, 324 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, 325 DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, 326 } DCIO_GSL1_TIMING_SYNC_SEL; 327 typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL { 328 DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, 329 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, 330 DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, 331 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, 332 DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, 333 } DCIO_GSL1_GLOBAL_UNLOCK_SEL; 334 typedef enum DCIO_GSL2_TIMING_SYNC_SEL { 335 DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0, 336 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1, 337 DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2, 338 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3, 339 DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4, 340 } DCIO_GSL2_TIMING_SYNC_SEL; 341 typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL { 342 DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0, 343 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1, 344 DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2, 345 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3, 346 DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4, 347 } DCIO_GSL2_GLOBAL_UNLOCK_SEL; 348 typedef enum DCIO_DC_GPU_TIMER_START_POSITION { 349 DCIO_GPU_TIMER_START_0_END_27 = 0x0, 350 DCIO_GPU_TIMER_START_1_END_28 = 0x1, 351 DCIO_GPU_TIMER_START_2_END_29 = 0x2, 352 DCIO_GPU_TIMER_START_3_END_30 = 0x3, 353 DCIO_GPU_TIMER_START_4_END_31 = 0x4, 354 DCIO_GPU_TIMER_START_6_END_33 = 0x5, 355 DCIO_GPU_TIMER_START_8_END_35 = 0x6, 356 DCIO_GPU_TIMER_START_10_END_37 = 0x7, 357 } DCIO_DC_GPU_TIMER_START_POSITION; 358 typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL { 359 DCIO_TEST_CLK_SEL_DISPCLK = 0x0, 360 DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1, 361 DCIO_TEST_CLK_SEL_SCLK = 0x2, 362 } DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; 363 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS { 364 DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0, 365 DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1, 366 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; 367 typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS { 368 DCIO_DISPCLK_R_DCIO_RAMP_DISABLE = 0x0, 369 DCIO_DISPCLK_R_DCIO_RAMP_ENABLE = 0x1, 370 } DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS; 371 typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX { 372 DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0, 373 DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1, 374 DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2, 375 DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3, 376 DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4, 377 DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5, 378 DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6, 379 DCIO_EXT_VSYNC_MUX_GENERICB = 0x7, 380 } DCIO_DCO_DCFE_EXT_VSYNC_MUX; 381 typedef enum DCIO_DCO_EXT_VSYNC_MASK { 382 DCIO_EXT_VSYNC_MASK_NONE = 0x0, 383 DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1, 384 DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2, 385 DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3, 386 DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4, 387 DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5, 388 DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6, 389 DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7, 390 } DCIO_DCO_EXT_VSYNC_MASK; 391 typedef enum DCIO_DBG_OUT_PIN_SEL { 392 DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0, 393 DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1, 394 } DCIO_DBG_OUT_PIN_SEL; 395 typedef enum DCIO_DBG_OUT_12BIT_SEL { 396 DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0, 397 DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1, 398 DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2, 399 DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3, 400 } DCIO_DBG_OUT_12BIT_SEL; 401 typedef enum DCIO_DSYNC_SOFT_RESET { 402 DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0, 403 DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1, 404 } DCIO_DSYNC_SOFT_RESET; 405 typedef enum DCIO_DACA_SOFT_RESET { 406 DCIO_DACA_SOFT_RESET_DEASSERT = 0x0, 407 DCIO_DACA_SOFT_RESET_ASSERT = 0x1, 408 } DCIO_DACA_SOFT_RESET; 409 typedef enum DCIO_DCRXPHY_SOFT_RESET { 410 DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0, 411 DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1, 412 } DCIO_DCRXPHY_SOFT_RESET; 413 typedef enum DCIO_DPHY_LANE_SEL { 414 DCIO_DPHY_LANE_SEL_LANE0 = 0x0, 415 DCIO_DPHY_LANE_SEL_LANE1 = 0x1, 416 DCIO_DPHY_LANE_SEL_LANE2 = 0x2, 417 DCIO_DPHY_LANE_SEL_LANE3 = 0x3, 418 } DCIO_DPHY_LANE_SEL; 419 typedef enum DCIO_DC_GPU_TIMER_READ_SELECT { 420 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0, 421 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1, 422 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2, 423 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3, 424 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4, 425 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5, 426 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x6, 427 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x7, 428 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x8, 429 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9, 430 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa, 431 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0xb, 432 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc, 433 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd, 434 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe, 435 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf, 436 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10, 437 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11, 438 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x12, 439 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x13, 440 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x14, 441 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x15, 442 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x16, 443 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x17, 444 DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18, 445 DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19, 446 DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a, 447 DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b, 448 DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c, 449 DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d, 450 DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x1e, 451 DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x1f, 452 DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x20, 453 DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x21, 454 DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x22, 455 DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x23, 456 } DCIO_DC_GPU_TIMER_READ_SELECT; 457 typedef enum DCIO_IMPCAL_STEP_DELAY { 458 DCIO_IMPCAL_STEP_DELAY_1us = 0x0, 459 DCIO_IMPCAL_STEP_DELAY_2us = 0x1, 460 DCIO_IMPCAL_STEP_DELAY_3us = 0x2, 461 DCIO_IMPCAL_STEP_DELAY_4us = 0x3, 462 DCIO_IMPCAL_STEP_DELAY_5us = 0x4, 463 DCIO_IMPCAL_STEP_DELAY_6us = 0x5, 464 DCIO_IMPCAL_STEP_DELAY_7us = 0x6, 465 DCIO_IMPCAL_STEP_DELAY_8us = 0x7, 466 DCIO_IMPCAL_STEP_DELAY_9us = 0x8, 467 DCIO_IMPCAL_STEP_DELAY_10us = 0x9, 468 DCIO_IMPCAL_STEP_DELAY_11us = 0xa, 469 DCIO_IMPCAL_STEP_DELAY_12us = 0xb, 470 DCIO_IMPCAL_STEP_DELAY_13us = 0xc, 471 DCIO_IMPCAL_STEP_DELAY_14us = 0xd, 472 DCIO_IMPCAL_STEP_DELAY_15us = 0xe, 473 DCIO_IMPCAL_STEP_DELAY_16us = 0xf, 474 } DCIO_IMPCAL_STEP_DELAY; 475 typedef enum DCIO_UNIPHY_IMPCAL_SEL { 476 DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0, 477 DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1, 478 } DCIO_UNIPHY_IMPCAL_SEL; 479 typedef enum DCIOCHIP_HPD_SEL { 480 DCIOCHIP_HPD_SEL_ASYNC = 0x0, 481 DCIOCHIP_HPD_SEL_CLOCKED = 0x1, 482 } DCIOCHIP_HPD_SEL; 483 typedef enum DCIOCHIP_PAD_MODE { 484 DCIOCHIP_PAD_MODE_DDC = 0x0, 485 DCIOCHIP_PAD_MODE_DP = 0x1, 486 } DCIOCHIP_PAD_MODE; 487 typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE { 488 DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0, 489 DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1, 490 } DCIOCHIP_AUXSLAVE_PAD_MODE; 491 typedef enum DCIOCHIP_INVERT { 492 DCIOCHIP_POL_NON_INVERT = 0x0, 493 DCIOCHIP_POL_INVERT = 0x1, 494 } DCIOCHIP_INVERT; 495 typedef enum DCIOCHIP_PD_EN { 496 DCIOCHIP_PD_EN_NOTALLOW = 0x0, 497 DCIOCHIP_PD_EN_ALLOW = 0x1, 498 } DCIOCHIP_PD_EN; 499 typedef enum DCIOCHIP_GPIO_MASK_EN { 500 DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0, 501 DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1, 502 } DCIOCHIP_GPIO_MASK_EN; 503 typedef enum DCIOCHIP_MASK { 504 DCIOCHIP_MASK_DISABLE = 0x0, 505 DCIOCHIP_MASK_ENABLE = 0x1, 506 } DCIOCHIP_MASK; 507 typedef enum DCIOCHIP_GPIO_I2C_MASK { 508 DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0, 509 DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1, 510 } DCIOCHIP_GPIO_I2C_MASK; 511 typedef enum DCIOCHIP_GPIO_I2C_DRIVE { 512 DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0, 513 DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1, 514 } DCIOCHIP_GPIO_I2C_DRIVE; 515 typedef enum DCIOCHIP_GPIO_I2C_EN { 516 DCIOCHIP_GPIO_I2C_DISABLE = 0x0, 517 DCIOCHIP_GPIO_I2C_ENABLE = 0x1, 518 } DCIOCHIP_GPIO_I2C_EN; 519 typedef enum DCIOCHIP_MASK_4BIT { 520 DCIOCHIP_MASK_4BIT_DISABLE = 0x0, 521 DCIOCHIP_MASK_4BIT_ENABLE = 0xf, 522 } DCIOCHIP_MASK_4BIT; 523 typedef enum DCIOCHIP_ENABLE_4BIT { 524 DCIOCHIP_4BIT_DISABLE = 0x0, 525 DCIOCHIP_4BIT_ENABLE = 0xf, 526 } DCIOCHIP_ENABLE_4BIT; 527 typedef enum DCIOCHIP_MASK_5BIT { 528 DCIOCHIP_MASIK_5BIT_DISABLE = 0x0, 529 DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f, 530 } DCIOCHIP_MASK_5BIT; 531 typedef enum DCIOCHIP_ENABLE_5BIT { 532 DCIOCHIP_5BIT_DISABLE = 0x0, 533 DCIOCHIP_5BIT_ENABLE = 0x1f, 534 } DCIOCHIP_ENABLE_5BIT; 535 typedef enum DCIOCHIP_MASK_2BIT { 536 DCIOCHIP_MASK_2BIT_DISABLE = 0x0, 537 DCIOCHIP_MASK_2BIT_ENABLE = 0x3, 538 } DCIOCHIP_MASK_2BIT; 539 typedef enum DCIOCHIP_ENABLE_2BIT { 540 DCIOCHIP_2BIT_DISABLE = 0x0, 541 DCIOCHIP_2BIT_ENABLE = 0x3, 542 } DCIOCHIP_ENABLE_2BIT; 543 typedef enum DCIOCHIP_REF_27_SRC_SEL { 544 DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0, 545 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1, 546 DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2, 547 DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3, 548 } DCIOCHIP_REF_27_SRC_SEL; 549 typedef enum DCIOCHIP_DVO_VREFPON { 550 DCIOCHIP_DVO_VREFPON_DISABLE = 0x0, 551 DCIOCHIP_DVO_VREFPON_ENABLE = 0x1, 552 } DCIOCHIP_DVO_VREFPON; 553 typedef enum DCIOCHIP_DVO_VREFSEL { 554 DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0, 555 DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1, 556 } DCIOCHIP_DVO_VREFSEL; 557 typedef enum COL_MAN_UPDATE_LOCK { 558 COL_MAN_UPDATE_UNLOCKED = 0x0, 559 COL_MAN_UPDATE_LOCKED = 0x1, 560 } COL_MAN_UPDATE_LOCK; 561 typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE { 562 COL_MAN_MULTIPLE_UPDATE = 0x0, 563 COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1, 564 } COL_MAN_DISABLE_MULTIPLE_UPDATE; 565 typedef enum COL_MAN_INPUTCSC_MODE { 566 INPUTCSC_MODE_BYPASS = 0x0, 567 INPUTCSC_MODE_A = 0x1, 568 INPUTCSC_MODE_B = 0x2, 569 INPUTCSC_MODE_UNITY = 0x3, 570 } COL_MAN_INPUTCSC_MODE; 571 typedef enum COL_MAN_INPUTCSC_TYPE { 572 INPUTCSC_TYPE_12_0 = 0x0, 573 INPUTCSC_TYPE_10_2 = 0x1, 574 INPUTCSC_TYPE_8_4 = 0x2, 575 } COL_MAN_INPUTCSC_TYPE; 576 typedef enum COL_MAN_INPUTCSC_CONVERT { 577 INPUTCSC_ROUND = 0x0, 578 INPUTCSC_TRUNCATE = 0x1, 579 } COL_MAN_INPUTCSC_CONVERT; 580 typedef enum COL_MAN_PRESCALE_MODE { 581 PRESCALE_MODE_BYPASS = 0x0, 582 PRESCALE_MODE_PROGRAM = 0x1, 583 PRESCALE_MODE_UNITY = 0x2, 584 } COL_MAN_PRESCALE_MODE; 585 typedef enum COL_MAN_OUTPUT_CSC_MODE { 586 COL_MAN_OUTPUT_CSC_BYPASS = 0x0, 587 COL_MAN_OUTPUT_CSC_RGB = 0x1, 588 COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2, 589 COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3, 590 COL_MAN_OUTPUT_CSC_A = 0x4, 591 COL_MAN_OUTPUT_CSC_B = 0x5, 592 } COL_MAN_OUTPUT_CSC_MODE; 593 typedef enum COL_MAN_DENORM_CLAMP_CONTROL { 594 DENORM_CLAMP_CONTROL_UNITY = 0x0, 595 DENORM_CLAMP_CONTROL_8 = 0x1, 596 DENORM_CLAMP_CONTROL_10 = 0x2, 597 DENORM_CLAMP_CONTROL_12 = 0x3, 598 } COL_MAN_DENORM_CLAMP_CONTROL; 599 typedef enum COL_MAN_GAMMA_CORR_CONTROL { 600 GAMMA_CORR_CONTROL_BYPASS = 0x0, 601 GAMMA_CORR_CONTROL_A = 0x1, 602 GAMMA_CORR_CONTROL_B = 0x2, 603 } COL_MAN_GAMMA_CORR_CONTROL; 604 typedef enum SurfaceEndian { 605 ENDIAN_NONE = 0x0, 606 ENDIAN_8IN16 = 0x1, 607 ENDIAN_8IN32 = 0x2, 608 ENDIAN_8IN64 = 0x3, 609 } SurfaceEndian; 610 typedef enum ArrayMode { 611 ARRAY_LINEAR_GENERAL = 0x0, 612 ARRAY_LINEAR_ALIGNED = 0x1, 613 ARRAY_1D_TILED_THIN1 = 0x2, 614 ARRAY_1D_TILED_THICK = 0x3, 615 ARRAY_2D_TILED_THIN1 = 0x4, 616 ARRAY_PRT_TILED_THIN1 = 0x5, 617 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 618 ARRAY_2D_TILED_THICK = 0x7, 619 ARRAY_2D_TILED_XTHICK = 0x8, 620 ARRAY_PRT_TILED_THICK = 0x9, 621 ARRAY_PRT_2D_TILED_THICK = 0xa, 622 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 623 ARRAY_3D_TILED_THIN1 = 0xc, 624 ARRAY_3D_TILED_THICK = 0xd, 625 ARRAY_3D_TILED_XTHICK = 0xe, 626 ARRAY_PRT_3D_TILED_THICK = 0xf, 627 } ArrayMode; 628 typedef enum PipeTiling { 629 CONFIG_1_PIPE = 0x0, 630 CONFIG_2_PIPE = 0x1, 631 CONFIG_4_PIPE = 0x2, 632 CONFIG_8_PIPE = 0x3, 633 } PipeTiling; 634 typedef enum BankTiling { 635 CONFIG_4_BANK = 0x0, 636 CONFIG_8_BANK = 0x1, 637 } BankTiling; 638 typedef enum GroupInterleave { 639 CONFIG_256B_GROUP = 0x0, 640 CONFIG_512B_GROUP = 0x1, 641 } GroupInterleave; 642 typedef enum RowTiling { 643 CONFIG_1KB_ROW = 0x0, 644 CONFIG_2KB_ROW = 0x1, 645 CONFIG_4KB_ROW = 0x2, 646 CONFIG_8KB_ROW = 0x3, 647 CONFIG_1KB_ROW_OPT = 0x4, 648 CONFIG_2KB_ROW_OPT = 0x5, 649 CONFIG_4KB_ROW_OPT = 0x6, 650 CONFIG_8KB_ROW_OPT = 0x7, 651 } RowTiling; 652 typedef enum BankSwapBytes { 653 CONFIG_128B_SWAPS = 0x0, 654 CONFIG_256B_SWAPS = 0x1, 655 CONFIG_512B_SWAPS = 0x2, 656 CONFIG_1KB_SWAPS = 0x3, 657 } BankSwapBytes; 658 typedef enum SampleSplitBytes { 659 CONFIG_1KB_SPLIT = 0x0, 660 CONFIG_2KB_SPLIT = 0x1, 661 CONFIG_4KB_SPLIT = 0x2, 662 CONFIG_8KB_SPLIT = 0x3, 663 } SampleSplitBytes; 664 typedef enum NumPipes { 665 ADDR_CONFIG_1_PIPE = 0x0, 666 ADDR_CONFIG_2_PIPE = 0x1, 667 ADDR_CONFIG_4_PIPE = 0x2, 668 ADDR_CONFIG_8_PIPE = 0x3, 669 } NumPipes; 670 typedef enum PipeInterleaveSize { 671 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 672 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 673 } PipeInterleaveSize; 674 typedef enum BankInterleaveSize { 675 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 676 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 677 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 678 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 679 } BankInterleaveSize; 680 typedef enum NumShaderEngines { 681 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 682 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 683 } NumShaderEngines; 684 typedef enum ShaderEngineTileSize { 685 ADDR_CONFIG_SE_TILE_16 = 0x0, 686 ADDR_CONFIG_SE_TILE_32 = 0x1, 687 } ShaderEngineTileSize; 688 typedef enum NumGPUs { 689 ADDR_CONFIG_1_GPU = 0x0, 690 ADDR_CONFIG_2_GPU = 0x1, 691 ADDR_CONFIG_4_GPU = 0x2, 692 } NumGPUs; 693 typedef enum MultiGPUTileSize { 694 ADDR_CONFIG_GPU_TILE_16 = 0x0, 695 ADDR_CONFIG_GPU_TILE_32 = 0x1, 696 ADDR_CONFIG_GPU_TILE_64 = 0x2, 697 ADDR_CONFIG_GPU_TILE_128 = 0x3, 698 } MultiGPUTileSize; 699 typedef enum RowSize { 700 ADDR_CONFIG_1KB_ROW = 0x0, 701 ADDR_CONFIG_2KB_ROW = 0x1, 702 ADDR_CONFIG_4KB_ROW = 0x2, 703 } RowSize; 704 typedef enum NumLowerPipes { 705 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 706 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 707 } NumLowerPipes; 708 typedef enum DebugBlockId { 709 DBG_CLIENT_BLKID_RESERVED = 0x0, 710 DBG_CLIENT_BLKID_dbg = 0x1, 711 DBG_CLIENT_BLKID_scf2 = 0x2, 712 DBG_CLIENT_BLKID_mcd5 = 0x3, 713 DBG_CLIENT_BLKID_vmc = 0x4, 714 DBG_CLIENT_BLKID_sx30 = 0x5, 715 DBG_CLIENT_BLKID_mcd2 = 0x6, 716 DBG_CLIENT_BLKID_bci1 = 0x7, 717 DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8, 718 DBG_CLIENT_BLKID_mcc0 = 0x9, 719 DBG_CLIENT_BLKID_uvdf_0 = 0xa, 720 DBG_CLIENT_BLKID_uvdf_1 = 0xb, 721 DBG_CLIENT_BLKID_uvdf_2 = 0xc, 722 DBG_CLIENT_BLKID_uvdi_0 = 0xd, 723 DBG_CLIENT_BLKID_bci0 = 0xe, 724 DBG_CLIENT_BLKID_vcec0_0 = 0xf, 725 DBG_CLIENT_BLKID_cb100 = 0x10, 726 DBG_CLIENT_BLKID_cb001 = 0x11, 727 DBG_CLIENT_BLKID_mcd4 = 0x12, 728 DBG_CLIENT_BLKID_tmonw00 = 0x13, 729 DBG_CLIENT_BLKID_cb101 = 0x14, 730 DBG_CLIENT_BLKID_sx10 = 0x15, 731 DBG_CLIENT_BLKID_cb301 = 0x16, 732 DBG_CLIENT_BLKID_tmonw01 = 0x17, 733 DBG_CLIENT_BLKID_vcea0_0 = 0x18, 734 DBG_CLIENT_BLKID_vcea0_1 = 0x19, 735 DBG_CLIENT_BLKID_vcea0_2 = 0x1a, 736 DBG_CLIENT_BLKID_vcea0_3 = 0x1b, 737 DBG_CLIENT_BLKID_scf1 = 0x1c, 738 DBG_CLIENT_BLKID_sx20 = 0x1d, 739 DBG_CLIENT_BLKID_spim1 = 0x1e, 740 DBG_CLIENT_BLKID_pa10 = 0x1f, 741 DBG_CLIENT_BLKID_pa00 = 0x20, 742 DBG_CLIENT_BLKID_gmcon = 0x21, 743 DBG_CLIENT_BLKID_mcb = 0x22, 744 DBG_CLIENT_BLKID_vgt0 = 0x23, 745 DBG_CLIENT_BLKID_pc0 = 0x24, 746 DBG_CLIENT_BLKID_bci2 = 0x25, 747 DBG_CLIENT_BLKID_uvdb_0 = 0x26, 748 DBG_CLIENT_BLKID_spim3 = 0x27, 749 DBG_CLIENT_BLKID_cpc_0 = 0x28, 750 DBG_CLIENT_BLKID_cpc_1 = 0x29, 751 DBG_CLIENT_BLKID_uvdm_0 = 0x2a, 752 DBG_CLIENT_BLKID_uvdm_1 = 0x2b, 753 DBG_CLIENT_BLKID_uvdm_2 = 0x2c, 754 DBG_CLIENT_BLKID_uvdm_3 = 0x2d, 755 DBG_CLIENT_BLKID_cb000 = 0x2e, 756 DBG_CLIENT_BLKID_spim0 = 0x2f, 757 DBG_CLIENT_BLKID_mcc2 = 0x30, 758 DBG_CLIENT_BLKID_ds0 = 0x31, 759 DBG_CLIENT_BLKID_srbm = 0x32, 760 DBG_CLIENT_BLKID_ih = 0x33, 761 DBG_CLIENT_BLKID_sem = 0x34, 762 DBG_CLIENT_BLKID_sdma_0 = 0x35, 763 DBG_CLIENT_BLKID_sdma_1 = 0x36, 764 DBG_CLIENT_BLKID_hdp = 0x37, 765 DBG_CLIENT_BLKID_acp_0 = 0x38, 766 DBG_CLIENT_BLKID_acp_1 = 0x39, 767 DBG_CLIENT_BLKID_cb200 = 0x3a, 768 DBG_CLIENT_BLKID_scf3 = 0x3b, 769 DBG_CLIENT_BLKID_vceb1_0 = 0x3c, 770 DBG_CLIENT_BLKID_vcea1_0 = 0x3d, 771 DBG_CLIENT_BLKID_vcea1_1 = 0x3e, 772 DBG_CLIENT_BLKID_vcea1_2 = 0x3f, 773 DBG_CLIENT_BLKID_vcea1_3 = 0x40, 774 DBG_CLIENT_BLKID_bci3 = 0x41, 775 DBG_CLIENT_BLKID_mcd0 = 0x42, 776 DBG_CLIENT_BLKID_pa11 = 0x43, 777 DBG_CLIENT_BLKID_pa01 = 0x44, 778 DBG_CLIENT_BLKID_cb201 = 0x45, 779 DBG_CLIENT_BLKID_spim2 = 0x46, 780 DBG_CLIENT_BLKID_vgt2 = 0x47, 781 DBG_CLIENT_BLKID_pc2 = 0x48, 782 DBG_CLIENT_BLKID_smu_0 = 0x49, 783 DBG_CLIENT_BLKID_smu_1 = 0x4a, 784 DBG_CLIENT_BLKID_smu_2 = 0x4b, 785 DBG_CLIENT_BLKID_cb1 = 0x4c, 786 DBG_CLIENT_BLKID_ia0 = 0x4d, 787 DBG_CLIENT_BLKID_wd = 0x4e, 788 DBG_CLIENT_BLKID_ia1 = 0x4f, 789 DBG_CLIENT_BLKID_vcec1_0 = 0x50, 790 DBG_CLIENT_BLKID_scf0 = 0x51, 791 DBG_CLIENT_BLKID_vgt1 = 0x52, 792 DBG_CLIENT_BLKID_pc1 = 0x53, 793 DBG_CLIENT_BLKID_cb0 = 0x54, 794 DBG_CLIENT_BLKID_gdc_one_0 = 0x55, 795 DBG_CLIENT_BLKID_gdc_one_1 = 0x56, 796 DBG_CLIENT_BLKID_gdc_one_2 = 0x57, 797 DBG_CLIENT_BLKID_gdc_one_3 = 0x58, 798 DBG_CLIENT_BLKID_gdc_one_4 = 0x59, 799 DBG_CLIENT_BLKID_gdc_one_5 = 0x5a, 800 DBG_CLIENT_BLKID_gdc_one_6 = 0x5b, 801 DBG_CLIENT_BLKID_gdc_one_7 = 0x5c, 802 DBG_CLIENT_BLKID_gdc_one_8 = 0x5d, 803 DBG_CLIENT_BLKID_gdc_one_9 = 0x5e, 804 DBG_CLIENT_BLKID_gdc_one_10 = 0x5f, 805 DBG_CLIENT_BLKID_gdc_one_11 = 0x60, 806 DBG_CLIENT_BLKID_gdc_one_12 = 0x61, 807 DBG_CLIENT_BLKID_gdc_one_13 = 0x62, 808 DBG_CLIENT_BLKID_gdc_one_14 = 0x63, 809 DBG_CLIENT_BLKID_gdc_one_15 = 0x64, 810 DBG_CLIENT_BLKID_gdc_one_16 = 0x65, 811 DBG_CLIENT_BLKID_gdc_one_17 = 0x66, 812 DBG_CLIENT_BLKID_gdc_one_18 = 0x67, 813 DBG_CLIENT_BLKID_gdc_one_19 = 0x68, 814 DBG_CLIENT_BLKID_gdc_one_20 = 0x69, 815 DBG_CLIENT_BLKID_gdc_one_21 = 0x6a, 816 DBG_CLIENT_BLKID_gdc_one_22 = 0x6b, 817 DBG_CLIENT_BLKID_gdc_one_23 = 0x6c, 818 DBG_CLIENT_BLKID_gdc_one_24 = 0x6d, 819 DBG_CLIENT_BLKID_gdc_one_25 = 0x6e, 820 DBG_CLIENT_BLKID_gdc_one_26 = 0x6f, 821 DBG_CLIENT_BLKID_gdc_one_27 = 0x70, 822 DBG_CLIENT_BLKID_gdc_one_28 = 0x71, 823 DBG_CLIENT_BLKID_gdc_one_29 = 0x72, 824 DBG_CLIENT_BLKID_gdc_one_30 = 0x73, 825 DBG_CLIENT_BLKID_gdc_one_31 = 0x74, 826 DBG_CLIENT_BLKID_gdc_one_32 = 0x75, 827 DBG_CLIENT_BLKID_gdc_one_33 = 0x76, 828 DBG_CLIENT_BLKID_gdc_one_34 = 0x77, 829 DBG_CLIENT_BLKID_gdc_one_35 = 0x78, 830 DBG_CLIENT_BLKID_vceb0_0 = 0x79, 831 DBG_CLIENT_BLKID_vgt3 = 0x7a, 832 DBG_CLIENT_BLKID_pc3 = 0x7b, 833 DBG_CLIENT_BLKID_mcd3 = 0x7c, 834 DBG_CLIENT_BLKID_uvdu_0 = 0x7d, 835 DBG_CLIENT_BLKID_uvdu_1 = 0x7e, 836 DBG_CLIENT_BLKID_uvdu_2 = 0x7f, 837 DBG_CLIENT_BLKID_uvdu_3 = 0x80, 838 DBG_CLIENT_BLKID_uvdu_4 = 0x81, 839 DBG_CLIENT_BLKID_uvdu_5 = 0x82, 840 DBG_CLIENT_BLKID_uvdu_6 = 0x83, 841 DBG_CLIENT_BLKID_cb300 = 0x84, 842 DBG_CLIENT_BLKID_mcd1 = 0x85, 843 DBG_CLIENT_BLKID_sx00 = 0x86, 844 DBG_CLIENT_BLKID_uvdc_0 = 0x87, 845 DBG_CLIENT_BLKID_uvdc_1 = 0x88, 846 DBG_CLIENT_BLKID_mcc3 = 0x89, 847 DBG_CLIENT_BLKID_cpg_0 = 0x8a, 848 DBG_CLIENT_BLKID_cpg_1 = 0x8b, 849 DBG_CLIENT_BLKID_gck = 0x8c, 850 DBG_CLIENT_BLKID_mcc1 = 0x8d, 851 DBG_CLIENT_BLKID_cpf_0 = 0x8e, 852 DBG_CLIENT_BLKID_cpf_1 = 0x8f, 853 DBG_CLIENT_BLKID_rlc = 0x90, 854 DBG_CLIENT_BLKID_grbm = 0x91, 855 DBG_CLIENT_BLKID_sammsp = 0x92, 856 DBG_CLIENT_BLKID_dci_pg = 0x93, 857 DBG_CLIENT_BLKID_dci_0 = 0x94, 858 DBG_CLIENT_BLKID_dccg0_0 = 0x95, 859 DBG_CLIENT_BLKID_dccg0_1 = 0x96, 860 DBG_CLIENT_BLKID_dcfe01_0 = 0x97, 861 DBG_CLIENT_BLKID_dcfe02_0 = 0x98, 862 DBG_CLIENT_BLKID_dcfe03_0 = 0x99, 863 DBG_CLIENT_BLKID_dcfe04_0 = 0x9a, 864 DBG_CLIENT_BLKID_dcfe05_0 = 0x9b, 865 DBG_CLIENT_BLKID_dcfe06_0 = 0x9c, 866 DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d, 867 } DebugBlockId; 868 typedef enum DebugBlockId_OLD { 869 DBG_BLOCK_ID_RESERVED = 0x0, 870 DBG_BLOCK_ID_DBG = 0x1, 871 DBG_BLOCK_ID_VMC = 0x2, 872 DBG_BLOCK_ID_PDMA = 0x3, 873 DBG_BLOCK_ID_CG = 0x4, 874 DBG_BLOCK_ID_SRBM = 0x5, 875 DBG_BLOCK_ID_GRBM = 0x6, 876 DBG_BLOCK_ID_RLC = 0x7, 877 DBG_BLOCK_ID_CSC = 0x8, 878 DBG_BLOCK_ID_SEM = 0x9, 879 DBG_BLOCK_ID_IH = 0xa, 880 DBG_BLOCK_ID_SC = 0xb, 881 DBG_BLOCK_ID_SQ = 0xc, 882 DBG_BLOCK_ID_AVP = 0xd, 883 DBG_BLOCK_ID_GMCON = 0xe, 884 DBG_BLOCK_ID_SMU = 0xf, 885 DBG_BLOCK_ID_DMA0 = 0x10, 886 DBG_BLOCK_ID_DMA1 = 0x11, 887 DBG_BLOCK_ID_SPIM = 0x12, 888 DBG_BLOCK_ID_GDS = 0x13, 889 DBG_BLOCK_ID_SPIS = 0x14, 890 DBG_BLOCK_ID_UNUSED0 = 0x15, 891 DBG_BLOCK_ID_PA0 = 0x16, 892 DBG_BLOCK_ID_PA1 = 0x17, 893 DBG_BLOCK_ID_CP0 = 0x18, 894 DBG_BLOCK_ID_CP1 = 0x19, 895 DBG_BLOCK_ID_CP2 = 0x1a, 896 DBG_BLOCK_ID_UNUSED1 = 0x1b, 897 DBG_BLOCK_ID_UVDU = 0x1c, 898 DBG_BLOCK_ID_UVDM = 0x1d, 899 DBG_BLOCK_ID_VCE = 0x1e, 900 DBG_BLOCK_ID_UNUSED2 = 0x1f, 901 DBG_BLOCK_ID_VGT0 = 0x20, 902 DBG_BLOCK_ID_VGT1 = 0x21, 903 DBG_BLOCK_ID_IA = 0x22, 904 DBG_BLOCK_ID_UNUSED3 = 0x23, 905 DBG_BLOCK_ID_SCT0 = 0x24, 906 DBG_BLOCK_ID_SCT1 = 0x25, 907 DBG_BLOCK_ID_SPM0 = 0x26, 908 DBG_BLOCK_ID_SPM1 = 0x27, 909 DBG_BLOCK_ID_TCAA = 0x28, 910 DBG_BLOCK_ID_TCAB = 0x29, 911 DBG_BLOCK_ID_TCCA = 0x2a, 912 DBG_BLOCK_ID_TCCB = 0x2b, 913 DBG_BLOCK_ID_MCC0 = 0x2c, 914 DBG_BLOCK_ID_MCC1 = 0x2d, 915 DBG_BLOCK_ID_MCC2 = 0x2e, 916 DBG_BLOCK_ID_MCC3 = 0x2f, 917 DBG_BLOCK_ID_SX0 = 0x30, 918 DBG_BLOCK_ID_SX1 = 0x31, 919 DBG_BLOCK_ID_SX2 = 0x32, 920 DBG_BLOCK_ID_SX3 = 0x33, 921 DBG_BLOCK_ID_UNUSED4 = 0x34, 922 DBG_BLOCK_ID_UNUSED5 = 0x35, 923 DBG_BLOCK_ID_UNUSED6 = 0x36, 924 DBG_BLOCK_ID_UNUSED7 = 0x37, 925 DBG_BLOCK_ID_PC0 = 0x38, 926 DBG_BLOCK_ID_PC1 = 0x39, 927 DBG_BLOCK_ID_UNUSED8 = 0x3a, 928 DBG_BLOCK_ID_UNUSED9 = 0x3b, 929 DBG_BLOCK_ID_UNUSED10 = 0x3c, 930 DBG_BLOCK_ID_UNUSED11 = 0x3d, 931 DBG_BLOCK_ID_MCB = 0x3e, 932 DBG_BLOCK_ID_UNUSED12 = 0x3f, 933 DBG_BLOCK_ID_SCB0 = 0x40, 934 DBG_BLOCK_ID_SCB1 = 0x41, 935 DBG_BLOCK_ID_UNUSED13 = 0x42, 936 DBG_BLOCK_ID_UNUSED14 = 0x43, 937 DBG_BLOCK_ID_SCF0 = 0x44, 938 DBG_BLOCK_ID_SCF1 = 0x45, 939 DBG_BLOCK_ID_UNUSED15 = 0x46, 940 DBG_BLOCK_ID_UNUSED16 = 0x47, 941 DBG_BLOCK_ID_BCI0 = 0x48, 942 DBG_BLOCK_ID_BCI1 = 0x49, 943 DBG_BLOCK_ID_BCI2 = 0x4a, 944 DBG_BLOCK_ID_BCI3 = 0x4b, 945 DBG_BLOCK_ID_UNUSED17 = 0x4c, 946 DBG_BLOCK_ID_UNUSED18 = 0x4d, 947 DBG_BLOCK_ID_UNUSED19 = 0x4e, 948 DBG_BLOCK_ID_UNUSED20 = 0x4f, 949 DBG_BLOCK_ID_CB00 = 0x50, 950 DBG_BLOCK_ID_CB01 = 0x51, 951 DBG_BLOCK_ID_CB02 = 0x52, 952 DBG_BLOCK_ID_CB03 = 0x53, 953 DBG_BLOCK_ID_CB04 = 0x54, 954 DBG_BLOCK_ID_UNUSED21 = 0x55, 955 DBG_BLOCK_ID_UNUSED22 = 0x56, 956 DBG_BLOCK_ID_UNUSED23 = 0x57, 957 DBG_BLOCK_ID_CB10 = 0x58, 958 DBG_BLOCK_ID_CB11 = 0x59, 959 DBG_BLOCK_ID_CB12 = 0x5a, 960 DBG_BLOCK_ID_CB13 = 0x5b, 961 DBG_BLOCK_ID_CB14 = 0x5c, 962 DBG_BLOCK_ID_UNUSED24 = 0x5d, 963 DBG_BLOCK_ID_UNUSED25 = 0x5e, 964 DBG_BLOCK_ID_UNUSED26 = 0x5f, 965 DBG_BLOCK_ID_TCP0 = 0x60, 966 DBG_BLOCK_ID_TCP1 = 0x61, 967 DBG_BLOCK_ID_TCP2 = 0x62, 968 DBG_BLOCK_ID_TCP3 = 0x63, 969 DBG_BLOCK_ID_TCP4 = 0x64, 970 DBG_BLOCK_ID_TCP5 = 0x65, 971 DBG_BLOCK_ID_TCP6 = 0x66, 972 DBG_BLOCK_ID_TCP7 = 0x67, 973 DBG_BLOCK_ID_TCP8 = 0x68, 974 DBG_BLOCK_ID_TCP9 = 0x69, 975 DBG_BLOCK_ID_TCP10 = 0x6a, 976 DBG_BLOCK_ID_TCP11 = 0x6b, 977 DBG_BLOCK_ID_TCP12 = 0x6c, 978 DBG_BLOCK_ID_TCP13 = 0x6d, 979 DBG_BLOCK_ID_TCP14 = 0x6e, 980 DBG_BLOCK_ID_TCP15 = 0x6f, 981 DBG_BLOCK_ID_TCP16 = 0x70, 982 DBG_BLOCK_ID_TCP17 = 0x71, 983 DBG_BLOCK_ID_TCP18 = 0x72, 984 DBG_BLOCK_ID_TCP19 = 0x73, 985 DBG_BLOCK_ID_TCP20 = 0x74, 986 DBG_BLOCK_ID_TCP21 = 0x75, 987 DBG_BLOCK_ID_TCP22 = 0x76, 988 DBG_BLOCK_ID_TCP23 = 0x77, 989 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 990 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 991 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 992 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 993 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 994 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 995 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 996 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 997 DBG_BLOCK_ID_DB00 = 0x80, 998 DBG_BLOCK_ID_DB01 = 0x81, 999 DBG_BLOCK_ID_DB02 = 0x82, 1000 DBG_BLOCK_ID_DB03 = 0x83, 1001 DBG_BLOCK_ID_DB04 = 0x84, 1002 DBG_BLOCK_ID_UNUSED27 = 0x85, 1003 DBG_BLOCK_ID_UNUSED28 = 0x86, 1004 DBG_BLOCK_ID_UNUSED29 = 0x87, 1005 DBG_BLOCK_ID_DB10 = 0x88, 1006 DBG_BLOCK_ID_DB11 = 0x89, 1007 DBG_BLOCK_ID_DB12 = 0x8a, 1008 DBG_BLOCK_ID_DB13 = 0x8b, 1009 DBG_BLOCK_ID_DB14 = 0x8c, 1010 DBG_BLOCK_ID_UNUSED30 = 0x8d, 1011 DBG_BLOCK_ID_UNUSED31 = 0x8e, 1012 DBG_BLOCK_ID_UNUSED32 = 0x8f, 1013 DBG_BLOCK_ID_TCC0 = 0x90, 1014 DBG_BLOCK_ID_TCC1 = 0x91, 1015 DBG_BLOCK_ID_TCC2 = 0x92, 1016 DBG_BLOCK_ID_TCC3 = 0x93, 1017 DBG_BLOCK_ID_TCC4 = 0x94, 1018 DBG_BLOCK_ID_TCC5 = 0x95, 1019 DBG_BLOCK_ID_TCC6 = 0x96, 1020 DBG_BLOCK_ID_TCC7 = 0x97, 1021 DBG_BLOCK_ID_SPS00 = 0x98, 1022 DBG_BLOCK_ID_SPS01 = 0x99, 1023 DBG_BLOCK_ID_SPS02 = 0x9a, 1024 DBG_BLOCK_ID_SPS10 = 0x9b, 1025 DBG_BLOCK_ID_SPS11 = 0x9c, 1026 DBG_BLOCK_ID_SPS12 = 0x9d, 1027 DBG_BLOCK_ID_UNUSED33 = 0x9e, 1028 DBG_BLOCK_ID_UNUSED34 = 0x9f, 1029 DBG_BLOCK_ID_TA00 = 0xa0, 1030 DBG_BLOCK_ID_TA01 = 0xa1, 1031 DBG_BLOCK_ID_TA02 = 0xa2, 1032 DBG_BLOCK_ID_TA03 = 0xa3, 1033 DBG_BLOCK_ID_TA04 = 0xa4, 1034 DBG_BLOCK_ID_TA05 = 0xa5, 1035 DBG_BLOCK_ID_TA06 = 0xa6, 1036 DBG_BLOCK_ID_TA07 = 0xa7, 1037 DBG_BLOCK_ID_TA08 = 0xa8, 1038 DBG_BLOCK_ID_TA09 = 0xa9, 1039 DBG_BLOCK_ID_TA0A = 0xaa, 1040 DBG_BLOCK_ID_TA0B = 0xab, 1041 DBG_BLOCK_ID_UNUSED35 = 0xac, 1042 DBG_BLOCK_ID_UNUSED36 = 0xad, 1043 DBG_BLOCK_ID_UNUSED37 = 0xae, 1044 DBG_BLOCK_ID_UNUSED38 = 0xaf, 1045 DBG_BLOCK_ID_TA10 = 0xb0, 1046 DBG_BLOCK_ID_TA11 = 0xb1, 1047 DBG_BLOCK_ID_TA12 = 0xb2, 1048 DBG_BLOCK_ID_TA13 = 0xb3, 1049 DBG_BLOCK_ID_TA14 = 0xb4, 1050 DBG_BLOCK_ID_TA15 = 0xb5, 1051 DBG_BLOCK_ID_TA16 = 0xb6, 1052 DBG_BLOCK_ID_TA17 = 0xb7, 1053 DBG_BLOCK_ID_TA18 = 0xb8, 1054 DBG_BLOCK_ID_TA19 = 0xb9, 1055 DBG_BLOCK_ID_TA1A = 0xba, 1056 DBG_BLOCK_ID_TA1B = 0xbb, 1057 DBG_BLOCK_ID_UNUSED39 = 0xbc, 1058 DBG_BLOCK_ID_UNUSED40 = 0xbd, 1059 DBG_BLOCK_ID_UNUSED41 = 0xbe, 1060 DBG_BLOCK_ID_UNUSED42 = 0xbf, 1061 DBG_BLOCK_ID_TD00 = 0xc0, 1062 DBG_BLOCK_ID_TD01 = 0xc1, 1063 DBG_BLOCK_ID_TD02 = 0xc2, 1064 DBG_BLOCK_ID_TD03 = 0xc3, 1065 DBG_BLOCK_ID_TD04 = 0xc4, 1066 DBG_BLOCK_ID_TD05 = 0xc5, 1067 DBG_BLOCK_ID_TD06 = 0xc6, 1068 DBG_BLOCK_ID_TD07 = 0xc7, 1069 DBG_BLOCK_ID_TD08 = 0xc8, 1070 DBG_BLOCK_ID_TD09 = 0xc9, 1071 DBG_BLOCK_ID_TD0A = 0xca, 1072 DBG_BLOCK_ID_TD0B = 0xcb, 1073 DBG_BLOCK_ID_UNUSED43 = 0xcc, 1074 DBG_BLOCK_ID_UNUSED44 = 0xcd, 1075 DBG_BLOCK_ID_UNUSED45 = 0xce, 1076 DBG_BLOCK_ID_UNUSED46 = 0xcf, 1077 DBG_BLOCK_ID_TD10 = 0xd0, 1078 DBG_BLOCK_ID_TD11 = 0xd1, 1079 DBG_BLOCK_ID_TD12 = 0xd2, 1080 DBG_BLOCK_ID_TD13 = 0xd3, 1081 DBG_BLOCK_ID_TD14 = 0xd4, 1082 DBG_BLOCK_ID_TD15 = 0xd5, 1083 DBG_BLOCK_ID_TD16 = 0xd6, 1084 DBG_BLOCK_ID_TD17 = 0xd7, 1085 DBG_BLOCK_ID_TD18 = 0xd8, 1086 DBG_BLOCK_ID_TD19 = 0xd9, 1087 DBG_BLOCK_ID_TD1A = 0xda, 1088 DBG_BLOCK_ID_TD1B = 0xdb, 1089 DBG_BLOCK_ID_UNUSED47 = 0xdc, 1090 DBG_BLOCK_ID_UNUSED48 = 0xdd, 1091 DBG_BLOCK_ID_UNUSED49 = 0xde, 1092 DBG_BLOCK_ID_UNUSED50 = 0xdf, 1093 DBG_BLOCK_ID_MCD0 = 0xe0, 1094 DBG_BLOCK_ID_MCD1 = 0xe1, 1095 DBG_BLOCK_ID_MCD2 = 0xe2, 1096 DBG_BLOCK_ID_MCD3 = 0xe3, 1097 DBG_BLOCK_ID_MCD4 = 0xe4, 1098 DBG_BLOCK_ID_MCD5 = 0xe5, 1099 DBG_BLOCK_ID_UNUSED51 = 0xe6, 1100 DBG_BLOCK_ID_UNUSED52 = 0xe7, 1101 } DebugBlockId_OLD; 1102 typedef enum DebugBlockId_BY2 { 1103 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 1104 DBG_BLOCK_ID_VMC_BY2 = 0x1, 1105 DBG_BLOCK_ID_CG_BY2 = 0x2, 1106 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 1107 DBG_BLOCK_ID_CSC_BY2 = 0x4, 1108 DBG_BLOCK_ID_IH_BY2 = 0x5, 1109 DBG_BLOCK_ID_SQ_BY2 = 0x6, 1110 DBG_BLOCK_ID_GMCON_BY2 = 0x7, 1111 DBG_BLOCK_ID_DMA0_BY2 = 0x8, 1112 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 1113 DBG_BLOCK_ID_SPIS_BY2 = 0xa, 1114 DBG_BLOCK_ID_PA0_BY2 = 0xb, 1115 DBG_BLOCK_ID_CP0_BY2 = 0xc, 1116 DBG_BLOCK_ID_CP2_BY2 = 0xd, 1117 DBG_BLOCK_ID_UVDU_BY2 = 0xe, 1118 DBG_BLOCK_ID_VCE_BY2 = 0xf, 1119 DBG_BLOCK_ID_VGT0_BY2 = 0x10, 1120 DBG_BLOCK_ID_IA_BY2 = 0x11, 1121 DBG_BLOCK_ID_SCT0_BY2 = 0x12, 1122 DBG_BLOCK_ID_SPM0_BY2 = 0x13, 1123 DBG_BLOCK_ID_TCAA_BY2 = 0x14, 1124 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 1125 DBG_BLOCK_ID_MCC0_BY2 = 0x16, 1126 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 1127 DBG_BLOCK_ID_SX0_BY2 = 0x18, 1128 DBG_BLOCK_ID_SX2_BY2 = 0x19, 1129 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 1130 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 1131 DBG_BLOCK_ID_PC0_BY2 = 0x1c, 1132 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 1133 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 1134 DBG_BLOCK_ID_MCB_BY2 = 0x1f, 1135 DBG_BLOCK_ID_SCB0_BY2 = 0x20, 1136 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 1137 DBG_BLOCK_ID_SCF0_BY2 = 0x22, 1138 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 1139 DBG_BLOCK_ID_BCI0_BY2 = 0x24, 1140 DBG_BLOCK_ID_BCI2_BY2 = 0x25, 1141 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 1142 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 1143 DBG_BLOCK_ID_CB00_BY2 = 0x28, 1144 DBG_BLOCK_ID_CB02_BY2 = 0x29, 1145 DBG_BLOCK_ID_CB04_BY2 = 0x2a, 1146 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 1147 DBG_BLOCK_ID_CB10_BY2 = 0x2c, 1148 DBG_BLOCK_ID_CB12_BY2 = 0x2d, 1149 DBG_BLOCK_ID_CB14_BY2 = 0x2e, 1150 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 1151 DBG_BLOCK_ID_TCP0_BY2 = 0x30, 1152 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 1153 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 1154 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 1155 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 1156 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 1157 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 1158 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 1159 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 1160 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 1161 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 1162 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 1163 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 1164 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 1165 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 1166 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 1167 DBG_BLOCK_ID_DB00_BY2 = 0x40, 1168 DBG_BLOCK_ID_DB02_BY2 = 0x41, 1169 DBG_BLOCK_ID_DB04_BY2 = 0x42, 1170 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 1171 DBG_BLOCK_ID_DB10_BY2 = 0x44, 1172 DBG_BLOCK_ID_DB12_BY2 = 0x45, 1173 DBG_BLOCK_ID_DB14_BY2 = 0x46, 1174 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 1175 DBG_BLOCK_ID_TCC0_BY2 = 0x48, 1176 DBG_BLOCK_ID_TCC2_BY2 = 0x49, 1177 DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 1178 DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 1179 DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 1180 DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 1181 DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 1182 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 1183 DBG_BLOCK_ID_TA00_BY2 = 0x50, 1184 DBG_BLOCK_ID_TA02_BY2 = 0x51, 1185 DBG_BLOCK_ID_TA04_BY2 = 0x52, 1186 DBG_BLOCK_ID_TA06_BY2 = 0x53, 1187 DBG_BLOCK_ID_TA08_BY2 = 0x54, 1188 DBG_BLOCK_ID_TA0A_BY2 = 0x55, 1189 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 1190 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 1191 DBG_BLOCK_ID_TA10_BY2 = 0x58, 1192 DBG_BLOCK_ID_TA12_BY2 = 0x59, 1193 DBG_BLOCK_ID_TA14_BY2 = 0x5a, 1194 DBG_BLOCK_ID_TA16_BY2 = 0x5b, 1195 DBG_BLOCK_ID_TA18_BY2 = 0x5c, 1196 DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 1197 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 1198 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 1199 DBG_BLOCK_ID_TD00_BY2 = 0x60, 1200 DBG_BLOCK_ID_TD02_BY2 = 0x61, 1201 DBG_BLOCK_ID_TD04_BY2 = 0x62, 1202 DBG_BLOCK_ID_TD06_BY2 = 0x63, 1203 DBG_BLOCK_ID_TD08_BY2 = 0x64, 1204 DBG_BLOCK_ID_TD0A_BY2 = 0x65, 1205 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 1206 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 1207 DBG_BLOCK_ID_TD10_BY2 = 0x68, 1208 DBG_BLOCK_ID_TD12_BY2 = 0x69, 1209 DBG_BLOCK_ID_TD14_BY2 = 0x6a, 1210 DBG_BLOCK_ID_TD16_BY2 = 0x6b, 1211 DBG_BLOCK_ID_TD18_BY2 = 0x6c, 1212 DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 1213 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 1214 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 1215 DBG_BLOCK_ID_MCD0_BY2 = 0x70, 1216 DBG_BLOCK_ID_MCD2_BY2 = 0x71, 1217 DBG_BLOCK_ID_MCD4_BY2 = 0x72, 1218 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 1219 } DebugBlockId_BY2; 1220 typedef enum DebugBlockId_BY4 { 1221 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 1222 DBG_BLOCK_ID_CG_BY4 = 0x1, 1223 DBG_BLOCK_ID_CSC_BY4 = 0x2, 1224 DBG_BLOCK_ID_SQ_BY4 = 0x3, 1225 DBG_BLOCK_ID_DMA0_BY4 = 0x4, 1226 DBG_BLOCK_ID_SPIS_BY4 = 0x5, 1227 DBG_BLOCK_ID_CP0_BY4 = 0x6, 1228 DBG_BLOCK_ID_UVDU_BY4 = 0x7, 1229 DBG_BLOCK_ID_VGT0_BY4 = 0x8, 1230 DBG_BLOCK_ID_SCT0_BY4 = 0x9, 1231 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 1232 DBG_BLOCK_ID_MCC0_BY4 = 0xb, 1233 DBG_BLOCK_ID_SX0_BY4 = 0xc, 1234 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 1235 DBG_BLOCK_ID_PC0_BY4 = 0xe, 1236 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 1237 DBG_BLOCK_ID_SCB0_BY4 = 0x10, 1238 DBG_BLOCK_ID_SCF0_BY4 = 0x11, 1239 DBG_BLOCK_ID_BCI0_BY4 = 0x12, 1240 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 1241 DBG_BLOCK_ID_CB00_BY4 = 0x14, 1242 DBG_BLOCK_ID_CB04_BY4 = 0x15, 1243 DBG_BLOCK_ID_CB10_BY4 = 0x16, 1244 DBG_BLOCK_ID_CB14_BY4 = 0x17, 1245 DBG_BLOCK_ID_TCP0_BY4 = 0x18, 1246 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 1247 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 1248 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 1249 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 1250 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 1251 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 1252 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 1253 DBG_BLOCK_ID_DB_BY4 = 0x20, 1254 DBG_BLOCK_ID_DB04_BY4 = 0x21, 1255 DBG_BLOCK_ID_DB10_BY4 = 0x22, 1256 DBG_BLOCK_ID_DB14_BY4 = 0x23, 1257 DBG_BLOCK_ID_TCC0_BY4 = 0x24, 1258 DBG_BLOCK_ID_TCC4_BY4 = 0x25, 1259 DBG_BLOCK_ID_SPS00_BY4 = 0x26, 1260 DBG_BLOCK_ID_SPS11_BY4 = 0x27, 1261 DBG_BLOCK_ID_TA00_BY4 = 0x28, 1262 DBG_BLOCK_ID_TA04_BY4 = 0x29, 1263 DBG_BLOCK_ID_TA08_BY4 = 0x2a, 1264 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 1265 DBG_BLOCK_ID_TA10_BY4 = 0x2c, 1266 DBG_BLOCK_ID_TA14_BY4 = 0x2d, 1267 DBG_BLOCK_ID_TA18_BY4 = 0x2e, 1268 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 1269 DBG_BLOCK_ID_TD00_BY4 = 0x30, 1270 DBG_BLOCK_ID_TD04_BY4 = 0x31, 1271 DBG_BLOCK_ID_TD08_BY4 = 0x32, 1272 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 1273 DBG_BLOCK_ID_TD10_BY4 = 0x34, 1274 DBG_BLOCK_ID_TD14_BY4 = 0x35, 1275 DBG_BLOCK_ID_TD18_BY4 = 0x36, 1276 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 1277 DBG_BLOCK_ID_MCD0_BY4 = 0x38, 1278 DBG_BLOCK_ID_MCD4_BY4 = 0x39, 1279 } DebugBlockId_BY4; 1280 typedef enum DebugBlockId_BY8 { 1281 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 1282 DBG_BLOCK_ID_CSC_BY8 = 0x1, 1283 DBG_BLOCK_ID_DMA0_BY8 = 0x2, 1284 DBG_BLOCK_ID_CP0_BY8 = 0x3, 1285 DBG_BLOCK_ID_VGT0_BY8 = 0x4, 1286 DBG_BLOCK_ID_TCAA_BY8 = 0x5, 1287 DBG_BLOCK_ID_SX0_BY8 = 0x6, 1288 DBG_BLOCK_ID_PC0_BY8 = 0x7, 1289 DBG_BLOCK_ID_SCB0_BY8 = 0x8, 1290 DBG_BLOCK_ID_BCI0_BY8 = 0x9, 1291 DBG_BLOCK_ID_CB00_BY8 = 0xa, 1292 DBG_BLOCK_ID_CB10_BY8 = 0xb, 1293 DBG_BLOCK_ID_TCP0_BY8 = 0xc, 1294 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 1295 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 1296 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 1297 DBG_BLOCK_ID_DB00_BY8 = 0x10, 1298 DBG_BLOCK_ID_DB10_BY8 = 0x11, 1299 DBG_BLOCK_ID_TCC0_BY8 = 0x12, 1300 DBG_BLOCK_ID_SPS00_BY8 = 0x13, 1301 DBG_BLOCK_ID_TA00_BY8 = 0x14, 1302 DBG_BLOCK_ID_TA08_BY8 = 0x15, 1303 DBG_BLOCK_ID_TA10_BY8 = 0x16, 1304 DBG_BLOCK_ID_TA18_BY8 = 0x17, 1305 DBG_BLOCK_ID_TD00_BY8 = 0x18, 1306 DBG_BLOCK_ID_TD08_BY8 = 0x19, 1307 DBG_BLOCK_ID_TD10_BY8 = 0x1a, 1308 DBG_BLOCK_ID_TD18_BY8 = 0x1b, 1309 DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 1310 } DebugBlockId_BY8; 1311 typedef enum DebugBlockId_BY16 { 1312 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 1313 DBG_BLOCK_ID_DMA0_BY16 = 0x1, 1314 DBG_BLOCK_ID_VGT0_BY16 = 0x2, 1315 DBG_BLOCK_ID_SX0_BY16 = 0x3, 1316 DBG_BLOCK_ID_SCB0_BY16 = 0x4, 1317 DBG_BLOCK_ID_CB00_BY16 = 0x5, 1318 DBG_BLOCK_ID_TCP0_BY16 = 0x6, 1319 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 1320 DBG_BLOCK_ID_DB00_BY16 = 0x8, 1321 DBG_BLOCK_ID_TCC0_BY16 = 0x9, 1322 DBG_BLOCK_ID_TA00_BY16 = 0xa, 1323 DBG_BLOCK_ID_TA10_BY16 = 0xb, 1324 DBG_BLOCK_ID_TD00_BY16 = 0xc, 1325 DBG_BLOCK_ID_TD10_BY16 = 0xd, 1326 DBG_BLOCK_ID_MCD0_BY16 = 0xe, 1327 } DebugBlockId_BY16; 1328 typedef enum ColorTransform { 1329 DCC_CT_AUTO = 0x0, 1330 DCC_CT_NONE = 0x1, 1331 ABGR_TO_A_BG_G_RB = 0x2, 1332 BGRA_TO_BG_G_RB_A = 0x3, 1333 } ColorTransform; 1334 typedef enum CompareRef { 1335 REF_NEVER = 0x0, 1336 REF_LESS = 0x1, 1337 REF_EQUAL = 0x2, 1338 REF_LEQUAL = 0x3, 1339 REF_GREATER = 0x4, 1340 REF_NOTEQUAL = 0x5, 1341 REF_GEQUAL = 0x6, 1342 REF_ALWAYS = 0x7, 1343 } CompareRef; 1344 typedef enum ReadSize { 1345 READ_256_BITS = 0x0, 1346 READ_512_BITS = 0x1, 1347 } ReadSize; 1348 typedef enum DepthFormat { 1349 DEPTH_INVALID = 0x0, 1350 DEPTH_16 = 0x1, 1351 DEPTH_X8_24 = 0x2, 1352 DEPTH_8_24 = 0x3, 1353 DEPTH_X8_24_FLOAT = 0x4, 1354 DEPTH_8_24_FLOAT = 0x5, 1355 DEPTH_32_FLOAT = 0x6, 1356 DEPTH_X24_8_32_FLOAT = 0x7, 1357 } DepthFormat; 1358 typedef enum ZFormat { 1359 Z_INVALID = 0x0, 1360 Z_16 = 0x1, 1361 Z_24 = 0x2, 1362 Z_32_FLOAT = 0x3, 1363 } ZFormat; 1364 typedef enum StencilFormat { 1365 STENCIL_INVALID = 0x0, 1366 STENCIL_8 = 0x1, 1367 } StencilFormat; 1368 typedef enum CmaskMode { 1369 CMASK_CLEAR_NONE = 0x0, 1370 CMASK_CLEAR_ONE = 0x1, 1371 CMASK_CLEAR_ALL = 0x2, 1372 CMASK_ANY_EXPANDED = 0x3, 1373 CMASK_ALPHA0_FRAG1 = 0x4, 1374 CMASK_ALPHA0_FRAG2 = 0x5, 1375 CMASK_ALPHA0_FRAG4 = 0x6, 1376 CMASK_ALPHA0_FRAGS = 0x7, 1377 CMASK_ALPHA1_FRAG1 = 0x8, 1378 CMASK_ALPHA1_FRAG2 = 0x9, 1379 CMASK_ALPHA1_FRAG4 = 0xa, 1380 CMASK_ALPHA1_FRAGS = 0xb, 1381 CMASK_ALPHAX_FRAG1 = 0xc, 1382 CMASK_ALPHAX_FRAG2 = 0xd, 1383 CMASK_ALPHAX_FRAG4 = 0xe, 1384 CMASK_ALPHAX_FRAGS = 0xf, 1385 } CmaskMode; 1386 typedef enum QuadExportFormat { 1387 EXPORT_UNUSED = 0x0, 1388 EXPORT_32_R = 0x1, 1389 EXPORT_32_GR = 0x2, 1390 EXPORT_32_AR = 0x3, 1391 EXPORT_FP16_ABGR = 0x4, 1392 EXPORT_UNSIGNED16_ABGR = 0x5, 1393 EXPORT_SIGNED16_ABGR = 0x6, 1394 EXPORT_32_ABGR = 0x7, 1395 } QuadExportFormat; 1396 typedef enum QuadExportFormatOld { 1397 EXPORT_4P_32BPC_ABGR = 0x0, 1398 EXPORT_4P_16BPC_ABGR = 0x1, 1399 EXPORT_4P_32BPC_GR = 0x2, 1400 EXPORT_4P_32BPC_AR = 0x3, 1401 EXPORT_2P_32BPC_ABGR = 0x4, 1402 EXPORT_8P_32BPC_R = 0x5, 1403 } QuadExportFormatOld; 1404 typedef enum ColorFormat { 1405 COLOR_INVALID = 0x0, 1406 COLOR_8 = 0x1, 1407 COLOR_16 = 0x2, 1408 COLOR_8_8 = 0x3, 1409 COLOR_32 = 0x4, 1410 COLOR_16_16 = 0x5, 1411 COLOR_10_11_11 = 0x6, 1412 COLOR_11_11_10 = 0x7, 1413 COLOR_10_10_10_2 = 0x8, 1414 COLOR_2_10_10_10 = 0x9, 1415 COLOR_8_8_8_8 = 0xa, 1416 COLOR_32_32 = 0xb, 1417 COLOR_16_16_16_16 = 0xc, 1418 COLOR_RESERVED_13 = 0xd, 1419 COLOR_32_32_32_32 = 0xe, 1420 COLOR_RESERVED_15 = 0xf, 1421 COLOR_5_6_5 = 0x10, 1422 COLOR_1_5_5_5 = 0x11, 1423 COLOR_5_5_5_1 = 0x12, 1424 COLOR_4_4_4_4 = 0x13, 1425 COLOR_8_24 = 0x14, 1426 COLOR_24_8 = 0x15, 1427 COLOR_X24_8_32_FLOAT = 0x16, 1428 COLOR_RESERVED_23 = 0x17, 1429 } ColorFormat; 1430 typedef enum SurfaceFormat { 1431 FMT_INVALID = 0x0, 1432 FMT_8 = 0x1, 1433 FMT_16 = 0x2, 1434 FMT_8_8 = 0x3, 1435 FMT_32 = 0x4, 1436 FMT_16_16 = 0x5, 1437 FMT_10_11_11 = 0x6, 1438 FMT_11_11_10 = 0x7, 1439 FMT_10_10_10_2 = 0x8, 1440 FMT_2_10_10_10 = 0x9, 1441 FMT_8_8_8_8 = 0xa, 1442 FMT_32_32 = 0xb, 1443 FMT_16_16_16_16 = 0xc, 1444 FMT_32_32_32 = 0xd, 1445 FMT_32_32_32_32 = 0xe, 1446 FMT_RESERVED_4 = 0xf, 1447 FMT_5_6_5 = 0x10, 1448 FMT_1_5_5_5 = 0x11, 1449 FMT_5_5_5_1 = 0x12, 1450 FMT_4_4_4_4 = 0x13, 1451 FMT_8_24 = 0x14, 1452 FMT_24_8 = 0x15, 1453 FMT_X24_8_32_FLOAT = 0x16, 1454 FMT_RESERVED_33 = 0x17, 1455 FMT_11_11_10_FLOAT = 0x18, 1456 FMT_16_FLOAT = 0x19, 1457 FMT_32_FLOAT = 0x1a, 1458 FMT_16_16_FLOAT = 0x1b, 1459 FMT_8_24_FLOAT = 0x1c, 1460 FMT_24_8_FLOAT = 0x1d, 1461 FMT_32_32_FLOAT = 0x1e, 1462 FMT_10_11_11_FLOAT = 0x1f, 1463 FMT_16_16_16_16_FLOAT = 0x20, 1464 FMT_3_3_2 = 0x21, 1465 FMT_6_5_5 = 0x22, 1466 FMT_32_32_32_32_FLOAT = 0x23, 1467 FMT_RESERVED_36 = 0x24, 1468 FMT_1 = 0x25, 1469 FMT_1_REVERSED = 0x26, 1470 FMT_GB_GR = 0x27, 1471 FMT_BG_RG = 0x28, 1472 FMT_32_AS_8 = 0x29, 1473 FMT_32_AS_8_8 = 0x2a, 1474 FMT_5_9_9_9_SHAREDEXP = 0x2b, 1475 FMT_8_8_8 = 0x2c, 1476 FMT_16_16_16 = 0x2d, 1477 FMT_16_16_16_FLOAT = 0x2e, 1478 FMT_4_4 = 0x2f, 1479 FMT_32_32_32_FLOAT = 0x30, 1480 FMT_BC1 = 0x31, 1481 FMT_BC2 = 0x32, 1482 FMT_BC3 = 0x33, 1483 FMT_BC4 = 0x34, 1484 FMT_BC5 = 0x35, 1485 FMT_BC6 = 0x36, 1486 FMT_BC7 = 0x37, 1487 FMT_32_AS_32_32_32_32 = 0x38, 1488 FMT_APC3 = 0x39, 1489 FMT_APC4 = 0x3a, 1490 FMT_APC5 = 0x3b, 1491 FMT_APC6 = 0x3c, 1492 FMT_APC7 = 0x3d, 1493 FMT_CTX1 = 0x3e, 1494 FMT_RESERVED_63 = 0x3f, 1495 } SurfaceFormat; 1496 typedef enum BUF_DATA_FORMAT { 1497 BUF_DATA_FORMAT_INVALID = 0x0, 1498 BUF_DATA_FORMAT_8 = 0x1, 1499 BUF_DATA_FORMAT_16 = 0x2, 1500 BUF_DATA_FORMAT_8_8 = 0x3, 1501 BUF_DATA_FORMAT_32 = 0x4, 1502 BUF_DATA_FORMAT_16_16 = 0x5, 1503 BUF_DATA_FORMAT_10_11_11 = 0x6, 1504 BUF_DATA_FORMAT_11_11_10 = 0x7, 1505 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 1506 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 1507 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 1508 BUF_DATA_FORMAT_32_32 = 0xb, 1509 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 1510 BUF_DATA_FORMAT_32_32_32 = 0xd, 1511 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 1512 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 1513 } BUF_DATA_FORMAT; 1514 typedef enum IMG_DATA_FORMAT { 1515 IMG_DATA_FORMAT_INVALID = 0x0, 1516 IMG_DATA_FORMAT_8 = 0x1, 1517 IMG_DATA_FORMAT_16 = 0x2, 1518 IMG_DATA_FORMAT_8_8 = 0x3, 1519 IMG_DATA_FORMAT_32 = 0x4, 1520 IMG_DATA_FORMAT_16_16 = 0x5, 1521 IMG_DATA_FORMAT_10_11_11 = 0x6, 1522 IMG_DATA_FORMAT_11_11_10 = 0x7, 1523 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 1524 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 1525 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 1526 IMG_DATA_FORMAT_32_32 = 0xb, 1527 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 1528 IMG_DATA_FORMAT_32_32_32 = 0xd, 1529 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 1530 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 1531 IMG_DATA_FORMAT_5_6_5 = 0x10, 1532 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 1533 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 1534 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 1535 IMG_DATA_FORMAT_8_24 = 0x14, 1536 IMG_DATA_FORMAT_24_8 = 0x15, 1537 IMG_DATA_FORMAT_X24_8_32 = 0x16, 1538 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 1539 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 1540 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 1541 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 1542 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 1543 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 1544 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 1545 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 1546 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 1547 IMG_DATA_FORMAT_GB_GR = 0x20, 1548 IMG_DATA_FORMAT_BG_RG = 0x21, 1549 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 1550 IMG_DATA_FORMAT_BC1 = 0x23, 1551 IMG_DATA_FORMAT_BC2 = 0x24, 1552 IMG_DATA_FORMAT_BC3 = 0x25, 1553 IMG_DATA_FORMAT_BC4 = 0x26, 1554 IMG_DATA_FORMAT_BC5 = 0x27, 1555 IMG_DATA_FORMAT_BC6 = 0x28, 1556 IMG_DATA_FORMAT_BC7 = 0x29, 1557 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 1558 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 1559 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 1560 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 1561 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 1562 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 1563 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 1564 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 1565 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 1566 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 1567 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 1568 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 1569 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 1570 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 1571 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 1572 IMG_DATA_FORMAT_4_4 = 0x39, 1573 IMG_DATA_FORMAT_6_5_5 = 0x3a, 1574 IMG_DATA_FORMAT_1 = 0x3b, 1575 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 1576 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1577 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1578 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1579 } IMG_DATA_FORMAT; 1580 typedef enum BUF_NUM_FORMAT { 1581 BUF_NUM_FORMAT_UNORM = 0x0, 1582 BUF_NUM_FORMAT_SNORM = 0x1, 1583 BUF_NUM_FORMAT_USCALED = 0x2, 1584 BUF_NUM_FORMAT_SSCALED = 0x3, 1585 BUF_NUM_FORMAT_UINT = 0x4, 1586 BUF_NUM_FORMAT_SINT = 0x5, 1587 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1588 BUF_NUM_FORMAT_FLOAT = 0x7, 1589 } BUF_NUM_FORMAT; 1590 typedef enum IMG_NUM_FORMAT { 1591 IMG_NUM_FORMAT_UNORM = 0x0, 1592 IMG_NUM_FORMAT_SNORM = 0x1, 1593 IMG_NUM_FORMAT_USCALED = 0x2, 1594 IMG_NUM_FORMAT_SSCALED = 0x3, 1595 IMG_NUM_FORMAT_UINT = 0x4, 1596 IMG_NUM_FORMAT_SINT = 0x5, 1597 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1598 IMG_NUM_FORMAT_FLOAT = 0x7, 1599 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1600 IMG_NUM_FORMAT_SRGB = 0x9, 1601 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1602 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1603 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1604 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1605 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1606 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1607 } IMG_NUM_FORMAT; 1608 typedef enum TileType { 1609 ARRAY_COLOR_TILE = 0x0, 1610 ARRAY_DEPTH_TILE = 0x1, 1611 } TileType; 1612 typedef enum NonDispTilingOrder { 1613 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1614 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1615 } NonDispTilingOrder; 1616 typedef enum MicroTileMode { 1617 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1618 ADDR_SURF_THIN_MICRO_TILING = 0x1, 1619 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1620 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1621 ADDR_SURF_THICK_MICRO_TILING = 0x4, 1622 } MicroTileMode; 1623 typedef enum TileSplit { 1624 ADDR_SURF_TILE_SPLIT_64B = 0x0, 1625 ADDR_SURF_TILE_SPLIT_128B = 0x1, 1626 ADDR_SURF_TILE_SPLIT_256B = 0x2, 1627 ADDR_SURF_TILE_SPLIT_512B = 0x3, 1628 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1629 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1630 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1631 } TileSplit; 1632 typedef enum SampleSplit { 1633 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1634 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1635 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1636 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1637 } SampleSplit; 1638 typedef enum PipeConfig { 1639 ADDR_SURF_P2 = 0x0, 1640 ADDR_SURF_P2_RESERVED0 = 0x1, 1641 ADDR_SURF_P2_RESERVED1 = 0x2, 1642 ADDR_SURF_P2_RESERVED2 = 0x3, 1643 ADDR_SURF_P4_8x16 = 0x4, 1644 ADDR_SURF_P4_16x16 = 0x5, 1645 ADDR_SURF_P4_16x32 = 0x6, 1646 ADDR_SURF_P4_32x32 = 0x7, 1647 ADDR_SURF_P8_16x16_8x16 = 0x8, 1648 ADDR_SURF_P8_16x32_8x16 = 0x9, 1649 ADDR_SURF_P8_32x32_8x16 = 0xa, 1650 ADDR_SURF_P8_16x32_16x16 = 0xb, 1651 ADDR_SURF_P8_32x32_16x16 = 0xc, 1652 ADDR_SURF_P8_32x32_16x32 = 0xd, 1653 ADDR_SURF_P8_32x64_32x32 = 0xe, 1654 ADDR_SURF_P8_RESERVED0 = 0xf, 1655 ADDR_SURF_P16_32x32_8x16 = 0x10, 1656 ADDR_SURF_P16_32x32_16x16 = 0x11, 1657 } PipeConfig; 1658 typedef enum NumBanks { 1659 ADDR_SURF_2_BANK = 0x0, 1660 ADDR_SURF_4_BANK = 0x1, 1661 ADDR_SURF_8_BANK = 0x2, 1662 ADDR_SURF_16_BANK = 0x3, 1663 } NumBanks; 1664 typedef enum BankWidth { 1665 ADDR_SURF_BANK_WIDTH_1 = 0x0, 1666 ADDR_SURF_BANK_WIDTH_2 = 0x1, 1667 ADDR_SURF_BANK_WIDTH_4 = 0x2, 1668 ADDR_SURF_BANK_WIDTH_8 = 0x3, 1669 } BankWidth; 1670 typedef enum BankHeight { 1671 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1672 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1673 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1674 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1675 } BankHeight; 1676 typedef enum BankWidthHeight { 1677 ADDR_SURF_BANK_WH_1 = 0x0, 1678 ADDR_SURF_BANK_WH_2 = 0x1, 1679 ADDR_SURF_BANK_WH_4 = 0x2, 1680 ADDR_SURF_BANK_WH_8 = 0x3, 1681 } BankWidthHeight; 1682 typedef enum MacroTileAspect { 1683 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1684 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1685 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1686 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1687 } MacroTileAspect; 1688 typedef enum GATCL1RequestType { 1689 GATCL1_TYPE_NORMAL = 0x0, 1690 GATCL1_TYPE_SHOOTDOWN = 0x1, 1691 GATCL1_TYPE_BYPASS = 0x2, 1692 } GATCL1RequestType; 1693 typedef enum TCC_CACHE_POLICIES { 1694 TCC_CACHE_POLICY_LRU = 0x0, 1695 TCC_CACHE_POLICY_STREAM = 0x1, 1696 } TCC_CACHE_POLICIES; 1697 typedef enum MTYPE { 1698 MTYPE_NC_NV = 0x0, 1699 MTYPE_NC = 0x1, 1700 MTYPE_CC = 0x2, 1701 MTYPE_UC = 0x3, 1702 } MTYPE; 1703 typedef enum PERFMON_COUNTER_MODE { 1704 PERFMON_COUNTER_MODE_ACCUM = 0x0, 1705 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1706 PERFMON_COUNTER_MODE_MAX = 0x2, 1707 PERFMON_COUNTER_MODE_DIRTY = 0x3, 1708 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1709 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1710 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1711 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1712 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1713 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1714 PERFMON_COUNTER_MODE_RESERVED = 0xf, 1715 } PERFMON_COUNTER_MODE; 1716 typedef enum PERFMON_SPM_MODE { 1717 PERFMON_SPM_MODE_OFF = 0x0, 1718 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1719 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1720 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1721 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1722 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1723 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1724 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1725 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1726 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1727 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1728 } PERFMON_SPM_MODE; 1729 typedef enum SurfaceTiling { 1730 ARRAY_LINEAR = 0x0, 1731 ARRAY_TILED = 0x1, 1732 } SurfaceTiling; 1733 typedef enum SurfaceArray { 1734 ARRAY_1D = 0x0, 1735 ARRAY_2D = 0x1, 1736 ARRAY_3D = 0x2, 1737 ARRAY_3D_SLICE = 0x3, 1738 } SurfaceArray; 1739 typedef enum ColorArray { 1740 ARRAY_2D_ALT_COLOR = 0x0, 1741 ARRAY_2D_COLOR = 0x1, 1742 ARRAY_3D_SLICE_COLOR = 0x3, 1743 } ColorArray; 1744 typedef enum DepthArray { 1745 ARRAY_2D_ALT_DEPTH = 0x0, 1746 ARRAY_2D_DEPTH = 0x1, 1747 } DepthArray; 1748 typedef enum ENUM_NUM_SIMD_PER_CU { 1749 NUM_SIMD_PER_CU = 0x4, 1750 } ENUM_NUM_SIMD_PER_CU; 1751 typedef enum MEM_PWR_FORCE_CTRL { 1752 NO_FORCE_REQUEST = 0x0, 1753 FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1754 FORCE_DEEP_SLEEP_REQUEST = 0x2, 1755 FORCE_SHUT_DOWN_REQUEST = 0x3, 1756 } MEM_PWR_FORCE_CTRL; 1757 typedef enum MEM_PWR_FORCE_CTRL2 { 1758 NO_FORCE_REQ = 0x0, 1759 FORCE_LIGHT_SLEEP_REQ = 0x1, 1760 } MEM_PWR_FORCE_CTRL2; 1761 typedef enum MEM_PWR_DIS_CTRL { 1762 ENABLE_MEM_PWR_CTRL = 0x0, 1763 DISABLE_MEM_PWR_CTRL = 0x1, 1764 } MEM_PWR_DIS_CTRL; 1765 typedef enum MEM_PWR_SEL_CTRL { 1766 DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1767 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1768 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1769 } MEM_PWR_SEL_CTRL; 1770 typedef enum MEM_PWR_SEL_CTRL2 { 1771 DYNAMIC_DEEP_SLEEP_EN = 0x0, 1772 DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1773 } MEM_PWR_SEL_CTRL2; 1774 1775 #endif /* DCE_10_0_ENUM_H */ 1776